drivers/media/i2c/ov2640.c

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This source file includes following definitions.
to_ov2640
ov2640_write_array
ov2640_mask_set
ov2640_reset
ov2640_s_ctrl
ov2640_g_register
ov2640_s_register
ov2640_set_power
ov2640_s_power
ov2640_select_win
ov2640_set_params
ov2640_get_fmt
ov2640_set_fmt
ov2640_init_cfg
ov2640_enum_mbus_code
ov2640_get_selection
ov2640_s_stream
ov2640_video_probe
ov2640_probe_dt
ov2640_probe
ov2640_remove
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ov2640 Camera Driver
   4  *
   5  * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
   6  *
   7  * Based on ov772x, ov9640 drivers and previous non merged implementations.
   8  *
   9  * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  10  * Copyright (C) 2006, OmniVision
  11  */
  12 
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/i2c.h>
  16 #include <linux/clk.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/gpio.h>
  20 #include <linux/gpio/consumer.h>
  21 #include <linux/of_gpio.h>
  22 #include <linux/v4l2-mediabus.h>
  23 #include <linux/videodev2.h>
  24 
  25 #include <media/v4l2-device.h>
  26 #include <media/v4l2-event.h>
  27 #include <media/v4l2-subdev.h>
  28 #include <media/v4l2-ctrls.h>
  29 #include <media/v4l2-image-sizes.h>
  30 
  31 #define VAL_SET(x, mask, rshift, lshift)  \
  32                 ((((x) >> rshift) & mask) << lshift)
  33 /*
  34  * DSP registers
  35  * register offset for BANK_SEL == BANK_SEL_DSP
  36  */
  37 #define R_BYPASS    0x05 /* Bypass DSP */
  38 #define   R_BYPASS_DSP_BYPAS    0x01 /* Bypass DSP, sensor out directly */
  39 #define   R_BYPASS_USE_DSP      0x00 /* Use the internal DSP */
  40 #define QS          0x44 /* Quantization Scale Factor */
  41 #define CTRLI       0x50
  42 #define   CTRLI_LP_DP           0x80
  43 #define   CTRLI_ROUND           0x40
  44 #define   CTRLI_V_DIV_SET(x)    VAL_SET(x, 0x3, 0, 3)
  45 #define   CTRLI_H_DIV_SET(x)    VAL_SET(x, 0x3, 0, 0)
  46 #define HSIZE       0x51 /* H_SIZE[7:0] (real/4) */
  47 #define   HSIZE_SET(x)          VAL_SET(x, 0xFF, 2, 0)
  48 #define VSIZE       0x52 /* V_SIZE[7:0] (real/4) */
  49 #define   VSIZE_SET(x)          VAL_SET(x, 0xFF, 2, 0)
  50 #define XOFFL       0x53 /* OFFSET_X[7:0] */
  51 #define   XOFFL_SET(x)          VAL_SET(x, 0xFF, 0, 0)
  52 #define YOFFL       0x54 /* OFFSET_Y[7:0] */
  53 #define   YOFFL_SET(x)          VAL_SET(x, 0xFF, 0, 0)
  54 #define VHYX        0x55 /* Offset and size completion */
  55 #define   VHYX_VSIZE_SET(x)     VAL_SET(x, 0x1, (8+2), 7)
  56 #define   VHYX_HSIZE_SET(x)     VAL_SET(x, 0x1, (8+2), 3)
  57 #define   VHYX_YOFF_SET(x)      VAL_SET(x, 0x3, 8, 4)
  58 #define   VHYX_XOFF_SET(x)      VAL_SET(x, 0x3, 8, 0)
  59 #define DPRP        0x56
  60 #define TEST        0x57 /* Horizontal size completion */
  61 #define   TEST_HSIZE_SET(x)     VAL_SET(x, 0x1, (9+2), 7)
  62 #define ZMOW        0x5A /* Zoom: Out Width  OUTW[7:0] (real/4) */
  63 #define   ZMOW_OUTW_SET(x)      VAL_SET(x, 0xFF, 2, 0)
  64 #define ZMOH        0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */
  65 #define   ZMOH_OUTH_SET(x)      VAL_SET(x, 0xFF, 2, 0)
  66 #define ZMHH        0x5C /* Zoom: Speed and H&W completion */
  67 #define   ZMHH_ZSPEED_SET(x)    VAL_SET(x, 0x0F, 0, 4)
  68 #define   ZMHH_OUTH_SET(x)      VAL_SET(x, 0x1, (8+2), 2)
  69 #define   ZMHH_OUTW_SET(x)      VAL_SET(x, 0x3, (8+2), 0)
  70 #define BPADDR      0x7C /* SDE Indirect Register Access: Address */
  71 #define BPDATA      0x7D /* SDE Indirect Register Access: Data */
  72 #define CTRL2       0x86 /* DSP Module enable 2 */
  73 #define   CTRL2_DCW_EN          0x20
  74 #define   CTRL2_SDE_EN          0x10
  75 #define   CTRL2_UV_ADJ_EN       0x08
  76 #define   CTRL2_UV_AVG_EN       0x04
  77 #define   CTRL2_CMX_EN          0x01
  78 #define CTRL3       0x87 /* DSP Module enable 3 */
  79 #define   CTRL3_BPC_EN          0x80
  80 #define   CTRL3_WPC_EN          0x40
  81 #define SIZEL       0x8C /* Image Size Completion */
  82 #define   SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6)
  83 #define   SIZEL_HSIZE8_SET(x)    VAL_SET(x, 0x7, 0, 3)
  84 #define   SIZEL_VSIZE8_SET(x)    VAL_SET(x, 0x7, 0, 0)
  85 #define HSIZE8      0xC0 /* Image Horizontal Size HSIZE[10:3] */
  86 #define   HSIZE8_SET(x)         VAL_SET(x, 0xFF, 3, 0)
  87 #define VSIZE8      0xC1 /* Image Vertical Size VSIZE[10:3] */
  88 #define   VSIZE8_SET(x)         VAL_SET(x, 0xFF, 3, 0)
  89 #define CTRL0       0xC2 /* DSP Module enable 0 */
  90 #define   CTRL0_AEC_EN       0x80
  91 #define   CTRL0_AEC_SEL      0x40
  92 #define   CTRL0_STAT_SEL     0x20
  93 #define   CTRL0_VFIRST       0x10
  94 #define   CTRL0_YUV422       0x08
  95 #define   CTRL0_YUV_EN       0x04
  96 #define   CTRL0_RGB_EN       0x02
  97 #define   CTRL0_RAW_EN       0x01
  98 #define CTRL1       0xC3 /* DSP Module enable 1 */
  99 #define   CTRL1_CIP          0x80
 100 #define   CTRL1_DMY          0x40
 101 #define   CTRL1_RAW_GMA      0x20
 102 #define   CTRL1_DG           0x10
 103 #define   CTRL1_AWB          0x08
 104 #define   CTRL1_AWB_GAIN     0x04
 105 #define   CTRL1_LENC         0x02
 106 #define   CTRL1_PRE          0x01
 107 /*      REG 0xC7 (unknown name): affects Auto White Balance (AWB)
 108  *        AWB_OFF            0x40
 109  *        AWB_SIMPLE         0x10
 110  *        AWB_ON             0x00       (Advanced AWB ?) */
 111 #define R_DVP_SP    0xD3 /* DVP output speed control */
 112 #define   R_DVP_SP_AUTO_MODE 0x80
 113 #define   R_DVP_SP_DVP_MASK  0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0);
 114                                    *          = sysclk (48)/(2*[6:0]) (RAW);*/
 115 #define IMAGE_MODE  0xDA /* Image Output Format Select */
 116 #define   IMAGE_MODE_Y8_DVP_EN   0x40
 117 #define   IMAGE_MODE_JPEG_EN     0x10
 118 #define   IMAGE_MODE_YUV422      0x00
 119 #define   IMAGE_MODE_RAW10       0x04 /* (DVP) */
 120 #define   IMAGE_MODE_RGB565      0x08
 121 #define   IMAGE_MODE_HREF_VSYNC  0x02 /* HREF timing select in DVP JPEG output
 122                                        * mode (0 for HREF is same as sensor) */
 123 #define   IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP
 124                                        *    1: Low byte first UYVY (C2[4] =0)
 125                                        *        VYUY (C2[4] =1)
 126                                        *    0: High byte first YUYV (C2[4]=0)
 127                                        *        YVYU (C2[4] = 1) */
 128 #define RESET       0xE0 /* Reset */
 129 #define   RESET_MICROC       0x40
 130 #define   RESET_SCCB         0x20
 131 #define   RESET_JPEG         0x10
 132 #define   RESET_DVP          0x04
 133 #define   RESET_IPU          0x02
 134 #define   RESET_CIF          0x01
 135 #define REGED       0xED /* Register ED */
 136 #define   REGED_CLK_OUT_DIS  0x10
 137 #define MS_SP       0xF0 /* SCCB Master Speed */
 138 #define SS_ID       0xF7 /* SCCB Slave ID */
 139 #define SS_CTRL     0xF8 /* SCCB Slave Control */
 140 #define   SS_CTRL_ADD_AUTO_INC  0x20
 141 #define   SS_CTRL_EN            0x08
 142 #define   SS_CTRL_DELAY_CLK     0x04
 143 #define   SS_CTRL_ACC_EN        0x02
 144 #define   SS_CTRL_SEN_PASS_THR  0x01
 145 #define MC_BIST     0xF9 /* Microcontroller misc register */
 146 #define   MC_BIST_RESET           0x80 /* Microcontroller Reset */
 147 #define   MC_BIST_BOOT_ROM_SEL    0x40
 148 #define   MC_BIST_12KB_SEL        0x20
 149 #define   MC_BIST_12KB_MASK       0x30
 150 #define   MC_BIST_512KB_SEL       0x08
 151 #define   MC_BIST_512KB_MASK      0x0C
 152 #define   MC_BIST_BUSY_BIT_R      0x02
 153 #define   MC_BIST_MC_RES_ONE_SH_W 0x02
 154 #define   MC_BIST_LAUNCH          0x01
 155 #define BANK_SEL    0xFF /* Register Bank Select */
 156 #define   BANK_SEL_DSP     0x00
 157 #define   BANK_SEL_SENS    0x01
 158 
 159 /*
 160  * Sensor registers
 161  * register offset for BANK_SEL == BANK_SEL_SENS
 162  */
 163 #define GAIN        0x00 /* AGC - Gain control gain setting */
 164 #define COM1        0x03 /* Common control 1 */
 165 #define   COM1_1_DUMMY_FR          0x40
 166 #define   COM1_3_DUMMY_FR          0x80
 167 #define   COM1_7_DUMMY_FR          0xC0
 168 #define   COM1_VWIN_LSB_UXGA       0x0F
 169 #define   COM1_VWIN_LSB_SVGA       0x0A
 170 #define   COM1_VWIN_LSB_CIF        0x06
 171 #define REG04       0x04 /* Register 04 */
 172 #define   REG04_DEF             0x20 /* Always set */
 173 #define   REG04_HFLIP_IMG       0x80 /* Horizontal mirror image ON/OFF */
 174 #define   REG04_VFLIP_IMG       0x40 /* Vertical flip image ON/OFF */
 175 #define   REG04_VREF_EN         0x10
 176 #define   REG04_HREF_EN         0x08
 177 #define   REG04_AEC_SET(x)      VAL_SET(x, 0x3, 0, 0)
 178 #define REG08       0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */
 179 #define COM2        0x09 /* Common control 2 */
 180 #define   COM2_SOFT_SLEEP_MODE  0x10 /* Soft sleep mode */
 181                                      /* Output drive capability */
 182 #define   COM2_OCAP_Nx_SET(N)   (((N) - 1) & 0x03) /* N = [1x .. 4x] */
 183 #define PID         0x0A /* Product ID Number MSB */
 184 #define VER         0x0B /* Product ID Number LSB */
 185 #define COM3        0x0C /* Common control 3 */
 186 #define   COM3_BAND_50H        0x04 /* 0 For Banding at 60H */
 187 #define   COM3_BAND_AUTO       0x02 /* Auto Banding */
 188 #define   COM3_SING_FR_SNAPSH  0x01 /* 0 For enable live video output after the
 189                                      * snapshot sequence*/
 190 #define AEC         0x10 /* AEC[9:2] Exposure Value */
 191 #define CLKRC       0x11 /* Internal clock */
 192 #define   CLKRC_EN             0x80
 193 #define   CLKRC_DIV_SET(x)     (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */
 194 #define COM7        0x12 /* Common control 7 */
 195 #define   COM7_SRST            0x80 /* Initiates system reset. All registers are
 196                                      * set to factory default values after which
 197                                      * the chip resumes normal operation */
 198 #define   COM7_RES_UXGA        0x00 /* Resolution selectors for UXGA */
 199 #define   COM7_RES_SVGA        0x40 /* SVGA */
 200 #define   COM7_RES_CIF         0x20 /* CIF */
 201 #define   COM7_ZOOM_EN         0x04 /* Enable Zoom mode */
 202 #define   COM7_COLOR_BAR_TEST  0x02 /* Enable Color Bar Test Pattern */
 203 #define COM8        0x13 /* Common control 8 */
 204 #define   COM8_DEF             0xC0
 205 #define   COM8_BNDF_EN         0x20 /* Banding filter ON/OFF */
 206 #define   COM8_AGC_EN          0x04 /* AGC Auto/Manual control selection */
 207 #define   COM8_AEC_EN          0x01 /* Auto/Manual Exposure control */
 208 #define COM9        0x14 /* Common control 9
 209                           * Automatic gain ceiling - maximum AGC value [7:5]*/
 210 #define   COM9_AGC_GAIN_2x     0x00 /* 000 :   2x */
 211 #define   COM9_AGC_GAIN_4x     0x20 /* 001 :   4x */
 212 #define   COM9_AGC_GAIN_8x     0x40 /* 010 :   8x */
 213 #define   COM9_AGC_GAIN_16x    0x60 /* 011 :  16x */
 214 #define   COM9_AGC_GAIN_32x    0x80 /* 100 :  32x */
 215 #define   COM9_AGC_GAIN_64x    0xA0 /* 101 :  64x */
 216 #define   COM9_AGC_GAIN_128x   0xC0 /* 110 : 128x */
 217 #define COM10       0x15 /* Common control 10 */
 218 #define   COM10_PCLK_HREF      0x20 /* PCLK output qualified by HREF */
 219 #define   COM10_PCLK_RISE      0x10 /* Data is updated at the rising edge of
 220                                      * PCLK (user can latch data at the next
 221                                      * falling edge of PCLK).
 222                                      * 0 otherwise. */
 223 #define   COM10_HREF_INV       0x08 /* Invert HREF polarity:
 224                                      * HREF negative for valid data*/
 225 #define   COM10_VSINC_INV      0x02 /* Invert VSYNC polarity */
 226 #define HSTART      0x17 /* Horizontal Window start MSB 8 bit */
 227 #define HEND        0x18 /* Horizontal Window end MSB 8 bit */
 228 #define VSTART      0x19 /* Vertical Window start MSB 8 bit */
 229 #define VEND        0x1A /* Vertical Window end MSB 8 bit */
 230 #define MIDH        0x1C /* Manufacturer ID byte - high */
 231 #define MIDL        0x1D /* Manufacturer ID byte - low  */
 232 #define AEW         0x24 /* AGC/AEC - Stable operating region (upper limit) */
 233 #define AEB         0x25 /* AGC/AEC - Stable operating region (lower limit) */
 234 #define VV          0x26 /* AGC/AEC Fast mode operating region */
 235 #define   VV_HIGH_TH_SET(x)      VAL_SET(x, 0xF, 0, 4)
 236 #define   VV_LOW_TH_SET(x)       VAL_SET(x, 0xF, 0, 0)
 237 #define REG2A       0x2A /* Dummy pixel insert MSB */
 238 #define FRARL       0x2B /* Dummy pixel insert LSB */
 239 #define ADDVFL      0x2D /* LSB of insert dummy lines in Vertical direction */
 240 #define ADDVFH      0x2E /* MSB of insert dummy lines in Vertical direction */
 241 #define YAVG        0x2F /* Y/G Channel Average value */
 242 #define REG32       0x32 /* Common Control 32 */
 243 #define   REG32_PCLK_DIV_2    0x80 /* PCLK freq divided by 2 */
 244 #define   REG32_PCLK_DIV_4    0xC0 /* PCLK freq divided by 4 */
 245 #define ARCOM2      0x34 /* Zoom: Horizontal start point */
 246 #define REG45       0x45 /* Register 45 */
 247 #define FLL         0x46 /* Frame Length Adjustment LSBs */
 248 #define FLH         0x47 /* Frame Length Adjustment MSBs */
 249 #define COM19       0x48 /* Zoom: Vertical start point */
 250 #define ZOOMS       0x49 /* Zoom: Vertical start point */
 251 #define COM22       0x4B /* Flash light control */
 252 #define COM25       0x4E /* For Banding operations */
 253 #define   COM25_50HZ_BANDING_AEC_MSBS_MASK      0xC0 /* 50Hz Bd. AEC 2 MSBs */
 254 #define   COM25_60HZ_BANDING_AEC_MSBS_MASK      0x30 /* 60Hz Bd. AEC 2 MSBs */
 255 #define   COM25_50HZ_BANDING_AEC_MSBS_SET(x)    VAL_SET(x, 0x3, 8, 6)
 256 #define   COM25_60HZ_BANDING_AEC_MSBS_SET(x)    VAL_SET(x, 0x3, 8, 4)
 257 #define BD50        0x4F /* 50Hz Banding AEC 8 LSBs */
 258 #define   BD50_50HZ_BANDING_AEC_LSBS_SET(x)     VAL_SET(x, 0xFF, 0, 0)
 259 #define BD60        0x50 /* 60Hz Banding AEC 8 LSBs */
 260 #define   BD60_60HZ_BANDING_AEC_LSBS_SET(x)     VAL_SET(x, 0xFF, 0, 0)
 261 #define REG5A       0x5A /* 50/60Hz Banding Maximum AEC Step */
 262 #define   BD50_MAX_AEC_STEP_MASK         0xF0 /* 50Hz Banding Max. AEC Step */
 263 #define   BD60_MAX_AEC_STEP_MASK         0x0F /* 60Hz Banding Max. AEC Step */
 264 #define   BD50_MAX_AEC_STEP_SET(x)       VAL_SET((x - 1), 0x0F, 0, 4)
 265 #define   BD60_MAX_AEC_STEP_SET(x)       VAL_SET((x - 1), 0x0F, 0, 0)
 266 #define REG5D       0x5D /* AVGsel[7:0],   16-zone average weight option */
 267 #define REG5E       0x5E /* AVGsel[15:8],  16-zone average weight option */
 268 #define REG5F       0x5F /* AVGsel[23:16], 16-zone average weight option */
 269 #define REG60       0x60 /* AVGsel[31:24], 16-zone average weight option */
 270 #define HISTO_LOW   0x61 /* Histogram Algorithm Low Level */
 271 #define HISTO_HIGH  0x62 /* Histogram Algorithm High Level */
 272 
 273 /*
 274  * ID
 275  */
 276 #define MANUFACTURER_ID 0x7FA2
 277 #define PID_OV2640      0x2642
 278 #define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF))
 279 
 280 /*
 281  * Struct
 282  */
 283 struct regval_list {
 284         u8 reg_num;
 285         u8 value;
 286 };
 287 
 288 struct ov2640_win_size {
 289         char                            *name;
 290         u32                             width;
 291         u32                             height;
 292         const struct regval_list        *regs;
 293 };
 294 
 295 
 296 struct ov2640_priv {
 297         struct v4l2_subdev              subdev;
 298 #if defined(CONFIG_MEDIA_CONTROLLER)
 299         struct media_pad pad;
 300 #endif
 301         struct v4l2_ctrl_handler        hdl;
 302         u32     cfmt_code;
 303         struct clk                      *clk;
 304         const struct ov2640_win_size    *win;
 305 
 306         struct gpio_desc *resetb_gpio;
 307         struct gpio_desc *pwdn_gpio;
 308 
 309         struct mutex lock; /* lock to protect streaming and power_count */
 310         bool streaming;
 311         int power_count;
 312 };
 313 
 314 /*
 315  * Registers settings
 316  */
 317 
 318 #define ENDMARKER { 0xff, 0xff }
 319 
 320 static const struct regval_list ov2640_init_regs[] = {
 321         { BANK_SEL, BANK_SEL_DSP },
 322         { 0x2c,   0xff },
 323         { 0x2e,   0xdf },
 324         { BANK_SEL, BANK_SEL_SENS },
 325         { 0x3c,   0x32 },
 326         { CLKRC,  CLKRC_DIV_SET(1) },
 327         { COM2,   COM2_OCAP_Nx_SET(3) },
 328         { REG04,  REG04_DEF | REG04_HREF_EN },
 329         { COM8,   COM8_DEF | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN },
 330         { COM9,   COM9_AGC_GAIN_8x | 0x08},
 331         { 0x2c,   0x0c },
 332         { 0x33,   0x78 },
 333         { 0x3a,   0x33 },
 334         { 0x3b,   0xfb },
 335         { 0x3e,   0x00 },
 336         { 0x43,   0x11 },
 337         { 0x16,   0x10 },
 338         { 0x39,   0x02 },
 339         { 0x35,   0x88 },
 340         { 0x22,   0x0a },
 341         { 0x37,   0x40 },
 342         { 0x23,   0x00 },
 343         { ARCOM2, 0xa0 },
 344         { 0x06,   0x02 },
 345         { 0x06,   0x88 },
 346         { 0x07,   0xc0 },
 347         { 0x0d,   0xb7 },
 348         { 0x0e,   0x01 },
 349         { 0x4c,   0x00 },
 350         { 0x4a,   0x81 },
 351         { 0x21,   0x99 },
 352         { AEW,    0x40 },
 353         { AEB,    0x38 },
 354         { VV,     VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) },
 355         { 0x5c,   0x00 },
 356         { 0x63,   0x00 },
 357         { FLL,    0x22 },
 358         { COM3,   0x38 | COM3_BAND_AUTO },
 359         { REG5D,  0x55 },
 360         { REG5E,  0x7d },
 361         { REG5F,  0x7d },
 362         { REG60,  0x55 },
 363         { HISTO_LOW,   0x70 },
 364         { HISTO_HIGH,  0x80 },
 365         { 0x7c,   0x05 },
 366         { 0x20,   0x80 },
 367         { 0x28,   0x30 },
 368         { 0x6c,   0x00 },
 369         { 0x6d,   0x80 },
 370         { 0x6e,   0x00 },
 371         { 0x70,   0x02 },
 372         { 0x71,   0x94 },
 373         { 0x73,   0xc1 },
 374         { 0x3d,   0x34 },
 375         { COM7,   COM7_RES_UXGA | COM7_ZOOM_EN },
 376         { REG5A,  BD50_MAX_AEC_STEP_SET(6)
 377                    | BD60_MAX_AEC_STEP_SET(8) },                /* 0x57 */
 378         { COM25,  COM25_50HZ_BANDING_AEC_MSBS_SET(0x0bb)
 379                    | COM25_60HZ_BANDING_AEC_MSBS_SET(0x09c) },  /* 0x00 */
 380         { BD50,   BD50_50HZ_BANDING_AEC_LSBS_SET(0x0bb) },      /* 0xbb */
 381         { BD60,   BD60_60HZ_BANDING_AEC_LSBS_SET(0x09c) },      /* 0x9c */
 382         { BANK_SEL,  BANK_SEL_DSP },
 383         { 0xe5,   0x7f },
 384         { MC_BIST,  MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL },
 385         { 0x41,   0x24 },
 386         { RESET,  RESET_JPEG | RESET_DVP },
 387         { 0x76,   0xff },
 388         { 0x33,   0xa0 },
 389         { 0x42,   0x20 },
 390         { 0x43,   0x18 },
 391         { 0x4c,   0x00 },
 392         { CTRL3,  CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
 393         { 0x88,   0x3f },
 394         { 0xd7,   0x03 },
 395         { 0xd9,   0x10 },
 396         { R_DVP_SP,  R_DVP_SP_AUTO_MODE | 0x2 },
 397         { 0xc8,   0x08 },
 398         { 0xc9,   0x80 },
 399         { BPADDR, 0x00 },
 400         { BPDATA, 0x00 },
 401         { BPADDR, 0x03 },
 402         { BPDATA, 0x48 },
 403         { BPDATA, 0x48 },
 404         { BPADDR, 0x08 },
 405         { BPDATA, 0x20 },
 406         { BPDATA, 0x10 },
 407         { BPDATA, 0x0e },
 408         { 0x90,   0x00 },
 409         { 0x91,   0x0e },
 410         { 0x91,   0x1a },
 411         { 0x91,   0x31 },
 412         { 0x91,   0x5a },
 413         { 0x91,   0x69 },
 414         { 0x91,   0x75 },
 415         { 0x91,   0x7e },
 416         { 0x91,   0x88 },
 417         { 0x91,   0x8f },
 418         { 0x91,   0x96 },
 419         { 0x91,   0xa3 },
 420         { 0x91,   0xaf },
 421         { 0x91,   0xc4 },
 422         { 0x91,   0xd7 },
 423         { 0x91,   0xe8 },
 424         { 0x91,   0x20 },
 425         { 0x92,   0x00 },
 426         { 0x93,   0x06 },
 427         { 0x93,   0xe3 },
 428         { 0x93,   0x03 },
 429         { 0x93,   0x03 },
 430         { 0x93,   0x00 },
 431         { 0x93,   0x02 },
 432         { 0x93,   0x00 },
 433         { 0x93,   0x00 },
 434         { 0x93,   0x00 },
 435         { 0x93,   0x00 },
 436         { 0x93,   0x00 },
 437         { 0x93,   0x00 },
 438         { 0x93,   0x00 },
 439         { 0x96,   0x00 },
 440         { 0x97,   0x08 },
 441         { 0x97,   0x19 },
 442         { 0x97,   0x02 },
 443         { 0x97,   0x0c },
 444         { 0x97,   0x24 },
 445         { 0x97,   0x30 },
 446         { 0x97,   0x28 },
 447         { 0x97,   0x26 },
 448         { 0x97,   0x02 },
 449         { 0x97,   0x98 },
 450         { 0x97,   0x80 },
 451         { 0x97,   0x00 },
 452         { 0x97,   0x00 },
 453         { 0xa4,   0x00 },
 454         { 0xa8,   0x00 },
 455         { 0xc5,   0x11 },
 456         { 0xc6,   0x51 },
 457         { 0xbf,   0x80 },
 458         { 0xc7,   0x10 },       /* simple AWB */
 459         { 0xb6,   0x66 },
 460         { 0xb8,   0xA5 },
 461         { 0xb7,   0x64 },
 462         { 0xb9,   0x7C },
 463         { 0xb3,   0xaf },
 464         { 0xb4,   0x97 },
 465         { 0xb5,   0xFF },
 466         { 0xb0,   0xC5 },
 467         { 0xb1,   0x94 },
 468         { 0xb2,   0x0f },
 469         { 0xc4,   0x5c },
 470         { 0xa6,   0x00 },
 471         { 0xa7,   0x20 },
 472         { 0xa7,   0xd8 },
 473         { 0xa7,   0x1b },
 474         { 0xa7,   0x31 },
 475         { 0xa7,   0x00 },
 476         { 0xa7,   0x18 },
 477         { 0xa7,   0x20 },
 478         { 0xa7,   0xd8 },
 479         { 0xa7,   0x19 },
 480         { 0xa7,   0x31 },
 481         { 0xa7,   0x00 },
 482         { 0xa7,   0x18 },
 483         { 0xa7,   0x20 },
 484         { 0xa7,   0xd8 },
 485         { 0xa7,   0x19 },
 486         { 0xa7,   0x31 },
 487         { 0xa7,   0x00 },
 488         { 0xa7,   0x18 },
 489         { 0x7f,   0x00 },
 490         { 0xe5,   0x1f },
 491         { 0xe1,   0x77 },
 492         { 0xdd,   0x7f },
 493         { CTRL0,  CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN },
 494         ENDMARKER,
 495 };
 496 
 497 /*
 498  * Register settings for window size
 499  * The preamble, setup the internal DSP to input an UXGA (1600x1200) image.
 500  * Then the different zooming configurations will setup the output image size.
 501  */
 502 static const struct regval_list ov2640_size_change_preamble_regs[] = {
 503         { BANK_SEL, BANK_SEL_DSP },
 504         { RESET, RESET_DVP },
 505         { SIZEL, SIZEL_HSIZE8_11_SET(UXGA_WIDTH) |
 506                  SIZEL_HSIZE8_SET(UXGA_WIDTH) |
 507                  SIZEL_VSIZE8_SET(UXGA_HEIGHT) },
 508         { HSIZE8, HSIZE8_SET(UXGA_WIDTH) },
 509         { VSIZE8, VSIZE8_SET(UXGA_HEIGHT) },
 510         { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
 511                  CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
 512         { HSIZE, HSIZE_SET(UXGA_WIDTH) },
 513         { VSIZE, VSIZE_SET(UXGA_HEIGHT) },
 514         { XOFFL, XOFFL_SET(0) },
 515         { YOFFL, YOFFL_SET(0) },
 516         { VHYX, VHYX_HSIZE_SET(UXGA_WIDTH) | VHYX_VSIZE_SET(UXGA_HEIGHT) |
 517                 VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)},
 518         { TEST, TEST_HSIZE_SET(UXGA_WIDTH) },
 519         ENDMARKER,
 520 };
 521 
 522 #define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div)  \
 523         { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \
 524                  CTRLI_H_DIV_SET(h_div)},               \
 525         { ZMOW, ZMOW_OUTW_SET(x) },                     \
 526         { ZMOH, ZMOH_OUTH_SET(y) },                     \
 527         { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) },  \
 528         { R_DVP_SP, pclk_div },                         \
 529         { RESET, 0x00}
 530 
 531 static const struct regval_list ov2640_qcif_regs[] = {
 532         PER_SIZE_REG_SEQ(QCIF_WIDTH, QCIF_HEIGHT, 3, 3, 4),
 533         ENDMARKER,
 534 };
 535 
 536 static const struct regval_list ov2640_qvga_regs[] = {
 537         PER_SIZE_REG_SEQ(QVGA_WIDTH, QVGA_HEIGHT, 2, 2, 4),
 538         ENDMARKER,
 539 };
 540 
 541 static const struct regval_list ov2640_cif_regs[] = {
 542         PER_SIZE_REG_SEQ(CIF_WIDTH, CIF_HEIGHT, 2, 2, 8),
 543         ENDMARKER,
 544 };
 545 
 546 static const struct regval_list ov2640_vga_regs[] = {
 547         PER_SIZE_REG_SEQ(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2),
 548         ENDMARKER,
 549 };
 550 
 551 static const struct regval_list ov2640_svga_regs[] = {
 552         PER_SIZE_REG_SEQ(SVGA_WIDTH, SVGA_HEIGHT, 1, 1, 2),
 553         ENDMARKER,
 554 };
 555 
 556 static const struct regval_list ov2640_xga_regs[] = {
 557         PER_SIZE_REG_SEQ(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2),
 558         { CTRLI,    0x00},
 559         ENDMARKER,
 560 };
 561 
 562 static const struct regval_list ov2640_sxga_regs[] = {
 563         PER_SIZE_REG_SEQ(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2),
 564         { CTRLI,    0x00},
 565         { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE },
 566         ENDMARKER,
 567 };
 568 
 569 static const struct regval_list ov2640_uxga_regs[] = {
 570         PER_SIZE_REG_SEQ(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0),
 571         { CTRLI,    0x00},
 572         { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE },
 573         ENDMARKER,
 574 };
 575 
 576 #define OV2640_SIZE(n, w, h, r) \
 577         {.name = n, .width = w , .height = h, .regs = r }
 578 
 579 static const struct ov2640_win_size ov2640_supported_win_sizes[] = {
 580         OV2640_SIZE("QCIF", QCIF_WIDTH, QCIF_HEIGHT, ov2640_qcif_regs),
 581         OV2640_SIZE("QVGA", QVGA_WIDTH, QVGA_HEIGHT, ov2640_qvga_regs),
 582         OV2640_SIZE("CIF", CIF_WIDTH, CIF_HEIGHT, ov2640_cif_regs),
 583         OV2640_SIZE("VGA", VGA_WIDTH, VGA_HEIGHT, ov2640_vga_regs),
 584         OV2640_SIZE("SVGA", SVGA_WIDTH, SVGA_HEIGHT, ov2640_svga_regs),
 585         OV2640_SIZE("XGA", XGA_WIDTH, XGA_HEIGHT, ov2640_xga_regs),
 586         OV2640_SIZE("SXGA", SXGA_WIDTH, SXGA_HEIGHT, ov2640_sxga_regs),
 587         OV2640_SIZE("UXGA", UXGA_WIDTH, UXGA_HEIGHT, ov2640_uxga_regs),
 588 };
 589 
 590 /*
 591  * Register settings for pixel formats
 592  */
 593 static const struct regval_list ov2640_format_change_preamble_regs[] = {
 594         { BANK_SEL, BANK_SEL_DSP },
 595         { R_BYPASS, R_BYPASS_USE_DSP },
 596         ENDMARKER,
 597 };
 598 
 599 static const struct regval_list ov2640_yuyv_regs[] = {
 600         { IMAGE_MODE, IMAGE_MODE_YUV422 },
 601         { 0xd7, 0x03 },
 602         { 0x33, 0xa0 },
 603         { 0xe5, 0x1f },
 604         { 0xe1, 0x67 },
 605         { RESET,  0x00 },
 606         { R_BYPASS, R_BYPASS_USE_DSP },
 607         ENDMARKER,
 608 };
 609 
 610 static const struct regval_list ov2640_uyvy_regs[] = {
 611         { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 },
 612         { 0xd7, 0x01 },
 613         { 0x33, 0xa0 },
 614         { 0xe1, 0x67 },
 615         { RESET,  0x00 },
 616         { R_BYPASS, R_BYPASS_USE_DSP },
 617         ENDMARKER,
 618 };
 619 
 620 static const struct regval_list ov2640_rgb565_be_regs[] = {
 621         { IMAGE_MODE, IMAGE_MODE_RGB565 },
 622         { 0xd7, 0x03 },
 623         { RESET,  0x00 },
 624         { R_BYPASS, R_BYPASS_USE_DSP },
 625         ENDMARKER,
 626 };
 627 
 628 static const struct regval_list ov2640_rgb565_le_regs[] = {
 629         { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 },
 630         { 0xd7, 0x03 },
 631         { RESET,  0x00 },
 632         { R_BYPASS, R_BYPASS_USE_DSP },
 633         ENDMARKER,
 634 };
 635 
 636 static u32 ov2640_codes[] = {
 637         MEDIA_BUS_FMT_YUYV8_2X8,
 638         MEDIA_BUS_FMT_UYVY8_2X8,
 639         MEDIA_BUS_FMT_YVYU8_2X8,
 640         MEDIA_BUS_FMT_VYUY8_2X8,
 641         MEDIA_BUS_FMT_RGB565_2X8_BE,
 642         MEDIA_BUS_FMT_RGB565_2X8_LE,
 643 };
 644 
 645 /*
 646  * General functions
 647  */
 648 static struct ov2640_priv *to_ov2640(const struct i2c_client *client)
 649 {
 650         return container_of(i2c_get_clientdata(client), struct ov2640_priv,
 651                             subdev);
 652 }
 653 
 654 static int ov2640_write_array(struct i2c_client *client,
 655                               const struct regval_list *vals)
 656 {
 657         int ret;
 658 
 659         while ((vals->reg_num != 0xff) || (vals->value != 0xff)) {
 660                 ret = i2c_smbus_write_byte_data(client,
 661                                                 vals->reg_num, vals->value);
 662                 dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x",
 663                          vals->reg_num, vals->value);
 664 
 665                 if (ret < 0)
 666                         return ret;
 667                 vals++;
 668         }
 669         return 0;
 670 }
 671 
 672 static int ov2640_mask_set(struct i2c_client *client,
 673                            u8  reg, u8  mask, u8  set)
 674 {
 675         s32 val = i2c_smbus_read_byte_data(client, reg);
 676         if (val < 0)
 677                 return val;
 678 
 679         val &= ~mask;
 680         val |= set & mask;
 681 
 682         dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val);
 683 
 684         return i2c_smbus_write_byte_data(client, reg, val);
 685 }
 686 
 687 static int ov2640_reset(struct i2c_client *client)
 688 {
 689         int ret;
 690         static const struct regval_list reset_seq[] = {
 691                 {BANK_SEL, BANK_SEL_SENS},
 692                 {COM7, COM7_SRST},
 693                 ENDMARKER,
 694         };
 695 
 696         ret = ov2640_write_array(client, reset_seq);
 697         if (ret)
 698                 goto err;
 699 
 700         msleep(5);
 701 err:
 702         dev_dbg(&client->dev, "%s: (ret %d)", __func__, ret);
 703         return ret;
 704 }
 705 
 706 static const char * const ov2640_test_pattern_menu[] = {
 707         "Disabled",
 708         "Eight Vertical Colour Bars",
 709 };
 710 
 711 /*
 712  * functions
 713  */
 714 static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl)
 715 {
 716         struct v4l2_subdev *sd =
 717                 &container_of(ctrl->handler, struct ov2640_priv, hdl)->subdev;
 718         struct i2c_client  *client = v4l2_get_subdevdata(sd);
 719         struct ov2640_priv *priv = to_ov2640(client);
 720         u8 val;
 721         int ret;
 722 
 723         /* v4l2_ctrl_lock() locks our own mutex */
 724 
 725         /*
 726          * If the device is not powered up by the host driver, do not apply any
 727          * controls to H/W at this time. Instead the controls will be restored
 728          * when the streaming is started.
 729          */
 730         if (!priv->power_count)
 731                 return 0;
 732 
 733         ret = i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
 734         if (ret < 0)
 735                 return ret;
 736 
 737         switch (ctrl->id) {
 738         case V4L2_CID_VFLIP:
 739                 val = ctrl->val ? REG04_VFLIP_IMG | REG04_VREF_EN : 0x00;
 740                 return ov2640_mask_set(client, REG04,
 741                                        REG04_VFLIP_IMG | REG04_VREF_EN, val);
 742                 /* NOTE: REG04_VREF_EN: 1 line shift / even/odd line swap */
 743         case V4L2_CID_HFLIP:
 744                 val = ctrl->val ? REG04_HFLIP_IMG : 0x00;
 745                 return ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val);
 746         case V4L2_CID_TEST_PATTERN:
 747                 val = ctrl->val ? COM7_COLOR_BAR_TEST : 0x00;
 748                 return ov2640_mask_set(client, COM7, COM7_COLOR_BAR_TEST, val);
 749         }
 750 
 751         return -EINVAL;
 752 }
 753 
 754 #ifdef CONFIG_VIDEO_ADV_DEBUG
 755 static int ov2640_g_register(struct v4l2_subdev *sd,
 756                              struct v4l2_dbg_register *reg)
 757 {
 758         struct i2c_client *client = v4l2_get_subdevdata(sd);
 759         int ret;
 760 
 761         reg->size = 1;
 762         if (reg->reg > 0xff)
 763                 return -EINVAL;
 764 
 765         ret = i2c_smbus_read_byte_data(client, reg->reg);
 766         if (ret < 0)
 767                 return ret;
 768 
 769         reg->val = ret;
 770 
 771         return 0;
 772 }
 773 
 774 static int ov2640_s_register(struct v4l2_subdev *sd,
 775                              const struct v4l2_dbg_register *reg)
 776 {
 777         struct i2c_client *client = v4l2_get_subdevdata(sd);
 778 
 779         if (reg->reg > 0xff ||
 780             reg->val > 0xff)
 781                 return -EINVAL;
 782 
 783         return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
 784 }
 785 #endif
 786 
 787 static void ov2640_set_power(struct ov2640_priv *priv, int on)
 788 {
 789 #ifdef CONFIG_GPIOLIB
 790         if (priv->pwdn_gpio)
 791                 gpiod_direction_output(priv->pwdn_gpio, !on);
 792         if (on && priv->resetb_gpio) {
 793                 /* Active the resetb pin to perform a reset pulse */
 794                 gpiod_direction_output(priv->resetb_gpio, 1);
 795                 usleep_range(3000, 5000);
 796                 gpiod_set_value(priv->resetb_gpio, 0);
 797         }
 798 #endif
 799 }
 800 
 801 static int ov2640_s_power(struct v4l2_subdev *sd, int on)
 802 {
 803         struct i2c_client *client = v4l2_get_subdevdata(sd);
 804         struct ov2640_priv *priv = to_ov2640(client);
 805 
 806         mutex_lock(&priv->lock);
 807 
 808         /*
 809          * If the power count is modified from 0 to != 0 or from != 0 to 0,
 810          * update the power state.
 811          */
 812         if (priv->power_count == !on)
 813                 ov2640_set_power(priv, on);
 814         priv->power_count += on ? 1 : -1;
 815         WARN_ON(priv->power_count < 0);
 816         mutex_unlock(&priv->lock);
 817 
 818         return 0;
 819 }
 820 
 821 /* Select the nearest higher resolution for capture */
 822 static const struct ov2640_win_size *ov2640_select_win(u32 width, u32 height)
 823 {
 824         int i, default_size = ARRAY_SIZE(ov2640_supported_win_sizes) - 1;
 825 
 826         for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) {
 827                 if (ov2640_supported_win_sizes[i].width  >= width &&
 828                     ov2640_supported_win_sizes[i].height >= height)
 829                         return &ov2640_supported_win_sizes[i];
 830         }
 831 
 832         return &ov2640_supported_win_sizes[default_size];
 833 }
 834 
 835 static int ov2640_set_params(struct i2c_client *client,
 836                              const struct ov2640_win_size *win, u32 code)
 837 {
 838         const struct regval_list *selected_cfmt_regs;
 839         u8 val;
 840         int ret;
 841 
 842         switch (code) {
 843         case MEDIA_BUS_FMT_RGB565_2X8_BE:
 844                 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 BE", __func__);
 845                 selected_cfmt_regs = ov2640_rgb565_be_regs;
 846                 break;
 847         case MEDIA_BUS_FMT_RGB565_2X8_LE:
 848                 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 LE", __func__);
 849                 selected_cfmt_regs = ov2640_rgb565_le_regs;
 850                 break;
 851         case MEDIA_BUS_FMT_YUYV8_2X8:
 852                 dev_dbg(&client->dev, "%s: Selected cfmt YUYV (YUV422)", __func__);
 853                 selected_cfmt_regs = ov2640_yuyv_regs;
 854                 break;
 855         case MEDIA_BUS_FMT_UYVY8_2X8:
 856         default:
 857                 dev_dbg(&client->dev, "%s: Selected cfmt UYVY", __func__);
 858                 selected_cfmt_regs = ov2640_uyvy_regs;
 859                 break;
 860         case MEDIA_BUS_FMT_YVYU8_2X8:
 861                 dev_dbg(&client->dev, "%s: Selected cfmt YVYU", __func__);
 862                 selected_cfmt_regs = ov2640_yuyv_regs;
 863                 break;
 864         case MEDIA_BUS_FMT_VYUY8_2X8:
 865                 dev_dbg(&client->dev, "%s: Selected cfmt VYUY", __func__);
 866                 selected_cfmt_regs = ov2640_uyvy_regs;
 867                 break;
 868         }
 869 
 870         /* reset hardware */
 871         ov2640_reset(client);
 872 
 873         /* initialize the sensor with default data */
 874         dev_dbg(&client->dev, "%s: Init default", __func__);
 875         ret = ov2640_write_array(client, ov2640_init_regs);
 876         if (ret < 0)
 877                 goto err;
 878 
 879         /* select preamble */
 880         dev_dbg(&client->dev, "%s: Set size to %s", __func__, win->name);
 881         ret = ov2640_write_array(client, ov2640_size_change_preamble_regs);
 882         if (ret < 0)
 883                 goto err;
 884 
 885         /* set size win */
 886         ret = ov2640_write_array(client, win->regs);
 887         if (ret < 0)
 888                 goto err;
 889 
 890         /* cfmt preamble */
 891         dev_dbg(&client->dev, "%s: Set cfmt", __func__);
 892         ret = ov2640_write_array(client, ov2640_format_change_preamble_regs);
 893         if (ret < 0)
 894                 goto err;
 895 
 896         /* set cfmt */
 897         ret = ov2640_write_array(client, selected_cfmt_regs);
 898         if (ret < 0)
 899                 goto err;
 900         val = (code == MEDIA_BUS_FMT_YVYU8_2X8)
 901               || (code == MEDIA_BUS_FMT_VYUY8_2X8) ? CTRL0_VFIRST : 0x00;
 902         ret = ov2640_mask_set(client, CTRL0, CTRL0_VFIRST, val);
 903         if (ret < 0)
 904                 goto err;
 905 
 906         return 0;
 907 
 908 err:
 909         dev_err(&client->dev, "%s: Error %d", __func__, ret);
 910         ov2640_reset(client);
 911 
 912         return ret;
 913 }
 914 
 915 static int ov2640_get_fmt(struct v4l2_subdev *sd,
 916                 struct v4l2_subdev_pad_config *cfg,
 917                 struct v4l2_subdev_format *format)
 918 {
 919         struct v4l2_mbus_framefmt *mf = &format->format;
 920         struct i2c_client  *client = v4l2_get_subdevdata(sd);
 921         struct ov2640_priv *priv = to_ov2640(client);
 922 
 923         if (format->pad)
 924                 return -EINVAL;
 925 
 926         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
 927 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
 928                 mf = v4l2_subdev_get_try_format(sd, cfg, 0);
 929                 format->format = *mf;
 930                 return 0;
 931 #else
 932                 return -EINVAL;
 933 #endif
 934         }
 935 
 936         mf->width       = priv->win->width;
 937         mf->height      = priv->win->height;
 938         mf->code        = priv->cfmt_code;
 939         mf->colorspace  = V4L2_COLORSPACE_SRGB;
 940         mf->field       = V4L2_FIELD_NONE;
 941         mf->ycbcr_enc   = V4L2_YCBCR_ENC_DEFAULT;
 942         mf->quantization = V4L2_QUANTIZATION_DEFAULT;
 943         mf->xfer_func   = V4L2_XFER_FUNC_DEFAULT;
 944 
 945         return 0;
 946 }
 947 
 948 static int ov2640_set_fmt(struct v4l2_subdev *sd,
 949                 struct v4l2_subdev_pad_config *cfg,
 950                 struct v4l2_subdev_format *format)
 951 {
 952         struct v4l2_mbus_framefmt *mf = &format->format;
 953         struct i2c_client *client = v4l2_get_subdevdata(sd);
 954         struct ov2640_priv *priv = to_ov2640(client);
 955         const struct ov2640_win_size *win;
 956         int ret = 0;
 957 
 958         if (format->pad)
 959                 return -EINVAL;
 960 
 961         mutex_lock(&priv->lock);
 962 
 963         /* select suitable win */
 964         win = ov2640_select_win(mf->width, mf->height);
 965         mf->width       = win->width;
 966         mf->height      = win->height;
 967 
 968         mf->field       = V4L2_FIELD_NONE;
 969         mf->colorspace  = V4L2_COLORSPACE_SRGB;
 970         mf->ycbcr_enc   = V4L2_YCBCR_ENC_DEFAULT;
 971         mf->quantization = V4L2_QUANTIZATION_DEFAULT;
 972         mf->xfer_func   = V4L2_XFER_FUNC_DEFAULT;
 973 
 974         switch (mf->code) {
 975         case MEDIA_BUS_FMT_RGB565_2X8_BE:
 976         case MEDIA_BUS_FMT_RGB565_2X8_LE:
 977         case MEDIA_BUS_FMT_YUYV8_2X8:
 978         case MEDIA_BUS_FMT_UYVY8_2X8:
 979         case MEDIA_BUS_FMT_YVYU8_2X8:
 980         case MEDIA_BUS_FMT_VYUY8_2X8:
 981                 break;
 982         default:
 983                 mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
 984                 break;
 985         }
 986 
 987         if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
 988                 struct ov2640_priv *priv = to_ov2640(client);
 989 
 990                 if (priv->streaming) {
 991                         ret = -EBUSY;
 992                         goto out;
 993                 }
 994                 /* select win */
 995                 priv->win = win;
 996                 /* select format */
 997                 priv->cfmt_code = mf->code;
 998         } else {
 999                 cfg->try_fmt = *mf;
1000         }
1001 out:
1002         mutex_unlock(&priv->lock);
1003 
1004         return ret;
1005 }
1006 
1007 static int ov2640_init_cfg(struct v4l2_subdev *sd,
1008                            struct v4l2_subdev_pad_config *cfg)
1009 {
1010 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1011         struct v4l2_mbus_framefmt *try_fmt =
1012                 v4l2_subdev_get_try_format(sd, cfg, 0);
1013         const struct ov2640_win_size *win =
1014                 ov2640_select_win(SVGA_WIDTH, SVGA_HEIGHT);
1015 
1016         try_fmt->width = win->width;
1017         try_fmt->height = win->height;
1018         try_fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
1019         try_fmt->colorspace = V4L2_COLORSPACE_SRGB;
1020         try_fmt->field = V4L2_FIELD_NONE;
1021         try_fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
1022         try_fmt->quantization = V4L2_QUANTIZATION_DEFAULT;
1023         try_fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
1024 #endif
1025         return 0;
1026 }
1027 
1028 static int ov2640_enum_mbus_code(struct v4l2_subdev *sd,
1029                 struct v4l2_subdev_pad_config *cfg,
1030                 struct v4l2_subdev_mbus_code_enum *code)
1031 {
1032         if (code->pad || code->index >= ARRAY_SIZE(ov2640_codes))
1033                 return -EINVAL;
1034 
1035         code->code = ov2640_codes[code->index];
1036         return 0;
1037 }
1038 
1039 static int ov2640_get_selection(struct v4l2_subdev *sd,
1040                 struct v4l2_subdev_pad_config *cfg,
1041                 struct v4l2_subdev_selection *sel)
1042 {
1043         if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1044                 return -EINVAL;
1045 
1046         switch (sel->target) {
1047         case V4L2_SEL_TGT_CROP_BOUNDS:
1048         case V4L2_SEL_TGT_CROP:
1049                 sel->r.left = 0;
1050                 sel->r.top = 0;
1051                 sel->r.width = UXGA_WIDTH;
1052                 sel->r.height = UXGA_HEIGHT;
1053                 return 0;
1054         default:
1055                 return -EINVAL;
1056         }
1057 }
1058 
1059 static int ov2640_s_stream(struct v4l2_subdev *sd, int on)
1060 {
1061         struct i2c_client *client = v4l2_get_subdevdata(sd);
1062         struct ov2640_priv *priv = to_ov2640(client);
1063         int ret = 0;
1064 
1065         mutex_lock(&priv->lock);
1066         if (priv->streaming == !on) {
1067                 if (on) {
1068                         ret = ov2640_set_params(client, priv->win,
1069                                                 priv->cfmt_code);
1070                         if (!ret)
1071                                 ret = __v4l2_ctrl_handler_setup(&priv->hdl);
1072                 }
1073         }
1074         if (!ret)
1075                 priv->streaming = on;
1076         mutex_unlock(&priv->lock);
1077 
1078         return ret;
1079 }
1080 
1081 static int ov2640_video_probe(struct i2c_client *client)
1082 {
1083         struct ov2640_priv *priv = to_ov2640(client);
1084         u8 pid, ver, midh, midl;
1085         const char *devname;
1086         int ret;
1087 
1088         ret = ov2640_s_power(&priv->subdev, 1);
1089         if (ret < 0)
1090                 return ret;
1091 
1092         /*
1093          * check and show product ID and manufacturer ID
1094          */
1095         i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
1096         pid  = i2c_smbus_read_byte_data(client, PID);
1097         ver  = i2c_smbus_read_byte_data(client, VER);
1098         midh = i2c_smbus_read_byte_data(client, MIDH);
1099         midl = i2c_smbus_read_byte_data(client, MIDL);
1100 
1101         switch (VERSION(pid, ver)) {
1102         case PID_OV2640:
1103                 devname     = "ov2640";
1104                 break;
1105         default:
1106                 dev_err(&client->dev,
1107                         "Product ID error %x:%x\n", pid, ver);
1108                 ret = -ENODEV;
1109                 goto done;
1110         }
1111 
1112         dev_info(&client->dev,
1113                  "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
1114                  devname, pid, ver, midh, midl);
1115 
1116 done:
1117         ov2640_s_power(&priv->subdev, 0);
1118         return ret;
1119 }
1120 
1121 static const struct v4l2_ctrl_ops ov2640_ctrl_ops = {
1122         .s_ctrl = ov2640_s_ctrl,
1123 };
1124 
1125 static const struct v4l2_subdev_core_ops ov2640_subdev_core_ops = {
1126         .log_status = v4l2_ctrl_subdev_log_status,
1127         .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1128         .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1129 #ifdef CONFIG_VIDEO_ADV_DEBUG
1130         .g_register     = ov2640_g_register,
1131         .s_register     = ov2640_s_register,
1132 #endif
1133         .s_power        = ov2640_s_power,
1134 };
1135 
1136 static const struct v4l2_subdev_pad_ops ov2640_subdev_pad_ops = {
1137         .init_cfg       = ov2640_init_cfg,
1138         .enum_mbus_code = ov2640_enum_mbus_code,
1139         .get_selection  = ov2640_get_selection,
1140         .get_fmt        = ov2640_get_fmt,
1141         .set_fmt        = ov2640_set_fmt,
1142 };
1143 
1144 static const struct v4l2_subdev_video_ops ov2640_subdev_video_ops = {
1145         .s_stream = ov2640_s_stream,
1146 };
1147 
1148 static const struct v4l2_subdev_ops ov2640_subdev_ops = {
1149         .core   = &ov2640_subdev_core_ops,
1150         .pad    = &ov2640_subdev_pad_ops,
1151         .video  = &ov2640_subdev_video_ops,
1152 };
1153 
1154 static int ov2640_probe_dt(struct i2c_client *client,
1155                 struct ov2640_priv *priv)
1156 {
1157         int ret;
1158 
1159         /* Request the reset GPIO deasserted */
1160         priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb",
1161                         GPIOD_OUT_LOW);
1162 
1163         if (!priv->resetb_gpio)
1164                 dev_dbg(&client->dev, "resetb gpio is not assigned!\n");
1165 
1166         ret = PTR_ERR_OR_ZERO(priv->resetb_gpio);
1167         if (ret && ret != -ENOSYS) {
1168                 dev_dbg(&client->dev,
1169                         "Error %d while getting resetb gpio\n", ret);
1170                 return ret;
1171         }
1172 
1173         /* Request the power down GPIO asserted */
1174         priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn",
1175                         GPIOD_OUT_HIGH);
1176 
1177         if (!priv->pwdn_gpio)
1178                 dev_dbg(&client->dev, "pwdn gpio is not assigned!\n");
1179 
1180         ret = PTR_ERR_OR_ZERO(priv->pwdn_gpio);
1181         if (ret && ret != -ENOSYS) {
1182                 dev_dbg(&client->dev,
1183                         "Error %d while getting pwdn gpio\n", ret);
1184                 return ret;
1185         }
1186 
1187         return 0;
1188 }
1189 
1190 /*
1191  * i2c_driver functions
1192  */
1193 static int ov2640_probe(struct i2c_client *client)
1194 {
1195         struct ov2640_priv      *priv;
1196         struct i2c_adapter      *adapter = client->adapter;
1197         int                     ret;
1198 
1199         if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1200                 dev_err(&adapter->dev,
1201                         "OV2640: I2C-Adapter doesn't support SMBUS\n");
1202                 return -EIO;
1203         }
1204 
1205         priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1206         if (!priv)
1207                 return -ENOMEM;
1208 
1209         if (client->dev.of_node) {
1210                 priv->clk = devm_clk_get(&client->dev, "xvclk");
1211                 if (IS_ERR(priv->clk))
1212                         return PTR_ERR(priv->clk);
1213                 ret = clk_prepare_enable(priv->clk);
1214                 if (ret)
1215                         return ret;
1216         }
1217 
1218         ret = ov2640_probe_dt(client, priv);
1219         if (ret)
1220                 goto err_clk;
1221 
1222         priv->win = ov2640_select_win(SVGA_WIDTH, SVGA_HEIGHT);
1223         priv->cfmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
1224 
1225         v4l2_i2c_subdev_init(&priv->subdev, client, &ov2640_subdev_ops);
1226         priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1227                               V4L2_SUBDEV_FL_HAS_EVENTS;
1228         mutex_init(&priv->lock);
1229         v4l2_ctrl_handler_init(&priv->hdl, 3);
1230         priv->hdl.lock = &priv->lock;
1231         v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops,
1232                         V4L2_CID_VFLIP, 0, 1, 1, 0);
1233         v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops,
1234                         V4L2_CID_HFLIP, 0, 1, 1, 0);
1235         v4l2_ctrl_new_std_menu_items(&priv->hdl, &ov2640_ctrl_ops,
1236                         V4L2_CID_TEST_PATTERN,
1237                         ARRAY_SIZE(ov2640_test_pattern_menu) - 1, 0, 0,
1238                         ov2640_test_pattern_menu);
1239         priv->subdev.ctrl_handler = &priv->hdl;
1240         if (priv->hdl.error) {
1241                 ret = priv->hdl.error;
1242                 goto err_hdl;
1243         }
1244 #if defined(CONFIG_MEDIA_CONTROLLER)
1245         priv->pad.flags = MEDIA_PAD_FL_SOURCE;
1246         priv->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1247         ret = media_entity_pads_init(&priv->subdev.entity, 1, &priv->pad);
1248         if (ret < 0)
1249                 goto err_hdl;
1250 #endif
1251 
1252         ret = ov2640_video_probe(client);
1253         if (ret < 0)
1254                 goto err_videoprobe;
1255 
1256         ret = v4l2_async_register_subdev(&priv->subdev);
1257         if (ret < 0)
1258                 goto err_videoprobe;
1259 
1260         dev_info(&adapter->dev, "OV2640 Probed\n");
1261 
1262         return 0;
1263 
1264 err_videoprobe:
1265         media_entity_cleanup(&priv->subdev.entity);
1266 err_hdl:
1267         v4l2_ctrl_handler_free(&priv->hdl);
1268         mutex_destroy(&priv->lock);
1269 err_clk:
1270         clk_disable_unprepare(priv->clk);
1271         return ret;
1272 }
1273 
1274 static int ov2640_remove(struct i2c_client *client)
1275 {
1276         struct ov2640_priv       *priv = to_ov2640(client);
1277 
1278         v4l2_async_unregister_subdev(&priv->subdev);
1279         v4l2_ctrl_handler_free(&priv->hdl);
1280         mutex_destroy(&priv->lock);
1281         media_entity_cleanup(&priv->subdev.entity);
1282         v4l2_device_unregister_subdev(&priv->subdev);
1283         clk_disable_unprepare(priv->clk);
1284         return 0;
1285 }
1286 
1287 static const struct i2c_device_id ov2640_id[] = {
1288         { "ov2640", 0 },
1289         { }
1290 };
1291 MODULE_DEVICE_TABLE(i2c, ov2640_id);
1292 
1293 static const struct of_device_id ov2640_of_match[] = {
1294         {.compatible = "ovti,ov2640", },
1295         {},
1296 };
1297 MODULE_DEVICE_TABLE(of, ov2640_of_match);
1298 
1299 static struct i2c_driver ov2640_i2c_driver = {
1300         .driver = {
1301                 .name = "ov2640",
1302                 .of_match_table = of_match_ptr(ov2640_of_match),
1303         },
1304         .probe_new = ov2640_probe,
1305         .remove   = ov2640_remove,
1306         .id_table = ov2640_id,
1307 };
1308 
1309 module_i2c_driver(ov2640_i2c_driver);
1310 
1311 MODULE_DESCRIPTION("Driver for Omni Vision 2640 sensor");
1312 MODULE_AUTHOR("Alberto Panizzo");
1313 MODULE_LICENSE("GPL v2");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/media/i2c/ov2640.c

DEFINITIONS
