This source file includes following definitions.
- to_ov2659
- ov2659_write
- ov2659_read
- ov2659_write_array
- ov2659_pll_calc_params
- ov2659_set_pixel_clock
- ov2659_get_default_format
- ov2659_set_streaming
- ov2659_init
- ov2659_enum_mbus_code
- ov2659_enum_frame_sizes
- ov2659_get_fmt
- __ov2659_try_frame_size
- ov2659_set_fmt
- ov2659_set_frame_size
- ov2659_set_format
- ov2659_s_stream
- ov2659_set_test_pattern
- ov2659_s_ctrl
- ov2659_open
- ov2659_detect
- ov2659_get_pdata
- ov2659_probe
- ov2659_remove
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23 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/media.h>
32 #include <linux/module.h>
33 #include <linux/of.h>
34 #include <linux/of_graph.h>
35 #include <linux/slab.h>
36 #include <linux/uaccess.h>
37 #include <linux/videodev2.h>
38
39 #include <media/media-entity.h>
40 #include <media/i2c/ov2659.h>
41 #include <media/v4l2-common.h>
42 #include <media/v4l2-ctrls.h>
43 #include <media/v4l2-device.h>
44 #include <media/v4l2-event.h>
45 #include <media/v4l2-fwnode.h>
46 #include <media/v4l2-image-sizes.h>
47 #include <media/v4l2-mediabus.h>
48 #include <media/v4l2-subdev.h>
49
50 #define DRIVER_NAME "ov2659"
51
52
53
54
55 #define REG_SOFTWARE_STANDBY 0x0100
56 #define REG_SOFTWARE_RESET 0x0103
57 #define REG_IO_CTRL00 0x3000
58 #define REG_IO_CTRL01 0x3001
59 #define REG_IO_CTRL02 0x3002
60 #define REG_OUTPUT_VALUE00 0x3008
61 #define REG_OUTPUT_VALUE01 0x3009
62 #define REG_OUTPUT_VALUE02 0x300d
63 #define REG_OUTPUT_SELECT00 0x300e
64 #define REG_OUTPUT_SELECT01 0x300f
65 #define REG_OUTPUT_SELECT02 0x3010
66 #define REG_OUTPUT_DRIVE 0x3011
67 #define REG_INPUT_READOUT00 0x302d
68 #define REG_INPUT_READOUT01 0x302e
69 #define REG_INPUT_READOUT02 0x302f
70
71 #define REG_SC_PLL_CTRL0 0x3003
72 #define REG_SC_PLL_CTRL1 0x3004
73 #define REG_SC_PLL_CTRL2 0x3005
74 #define REG_SC_PLL_CTRL3 0x3006
75 #define REG_SC_CHIP_ID_H 0x300a
76 #define REG_SC_CHIP_ID_L 0x300b
77 #define REG_SC_PWC 0x3014
78 #define REG_SC_CLKRST0 0x301a
79 #define REG_SC_CLKRST1 0x301b
80 #define REG_SC_CLKRST2 0x301c
81 #define REG_SC_CLKRST3 0x301d
82 #define REG_SC_SUB_ID 0x302a
83 #define REG_SC_SCCB_ID 0x302b
84
85 #define REG_GROUP_ADDRESS_00 0x3200
86 #define REG_GROUP_ADDRESS_01 0x3201
87 #define REG_GROUP_ADDRESS_02 0x3202
88 #define REG_GROUP_ADDRESS_03 0x3203
89 #define REG_GROUP_ACCESS 0x3208
90
91 #define REG_AWB_R_GAIN_H 0x3400
92 #define REG_AWB_R_GAIN_L 0x3401
93 #define REG_AWB_G_GAIN_H 0x3402
94 #define REG_AWB_G_GAIN_L 0x3403
95 #define REG_AWB_B_GAIN_H 0x3404
96 #define REG_AWB_B_GAIN_L 0x3405
97 #define REG_AWB_MANUAL_CONTROL 0x3406
98
99 #define REG_TIMING_HS_H 0x3800
100 #define REG_TIMING_HS_L 0x3801
101 #define REG_TIMING_VS_H 0x3802
102 #define REG_TIMING_VS_L 0x3803
103 #define REG_TIMING_HW_H 0x3804
104 #define REG_TIMING_HW_L 0x3805
105 #define REG_TIMING_VH_H 0x3806
106 #define REG_TIMING_VH_L 0x3807
107 #define REG_TIMING_DVPHO_H 0x3808
108 #define REG_TIMING_DVPHO_L 0x3809
109 #define REG_TIMING_DVPVO_H 0x380a
110 #define REG_TIMING_DVPVO_L 0x380b
111 #define REG_TIMING_HTS_H 0x380c
112 #define REG_TIMING_HTS_L 0x380d
113 #define REG_TIMING_VTS_H 0x380e
114 #define REG_TIMING_VTS_L 0x380f
115 #define REG_TIMING_HOFFS_H 0x3810
116 #define REG_TIMING_HOFFS_L 0x3811
117 #define REG_TIMING_VOFFS_H 0x3812
118 #define REG_TIMING_VOFFS_L 0x3813
119 #define REG_TIMING_XINC 0x3814
120 #define REG_TIMING_YINC 0x3815
121 #define REG_TIMING_VERT_FORMAT 0x3820
122 #define REG_TIMING_HORIZ_FORMAT 0x3821
123
124 #define REG_FORMAT_CTRL00 0x4300
125
126 #define REG_VFIFO_READ_START_H 0x4608
127 #define REG_VFIFO_READ_START_L 0x4609
128
129 #define REG_DVP_CTRL02 0x4708
130
131 #define REG_ISP_CTRL00 0x5000
132 #define REG_ISP_CTRL01 0x5001
133 #define REG_ISP_CTRL02 0x5002
134
135 #define REG_LENC_RED_X0_H 0x500c
136 #define REG_LENC_RED_X0_L 0x500d
137 #define REG_LENC_RED_Y0_H 0x500e
138 #define REG_LENC_RED_Y0_L 0x500f
139 #define REG_LENC_RED_A1 0x5010
140 #define REG_LENC_RED_B1 0x5011
141 #define REG_LENC_RED_A2_B2 0x5012
142 #define REG_LENC_GREEN_X0_H 0x5013
143 #define REG_LENC_GREEN_X0_L 0x5014
144 #define REG_LENC_GREEN_Y0_H 0x5015
145 #define REG_LENC_GREEN_Y0_L 0x5016
146 #define REG_LENC_GREEN_A1 0x5017
147 #define REG_LENC_GREEN_B1 0x5018
148 #define REG_LENC_GREEN_A2_B2 0x5019
149 #define REG_LENC_BLUE_X0_H 0x501a
150 #define REG_LENC_BLUE_X0_L 0x501b
151 #define REG_LENC_BLUE_Y0_H 0x501c
152 #define REG_LENC_BLUE_Y0_L 0x501d
153 #define REG_LENC_BLUE_A1 0x501e
154 #define REG_LENC_BLUE_B1 0x501f
155 #define REG_LENC_BLUE_A2_B2 0x5020
156
157 #define REG_AWB_CTRL00 0x5035
158 #define REG_AWB_CTRL01 0x5036
159 #define REG_AWB_CTRL02 0x5037
160 #define REG_AWB_CTRL03 0x5038
161 #define REG_AWB_CTRL04 0x5039
162 #define REG_AWB_LOCAL_LIMIT 0x503a
163 #define REG_AWB_CTRL12 0x5049
164 #define REG_AWB_CTRL13 0x504a
165 #define REG_AWB_CTRL14 0x504b
166
167 #define REG_SHARPENMT_THRESH1 0x5064
168 #define REG_SHARPENMT_THRESH2 0x5065
169 #define REG_SHARPENMT_OFFSET1 0x5066
170 #define REG_SHARPENMT_OFFSET2 0x5067
171 #define REG_DENOISE_THRESH1 0x5068
172 #define REG_DENOISE_THRESH2 0x5069
173 #define REG_DENOISE_OFFSET1 0x506a
174 #define REG_DENOISE_OFFSET2 0x506b
175 #define REG_SHARPEN_THRESH1 0x506c
176 #define REG_SHARPEN_THRESH2 0x506d
177 #define REG_CIP_CTRL00 0x506e
178 #define REG_CIP_CTRL01 0x506f
179
180 #define REG_CMX_SIGN 0x5079
181 #define REG_CMX_MISC_CTRL 0x507a
182
183 #define REG_PRE_ISP_CTRL00 0x50a0
184 #define TEST_PATTERN_ENABLE BIT(7)
185 #define VERTICAL_COLOR_BAR_MASK 0x53
186
187 #define REG_NULL 0x0000
188
189 #define OV265X_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
190 #define OV2659_ID 0x2656
191
192 struct sensor_register {
193 u16 addr;
194 u8 value;
195 };
196
197 struct ov2659_framesize {
198 u16 width;
199 u16 height;
200 u16 max_exp_lines;
201 const struct sensor_register *regs;
202 };
203
204 struct ov2659_pll_ctrl {
205 u8 ctrl1;
206 u8 ctrl2;
207 u8 ctrl3;
208 };
209
210 struct ov2659_pixfmt {
211 u32 code;
212
213 struct sensor_register *format_ctrl_regs;
214 };
215
216 struct pll_ctrl_reg {
217 unsigned int div;
218 unsigned char reg;
219 };
220
221 struct ov2659 {
222 struct v4l2_subdev sd;
223 struct media_pad pad;
224 struct v4l2_mbus_framefmt format;
225 unsigned int xvclk_frequency;
226 const struct ov2659_platform_data *pdata;
227 struct mutex lock;
228 struct i2c_client *client;
229 struct v4l2_ctrl_handler ctrls;
230 struct v4l2_ctrl *link_frequency;
231 const struct ov2659_framesize *frame_size;
232 struct sensor_register *format_ctrl_regs;
233 struct ov2659_pll_ctrl pll;
234 int streaming;
235 };
236
237 static const struct sensor_register ov2659_init_regs[] = {
238 { REG_IO_CTRL00, 0x03 },
239 { REG_IO_CTRL01, 0xff },
240 { REG_IO_CTRL02, 0xe0 },
241 { 0x3633, 0x3d },
242 { 0x3620, 0x02 },
243 { 0x3631, 0x11 },
244 { 0x3612, 0x04 },
245 { 0x3630, 0x20 },
246 { 0x4702, 0x02 },
247 { 0x370c, 0x34 },
248 { REG_TIMING_HS_H, 0x00 },
249 { REG_TIMING_HS_L, 0x00 },
250 { REG_TIMING_VS_H, 0x00 },
251 { REG_TIMING_VS_L, 0x00 },
252 { REG_TIMING_HW_H, 0x06 },
253 { REG_TIMING_HW_L, 0x5f },
254 { REG_TIMING_VH_H, 0x04 },
255 { REG_TIMING_VH_L, 0xb7 },
256 { REG_TIMING_DVPHO_H, 0x03 },
257 { REG_TIMING_DVPHO_L, 0x20 },
258 { REG_TIMING_DVPVO_H, 0x02 },
259 { REG_TIMING_DVPVO_L, 0x58 },
260 { REG_TIMING_HTS_H, 0x05 },
261 { REG_TIMING_HTS_L, 0x14 },
262 { REG_TIMING_VTS_H, 0x02 },
263 { REG_TIMING_VTS_L, 0x68 },
264 { REG_TIMING_HOFFS_L, 0x08 },
265 { REG_TIMING_VOFFS_L, 0x02 },
266 { REG_TIMING_XINC, 0x31 },
267 { REG_TIMING_YINC, 0x31 },
268 { 0x3a02, 0x02 },
269 { 0x3a03, 0x68 },
270 { 0x3a08, 0x00 },
271 { 0x3a09, 0x5c },
272 { 0x3a0a, 0x00 },
273 { 0x3a0b, 0x4d },
274 { 0x3a0d, 0x08 },
275 { 0x3a0e, 0x06 },
276 { 0x3a14, 0x02 },
277 { 0x3a15, 0x28 },
278 { REG_DVP_CTRL02, 0x01 },
279 { 0x3623, 0x00 },
280 { 0x3634, 0x76 },
281 { 0x3701, 0x44 },
282 { 0x3702, 0x18 },
283 { 0x3703, 0x24 },
284 { 0x3704, 0x24 },
285 { 0x3705, 0x0c },
286 { REG_TIMING_VERT_FORMAT, 0x81 },
287 { REG_TIMING_HORIZ_FORMAT, 0x01 },
288 { 0x370a, 0x52 },
289 { REG_VFIFO_READ_START_H, 0x00 },
290 { REG_VFIFO_READ_START_L, 0x80 },
291 { REG_FORMAT_CTRL00, 0x30 },
292 { 0x5086, 0x02 },
293 { REG_ISP_CTRL00, 0xfb },
294 { REG_ISP_CTRL01, 0x1f },
295 { REG_ISP_CTRL02, 0x00 },
296 { 0x5025, 0x0e },
297 { 0x5026, 0x18 },
298 { 0x5027, 0x34 },
299 { 0x5028, 0x4c },
300 { 0x5029, 0x62 },
301 { 0x502a, 0x74 },
302 { 0x502b, 0x85 },
303 { 0x502c, 0x92 },
304 { 0x502d, 0x9e },
305 { 0x502e, 0xb2 },
306 { 0x502f, 0xc0 },
307 { 0x5030, 0xcc },
308 { 0x5031, 0xe0 },
309 { 0x5032, 0xee },
310 { 0x5033, 0xf6 },
311 { 0x5034, 0x11 },
312 { 0x5070, 0x1c },
313 { 0x5071, 0x5b },
314 { 0x5072, 0x05 },
315 { 0x5073, 0x20 },
316 { 0x5074, 0x94 },
317 { 0x5075, 0xb4 },
318 { 0x5076, 0xb4 },
319 { 0x5077, 0xaf },
320 { 0x5078, 0x05 },
321 { REG_CMX_SIGN, 0x98 },
322 { REG_CMX_MISC_CTRL, 0x21 },
323 { REG_AWB_CTRL00, 0x6a },
324 { REG_AWB_CTRL01, 0x11 },
325 { REG_AWB_CTRL02, 0x92 },
326 { REG_AWB_CTRL03, 0x21 },
327 { REG_AWB_CTRL04, 0xe1 },
328 { REG_AWB_LOCAL_LIMIT, 0x01 },
329 { 0x503c, 0x05 },
330 { 0x503d, 0x08 },
331 { 0x503e, 0x08 },
332 { 0x503f, 0x64 },
333 { 0x5040, 0x58 },
334 { 0x5041, 0x2a },
335 { 0x5042, 0xc5 },
336 { 0x5043, 0x2e },
337 { 0x5044, 0x3a },
338 { 0x5045, 0x3c },
339 { 0x5046, 0x44 },
340 { 0x5047, 0xf8 },
341 { 0x5048, 0x08 },
342 { REG_AWB_CTRL12, 0x70 },
343 { REG_AWB_CTRL13, 0xf0 },
344 { REG_AWB_CTRL14, 0xf0 },
345 { REG_LENC_RED_X0_H, 0x03 },
346 { REG_LENC_RED_X0_L, 0x20 },
347 { REG_LENC_RED_Y0_H, 0x02 },
348 { REG_LENC_RED_Y0_L, 0x5c },
349 { REG_LENC_RED_A1, 0x48 },
350 { REG_LENC_RED_B1, 0x00 },
351 { REG_LENC_RED_A2_B2, 0x66 },
352 { REG_LENC_GREEN_X0_H, 0x03 },
353 { REG_LENC_GREEN_X0_L, 0x30 },
354 { REG_LENC_GREEN_Y0_H, 0x02 },
355 { REG_LENC_GREEN_Y0_L, 0x7c },
356 { REG_LENC_GREEN_A1, 0x40 },
357 { REG_LENC_GREEN_B1, 0x00 },
358 { REG_LENC_GREEN_A2_B2, 0x66 },
359 { REG_LENC_BLUE_X0_H, 0x03 },
360 { REG_LENC_BLUE_X0_L, 0x10 },
361 { REG_LENC_BLUE_Y0_H, 0x02 },
362 { REG_LENC_BLUE_Y0_L, 0x7c },
363 { REG_LENC_BLUE_A1, 0x3a },
364 { REG_LENC_BLUE_B1, 0x00 },
365 { REG_LENC_BLUE_A2_B2, 0x66 },
366 { REG_CIP_CTRL00, 0x44 },
367 { REG_SHARPENMT_THRESH1, 0x08 },
368 { REG_SHARPENMT_THRESH2, 0x10 },
369 { REG_SHARPENMT_OFFSET1, 0x12 },
370 { REG_SHARPENMT_OFFSET2, 0x02 },
371 { REG_SHARPEN_THRESH1, 0x08 },
372 { REG_SHARPEN_THRESH2, 0x10 },
373 { REG_CIP_CTRL01, 0xa6 },
374 { REG_DENOISE_THRESH1, 0x08 },
375 { REG_DENOISE_THRESH2, 0x10 },
376 { REG_DENOISE_OFFSET1, 0x04 },
377 { REG_DENOISE_OFFSET2, 0x12 },
378 { 0x507e, 0x40 },
379 { 0x507f, 0x20 },
380 { 0x507b, 0x02 },
381 { REG_CMX_MISC_CTRL, 0x01 },
382 { 0x5084, 0x0c },
383 { 0x5085, 0x3e },
384 { 0x5005, 0x80 },
385 { 0x3a0f, 0x30 },
386 { 0x3a10, 0x28 },
387 { 0x3a1b, 0x32 },
388 { 0x3a1e, 0x26 },
389 { 0x3a11, 0x60 },
390 { 0x3a1f, 0x14 },
391 { 0x5060, 0x69 },
392 { 0x5061, 0x7d },
393 { 0x5062, 0x7d },
394 { 0x5063, 0x69 },
395 { REG_NULL, 0x00 },
396 };
397
398
399 static struct sensor_register ov2659_720p[] = {
400 { REG_TIMING_HS_H, 0x00 },
401 { REG_TIMING_HS_L, 0xa0 },
402 { REG_TIMING_VS_H, 0x00 },
403 { REG_TIMING_VS_L, 0xf0 },
404 { REG_TIMING_HW_H, 0x05 },
405 { REG_TIMING_HW_L, 0xbf },
406 { REG_TIMING_VH_H, 0x03 },
407 { REG_TIMING_VH_L, 0xcb },
408 { REG_TIMING_DVPHO_H, 0x05 },
409 { REG_TIMING_DVPHO_L, 0x00 },
410 { REG_TIMING_DVPVO_H, 0x02 },
411 { REG_TIMING_DVPVO_L, 0xd0 },
412 { REG_TIMING_HTS_H, 0x06 },
413 { REG_TIMING_HTS_L, 0x4c },
414 { REG_TIMING_VTS_H, 0x02 },
415 { REG_TIMING_VTS_L, 0xe8 },
416 { REG_TIMING_HOFFS_L, 0x10 },
417 { REG_TIMING_VOFFS_L, 0x06 },
418 { REG_TIMING_XINC, 0x11 },
419 { REG_TIMING_YINC, 0x11 },
420 { REG_TIMING_VERT_FORMAT, 0x80 },
421 { REG_TIMING_HORIZ_FORMAT, 0x00 },
422 { 0x370a, 0x12 },
423 { 0x3a03, 0xe8 },
424 { 0x3a09, 0x6f },
425 { 0x3a0b, 0x5d },
426 { 0x3a15, 0x9a },
427 { REG_VFIFO_READ_START_H, 0x00 },
428 { REG_VFIFO_READ_START_L, 0x80 },
429 { REG_ISP_CTRL02, 0x00 },
430 { REG_NULL, 0x00 },
431 };
432
433
434 static struct sensor_register ov2659_uxga[] = {
435 { REG_TIMING_HS_H, 0x00 },
436 { REG_TIMING_HS_L, 0x00 },
437 { REG_TIMING_VS_H, 0x00 },
438 { REG_TIMING_VS_L, 0x00 },
439 { REG_TIMING_HW_H, 0x06 },
440 { REG_TIMING_HW_L, 0x5f },
441 { REG_TIMING_VH_H, 0x04 },
442 { REG_TIMING_VH_L, 0xbb },
443 { REG_TIMING_DVPHO_H, 0x06 },
444 { REG_TIMING_DVPHO_L, 0x40 },
445 { REG_TIMING_DVPVO_H, 0x04 },
446 { REG_TIMING_DVPVO_L, 0xb0 },
447 { REG_TIMING_HTS_H, 0x07 },
448 { REG_TIMING_HTS_L, 0x9f },
449 { REG_TIMING_VTS_H, 0x04 },
450 { REG_TIMING_VTS_L, 0xd0 },
451 { REG_TIMING_HOFFS_L, 0x10 },
452 { REG_TIMING_VOFFS_L, 0x06 },
453 { REG_TIMING_XINC, 0x11 },
454 { REG_TIMING_YINC, 0x11 },
455 { 0x3a02, 0x04 },
456 { 0x3a03, 0xd0 },
457 { 0x3a08, 0x00 },
458 { 0x3a09, 0xb8 },
459 { 0x3a0a, 0x00 },
460 { 0x3a0b, 0x9a },
461 { 0x3a0d, 0x08 },
462 { 0x3a0e, 0x06 },
463 { 0x3a14, 0x04 },
464 { 0x3a15, 0x50 },
465 { 0x3623, 0x00 },
466 { 0x3634, 0x44 },
467 { 0x3701, 0x44 },
468 { 0x3702, 0x30 },
469 { 0x3703, 0x48 },
470 { 0x3704, 0x48 },
471 { 0x3705, 0x18 },
472 { REG_TIMING_VERT_FORMAT, 0x80 },
473 { REG_TIMING_HORIZ_FORMAT, 0x00 },
474 { 0x370a, 0x12 },
475 { REG_VFIFO_READ_START_H, 0x00 },
476 { REG_VFIFO_READ_START_L, 0x80 },
477 { REG_ISP_CTRL02, 0x00 },
478 { REG_NULL, 0x00 },
479 };
480
481
482 static struct sensor_register ov2659_sxga[] = {
483 { REG_TIMING_HS_H, 0x00 },
484 { REG_TIMING_HS_L, 0x00 },
485 { REG_TIMING_VS_H, 0x00 },
486 { REG_TIMING_VS_L, 0x00 },
487 { REG_TIMING_HW_H, 0x06 },
488 { REG_TIMING_HW_L, 0x5f },
489 { REG_TIMING_VH_H, 0x04 },
490 { REG_TIMING_VH_L, 0xb7 },
491 { REG_TIMING_DVPHO_H, 0x05 },
492 { REG_TIMING_DVPHO_L, 0x00 },
493 { REG_TIMING_DVPVO_H, 0x04 },
494 { REG_TIMING_DVPVO_L, 0x00 },
495 { REG_TIMING_HTS_H, 0x07 },
496 { REG_TIMING_HTS_L, 0x9c },
497 { REG_TIMING_VTS_H, 0x04 },
498 { REG_TIMING_VTS_L, 0xd0 },
499 { REG_TIMING_HOFFS_L, 0x10 },
500 { REG_TIMING_VOFFS_L, 0x06 },
501 { REG_TIMING_XINC, 0x11 },
502 { REG_TIMING_YINC, 0x11 },
503 { 0x3a02, 0x02 },
504 { 0x3a03, 0x68 },
505 { 0x3a08, 0x00 },
506 { 0x3a09, 0x5c },
507 { 0x3a0a, 0x00 },
508 { 0x3a0b, 0x4d },
509 { 0x3a0d, 0x08 },
510 { 0x3a0e, 0x06 },
511 { 0x3a14, 0x02 },
512 { 0x3a15, 0x28 },
513 { 0x3623, 0x00 },
514 { 0x3634, 0x76 },
515 { 0x3701, 0x44 },
516 { 0x3702, 0x18 },
517 { 0x3703, 0x24 },
518 { 0x3704, 0x24 },
519 { 0x3705, 0x0c },
520 { REG_TIMING_VERT_FORMAT, 0x80 },
521 { REG_TIMING_HORIZ_FORMAT, 0x00 },
522 { 0x370a, 0x52 },
523 { REG_VFIFO_READ_START_H, 0x00 },
524 { REG_VFIFO_READ_START_L, 0x80 },
525 { REG_ISP_CTRL02, 0x00 },
526 { REG_NULL, 0x00 },
527 };
528
529
530 static struct sensor_register ov2659_xga[] = {
531 { REG_TIMING_HS_H, 0x00 },
532 { REG_TIMING_HS_L, 0x00 },
533 { REG_TIMING_VS_H, 0x00 },
534 { REG_TIMING_VS_L, 0x00 },
535 { REG_TIMING_HW_H, 0x06 },
536 { REG_TIMING_HW_L, 0x5f },
537 { REG_TIMING_VH_H, 0x04 },
538 { REG_TIMING_VH_L, 0xb7 },
539 { REG_TIMING_DVPHO_H, 0x04 },
540 { REG_TIMING_DVPHO_L, 0x00 },
541 { REG_TIMING_DVPVO_H, 0x03 },
542 { REG_TIMING_DVPVO_L, 0x00 },
543 { REG_TIMING_HTS_H, 0x07 },
544 { REG_TIMING_HTS_L, 0x9c },
545 { REG_TIMING_VTS_H, 0x04 },
546 { REG_TIMING_VTS_L, 0xd0 },
547 { REG_TIMING_HOFFS_L, 0x10 },
548 { REG_TIMING_VOFFS_L, 0x06 },
549 { REG_TIMING_XINC, 0x11 },
550 { REG_TIMING_YINC, 0x11 },
551 { 0x3a02, 0x02 },
552 { 0x3a03, 0x68 },
553 { 0x3a08, 0x00 },
554 { 0x3a09, 0x5c },
555 { 0x3a0a, 0x00 },
556 { 0x3a0b, 0x4d },
557 { 0x3a0d, 0x08 },
558 { 0x3a0e, 0x06 },
559 { 0x3a14, 0x02 },
560 { 0x3a15, 0x28 },
561 { 0x3623, 0x00 },
562 { 0x3634, 0x76 },
563 { 0x3701, 0x44 },
564 { 0x3702, 0x18 },
565 { 0x3703, 0x24 },
566 { 0x3704, 0x24 },
567 { 0x3705, 0x0c },
568 { REG_TIMING_VERT_FORMAT, 0x80 },
569 { REG_TIMING_HORIZ_FORMAT, 0x00 },
570 { 0x370a, 0x52 },
571 { REG_VFIFO_READ_START_H, 0x00 },
572 { REG_VFIFO_READ_START_L, 0x80 },
573 { REG_ISP_CTRL02, 0x00 },
574 { REG_NULL, 0x00 },
575 };
576
577
578 static struct sensor_register ov2659_svga[] = {
579 { REG_TIMING_HS_H, 0x00 },
580 { REG_TIMING_HS_L, 0x00 },
581 { REG_TIMING_VS_H, 0x00 },
582 { REG_TIMING_VS_L, 0x00 },
583 { REG_TIMING_HW_H, 0x06 },
584 { REG_TIMING_HW_L, 0x5f },
585 { REG_TIMING_VH_H, 0x04 },
586 { REG_TIMING_VH_L, 0xb7 },
587 { REG_TIMING_DVPHO_H, 0x03 },
588 { REG_TIMING_DVPHO_L, 0x20 },
589 { REG_TIMING_DVPVO_H, 0x02 },
590 { REG_TIMING_DVPVO_L, 0x58 },
591 { REG_TIMING_HTS_H, 0x05 },
592 { REG_TIMING_HTS_L, 0x14 },
593 { REG_TIMING_VTS_H, 0x02 },
594 { REG_TIMING_VTS_L, 0x68 },
595 { REG_TIMING_HOFFS_L, 0x08 },
596 { REG_TIMING_VOFFS_L, 0x02 },
597 { REG_TIMING_XINC, 0x31 },
598 { REG_TIMING_YINC, 0x31 },
599 { 0x3a02, 0x02 },
600 { 0x3a03, 0x68 },
601 { 0x3a08, 0x00 },
602 { 0x3a09, 0x5c },
603 { 0x3a0a, 0x00 },
604 { 0x3a0b, 0x4d },
605 { 0x3a0d, 0x08 },
606 { 0x3a0e, 0x06 },
607 { 0x3a14, 0x02 },
608 { 0x3a15, 0x28 },
609 { 0x3623, 0x00 },
610 { 0x3634, 0x76 },
611 { 0x3701, 0x44 },
612 { 0x3702, 0x18 },
613 { 0x3703, 0x24 },
614 { 0x3704, 0x24 },
615 { 0x3705, 0x0c },
616 { REG_TIMING_VERT_FORMAT, 0x81 },
617 { REG_TIMING_HORIZ_FORMAT, 0x01 },
618 { 0x370a, 0x52 },
619 { REG_VFIFO_READ_START_H, 0x00 },
620 { REG_VFIFO_READ_START_L, 0x80 },
621 { REG_ISP_CTRL02, 0x00 },
622 { REG_NULL, 0x00 },
623 };
624
625
626 static struct sensor_register ov2659_vga[] = {
627 { REG_TIMING_HS_H, 0x00 },
628 { REG_TIMING_HS_L, 0x00 },
629 { REG_TIMING_VS_H, 0x00 },
630 { REG_TIMING_VS_L, 0x00 },
631 { REG_TIMING_HW_H, 0x06 },
632 { REG_TIMING_HW_L, 0x5f },
633 { REG_TIMING_VH_H, 0x04 },
634 { REG_TIMING_VH_L, 0xb7 },
635 { REG_TIMING_DVPHO_H, 0x02 },
636 { REG_TIMING_DVPHO_L, 0x80 },
637 { REG_TIMING_DVPVO_H, 0x01 },
638 { REG_TIMING_DVPVO_L, 0xe0 },
639 { REG_TIMING_HTS_H, 0x05 },
640 { REG_TIMING_HTS_L, 0x14 },
641 { REG_TIMING_VTS_H, 0x02 },
642 { REG_TIMING_VTS_L, 0x68 },
643 { REG_TIMING_HOFFS_L, 0x08 },
644 { REG_TIMING_VOFFS_L, 0x02 },
645 { REG_TIMING_XINC, 0x31 },
646 { REG_TIMING_YINC, 0x31 },
647 { 0x3a02, 0x02 },
648 { 0x3a03, 0x68 },
649 { 0x3a08, 0x00 },
650 { 0x3a09, 0x5c },
651 { 0x3a0a, 0x00 },
652 { 0x3a0b, 0x4d },
653 { 0x3a0d, 0x08 },
654 { 0x3a0e, 0x06 },
655 { 0x3a14, 0x02 },
656 { 0x3a15, 0x28 },
657 { 0x3623, 0x00 },
658 { 0x3634, 0x76 },
659 { 0x3701, 0x44 },
660 { 0x3702, 0x18 },
661 { 0x3703, 0x24 },
662 { 0x3704, 0x24 },
663 { 0x3705, 0x0c },
664 { REG_TIMING_VERT_FORMAT, 0x81 },
665 { REG_TIMING_HORIZ_FORMAT, 0x01 },
666 { 0x370a, 0x52 },
667 { REG_VFIFO_READ_START_H, 0x00 },
668 { REG_VFIFO_READ_START_L, 0x80 },
669 { REG_ISP_CTRL02, 0x10 },
670 { REG_NULL, 0x00 },
671 };
672
673
674 static struct sensor_register ov2659_qvga[] = {
675 { REG_TIMING_HS_H, 0x00 },
676 { REG_TIMING_HS_L, 0x00 },
677 { REG_TIMING_VS_H, 0x00 },
678 { REG_TIMING_VS_L, 0x00 },
679 { REG_TIMING_HW_H, 0x06 },
680 { REG_TIMING_HW_L, 0x5f },
681 { REG_TIMING_VH_H, 0x04 },
682 { REG_TIMING_VH_L, 0xb7 },
683 { REG_TIMING_DVPHO_H, 0x01 },
684 { REG_TIMING_DVPHO_L, 0x40 },
685 { REG_TIMING_DVPVO_H, 0x00 },
686 { REG_TIMING_DVPVO_L, 0xf0 },
687 { REG_TIMING_HTS_H, 0x05 },
688 { REG_TIMING_HTS_L, 0x14 },
689 { REG_TIMING_VTS_H, 0x02 },
690 { REG_TIMING_VTS_L, 0x68 },
691 { REG_TIMING_HOFFS_L, 0x08 },
692 { REG_TIMING_VOFFS_L, 0x02 },
693 { REG_TIMING_XINC, 0x31 },
694 { REG_TIMING_YINC, 0x31 },
695 { 0x3a02, 0x02 },
696 { 0x3a03, 0x68 },
697 { 0x3a08, 0x00 },
698 { 0x3a09, 0x5c },
699 { 0x3a0a, 0x00 },
700 { 0x3a0b, 0x4d },
701 { 0x3a0d, 0x08 },
702 { 0x3a0e, 0x06 },
703 { 0x3a14, 0x02 },
704 { 0x3a15, 0x28 },
705 { 0x3623, 0x00 },
706 { 0x3634, 0x76 },
707 { 0x3701, 0x44 },
708 { 0x3702, 0x18 },
709 { 0x3703, 0x24 },
710 { 0x3704, 0x24 },
711 { 0x3705, 0x0c },
712 { REG_TIMING_VERT_FORMAT, 0x81 },
713 { REG_TIMING_HORIZ_FORMAT, 0x01 },
714 { 0x370a, 0x52 },
715 { REG_VFIFO_READ_START_H, 0x00 },
716 { REG_VFIFO_READ_START_L, 0x80 },
717 { REG_ISP_CTRL02, 0x10 },
718 { REG_NULL, 0x00 },
719 };
720
721 static const struct pll_ctrl_reg ctrl3[] = {
722 { 1, 0x00 },
723 { 2, 0x02 },
724 { 3, 0x03 },
725 { 4, 0x06 },
726 { 6, 0x0d },
727 { 8, 0x0e },
728 { 12, 0x0f },
729 { 16, 0x12 },
730 { 24, 0x13 },
731 { 32, 0x16 },
732 { 48, 0x1b },
733 { 64, 0x1e },
734 { 96, 0x1f },
735 { 0, 0x00 },
736 };
737
738 static const struct pll_ctrl_reg ctrl1[] = {
739 { 2, 0x10 },
740 { 4, 0x20 },
741 { 6, 0x30 },
742 { 8, 0x40 },
743 { 10, 0x50 },
744 { 12, 0x60 },
745 { 14, 0x70 },
746 { 16, 0x80 },
747 { 18, 0x90 },
748 { 20, 0xa0 },
749 { 22, 0xb0 },
750 { 24, 0xc0 },
751 { 26, 0xd0 },
752 { 28, 0xe0 },
753 { 30, 0xf0 },
754 { 0, 0x00 },
755 };
756
757 static const struct ov2659_framesize ov2659_framesizes[] = {
758 {
759 .width = 320,
760 .height = 240,
761 .regs = ov2659_qvga,
762 .max_exp_lines = 248,
763 }, {
764 .width = 640,
765 .height = 480,
766 .regs = ov2659_vga,
767 .max_exp_lines = 498,
768 }, {
769 .width = 800,
770 .height = 600,
771 .regs = ov2659_svga,
772 .max_exp_lines = 498,
773 }, {
774 .width = 1024,
775 .height = 768,
776 .regs = ov2659_xga,
777 .max_exp_lines = 498,
778 }, {
779 .width = 1280,
780 .height = 720,
781 .regs = ov2659_720p,
782 .max_exp_lines = 498,
783 }, {
784 .width = 1280,
785 .height = 1024,
786 .regs = ov2659_sxga,
787 .max_exp_lines = 1048,
788 }, {
789 .width = 1600,
790 .height = 1200,
791 .regs = ov2659_uxga,
792 .max_exp_lines = 498,
793 },
794 };
795
796
797 static struct sensor_register ov2659_format_yuyv[] = {
798 { REG_FORMAT_CTRL00, 0x30 },
799 { REG_NULL, 0x0 },
800 };
801
802
803 static struct sensor_register ov2659_format_uyvy[] = {
804 { REG_FORMAT_CTRL00, 0x32 },
805 { REG_NULL, 0x0 },
806 };
807
808
809 static struct sensor_register ov2659_format_bggr[] = {
810 { REG_FORMAT_CTRL00, 0x00 },
811 { REG_NULL, 0x0 },
812 };
813
814
815 static struct sensor_register ov2659_format_rgb565[] = {
816 { REG_FORMAT_CTRL00, 0x60 },
817 { REG_NULL, 0x0 },
818 };
819
820 static const struct ov2659_pixfmt ov2659_formats[] = {
821 {
822 .code = MEDIA_BUS_FMT_YUYV8_2X8,
823 .format_ctrl_regs = ov2659_format_yuyv,
824 }, {
825 .code = MEDIA_BUS_FMT_UYVY8_2X8,
826 .format_ctrl_regs = ov2659_format_uyvy,
827 }, {
828 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
829 .format_ctrl_regs = ov2659_format_rgb565,
830 }, {
831 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
832 .format_ctrl_regs = ov2659_format_bggr,
833 },
834 };
835
836 static inline struct ov2659 *to_ov2659(struct v4l2_subdev *sd)
837 {
838 return container_of(sd, struct ov2659, sd);
839 }
840
841
842 static int ov2659_write(struct i2c_client *client, u16 reg, u8 val)
843 {
844 struct i2c_msg msg;
845 u8 buf[3];
846 int ret;
847
848 buf[0] = reg >> 8;
849 buf[1] = reg & 0xFF;
850 buf[2] = val;
851
852 msg.addr = client->addr;
853 msg.flags = client->flags;
854 msg.buf = buf;
855 msg.len = sizeof(buf);
856
857 ret = i2c_transfer(client->adapter, &msg, 1);
858 if (ret >= 0)
859 return 0;
860
861 dev_dbg(&client->dev,
862 "ov2659 write reg(0x%x val:0x%x) failed !\n", reg, val);
863
864 return ret;
865 }
866
867
868 static int ov2659_read(struct i2c_client *client, u16 reg, u8 *val)
869 {
870 struct i2c_msg msg[2];
871 u8 buf[2];
872 int ret;
873
874 buf[0] = reg >> 8;
875 buf[1] = reg & 0xFF;
876
877 msg[0].addr = client->addr;
878 msg[0].flags = client->flags;
879 msg[0].buf = buf;
880 msg[0].len = sizeof(buf);
881
882 msg[1].addr = client->addr;
883 msg[1].flags = client->flags | I2C_M_RD;
884 msg[1].buf = buf;
885 msg[1].len = 1;
886
887 ret = i2c_transfer(client->adapter, msg, 2);
888 if (ret >= 0) {
889 *val = buf[0];
890 return 0;
891 }
892
893 dev_dbg(&client->dev,
894 "ov2659 read reg(0x%x val:0x%x) failed !\n", reg, *val);
895
896 return ret;
897 }
898
899 static int ov2659_write_array(struct i2c_client *client,
900 const struct sensor_register *regs)
901 {
902 int i, ret = 0;
903
904 for (i = 0; ret == 0 && regs[i].addr; i++)
905 ret = ov2659_write(client, regs[i].addr, regs[i].value);
906
907 return ret;
908 }
909
910 static void ov2659_pll_calc_params(struct ov2659 *ov2659)
911 {
912 const struct ov2659_platform_data *pdata = ov2659->pdata;
913 u8 ctrl1_reg = 0, ctrl2_reg = 0, ctrl3_reg = 0;
914 struct i2c_client *client = ov2659->client;
915 unsigned int desired = pdata->link_frequency;
916 u32 prediv, postdiv, mult;
917 u32 bestdelta = -1;
918 u32 delta, actual;
919 int i, j;
920
921 for (i = 0; ctrl1[i].div != 0; i++) {
922 postdiv = ctrl1[i].div;
923 for (j = 0; ctrl3[j].div != 0; j++) {
924 prediv = ctrl3[j].div;
925 for (mult = 1; mult <= 63; mult++) {
926 actual = ov2659->xvclk_frequency;
927 actual *= mult;
928 actual /= prediv;
929 actual /= postdiv;
930 delta = actual - desired;
931 delta = abs(delta);
932
933 if ((delta < bestdelta) || (bestdelta == -1)) {
934 bestdelta = delta;
935 ctrl1_reg = ctrl1[i].reg;
936 ctrl2_reg = mult;
937 ctrl3_reg = ctrl3[j].reg;
938 }
939 }
940 }
941 }
942
943 ov2659->pll.ctrl1 = ctrl1_reg;
944 ov2659->pll.ctrl2 = ctrl2_reg;
945 ov2659->pll.ctrl3 = ctrl3_reg;
946
947 dev_dbg(&client->dev,
948 "Actual reg config: ctrl1_reg: %02x ctrl2_reg: %02x ctrl3_reg: %02x\n",
949 ctrl1_reg, ctrl2_reg, ctrl3_reg);
950 }
951
952 static int ov2659_set_pixel_clock(struct ov2659 *ov2659)
953 {
954 struct i2c_client *client = ov2659->client;
955 struct sensor_register pll_regs[] = {
956 {REG_SC_PLL_CTRL1, ov2659->pll.ctrl1},
957 {REG_SC_PLL_CTRL2, ov2659->pll.ctrl2},
958 {REG_SC_PLL_CTRL3, ov2659->pll.ctrl3},
959 {REG_NULL, 0x00},
960 };
961
962 dev_dbg(&client->dev, "%s\n", __func__);
963
964 return ov2659_write_array(client, pll_regs);
965 };
966
967 static void ov2659_get_default_format(struct v4l2_mbus_framefmt *format)
968 {
969 format->width = ov2659_framesizes[2].width;
970 format->height = ov2659_framesizes[2].height;
971 format->colorspace = V4L2_COLORSPACE_SRGB;
972 format->code = ov2659_formats[0].code;
973 format->field = V4L2_FIELD_NONE;
974 }
975
976 static void ov2659_set_streaming(struct ov2659 *ov2659, int on)
977 {
978 struct i2c_client *client = ov2659->client;
979 int ret;
980
981 on = !!on;
982
983 dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
984
985 ret = ov2659_write(client, REG_SOFTWARE_STANDBY, on);
986 if (ret)
987 dev_err(&client->dev, "ov2659 soft standby failed\n");
988 }
989
990 static int ov2659_init(struct v4l2_subdev *sd, u32 val)
991 {
992 struct i2c_client *client = v4l2_get_subdevdata(sd);
993
994 return ov2659_write_array(client, ov2659_init_regs);
995 }
996
997
998
999
1000
1001 static int ov2659_enum_mbus_code(struct v4l2_subdev *sd,
1002 struct v4l2_subdev_pad_config *cfg,
1003 struct v4l2_subdev_mbus_code_enum *code)
1004 {
1005 struct i2c_client *client = v4l2_get_subdevdata(sd);
1006
1007 dev_dbg(&client->dev, "%s:\n", __func__);
1008
1009 if (code->index >= ARRAY_SIZE(ov2659_formats))
1010 return -EINVAL;
1011
1012 code->code = ov2659_formats[code->index].code;
1013
1014 return 0;
1015 }
1016
1017 static int ov2659_enum_frame_sizes(struct v4l2_subdev *sd,
1018 struct v4l2_subdev_pad_config *cfg,
1019 struct v4l2_subdev_frame_size_enum *fse)
1020 {
1021 struct i2c_client *client = v4l2_get_subdevdata(sd);
1022 int i = ARRAY_SIZE(ov2659_formats);
1023
1024 dev_dbg(&client->dev, "%s:\n", __func__);
1025
1026 if (fse->index >= ARRAY_SIZE(ov2659_framesizes))
1027 return -EINVAL;
1028
1029 while (--i)
1030 if (fse->code == ov2659_formats[i].code)
1031 break;
1032
1033 fse->code = ov2659_formats[i].code;
1034
1035 fse->min_width = ov2659_framesizes[fse->index].width;
1036 fse->max_width = fse->min_width;
1037 fse->max_height = ov2659_framesizes[fse->index].height;
1038 fse->min_height = fse->max_height;
1039
1040 return 0;
1041 }
1042
1043 static int ov2659_get_fmt(struct v4l2_subdev *sd,
1044 struct v4l2_subdev_pad_config *cfg,
1045 struct v4l2_subdev_format *fmt)
1046 {
1047 struct i2c_client *client = v4l2_get_subdevdata(sd);
1048 struct ov2659 *ov2659 = to_ov2659(sd);
1049
1050 dev_dbg(&client->dev, "ov2659_get_fmt\n");
1051
1052 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1053 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1054 struct v4l2_mbus_framefmt *mf;
1055
1056 mf = v4l2_subdev_get_try_format(sd, cfg, 0);
1057 mutex_lock(&ov2659->lock);
1058 fmt->format = *mf;
1059 mutex_unlock(&ov2659->lock);
1060 return 0;
1061 #else
1062 return -EINVAL;
1063 #endif
1064 }
1065
1066 mutex_lock(&ov2659->lock);
1067 fmt->format = ov2659->format;
1068 mutex_unlock(&ov2659->lock);
1069
1070 dev_dbg(&client->dev, "ov2659_get_fmt: %x %dx%d\n",
1071 ov2659->format.code, ov2659->format.width,
1072 ov2659->format.height);
1073
1074 return 0;
1075 }
1076
1077 static void __ov2659_try_frame_size(struct v4l2_mbus_framefmt *mf,
1078 const struct ov2659_framesize **size)
1079 {
1080 const struct ov2659_framesize *fsize = &ov2659_framesizes[0];
1081 const struct ov2659_framesize *match = NULL;
1082 int i = ARRAY_SIZE(ov2659_framesizes);
1083 unsigned int min_err = UINT_MAX;
1084
1085 while (i--) {
1086 int err = abs(fsize->width - mf->width)
1087 + abs(fsize->height - mf->height);
1088 if ((err < min_err) && (fsize->regs[0].addr)) {
1089 min_err = err;
1090 match = fsize;
1091 }
1092 fsize++;
1093 }
1094
1095 if (!match)
1096 match = &ov2659_framesizes[2];
1097
1098 mf->width = match->width;
1099 mf->height = match->height;
1100
1101 if (size)
1102 *size = match;
1103 }
1104
1105 static int ov2659_set_fmt(struct v4l2_subdev *sd,
1106 struct v4l2_subdev_pad_config *cfg,
1107 struct v4l2_subdev_format *fmt)
1108 {
1109 struct i2c_client *client = v4l2_get_subdevdata(sd);
1110 int index = ARRAY_SIZE(ov2659_formats);
1111 struct v4l2_mbus_framefmt *mf = &fmt->format;
1112 const struct ov2659_framesize *size = NULL;
1113 struct ov2659 *ov2659 = to_ov2659(sd);
1114 int ret = 0;
1115
1116 dev_dbg(&client->dev, "ov2659_set_fmt\n");
1117
1118 __ov2659_try_frame_size(mf, &size);
1119
1120 while (--index >= 0)
1121 if (ov2659_formats[index].code == mf->code)
1122 break;
1123
1124 if (index < 0) {
1125 index = 0;
1126 mf->code = ov2659_formats[index].code;
1127 }
1128
1129 mf->colorspace = V4L2_COLORSPACE_SRGB;
1130 mf->field = V4L2_FIELD_NONE;
1131
1132 mutex_lock(&ov2659->lock);
1133
1134 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1135 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1136 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1137 *mf = fmt->format;
1138 #endif
1139 } else {
1140 s64 val;
1141
1142 if (ov2659->streaming) {
1143 mutex_unlock(&ov2659->lock);
1144 return -EBUSY;
1145 }
1146
1147 ov2659->frame_size = size;
1148 ov2659->format = fmt->format;
1149 ov2659->format_ctrl_regs =
1150 ov2659_formats[index].format_ctrl_regs;
1151
1152 if (ov2659->format.code != MEDIA_BUS_FMT_SBGGR8_1X8)
1153 val = ov2659->pdata->link_frequency / 2;
1154 else
1155 val = ov2659->pdata->link_frequency;
1156
1157 ret = v4l2_ctrl_s_ctrl_int64(ov2659->link_frequency, val);
1158 if (ret < 0)
1159 dev_warn(&client->dev,
1160 "failed to set link_frequency rate (%d)\n",
1161 ret);
1162 }
1163
1164 mutex_unlock(&ov2659->lock);
1165 return ret;
1166 }
1167
1168 static int ov2659_set_frame_size(struct ov2659 *ov2659)
1169 {
1170 struct i2c_client *client = ov2659->client;
1171
1172 dev_dbg(&client->dev, "%s\n", __func__);
1173
1174 return ov2659_write_array(ov2659->client, ov2659->frame_size->regs);
1175 }
1176
1177 static int ov2659_set_format(struct ov2659 *ov2659)
1178 {
1179 struct i2c_client *client = ov2659->client;
1180
1181 dev_dbg(&client->dev, "%s\n", __func__);
1182
1183 return ov2659_write_array(ov2659->client, ov2659->format_ctrl_regs);
1184 }
1185
1186 static int ov2659_s_stream(struct v4l2_subdev *sd, int on)
1187 {
1188 struct i2c_client *client = v4l2_get_subdevdata(sd);
1189 struct ov2659 *ov2659 = to_ov2659(sd);
1190 int ret = 0;
1191
1192 dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
1193
1194 mutex_lock(&ov2659->lock);
1195
1196 on = !!on;
1197
1198 if (ov2659->streaming == on)
1199 goto unlock;
1200
1201 if (!on) {
1202
1203 ov2659_set_streaming(ov2659, 0);
1204 ov2659->streaming = on;
1205 goto unlock;
1206 }
1207
1208 ret = ov2659_set_pixel_clock(ov2659);
1209 if (!ret)
1210 ret = ov2659_set_frame_size(ov2659);
1211 if (!ret)
1212 ret = ov2659_set_format(ov2659);
1213 if (!ret) {
1214 ov2659_set_streaming(ov2659, 1);
1215 ov2659->streaming = on;
1216 }
1217
1218 unlock:
1219 mutex_unlock(&ov2659->lock);
1220 return ret;
1221 }
1222
1223 static int ov2659_set_test_pattern(struct ov2659 *ov2659, int value)
1224 {
1225 struct i2c_client *client = v4l2_get_subdevdata(&ov2659->sd);
1226 int ret;
1227 u8 val;
1228
1229 ret = ov2659_read(client, REG_PRE_ISP_CTRL00, &val);
1230 if (ret < 0)
1231 return ret;
1232
1233 switch (value) {
1234 case 0:
1235 val &= ~TEST_PATTERN_ENABLE;
1236 break;
1237 case 1:
1238 val &= VERTICAL_COLOR_BAR_MASK;
1239 val |= TEST_PATTERN_ENABLE;
1240 break;
1241 }
1242
1243 return ov2659_write(client, REG_PRE_ISP_CTRL00, val);
1244 }
1245
1246 static int ov2659_s_ctrl(struct v4l2_ctrl *ctrl)
1247 {
1248 struct ov2659 *ov2659 =
1249 container_of(ctrl->handler, struct ov2659, ctrls);
1250
1251 switch (ctrl->id) {
1252 case V4L2_CID_TEST_PATTERN:
1253 return ov2659_set_test_pattern(ov2659, ctrl->val);
1254 }
1255
1256 return 0;
1257 }
1258
1259 static const struct v4l2_ctrl_ops ov2659_ctrl_ops = {
1260 .s_ctrl = ov2659_s_ctrl,
1261 };
1262
1263 static const char * const ov2659_test_pattern_menu[] = {
1264 "Disabled",
1265 "Vertical Color Bars",
1266 };
1267
1268
1269
1270
1271
1272 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1273 static int ov2659_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1274 {
1275 struct i2c_client *client = v4l2_get_subdevdata(sd);
1276 struct v4l2_mbus_framefmt *format =
1277 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1278
1279 dev_dbg(&client->dev, "%s:\n", __func__);
1280
1281 ov2659_get_default_format(format);
1282
1283 return 0;
1284 }
1285 #endif
1286
1287 static const struct v4l2_subdev_core_ops ov2659_subdev_core_ops = {
1288 .log_status = v4l2_ctrl_subdev_log_status,
1289 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1290 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1291 };
1292
1293 static const struct v4l2_subdev_video_ops ov2659_subdev_video_ops = {
1294 .s_stream = ov2659_s_stream,
1295 };
1296
1297 static const struct v4l2_subdev_pad_ops ov2659_subdev_pad_ops = {
1298 .enum_mbus_code = ov2659_enum_mbus_code,
1299 .enum_frame_size = ov2659_enum_frame_sizes,
1300 .get_fmt = ov2659_get_fmt,
1301 .set_fmt = ov2659_set_fmt,
1302 };
1303
1304 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1305 static const struct v4l2_subdev_ops ov2659_subdev_ops = {
1306 .core = &ov2659_subdev_core_ops,
1307 .video = &ov2659_subdev_video_ops,
1308 .pad = &ov2659_subdev_pad_ops,
1309 };
1310
1311 static const struct v4l2_subdev_internal_ops ov2659_subdev_internal_ops = {
1312 .open = ov2659_open,
1313 };
1314 #endif
1315
1316 static int ov2659_detect(struct v4l2_subdev *sd)
1317 {
1318 struct i2c_client *client = v4l2_get_subdevdata(sd);
1319 u8 pid = 0;
1320 u8 ver = 0;
1321 int ret;
1322
1323 dev_dbg(&client->dev, "%s:\n", __func__);
1324
1325 ret = ov2659_write(client, REG_SOFTWARE_RESET, 0x01);
1326 if (ret != 0) {
1327 dev_err(&client->dev, "Sensor soft reset failed\n");
1328 return -ENODEV;
1329 }
1330 usleep_range(1000, 2000);
1331
1332
1333 ret = ov2659_read(client, REG_SC_CHIP_ID_H, &pid);
1334 if (!ret)
1335 ret = ov2659_read(client, REG_SC_CHIP_ID_L, &ver);
1336
1337 if (!ret) {
1338 unsigned short id;
1339
1340 id = OV265X_ID(pid, ver);
1341 if (id != OV2659_ID)
1342 dev_err(&client->dev,
1343 "Sensor detection failed (%04X, %d)\n",
1344 id, ret);
1345 else {
1346 dev_info(&client->dev, "Found OV%04X sensor\n", id);
1347 ret = ov2659_init(sd, 0);
1348 }
1349 }
1350
1351 return ret;
1352 }
1353
1354 static struct ov2659_platform_data *
1355 ov2659_get_pdata(struct i2c_client *client)
1356 {
1357 struct ov2659_platform_data *pdata;
1358 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
1359 struct device_node *endpoint;
1360 int ret;
1361
1362 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
1363 return client->dev.platform_data;
1364
1365 endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL);
1366 if (!endpoint)
1367 return NULL;
1368
1369 ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(endpoint),
1370 &bus_cfg);
1371 if (ret) {
1372 pdata = NULL;
1373 goto done;
1374 }
1375
1376 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1377 if (!pdata)
1378 goto done;
1379
1380 if (!bus_cfg.nr_of_link_frequencies) {
1381 dev_err(&client->dev,
1382 "link-frequencies property not found or too many\n");
1383 pdata = NULL;
1384 goto done;
1385 }
1386
1387 pdata->link_frequency = bus_cfg.link_frequencies[0];
1388
1389 done:
1390 v4l2_fwnode_endpoint_free(&bus_cfg);
1391 of_node_put(endpoint);
1392 return pdata;
1393 }
1394
1395 static int ov2659_probe(struct i2c_client *client)
1396 {
1397 const struct ov2659_platform_data *pdata = ov2659_get_pdata(client);
1398 struct v4l2_subdev *sd;
1399 struct ov2659 *ov2659;
1400 struct clk *clk;
1401 int ret;
1402
1403 if (!pdata) {
1404 dev_err(&client->dev, "platform data not specified\n");
1405 return -EINVAL;
1406 }
1407
1408 ov2659 = devm_kzalloc(&client->dev, sizeof(*ov2659), GFP_KERNEL);
1409 if (!ov2659)
1410 return -ENOMEM;
1411
1412 ov2659->pdata = pdata;
1413 ov2659->client = client;
1414
1415 clk = devm_clk_get(&client->dev, "xvclk");
1416 if (IS_ERR(clk))
1417 return PTR_ERR(clk);
1418
1419 ov2659->xvclk_frequency = clk_get_rate(clk);
1420 if (ov2659->xvclk_frequency < 6000000 ||
1421 ov2659->xvclk_frequency > 27000000)
1422 return -EINVAL;
1423
1424 v4l2_ctrl_handler_init(&ov2659->ctrls, 2);
1425 ov2659->link_frequency =
1426 v4l2_ctrl_new_std(&ov2659->ctrls, &ov2659_ctrl_ops,
1427 V4L2_CID_PIXEL_RATE,
1428 pdata->link_frequency / 2,
1429 pdata->link_frequency, 1,
1430 pdata->link_frequency);
1431 v4l2_ctrl_new_std_menu_items(&ov2659->ctrls, &ov2659_ctrl_ops,
1432 V4L2_CID_TEST_PATTERN,
1433 ARRAY_SIZE(ov2659_test_pattern_menu) - 1,
1434 0, 0, ov2659_test_pattern_menu);
1435 ov2659->sd.ctrl_handler = &ov2659->ctrls;
1436
1437 if (ov2659->ctrls.error) {
1438 dev_err(&client->dev, "%s: control initialization error %d\n",
1439 __func__, ov2659->ctrls.error);
1440 return ov2659->ctrls.error;
1441 }
1442
1443 sd = &ov2659->sd;
1444 client->flags |= I2C_CLIENT_SCCB;
1445 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1446 v4l2_i2c_subdev_init(sd, client, &ov2659_subdev_ops);
1447
1448 sd->internal_ops = &ov2659_subdev_internal_ops;
1449 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1450 V4L2_SUBDEV_FL_HAS_EVENTS;
1451 #endif
1452
1453 #if defined(CONFIG_MEDIA_CONTROLLER)
1454 ov2659->pad.flags = MEDIA_PAD_FL_SOURCE;
1455 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1456 ret = media_entity_pads_init(&sd->entity, 1, &ov2659->pad);
1457 if (ret < 0) {
1458 v4l2_ctrl_handler_free(&ov2659->ctrls);
1459 return ret;
1460 }
1461 #endif
1462
1463 mutex_init(&ov2659->lock);
1464
1465 ov2659_get_default_format(&ov2659->format);
1466 ov2659->frame_size = &ov2659_framesizes[2];
1467 ov2659->format_ctrl_regs = ov2659_formats[0].format_ctrl_regs;
1468
1469 ret = ov2659_detect(sd);
1470 if (ret < 0)
1471 goto error;
1472
1473
1474 ov2659_pll_calc_params(ov2659);
1475
1476 ret = v4l2_async_register_subdev(&ov2659->sd);
1477 if (ret)
1478 goto error;
1479
1480 dev_info(&client->dev, "%s sensor driver registered !!\n", sd->name);
1481
1482 return 0;
1483
1484 error:
1485 v4l2_ctrl_handler_free(&ov2659->ctrls);
1486 media_entity_cleanup(&sd->entity);
1487 mutex_destroy(&ov2659->lock);
1488 return ret;
1489 }
1490
1491 static int ov2659_remove(struct i2c_client *client)
1492 {
1493 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1494 struct ov2659 *ov2659 = to_ov2659(sd);
1495
1496 v4l2_ctrl_handler_free(&ov2659->ctrls);
1497 v4l2_async_unregister_subdev(sd);
1498 media_entity_cleanup(&sd->entity);
1499 mutex_destroy(&ov2659->lock);
1500
1501 return 0;
1502 }
1503
1504 static const struct i2c_device_id ov2659_id[] = {
1505 { "ov2659", 0 },
1506 { },
1507 };
1508 MODULE_DEVICE_TABLE(i2c, ov2659_id);
1509
1510 #if IS_ENABLED(CONFIG_OF)
1511 static const struct of_device_id ov2659_of_match[] = {
1512 { .compatible = "ovti,ov2659", },
1513 { },
1514 };
1515 MODULE_DEVICE_TABLE(of, ov2659_of_match);
1516 #endif
1517
1518 static struct i2c_driver ov2659_i2c_driver = {
1519 .driver = {
1520 .name = DRIVER_NAME,
1521 .of_match_table = of_match_ptr(ov2659_of_match),
1522 },
1523 .probe_new = ov2659_probe,
1524 .remove = ov2659_remove,
1525 .id_table = ov2659_id,
1526 };
1527
1528 module_i2c_driver(ov2659_i2c_driver);
1529
1530 MODULE_AUTHOR("Benoit Parrot <bparrot@ti.com>");
1531 MODULE_DESCRIPTION("OV2659 CMOS Image Sensor driver");
1532 MODULE_LICENSE("GPL v2");