drivers/media/i2c/adv748x/adv748x-hdmi.c

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This source file includes following definitions.
adv748x_hdmi_fill_format
adv748x_fill_optional_dv_timings
adv748x_hdmi_has_signal
adv748x_hdmi_read_pixelclock
adv748x_hdmi_set_de_timings
adv748x_hdmi_set_video_timings
adv748x_hdmi_s_dv_timings
adv748x_hdmi_g_dv_timings
adv748x_hdmi_query_dv_timings
adv748x_hdmi_g_input_status
adv748x_hdmi_s_stream
adv748x_hdmi_g_pixelaspect
adv748x_hdmi_propagate_pixelrate
adv748x_hdmi_enum_mbus_code
adv748x_hdmi_get_format
adv748x_hdmi_set_format
adv748x_hdmi_get_edid
adv748x_hdmi_edid_write_block
adv748x_hdmi_set_edid
adv748x_hdmi_check_dv_timings
adv748x_hdmi_enum_dv_timings
adv748x_hdmi_dv_timings_cap
adv748x_hdmi_s_ctrl
adv748x_hdmi_init_controls
adv748x_hdmi_init
adv748x_hdmi_cleanup
   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for Analog Devices ADV748X HDMI receiver and Component Processor (CP)
   4  *
   5  * Copyright (C) 2017 Renesas Electronics Corp.
   6  */
   7 
   8 #include <linux/module.h>
   9 #include <linux/mutex.h>
  10 
  11 #include <media/v4l2-ctrls.h>
  12 #include <media/v4l2-device.h>
  13 #include <media/v4l2-dv-timings.h>
  14 #include <media/v4l2-ioctl.h>
  15 
  16 #include <uapi/linux/v4l2-dv-timings.h>
  17 
  18 #include "adv748x.h"
  19 
  20 /* -----------------------------------------------------------------------------
  21  * HDMI and CP
  22  */
  23 
  24 #define ADV748X_HDMI_MIN_WIDTH          640
  25 #define ADV748X_HDMI_MAX_WIDTH          1920
  26 #define ADV748X_HDMI_MIN_HEIGHT         480
  27 #define ADV748X_HDMI_MAX_HEIGHT         1200
  28 
  29 /* V4L2_DV_BT_CEA_720X480I59_94 - 0.5 MHz */
  30 #define ADV748X_HDMI_MIN_PIXELCLOCK     13000000
  31 /* V4L2_DV_BT_DMT_1600X1200P60 */
  32 #define ADV748X_HDMI_MAX_PIXELCLOCK     162000000
  33 
  34 static const struct v4l2_dv_timings_cap adv748x_hdmi_timings_cap = {
  35         .type = V4L2_DV_BT_656_1120,
  36         /* keep this initialization for compatibility with GCC < 4.4.6 */
  37         .reserved = { 0 },
  38 
  39         V4L2_INIT_BT_TIMINGS(ADV748X_HDMI_MIN_WIDTH, ADV748X_HDMI_MAX_WIDTH,
  40                              ADV748X_HDMI_MIN_HEIGHT, ADV748X_HDMI_MAX_HEIGHT,
  41                              ADV748X_HDMI_MIN_PIXELCLOCK,
  42                              ADV748X_HDMI_MAX_PIXELCLOCK,
  43                              V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT,
  44                              V4L2_DV_BT_CAP_PROGRESSIVE)
  45 };
  46 
  47 struct adv748x_hdmi_video_standards {
  48         struct v4l2_dv_timings timings;
  49         u8 vid_std;
  50         u8 v_freq;
  51 };
  52 
  53 static const struct adv748x_hdmi_video_standards
  54 adv748x_hdmi_video_standards[] = {
  55         { V4L2_DV_BT_CEA_720X480P59_94, 0x4a, 0x00 },
  56         { V4L2_DV_BT_CEA_720X576P50, 0x4b, 0x00 },
  57         { V4L2_DV_BT_CEA_1280X720P60, 0x53, 0x00 },
  58         { V4L2_DV_BT_CEA_1280X720P50, 0x53, 0x01 },
  59         { V4L2_DV_BT_CEA_1280X720P30, 0x53, 0x02 },
  60         { V4L2_DV_BT_CEA_1280X720P25, 0x53, 0x03 },
  61         { V4L2_DV_BT_CEA_1280X720P24, 0x53, 0x04 },
  62         { V4L2_DV_BT_CEA_1920X1080P60, 0x5e, 0x00 },
  63         { V4L2_DV_BT_CEA_1920X1080P50, 0x5e, 0x01 },
  64         { V4L2_DV_BT_CEA_1920X1080P30, 0x5e, 0x02 },
  65         { V4L2_DV_BT_CEA_1920X1080P25, 0x5e, 0x03 },
  66         { V4L2_DV_BT_CEA_1920X1080P24, 0x5e, 0x04 },
  67         /* SVGA */
  68         { V4L2_DV_BT_DMT_800X600P56, 0x80, 0x00 },
  69         { V4L2_DV_BT_DMT_800X600P60, 0x81, 0x00 },
  70         { V4L2_DV_BT_DMT_800X600P72, 0x82, 0x00 },
  71         { V4L2_DV_BT_DMT_800X600P75, 0x83, 0x00 },
  72         { V4L2_DV_BT_DMT_800X600P85, 0x84, 0x00 },
  73         /* SXGA */
  74         { V4L2_DV_BT_DMT_1280X1024P60, 0x85, 0x00 },
  75         { V4L2_DV_BT_DMT_1280X1024P75, 0x86, 0x00 },
  76         /* VGA */
  77         { V4L2_DV_BT_DMT_640X480P60, 0x88, 0x00 },
  78         { V4L2_DV_BT_DMT_640X480P72, 0x89, 0x00 },
  79         { V4L2_DV_BT_DMT_640X480P75, 0x8a, 0x00 },
  80         { V4L2_DV_BT_DMT_640X480P85, 0x8b, 0x00 },
  81         /* XGA */
  82         { V4L2_DV_BT_DMT_1024X768P60, 0x8c, 0x00 },
  83         { V4L2_DV_BT_DMT_1024X768P70, 0x8d, 0x00 },
  84         { V4L2_DV_BT_DMT_1024X768P75, 0x8e, 0x00 },
  85         { V4L2_DV_BT_DMT_1024X768P85, 0x8f, 0x00 },
  86         /* UXGA */
  87         { V4L2_DV_BT_DMT_1600X1200P60, 0x96, 0x00 },
  88 };
  89 
  90 static void adv748x_hdmi_fill_format(struct adv748x_hdmi *hdmi,
  91                                      struct v4l2_mbus_framefmt *fmt)
  92 {
  93         memset(fmt, 0, sizeof(*fmt));
  94 
  95         fmt->code = MEDIA_BUS_FMT_RGB888_1X24;
  96         fmt->field = hdmi->timings.bt.interlaced ?
  97                         V4L2_FIELD_ALTERNATE : V4L2_FIELD_NONE;
  98 
  99         /* TODO: The colorspace depends on the AVI InfoFrame contents */
 100         fmt->colorspace = V4L2_COLORSPACE_SRGB;
 101 
 102         fmt->width = hdmi->timings.bt.width;
 103         fmt->height = hdmi->timings.bt.height;
 104 
 105         if (fmt->field == V4L2_FIELD_ALTERNATE)
 106                 fmt->height /= 2;
 107 }
 108 
 109 static void adv748x_fill_optional_dv_timings(struct v4l2_dv_timings *timings)
 110 {
 111         v4l2_find_dv_timings_cap(timings, &adv748x_hdmi_timings_cap,
 112                                  250000, NULL, NULL);
 113 }
 114 
 115 static bool adv748x_hdmi_has_signal(struct adv748x_state *state)
 116 {
 117         int val;
 118 
 119         /* Check that VERT_FILTER and DE_REGEN is locked */
 120         val = hdmi_read(state, ADV748X_HDMI_LW1);
 121         return (val & ADV748X_HDMI_LW1_VERT_FILTER) &&
 122                (val & ADV748X_HDMI_LW1_DE_REGEN);
 123 }
 124 
 125 static int adv748x_hdmi_read_pixelclock(struct adv748x_state *state)
 126 {
 127         int a, b;
 128 
 129         a = hdmi_read(state, ADV748X_HDMI_TMDS_1);
 130         b = hdmi_read(state, ADV748X_HDMI_TMDS_2);
 131         if (a < 0 || b < 0)
 132                 return -ENODATA;
 133 
 134         /*
 135          * The high 9 bits store TMDS frequency measurement in MHz
 136          * The low 7 bits of TMDS_2 store the 7-bit TMDS fractional frequency
 137          * measurement in 1/128 MHz
 138          */
 139         return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
 140 }
 141 
 142 /*
 143  * adv748x_hdmi_set_de_timings: Adjust horizontal picture offset through DE
 144  *
 145  * HDMI CP uses a Data Enable synchronisation timing reference
 146  *
 147  * Vary the leading and trailing edge position of the DE signal output by the CP
 148  * core. Values are stored as signed-twos-complement in one-pixel-clock units
 149  *
 150  * The start and end are shifted equally by the 10-bit shift value.
 151  */
 152 static void adv748x_hdmi_set_de_timings(struct adv748x_state *state, int shift)
 153 {
 154         u8 high, low;
 155 
 156         /* POS_HIGH stores bits 8 and 9 of both the start and end */
 157         high = ADV748X_CP_DE_POS_HIGH_SET;
 158         high |= (shift & 0x300) >> 8;
 159         low = shift & 0xff;
 160 
 161         /* The sequence of the writes is important and must be followed */
 162         cp_write(state, ADV748X_CP_DE_POS_HIGH, high);
 163         cp_write(state, ADV748X_CP_DE_POS_END_LOW, low);
 164 
 165         high |= (shift & 0x300) >> 6;
 166 
 167         cp_write(state, ADV748X_CP_DE_POS_HIGH, high);
 168         cp_write(state, ADV748X_CP_DE_POS_START_LOW, low);
 169 }
 170 
 171 static int adv748x_hdmi_set_video_timings(struct adv748x_state *state,
 172                                           const struct v4l2_dv_timings *timings)
 173 {
 174         const struct adv748x_hdmi_video_standards *stds =
 175                 adv748x_hdmi_video_standards;
 176         unsigned int i;
 177 
 178         for (i = 0; i < ARRAY_SIZE(adv748x_hdmi_video_standards); i++) {
 179                 if (!v4l2_match_dv_timings(timings, &stds[i].timings, 250000,
 180                                            false))
 181                         continue;
 182         }
 183 
 184         if (i >= ARRAY_SIZE(adv748x_hdmi_video_standards))
 185                 return -EINVAL;
 186 
 187         /*
 188          * When setting cp_vid_std to either 720p, 1080i, or 1080p, the video
 189          * will get shifted horizontally to the left in active video mode.
 190          * The de_h_start and de_h_end controls are used to centre the picture
 191          * correctly
 192          */
 193         switch (stds[i].vid_std) {
 194         case 0x53: /* 720p */
 195                 adv748x_hdmi_set_de_timings(state, -40);
 196                 break;
 197         case 0x54: /* 1080i */
 198         case 0x5e: /* 1080p */
 199                 adv748x_hdmi_set_de_timings(state, -44);
 200                 break;
 201         default:
 202                 adv748x_hdmi_set_de_timings(state, 0);
 203                 break;
 204         }
 205 
 206         io_write(state, ADV748X_IO_VID_STD, stds[i].vid_std);
 207         io_clrset(state, ADV748X_IO_DATAPATH, ADV748X_IO_DATAPATH_VFREQ_M,
 208                   stds[i].v_freq << ADV748X_IO_DATAPATH_VFREQ_SHIFT);
 209 
 210         return 0;
 211 }
 212 
 213 /* -----------------------------------------------------------------------------
 214  * v4l2_subdev_video_ops
 215  */
 216 
 217 static int adv748x_hdmi_s_dv_timings(struct v4l2_subdev *sd,
 218                                      struct v4l2_dv_timings *timings)
 219 {
 220         struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd);
 221         struct adv748x_state *state = adv748x_hdmi_to_state(hdmi);
 222         int ret;
 223 
 224         if (!timings)
 225                 return -EINVAL;
 226 
 227         if (v4l2_match_dv_timings(&hdmi->timings, timings, 0, false))
 228                 return 0;
 229 
 230         if (!v4l2_valid_dv_timings(timings, &adv748x_hdmi_timings_cap,
 231                                    NULL, NULL))
 232                 return -ERANGE;
 233 
 234         adv748x_fill_optional_dv_timings(timings);
 235 
 236         mutex_lock(&state->mutex);
 237 
 238         ret = adv748x_hdmi_set_video_timings(state, timings);
 239         if (ret)
 240                 goto error;
 241 
 242         hdmi->timings = *timings;
 243 
 244         cp_clrset(state, ADV748X_CP_VID_ADJ_2, ADV748X_CP_VID_ADJ_2_INTERLACED,
 245                   timings->bt.interlaced ?
 246                                   ADV748X_CP_VID_ADJ_2_INTERLACED : 0);
 247 
 248         mutex_unlock(&state->mutex);
 249 
 250         return 0;
 251 
 252 error:
 253         mutex_unlock(&state->mutex);
 254         return ret;
 255 }
 256 
 257 static int adv748x_hdmi_g_dv_timings(struct v4l2_subdev *sd,
 258                                      struct v4l2_dv_timings *timings)
 259 {
 260         struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd);
 261         struct adv748x_state *state = adv748x_hdmi_to_state(hdmi);
 262 
 263         mutex_lock(&state->mutex);
 264 
 265         *timings = hdmi->timings;
 266 
 267         mutex_unlock(&state->mutex);
 268 
 269         return 0;
 270 }
 271 
 272 static int adv748x_hdmi_query_dv_timings(struct v4l2_subdev *sd,
 273                                          struct v4l2_dv_timings *timings)
 274 {
 275         struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd);
 276         struct adv748x_state *state = adv748x_hdmi_to_state(hdmi);
 277         struct v4l2_bt_timings *bt = &timings->bt;
 278         int pixelclock;
 279         int polarity;
 280 
 281         if (!timings)
 282                 return -EINVAL;
 283 
 284         memset(timings, 0, sizeof(struct v4l2_dv_timings));
 285 
 286         if (!adv748x_hdmi_has_signal(state))
 287                 return -ENOLINK;
 288 
 289         pixelclock = adv748x_hdmi_read_pixelclock(state);
 290         if (pixelclock < 0)
 291                 return -ENODATA;
 292 
 293         timings->type = V4L2_DV_BT_656_1120;
 294 
 295         bt->pixelclock = pixelclock;
 296         bt->interlaced = hdmi_read(state, ADV748X_HDMI_F1H1) &
 297                                 ADV748X_HDMI_F1H1_INTERLACED ?
 298                                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
 299         bt->width = hdmi_read16(state, ADV748X_HDMI_LW1,
 300                                 ADV748X_HDMI_LW1_WIDTH_MASK);
 301         bt->height = hdmi_read16(state, ADV748X_HDMI_F0H1,
 302                                  ADV748X_HDMI_F0H1_HEIGHT_MASK);
 303         bt->hfrontporch = hdmi_read16(state, ADV748X_HDMI_HFRONT_PORCH,
 304                                       ADV748X_HDMI_HFRONT_PORCH_MASK);
 305         bt->hsync = hdmi_read16(state, ADV748X_HDMI_HSYNC_WIDTH,
 306                                 ADV748X_HDMI_HSYNC_WIDTH_MASK);
 307         bt->hbackporch = hdmi_read16(state, ADV748X_HDMI_HBACK_PORCH,
 308                                      ADV748X_HDMI_HBACK_PORCH_MASK);
 309         bt->vfrontporch = hdmi_read16(state, ADV748X_HDMI_VFRONT_PORCH,
 310                                       ADV748X_HDMI_VFRONT_PORCH_MASK) / 2;
 311         bt->vsync = hdmi_read16(state, ADV748X_HDMI_VSYNC_WIDTH,
 312                                 ADV748X_HDMI_VSYNC_WIDTH_MASK) / 2;
 313         bt->vbackporch = hdmi_read16(state, ADV748X_HDMI_VBACK_PORCH,
 314                                      ADV748X_HDMI_VBACK_PORCH_MASK) / 2;
 315 
 316         polarity = hdmi_read(state, 0x05);
 317         bt->polarities = (polarity & BIT(4) ? V4L2_DV_VSYNC_POS_POL : 0) |
 318                 (polarity & BIT(5) ? V4L2_DV_HSYNC_POS_POL : 0);
 319 
 320         if (bt->interlaced == V4L2_DV_INTERLACED) {
 321                 bt->height += hdmi_read16(state, 0x0b, 0x1fff);
 322                 bt->il_vfrontporch = hdmi_read16(state, 0x2c, 0x3fff) / 2;
 323                 bt->il_vsync = hdmi_read16(state, 0x30, 0x3fff) / 2;
 324                 bt->il_vbackporch = hdmi_read16(state, 0x34, 0x3fff) / 2;
 325         }
 326 
 327         adv748x_fill_optional_dv_timings(timings);
 328 
 329         /*
 330          * No interrupt handling is implemented yet.
 331          * There should be an IRQ when a cable is plugged and the new timings
 332          * should be figured out and stored to state.
 333          */
 334         hdmi->timings = *timings;
 335 
 336         return 0;
 337 }
 338 
 339 static int adv748x_hdmi_g_input_status(struct v4l2_subdev *sd, u32 *status)
 340 {
 341         struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd);
 342         struct adv748x_state *state = adv748x_hdmi_to_state(hdmi);
 343 
 344         mutex_lock(&state->mutex);
 345 
 346         *status = adv748x_hdmi_has_signal(state) ? 0 : V4L2_IN_ST_NO_SIGNAL;
 347 
 348         mutex_unlock(&state->mutex);
 349 
 350         return 0;
 351 }
 352 
 353 static int adv748x_hdmi_s_stream(struct v4l2_subdev *sd, int enable)
 354 {
 355         struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd);
 356         struct adv748x_state *state = adv748x_hdmi_to_state(hdmi);
 357         int ret;
 358 
 359         mutex_lock(&state->mutex);
 360 
 361         ret = adv748x_tx_power(hdmi->tx, enable);
 362         if (ret)
 363                 goto done;
 364 
 365         if (adv748x_hdmi_has_signal(state))
 366                 adv_dbg(state, "Detected HDMI signal\n");
 367         else
 368                 adv_dbg(state, "Couldn't detect HDMI video signal\n");
 369 
 370 done:
 371         mutex_unlock(&state->mutex);
 372         return ret;
 373 }
 374 
 375 static int adv748x_hdmi_g_pixelaspect(struct v4l2_subdev *sd,
 376                                       struct v4l2_fract *aspect)
 377 {
 378         aspect->numerator = 1;
 379         aspect->denominator = 1;
 380 
 381         return 0;
 382 }
 383 
 384 static const struct v4l2_subdev_video_ops adv748x_video_ops_hdmi = {
 385         .s_dv_timings = adv748x_hdmi_s_dv_timings,
 386         .g_dv_timings = adv748x_hdmi_g_dv_timings,
 387         .query_dv_timings = adv748x_hdmi_query_dv_timings,
 388         .g_input_status = adv748x_hdmi_g_input_status,
 389         .s_stream = adv748x_hdmi_s_stream,
 390         .g_pixelaspect = adv748x_hdmi_g_pixelaspect,
 391 };
 392 
 393 /* -----------------------------------------------------------------------------
 394  * v4l2_subdev_pad_ops
 395  */
 396 
 397 static int adv748x_hdmi_propagate_pixelrate(struct adv748x_hdmi *hdmi)
 398 {
 399         struct v4l2_subdev *tx;
 400         struct v4l2_dv_timings timings;
 401 
 402         tx = adv748x_get_remote_sd(&hdmi->pads[ADV748X_HDMI_SOURCE]);
 403         if (!tx)
 404                 return -ENOLINK;
 405 
 406         adv748x_hdmi_query_dv_timings(&hdmi->sd, &timings);
 407 
 408         return adv748x_csi2_set_pixelrate(tx, timings.bt.pixelclock);
 409 }
 410 
 411 static int adv748x_hdmi_enum_mbus_code(struct v4l2_subdev *sd,
 412                                   struct v4l2_subdev_pad_config *cfg,
 413                                   struct v4l2_subdev_mbus_code_enum *code)
 414 {
 415         if (code->index != 0)
 416                 return -EINVAL;
 417 
 418         code->code = MEDIA_BUS_FMT_RGB888_1X24;
 419 
 420         return 0;
 421 }
 422 
 423 static int adv748x_hdmi_get_format(struct v4l2_subdev *sd,
 424                                    struct v4l2_subdev_pad_config *cfg,
 425                                    struct v4l2_subdev_format *sdformat)
 426 {
 427         struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd);
 428         struct v4l2_mbus_framefmt *mbusformat;
 429 
 430         if (sdformat->pad != ADV748X_HDMI_SOURCE)
 431                 return -EINVAL;
 432 
 433         if (sdformat->which == V4L2_SUBDEV_FORMAT_TRY) {
 434                 mbusformat = v4l2_subdev_get_try_format(sd, cfg, sdformat->pad);
 435                 sdformat->format = *mbusformat;
 436         } else {
 437                 adv748x_hdmi_fill_format(hdmi, &sdformat->format);
 438                 adv748x_hdmi_propagate_pixelrate(hdmi);
 439         }
 440 
 441         return 0;
 442 }
 443 
 444 static int adv748x_hdmi_set_format(struct v4l2_subdev *sd,
 445                                    struct v4l2_subdev_pad_config *cfg,
 446                                    struct v4l2_subdev_format *sdformat)
 447 {
 448         struct v4l2_mbus_framefmt *mbusformat;
 449 
 450         if (sdformat->pad != ADV748X_HDMI_SOURCE)
 451                 return -EINVAL;
 452 
 453         if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
 454                 return adv748x_hdmi_get_format(sd, cfg, sdformat);
 455 
 456         mbusformat = v4l2_subdev_get_try_format(sd, cfg, sdformat->pad);
 457         *mbusformat = sdformat->format;
 458 
 459         return 0;
 460 }
 461 
 462 static int adv748x_hdmi_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
 463 {
 464         struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd);
 465 
 466         memset(edid->reserved, 0, sizeof(edid->reserved));
 467 
 468         if (!hdmi->edid.present)
 469                 return -ENODATA;
 470 
 471         if (edid->start_block == 0 && edid->blocks == 0) {
 472                 edid->blocks = hdmi->edid.blocks;
 473                 return 0;
 474         }
 475 
 476         if (edid->start_block >= hdmi->edid.blocks)
 477                 return -EINVAL;
 478 
 479         if (edid->start_block + edid->blocks > hdmi->edid.blocks)
 480                 edid->blocks = hdmi->edid.blocks - edid->start_block;
 481 
 482         memcpy(edid->edid, hdmi->edid.edid + edid->start_block * 128,
 483                         edid->blocks * 128);
 484 
 485         return 0;
 486 }
 487 
 488 static inline int adv748x_hdmi_edid_write_block(struct adv748x_hdmi *hdmi,
 489                                         unsigned int total_len, const u8 *val)
 490 {
 491         struct adv748x_state *state = adv748x_hdmi_to_state(hdmi);
 492         int err = 0;
 493         int i = 0;
 494         int len = 0;
 495 
 496         adv_dbg(state, "%s: write EDID block (%d byte)\n",
 497                                 __func__, total_len);
 498 
 499         while (!err && i < total_len) {
 500                 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
 501                                 I2C_SMBUS_BLOCK_MAX :
 502                                 (total_len - i);
 503 
 504                 err = adv748x_write_block(state, ADV748X_PAGE_EDID,
 505                                 i, val + i, len);
 506                 i += len;
 507         }
 508 
 509         return err;
 510 }
 511 
 512 static int adv748x_hdmi_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
 513 {
 514         struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd);
 515         struct adv748x_state *state = adv748x_hdmi_to_state(hdmi);
 516         int err;
 517 
 518         memset(edid->reserved, 0, sizeof(edid->reserved));
 519 
 520         if (edid->start_block != 0)
 521                 return -EINVAL;
 522 
 523         if (edid->blocks == 0) {
 524                 hdmi->edid.blocks = 0;
 525                 hdmi->edid.present = 0;
 526 
 527                 /* Fall back to a 16:9 aspect ratio */
 528                 hdmi->aspect_ratio.numerator = 16;
 529                 hdmi->aspect_ratio.denominator = 9;
 530 
 531                 /* Disable the EDID */
 532                 repeater_write(state, ADV748X_REPEATER_EDID_SZ,
 533                                edid->blocks << ADV748X_REPEATER_EDID_SZ_SHIFT);
 534 
 535                 repeater_write(state, ADV748X_REPEATER_EDID_CTL, 0);
 536 
 537                 return 0;
 538         }
 539 
 540         if (edid->blocks > 4) {
 541                 edid->blocks = 4;
 542                 return -E2BIG;
 543         }
 544 
 545         memcpy(hdmi->edid.edid, edid->edid, 128 * edid->blocks);
 546         hdmi->edid.blocks = edid->blocks;
 547         hdmi->edid.present = true;
 548 
 549         hdmi->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
 550                         edid->edid[0x16]);
 551 
 552         err = adv748x_hdmi_edid_write_block(hdmi, 128 * edid->blocks,
 553                         hdmi->edid.edid);
 554         if (err < 0) {
 555                 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
 556                 return err;
 557         }
 558 
 559         repeater_write(state, ADV748X_REPEATER_EDID_SZ,
 560                        edid->blocks << ADV748X_REPEATER_EDID_SZ_SHIFT);
 561 
 562         repeater_write(state, ADV748X_REPEATER_EDID_CTL,
 563                        ADV748X_REPEATER_EDID_CTL_EN);
 564 
 565         return 0;
 566 }
 567 
 568 static bool adv748x_hdmi_check_dv_timings(const struct v4l2_dv_timings *timings,
 569                                           void *hdl)
 570 {
 571         const struct adv748x_hdmi_video_standards *stds =
 572                 adv748x_hdmi_video_standards;
 573         unsigned int i;
 574 
 575         for (i = 0; stds[i].timings.bt.width; i++)
 576                 if (v4l2_match_dv_timings(timings, &stds[i].timings, 0, false))
 577                         return true;
 578 
 579         return false;
 580 }
 581 
 582 static int adv748x_hdmi_enum_dv_timings(struct v4l2_subdev *sd,
 583                                         struct v4l2_enum_dv_timings *timings)
 584 {
 585         return v4l2_enum_dv_timings_cap(timings, &adv748x_hdmi_timings_cap,
 586                                         adv748x_hdmi_check_dv_timings, NULL);
 587 }
 588 
 589 static int adv748x_hdmi_dv_timings_cap(struct v4l2_subdev *sd,
 590                                        struct v4l2_dv_timings_cap *cap)
 591 {
 592         *cap = adv748x_hdmi_timings_cap;
 593         return 0;
 594 }
 595 
 596 static const struct v4l2_subdev_pad_ops adv748x_pad_ops_hdmi = {
 597         .enum_mbus_code = adv748x_hdmi_enum_mbus_code,
 598         .set_fmt = adv748x_hdmi_set_format,
 599         .get_fmt = adv748x_hdmi_get_format,
 600         .get_edid = adv748x_hdmi_get_edid,
 601         .set_edid = adv748x_hdmi_set_edid,
 602         .dv_timings_cap = adv748x_hdmi_dv_timings_cap,
 603         .enum_dv_timings = adv748x_hdmi_enum_dv_timings,
 604 };
 605 
 606 /* -----------------------------------------------------------------------------
 607  * v4l2_subdev_ops
 608  */
 609 
 610 static const struct v4l2_subdev_ops adv748x_ops_hdmi = {
 611         .video = &adv748x_video_ops_hdmi,
 612         .pad = &adv748x_pad_ops_hdmi,
 613 };
 614 
 615 /* -----------------------------------------------------------------------------
 616  * Controls
 617  */
 618 
 619 static const char * const hdmi_ctrl_patgen_menu[] = {
 620         "Disabled",
 621         "Solid Color",
 622         "Color Bars",
 623         "Ramp Grey",
 624         "Ramp Blue",
 625         "Ramp Red",
 626         "Checkered"
 627 };
 628 
 629 static int adv748x_hdmi_s_ctrl(struct v4l2_ctrl *ctrl)
 630 {
 631         struct adv748x_hdmi *hdmi = adv748x_ctrl_to_hdmi(ctrl);
 632         struct adv748x_state *state = adv748x_hdmi_to_state(hdmi);
 633         int ret;
 634         u8 pattern;
 635 
 636         /* Enable video adjustment first */
 637         ret = cp_clrset(state, ADV748X_CP_VID_ADJ,
 638                         ADV748X_CP_VID_ADJ_ENABLE,
 639                         ADV748X_CP_VID_ADJ_ENABLE);
 640         if (ret < 0)
 641                 return ret;
 642 
 643         switch (ctrl->id) {
 644         case V4L2_CID_BRIGHTNESS:
 645                 ret = cp_write(state, ADV748X_CP_BRI, ctrl->val);
 646                 break;
 647         case V4L2_CID_HUE:
 648                 ret = cp_write(state, ADV748X_CP_HUE, ctrl->val);
 649                 break;
 650         case V4L2_CID_CONTRAST:
 651                 ret = cp_write(state, ADV748X_CP_CON, ctrl->val);
 652                 break;
 653         case V4L2_CID_SATURATION:
 654                 ret = cp_write(state, ADV748X_CP_SAT, ctrl->val);
 655                 break;
 656         case V4L2_CID_TEST_PATTERN:
 657                 pattern = ctrl->val;
 658 
 659                 /* Pattern is 0-indexed. Ctrl Menu is 1-indexed */
 660                 if (pattern) {
 661                         pattern--;
 662                         pattern |= ADV748X_CP_PAT_GEN_EN;
 663                 }
 664 
 665                 ret = cp_write(state, ADV748X_CP_PAT_GEN, pattern);
 666 
 667                 break;
 668         default:
 669                 return -EINVAL;
 670         }
 671 
 672         return ret;
 673 }
 674 
 675 static const struct v4l2_ctrl_ops adv748x_hdmi_ctrl_ops = {
 676         .s_ctrl = adv748x_hdmi_s_ctrl,
 677 };
 678 
 679 static int adv748x_hdmi_init_controls(struct adv748x_hdmi *hdmi)
 680 {
 681         struct adv748x_state *state = adv748x_hdmi_to_state(hdmi);
 682 
 683         v4l2_ctrl_handler_init(&hdmi->ctrl_hdl, 5);
 684 
 685         /* Use our mutex for the controls */
 686         hdmi->ctrl_hdl.lock = &state->mutex;
 687 
 688         v4l2_ctrl_new_std(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops,
 689                           V4L2_CID_BRIGHTNESS, ADV748X_CP_BRI_MIN,
 690                           ADV748X_CP_BRI_MAX, 1, ADV748X_CP_BRI_DEF);
 691         v4l2_ctrl_new_std(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops,
 692                           V4L2_CID_CONTRAST, ADV748X_CP_CON_MIN,
 693                           ADV748X_CP_CON_MAX, 1, ADV748X_CP_CON_DEF);
 694         v4l2_ctrl_new_std(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops,
 695                           V4L2_CID_SATURATION, ADV748X_CP_SAT_MIN,
 696                           ADV748X_CP_SAT_MAX, 1, ADV748X_CP_SAT_DEF);
 697         v4l2_ctrl_new_std(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops,
 698                           V4L2_CID_HUE, ADV748X_CP_HUE_MIN,
 699                           ADV748X_CP_HUE_MAX, 1, ADV748X_CP_HUE_DEF);
 700 
 701         /*
 702          * Todo: V4L2_CID_DV_RX_POWER_PRESENT should also be supported when
 703          * interrupts are handled correctly
 704          */
 705 
 706         v4l2_ctrl_new_std_menu_items(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops,
 707                                      V4L2_CID_TEST_PATTERN,
 708                                      ARRAY_SIZE(hdmi_ctrl_patgen_menu) - 1,
 709                                      0, 0, hdmi_ctrl_patgen_menu);
 710 
 711         hdmi->sd.ctrl_handler = &hdmi->ctrl_hdl;
 712         if (hdmi->ctrl_hdl.error) {
 713                 v4l2_ctrl_handler_free(&hdmi->ctrl_hdl);
 714                 return hdmi->ctrl_hdl.error;
 715         }
 716 
 717         return v4l2_ctrl_handler_setup(&hdmi->ctrl_hdl);
 718 }
 719 
 720 int adv748x_hdmi_init(struct adv748x_hdmi *hdmi)
 721 {
 722         struct adv748x_state *state = adv748x_hdmi_to_state(hdmi);
 723         static const struct v4l2_dv_timings cea1280x720 =
 724                 V4L2_DV_BT_CEA_1280X720P30;
 725         int ret;
 726 
 727         hdmi->timings = cea1280x720;
 728 
 729         /* Initialise a default 16:9 aspect ratio */
 730         hdmi->aspect_ratio.numerator = 16;
 731         hdmi->aspect_ratio.denominator = 9;
 732 
 733         adv748x_subdev_init(&hdmi->sd, state, &adv748x_ops_hdmi,
 734                             MEDIA_ENT_F_IO_DTV, "hdmi");
 735 
 736         hdmi->pads[ADV748X_HDMI_SINK].flags = MEDIA_PAD_FL_SINK;
 737         hdmi->pads[ADV748X_HDMI_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
 738 
 739         ret = media_entity_pads_init(&hdmi->sd.entity,
 740                                      ADV748X_HDMI_NR_PADS, hdmi->pads);
 741         if (ret)
 742                 return ret;
 743 
 744         ret = adv748x_hdmi_init_controls(hdmi);
 745         if (ret)
 746                 goto err_free_media;
 747 
 748         return 0;
 749 
 750 err_free_media:
 751         media_entity_cleanup(&hdmi->sd.entity);
 752 
 753         return ret;
 754 }
 755 
 756 void adv748x_hdmi_cleanup(struct adv748x_hdmi *hdmi)
 757 {
 758         v4l2_device_unregister_subdev(&hdmi->sd);
 759         media_entity_cleanup(&hdmi->sd.entity);
 760         v4l2_ctrl_handler_free(&hdmi->ctrl_hdl);
 761 }
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root/drivers/media/i2c/adv748x/adv748x-hdmi.c

DEFINITIONS
