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16 #ifndef __TC358743_REGS_H
17 #define __TC358743_REGS_H
18
19 #define CHIPID 0x0000
20 #define MASK_CHIPID 0xff00
21 #define MASK_REVID 0x00ff
22
23 #define SYSCTL 0x0002
24 #define MASK_IRRST 0x0800
25 #define MASK_CECRST 0x0400
26 #define MASK_CTXRST 0x0200
27 #define MASK_HDMIRST 0x0100
28 #define MASK_SLEEP 0x0001
29
30 #define CONFCTL 0x0004
31 #define MASK_PWRISO 0x8000
32 #define MASK_ACLKOPT 0x1000
33 #define MASK_AUDCHNUM 0x0c00
34 #define MASK_AUDCHNUM_8 0x0000
35 #define MASK_AUDCHNUM_6 0x0400
36 #define MASK_AUDCHNUM_4 0x0800
37 #define MASK_AUDCHNUM_2 0x0c00
38 #define MASK_AUDCHSEL 0x0200
39 #define MASK_I2SDLYOPT 0x0100
40 #define MASK_YCBCRFMT 0x00c0
41 #define MASK_YCBCRFMT_444 0x0000
42 #define MASK_YCBCRFMT_422_12_BIT 0x0040
43 #define MASK_YCBCRFMT_COLORBAR 0x0080
44 #define MASK_YCBCRFMT_422_8_BIT 0x00c0
45 #define MASK_INFRMEN 0x0020
46 #define MASK_AUDOUTSEL 0x0018
47 #define MASK_AUDOUTSEL_CSI 0x0000
48 #define MASK_AUDOUTSEL_I2S 0x0010
49 #define MASK_AUDOUTSEL_TDM 0x0018
50 #define MASK_AUTOINDEX 0x0004
51 #define MASK_ABUFEN 0x0002
52 #define MASK_VBUFEN 0x0001
53
54 #define FIFOCTL 0x0006
55
56 #define INTSTATUS 0x0014
57 #define MASK_AMUTE_INT 0x0400
58 #define MASK_HDMI_INT 0x0200
59 #define MASK_CSI_INT 0x0100
60 #define MASK_SYS_INT 0x0020
61 #define MASK_CEC_EINT 0x0010
62 #define MASK_CEC_TINT 0x0008
63 #define MASK_CEC_RINT 0x0004
64 #define MASK_IR_EINT 0x0002
65 #define MASK_IR_DINT 0x0001
66
67 #define INTMASK 0x0016
68 #define MASK_AMUTE_MSK 0x0400
69 #define MASK_HDMI_MSK 0x0200
70 #define MASK_CSI_MSK 0x0100
71 #define MASK_SYS_MSK 0x0020
72 #define MASK_CEC_EMSK 0x0010
73 #define MASK_CEC_TMSK 0x0008
74 #define MASK_CEC_RMSK 0x0004
75 #define MASK_IR_EMSK 0x0002
76 #define MASK_IR_DMSK 0x0001
77
78 #define INTFLAG 0x0018
79 #define INTSYSSTATUS 0x001A
80
81 #define PLLCTL0 0x0020
82 #define MASK_PLL_PRD 0xf000
83 #define SET_PLL_PRD(prd) ((((prd) - 1) << 12) &\
84 MASK_PLL_PRD)
85 #define MASK_PLL_FBD 0x01ff
86 #define SET_PLL_FBD(fbd) (((fbd) - 1) & MASK_PLL_FBD)
87
88 #define PLLCTL1 0x0022
89 #define MASK_PLL_FRS 0x0c00
90 #define SET_PLL_FRS(frs) (((frs) << 10) & MASK_PLL_FRS)
91 #define MASK_PLL_LBWS 0x0300
92 #define MASK_LFBREN 0x0040
93 #define MASK_BYPCKEN 0x0020
94 #define MASK_CKEN 0x0010
95 #define MASK_RESETB 0x0002
96 #define MASK_PLL_EN 0x0001
97
98 #define CLW_CNTRL 0x0140
99 #define MASK_CLW_LANEDISABLE 0x0001
100
101 #define D0W_CNTRL 0x0144
102 #define MASK_D0W_LANEDISABLE 0x0001
103
104 #define D1W_CNTRL 0x0148
105 #define MASK_D1W_LANEDISABLE 0x0001
106
107 #define D2W_CNTRL 0x014C
108 #define MASK_D2W_LANEDISABLE 0x0001
109
110 #define D3W_CNTRL 0x0150
111 #define MASK_D3W_LANEDISABLE 0x0001
112
113 #define STARTCNTRL 0x0204
114 #define MASK_START 0x00000001
115
116 #define LINEINITCNT 0x0210
117 #define LPTXTIMECNT 0x0214
118 #define TCLK_HEADERCNT 0x0218
119 #define TCLK_TRAILCNT 0x021C
120 #define THS_HEADERCNT 0x0220
121 #define TWAKEUP 0x0224
122 #define TCLK_POSTCNT 0x0228
123 #define THS_TRAILCNT 0x022C
124 #define HSTXVREGCNT 0x0230
125
126 #define HSTXVREGEN 0x0234
127 #define MASK_D3M_HSTXVREGEN 0x0010
128 #define MASK_D2M_HSTXVREGEN 0x0008
129 #define MASK_D1M_HSTXVREGEN 0x0004
130 #define MASK_D0M_HSTXVREGEN 0x0002
131 #define MASK_CLM_HSTXVREGEN 0x0001
132
133
134 #define TXOPTIONCNTRL 0x0238
135 #define MASK_CONTCLKMODE 0x00000001
136
137 #define CSI_CONTROL 0x040C
138 #define MASK_CSI_MODE 0x8000
139 #define MASK_HTXTOEN 0x0400
140 #define MASK_TXHSMD 0x0080
141 #define MASK_HSCKMD 0x0020
142 #define MASK_NOL 0x0006
143 #define MASK_NOL_1 0x0000
144 #define MASK_NOL_2 0x0002
145 #define MASK_NOL_3 0x0004
146 #define MASK_NOL_4 0x0006
147 #define MASK_EOTDIS 0x0001
148
149 #define CSI_INT 0x0414
150 #define MASK_INTHLT 0x00000008
151 #define MASK_INTER 0x00000004
152
153 #define CSI_INT_ENA 0x0418
154 #define MASK_IENHLT 0x00000008
155 #define MASK_IENER 0x00000004
156
157 #define CSI_ERR 0x044C
158 #define MASK_INER 0x00000200
159 #define MASK_WCER 0x00000100
160 #define MASK_QUNK 0x00000010
161 #define MASK_TXBRK 0x00000002
162
163 #define CSI_ERR_INTENA 0x0450
164 #define CSI_ERR_HALT 0x0454
165
166 #define CSI_CONFW 0x0500
167 #define MASK_MODE 0xe0000000
168 #define MASK_MODE_SET 0xa0000000
169 #define MASK_MODE_CLEAR 0xc0000000
170 #define MASK_ADDRESS 0x1f000000
171 #define MASK_ADDRESS_CSI_CONTROL 0x03000000
172 #define MASK_ADDRESS_CSI_INT_ENA 0x06000000
173 #define MASK_ADDRESS_CSI_ERR_INTENA 0x14000000
174 #define MASK_ADDRESS_CSI_ERR_HALT 0x15000000
175 #define MASK_DATA 0x0000ffff
176
177 #define CSI_INT_CLR 0x050C
178 #define MASK_ICRER 0x00000004
179
180 #define CSI_START 0x0518
181 #define MASK_STRT 0x00000001
182
183
184 #define CECHCLK 0x0028
185 #define MASK_CECHCLK (0x7ff << 0)
186
187 #define CECLCLK 0x002a
188 #define MASK_CECLCLK (0x7ff << 0)
189
190 #define CECEN 0x0600
191 #define MASK_CECEN 0x0001
192
193 #define CECADD 0x0604
194 #define CECRST 0x0608
195 #define MASK_CECRESET 0x0001
196
197 #define CECREN 0x060c
198 #define MASK_CECREN 0x0001
199
200 #define CECRCTL1 0x0614
201 #define MASK_CECACKDIS (1 << 24)
202 #define MASK_CECHNC (3 << 20)
203 #define MASK_CECLNC (7 << 16)
204 #define MASK_CECMIN (7 << 12)
205 #define MASK_CECMAX (7 << 8)
206 #define MASK_CECDAT (7 << 4)
207 #define MASK_CECTOUT (3 << 2)
208 #define MASK_CECRIHLD (1 << 1)
209 #define MASK_CECOTH (1 << 0)
210
211 #define CECRCTL2 0x0618
212 #define MASK_CECSWAV3 (7 << 12)
213 #define MASK_CECSWAV2 (7 << 8)
214 #define MASK_CECSWAV1 (7 << 4)
215 #define MASK_CECSWAV0 (7 << 0)
216
217 #define CECRCTL3 0x061c
218 #define MASK_CECWAV3 (7 << 20)
219 #define MASK_CECWAV2 (7 << 16)
220 #define MASK_CECWAV1 (7 << 12)
221 #define MASK_CECWAV0 (7 << 8)
222 #define MASK_CECACKEI (1 << 4)
223 #define MASK_CECMINEI (1 << 3)
224 #define MASK_CECMAXEI (1 << 2)
225 #define MASK_CECRSTEI (1 << 1)
226 #define MASK_CECWAVEI (1 << 0)
227
228 #define CECTEN 0x0620
229 #define MASK_CECTBUSY (1 << 1)
230 #define MASK_CECTEN (1 << 0)
231
232 #define CECTCTL 0x0628
233 #define MASK_CECSTRS (7 << 20)
234 #define MASK_CECSPRD (7 << 16)
235 #define MASK_CECDTRS (7 << 12)
236 #define MASK_CECDPRD (15 << 8)
237 #define MASK_CECBRD (1 << 4)
238 #define MASK_CECFREE (15 << 0)
239
240 #define CECRSTAT 0x062c
241 #define MASK_CECRIWA (1 << 6)
242 #define MASK_CECRIOR (1 << 5)
243 #define MASK_CECRIACK (1 << 4)
244 #define MASK_CECRIMIN (1 << 3)
245 #define MASK_CECRIMAX (1 << 2)
246 #define MASK_CECRISTA (1 << 1)
247 #define MASK_CECRIEND (1 << 0)
248
249 #define CECTSTAT 0x0630
250 #define MASK_CECTIUR (1 << 4)
251 #define MASK_CECTIACK (1 << 3)
252 #define MASK_CECTIAL (1 << 2)
253 #define MASK_CECTIEND (1 << 1)
254
255 #define CECRBUF1 0x0634
256 #define MASK_CECRACK (1 << 9)
257 #define MASK_CECEOM (1 << 8)
258 #define MASK_CECRBYTE (0xff << 0)
259
260 #define CECTBUF1 0x0674
261 #define MASK_CECTEOM (1 << 8)
262 #define MASK_CECTBYTE (0xff << 0)
263
264 #define CECRCTR 0x06b4
265 #define MASK_CECRCTR (0x1f << 0)
266
267 #define CECIMSK 0x06c0
268 #define MASK_CECTIM (1 << 1)
269 #define MASK_CECRIM (1 << 0)
270
271 #define CECICLR 0x06cc
272 #define MASK_CECTICLR (1 << 1)
273 #define MASK_CECRICLR (1 << 0)
274
275
276 #define HDMI_INT0 0x8500
277 #define MASK_I_KEY 0x80
278 #define MASK_I_MISC 0x02
279 #define MASK_I_PHYERR 0x01
280
281 #define HDMI_INT1 0x8501
282 #define MASK_I_GBD 0x80
283 #define MASK_I_HDCP 0x40
284 #define MASK_I_ERR 0x20
285 #define MASK_I_AUD 0x10
286 #define MASK_I_CBIT 0x08
287 #define MASK_I_PACKET 0x04
288 #define MASK_I_CLK 0x02
289 #define MASK_I_SYS 0x01
290
291 #define SYS_INT 0x8502
292 #define MASK_I_ACR_CTS 0x80
293 #define MASK_I_ACRN 0x40
294 #define MASK_I_DVI 0x20
295 #define MASK_I_HDMI 0x10
296 #define MASK_I_NOPMBDET 0x08
297 #define MASK_I_DPMBDET 0x04
298 #define MASK_I_TMDS 0x02
299 #define MASK_I_DDC 0x01
300
301 #define CLK_INT 0x8503
302 #define MASK_I_OUT_H_CHG 0x40
303 #define MASK_I_IN_DE_CHG 0x20
304 #define MASK_I_IN_HV_CHG 0x10
305 #define MASK_I_DC_CHG 0x08
306 #define MASK_I_PXCLK_CHG 0x04
307 #define MASK_I_PHYCLK_CHG 0x02
308 #define MASK_I_TMDSCLK_CHG 0x01
309
310 #define CBIT_INT 0x8505
311 #define MASK_I_AF_LOCK 0x80
312 #define MASK_I_AF_UNLOCK 0x40
313 #define MASK_I_CBIT_FS 0x02
314
315 #define AUDIO_INT 0x8506
316
317 #define ERR_INT 0x8507
318 #define MASK_I_EESS_ERR 0x80
319
320 #define HDCP_INT 0x8508
321 #define MASK_I_AVM_SET 0x80
322 #define MASK_I_AVM_CLR 0x40
323 #define MASK_I_LINKERR 0x20
324 #define MASK_I_SHA_END 0x10
325 #define MASK_I_R0_END 0x08
326 #define MASK_I_KM_END 0x04
327 #define MASK_I_AKSV_END 0x02
328 #define MASK_I_AN_END 0x01
329
330 #define MISC_INT 0x850B
331 #define MASK_I_AS_LAYOUT 0x10
332 #define MASK_I_NO_SPD 0x08
333 #define MASK_I_NO_VS 0x03
334 #define MASK_I_SYNC_CHG 0x02
335 #define MASK_I_AUDIO_MUTE 0x01
336
337 #define KEY_INT 0x850F
338
339 #define SYS_INTM 0x8512
340 #define MASK_M_ACR_CTS 0x80
341 #define MASK_M_ACR_N 0x40
342 #define MASK_M_DVI_DET 0x20
343 #define MASK_M_HDMI_DET 0x10
344 #define MASK_M_NOPMBDET 0x08
345 #define MASK_M_BPMBDET 0x04
346 #define MASK_M_TMDS 0x02
347 #define MASK_M_DDC 0x01
348
349 #define CLK_INTM 0x8513
350 #define MASK_M_OUT_H_CHG 0x40
351 #define MASK_M_IN_DE_CHG 0x20
352 #define MASK_M_IN_HV_CHG 0x10
353 #define MASK_M_DC_CHG 0x08
354 #define MASK_M_PXCLK_CHG 0x04
355 #define MASK_M_PHYCLK_CHG 0x02
356 #define MASK_M_TMDS_CHG 0x01
357
358 #define PACKET_INTM 0x8514
359
360 #define CBIT_INTM 0x8515
361 #define MASK_M_AF_LOCK 0x80
362 #define MASK_M_AF_UNLOCK 0x40
363 #define MASK_M_CBIT_FS 0x02
364
365 #define AUDIO_INTM 0x8516
366 #define MASK_M_BUFINIT_END 0x01
367
368 #define ERR_INTM 0x8517
369 #define MASK_M_EESS_ERR 0x80
370
371 #define HDCP_INTM 0x8518
372 #define MASK_M_AVM_SET 0x80
373 #define MASK_M_AVM_CLR 0x40
374 #define MASK_M_LINKERR 0x20
375 #define MASK_M_SHA_END 0x10
376 #define MASK_M_R0_END 0x08
377 #define MASK_M_KM_END 0x04
378 #define MASK_M_AKSV_END 0x02
379 #define MASK_M_AN_END 0x01
380
381 #define MISC_INTM 0x851B
382 #define MASK_M_AS_LAYOUT 0x10
383 #define MASK_M_NO_SPD 0x08
384 #define MASK_M_NO_VS 0x03
385 #define MASK_M_SYNC_CHG 0x02
386 #define MASK_M_AUDIO_MUTE 0x01
387
388 #define KEY_INTM 0x851F
389
390 #define SYS_STATUS 0x8520
391 #define MASK_S_SYNC 0x80
392 #define MASK_S_AVMUTE 0x40
393 #define MASK_S_HDCP 0x20
394 #define MASK_S_HDMI 0x10
395 #define MASK_S_PHY_SCDT 0x08
396 #define MASK_S_PHY_PLL 0x04
397 #define MASK_S_TMDS 0x02
398 #define MASK_S_DDC5V 0x01
399
400 #define CSI_STATUS 0x0410
401 #define MASK_S_WSYNC 0x0400
402 #define MASK_S_TXACT 0x0200
403 #define MASK_S_RXACT 0x0100
404 #define MASK_S_HLT 0x0001
405
406 #define VI_STATUS1 0x8522
407 #define MASK_S_V_GBD 0x08
408 #define MASK_S_DEEPCOLOR 0x0c
409 #define MASK_S_V_422 0x02
410 #define MASK_S_V_INTERLACE 0x01
411
412 #define AU_STATUS0 0x8523
413 #define MASK_S_A_SAMPLE 0x01
414
415 #define VI_STATUS3 0x8528
416 #define MASK_S_V_COLOR 0x1e
417 #define MASK_LIMITED 0x01
418
419 #define PHY_CTL0 0x8531
420 #define MASK_PHY_SYSCLK_IND 0x02
421 #define MASK_PHY_CTL 0x01
422
423
424 #define PHY_CTL1 0x8532
425 #define MASK_PHY_AUTO_RST1 0xf0
426 #define MASK_PHY_AUTO_RST1_OFF 0x00
427 #define SET_PHY_AUTO_RST1_US(us) ((((us) / 200) << 4) & \
428 MASK_PHY_AUTO_RST1)
429 #define MASK_FREQ_RANGE_MODE 0x0f
430 #define SET_FREQ_RANGE_MODE_CYCLES(cycles) (((cycles) - 1) & \
431 MASK_FREQ_RANGE_MODE)
432
433 #define PHY_CTL2 0x8533
434 #define MASK_PHY_AUTO_RST4 0x04
435 #define MASK_PHY_AUTO_RST3 0x02
436 #define MASK_PHY_AUTO_RST2 0x01
437 #define MASK_PHY_AUTO_RSTn (MASK_PHY_AUTO_RST4 | \
438 MASK_PHY_AUTO_RST3 | \
439 MASK_PHY_AUTO_RST2)
440
441 #define PHY_EN 0x8534
442 #define MASK_ENABLE_PHY 0x01
443
444 #define PHY_RST 0x8535
445 #define MASK_RESET_CTRL 0x01
446
447 #define PHY_BIAS 0x8536
448
449 #define PHY_CSQ 0x853F
450 #define MASK_CSQ_CNT 0x0f
451 #define SET_CSQ_CNT_LEVEL(n) (n & MASK_CSQ_CNT)
452
453 #define SYS_FREQ0 0x8540
454 #define SYS_FREQ1 0x8541
455
456 #define SYS_CLK 0x8542
457 #define MASK_CLK_DIFF 0x0C
458 #define MASK_CLK_DIV 0x03
459
460 #define DDC_CTL 0x8543
461 #define MASK_DDC_ACK_POL 0x08
462 #define MASK_DDC_ACTION 0x04
463 #define MASK_DDC5V_MODE 0x03
464 #define MASK_DDC5V_MODE_0MS 0x00
465 #define MASK_DDC5V_MODE_50MS 0x01
466 #define MASK_DDC5V_MODE_100MS 0x02
467 #define MASK_DDC5V_MODE_200MS 0x03
468
469 #define HPD_CTL 0x8544
470 #define MASK_HPD_CTL0 0x10
471 #define MASK_HPD_OUT0 0x01
472
473 #define ANA_CTL 0x8545
474 #define MASK_APPL_PCSX 0x30
475 #define MASK_APPL_PCSX_HIZ 0x00
476 #define MASK_APPL_PCSX_L_FIX 0x10
477 #define MASK_APPL_PCSX_H_FIX 0x20
478 #define MASK_APPL_PCSX_NORMAL 0x30
479 #define MASK_ANALOG_ON 0x01
480
481 #define AVM_CTL 0x8546
482
483 #define INIT_END 0x854A
484 #define MASK_INIT_END 0x01
485
486 #define HDMI_DET 0x8552
487 #define MASK_HDMI_DET_MOD1 0x80
488 #define MASK_HDMI_DET_MOD0 0x40
489 #define MASK_HDMI_DET_V 0x30
490 #define MASK_HDMI_DET_V_SYNC 0x00
491 #define MASK_HDMI_DET_V_ASYNC_25MS 0x10
492 #define MASK_HDMI_DET_V_ASYNC_50MS 0x20
493 #define MASK_HDMI_DET_V_ASYNC_100MS 0x30
494 #define MASK_HDMI_DET_NUM 0x0f
495
496 #define HDCP_MODE 0x8560
497 #define MASK_MODE_RST_TN 0x20
498 #define MASK_LINE_REKEY 0x10
499 #define MASK_AUTO_CLR 0x04
500 #define MASK_MANUAL_AUTHENTICATION 0x02
501
502 #define HDCP_REG1 0x8563
503 #define MASK_AUTH_UNAUTH_SEL 0x70
504 #define MASK_AUTH_UNAUTH_SEL_12_FRAMES 0x70
505 #define MASK_AUTH_UNAUTH_SEL_8_FRAMES 0x60
506 #define MASK_AUTH_UNAUTH_SEL_4_FRAMES 0x50
507 #define MASK_AUTH_UNAUTH_SEL_2_FRAMES 0x40
508 #define MASK_AUTH_UNAUTH_SEL_64_FRAMES 0x30
509 #define MASK_AUTH_UNAUTH_SEL_32_FRAMES 0x20
510 #define MASK_AUTH_UNAUTH_SEL_16_FRAMES 0x10
511 #define MASK_AUTH_UNAUTH_SEL_ONCE 0x00
512 #define MASK_AUTH_UNAUTH 0x01
513 #define MASK_AUTH_UNAUTH_AUTO 0x01
514
515 #define HDCP_REG2 0x8564
516 #define MASK_AUTO_P3_RESET 0x0F
517 #define SET_AUTO_P3_RESET_FRAMES(n) (n & MASK_AUTO_P3_RESET)
518 #define MASK_AUTO_P3_RESET_OFF 0x00
519
520 #define VI_MODE 0x8570
521 #define MASK_RGB_DVI 0x08
522
523 #define VOUT_SET2 0x8573
524 #define MASK_SEL422 0x80
525 #define MASK_VOUT_422FIL_100 0x40
526 #define MASK_VOUTCOLORMODE 0x03
527 #define MASK_VOUTCOLORMODE_THROUGH 0x00
528 #define MASK_VOUTCOLORMODE_AUTO 0x01
529 #define MASK_VOUTCOLORMODE_MANUAL 0x03
530
531 #define VOUT_SET3 0x8574
532 #define MASK_VOUT_EXTCNT 0x08
533
534 #define VI_REP 0x8576
535 #define MASK_VOUT_COLOR_SEL 0xe0
536 #define MASK_VOUT_COLOR_RGB_FULL 0x00
537 #define MASK_VOUT_COLOR_RGB_LIMITED 0x20
538 #define MASK_VOUT_COLOR_601_YCBCR_FULL 0x40
539 #define MASK_VOUT_COLOR_601_YCBCR_LIMITED 0x60
540 #define MASK_VOUT_COLOR_709_YCBCR_FULL 0x80
541 #define MASK_VOUT_COLOR_709_YCBCR_LIMITED 0xa0
542 #define MASK_VOUT_COLOR_FULL_TO_LIMITED 0xc0
543 #define MASK_VOUT_COLOR_LIMITED_TO_FULL 0xe0
544 #define MASK_IN_REP_HEN 0x10
545 #define MASK_IN_REP 0x0f
546
547 #define VI_MUTE 0x857F
548 #define MASK_AUTO_MUTE 0xc0
549 #define MASK_VI_MUTE 0x10
550
551 #define DE_WIDTH_H_LO 0x8582
552 #define DE_WIDTH_H_HI 0x8583
553 #define DE_WIDTH_V_LO 0x8588
554 #define DE_WIDTH_V_HI 0x8589
555 #define H_SIZE_LO 0x858A
556 #define H_SIZE_HI 0x858B
557 #define V_SIZE_LO 0x858C
558 #define V_SIZE_HI 0x858D
559 #define FV_CNT_LO 0x85A1
560 #define FV_CNT_HI 0x85A2
561
562 #define FH_MIN0 0x85AA
563 #define FH_MIN1 0x85AB
564 #define FH_MAX0 0x85AC
565 #define FH_MAX1 0x85AD
566
567 #define HV_RST 0x85AF
568 #define MASK_H_PI_RST 0x20
569 #define MASK_V_PI_RST 0x10
570
571 #define EDID_MODE 0x85C7
572 #define MASK_EDID_SPEED 0x40
573 #define MASK_EDID_MODE 0x03
574 #define MASK_EDID_MODE_DISABLE 0x00
575 #define MASK_EDID_MODE_DDC2B 0x01
576 #define MASK_EDID_MODE_E_DDC 0x02
577
578 #define EDID_LEN1 0x85CA
579 #define EDID_LEN2 0x85CB
580
581 #define HDCP_REG3 0x85D1
582 #define KEY_RD_CMD 0x01
583
584 #define FORCE_MUTE 0x8600
585 #define MASK_FORCE_AMUTE 0x10
586 #define MASK_FORCE_DMUTE 0x01
587
588 #define CMD_AUD 0x8601
589 #define MASK_CMD_BUFINIT 0x04
590 #define MASK_CMD_LOCKDET 0x02
591 #define MASK_CMD_MUTE 0x01
592
593 #define AUTO_CMD0 0x8602
594 #define MASK_AUTO_MUTE7 0x80
595 #define MASK_AUTO_MUTE6 0x40
596 #define MASK_AUTO_MUTE5 0x20
597 #define MASK_AUTO_MUTE4 0x10
598 #define MASK_AUTO_MUTE3 0x08
599 #define MASK_AUTO_MUTE2 0x04
600 #define MASK_AUTO_MUTE1 0x02
601 #define MASK_AUTO_MUTE0 0x01
602
603 #define AUTO_CMD1 0x8603
604 #define MASK_AUTO_MUTE10 0x04
605 #define MASK_AUTO_MUTE9 0x02
606 #define MASK_AUTO_MUTE8 0x01
607
608 #define AUTO_CMD2 0x8604
609 #define MASK_AUTO_PLAY3 0x08
610 #define MASK_AUTO_PLAY2 0x04
611
612 #define BUFINIT_START 0x8606
613 #define SET_BUFINIT_START_MS(milliseconds) ((milliseconds) / 100)
614
615 #define FS_MUTE 0x8607
616 #define MASK_FS_ELSE_MUTE 0x80
617 #define MASK_FS22_MUTE 0x40
618 #define MASK_FS24_MUTE 0x20
619 #define MASK_FS88_MUTE 0x10
620 #define MASK_FS96_MUTE 0x08
621 #define MASK_FS176_MUTE 0x04
622 #define MASK_FS192_MUTE 0x02
623 #define MASK_FS_NO_MUTE 0x01
624
625 #define FS_IMODE 0x8620
626 #define MASK_NLPCM_HMODE 0x40
627 #define MASK_NLPCM_SMODE 0x20
628 #define MASK_NLPCM_IMODE 0x10
629 #define MASK_FS_HMODE 0x08
630 #define MASK_FS_AMODE 0x04
631 #define MASK_FS_SMODE 0x02
632 #define MASK_FS_IMODE 0x01
633
634 #define FS_SET 0x8621
635 #define MASK_FS 0x0f
636
637 #define LOCKDET_REF0 0x8630
638 #define LOCKDET_REF1 0x8631
639 #define LOCKDET_REF2 0x8632
640
641 #define ACR_MODE 0x8640
642 #define MASK_ACR_LOAD 0x10
643 #define MASK_N_MODE 0x04
644 #define MASK_CTS_MODE 0x01
645
646 #define ACR_MDF0 0x8641
647 #define MASK_ACR_L2MDF 0x70
648 #define MASK_ACR_L2MDF_0_PPM 0x00
649 #define MASK_ACR_L2MDF_61_PPM 0x10
650 #define MASK_ACR_L2MDF_122_PPM 0x20
651 #define MASK_ACR_L2MDF_244_PPM 0x30
652 #define MASK_ACR_L2MDF_488_PPM 0x40
653 #define MASK_ACR_L2MDF_976_PPM 0x50
654 #define MASK_ACR_L2MDF_1976_PPM 0x60
655 #define MASK_ACR_L2MDF_3906_PPM 0x70
656 #define MASK_ACR_L1MDF 0x07
657 #define MASK_ACR_L1MDF_0_PPM 0x00
658 #define MASK_ACR_L1MDF_61_PPM 0x01
659 #define MASK_ACR_L1MDF_122_PPM 0x02
660 #define MASK_ACR_L1MDF_244_PPM 0x03
661 #define MASK_ACR_L1MDF_488_PPM 0x04
662 #define MASK_ACR_L1MDF_976_PPM 0x05
663 #define MASK_ACR_L1MDF_1976_PPM 0x06
664 #define MASK_ACR_L1MDF_3906_PPM 0x07
665
666 #define ACR_MDF1 0x8642
667 #define MASK_ACR_L3MDF 0x07
668 #define MASK_ACR_L3MDF_0_PPM 0x00
669 #define MASK_ACR_L3MDF_61_PPM 0x01
670 #define MASK_ACR_L3MDF_122_PPM 0x02
671 #define MASK_ACR_L3MDF_244_PPM 0x03
672 #define MASK_ACR_L3MDF_488_PPM 0x04
673 #define MASK_ACR_L3MDF_976_PPM 0x05
674 #define MASK_ACR_L3MDF_1976_PPM 0x06
675 #define MASK_ACR_L3MDF_3906_PPM 0x07
676
677 #define SDO_MODE1 0x8652
678 #define MASK_SDO_BIT_LENG 0x70
679 #define MASK_SDO_FMT 0x03
680 #define MASK_SDO_FMT_RIGHT 0x00
681 #define MASK_SDO_FMT_LEFT 0x01
682 #define MASK_SDO_FMT_I2S 0x02
683
684 #define DIV_MODE 0x8665
685 #define MASK_DIV_DLY 0xf0
686 #define SET_DIV_DLY_MS(milliseconds) ((((milliseconds) / 100) << 4) & \
687 MASK_DIV_DLY)
688 #define MASK_DIV_MODE 0x01
689
690 #define NCO_F0_MOD 0x8670
691 #define MASK_NCO_F0_MOD 0x03
692 #define MASK_NCO_F0_MOD_42MHZ 0x00
693 #define MASK_NCO_F0_MOD_27MHZ 0x01
694
695 #define PK_INT_MODE 0x8709
696 #define MASK_ISRC2_INT_MODE 0x80
697 #define MASK_ISRC_INT_MODE 0x40
698 #define MASK_ACP_INT_MODE 0x20
699 #define MASK_VS_INT_MODE 0x10
700 #define MASK_SPD_INT_MODE 0x08
701 #define MASK_MS_INT_MODE 0x04
702 #define MASK_AUD_INT_MODE 0x02
703 #define MASK_AVI_INT_MODE 0x01
704
705 #define NO_PKT_LIMIT 0x870B
706 #define MASK_NO_ACP_LIMIT 0xf0
707 #define SET_NO_ACP_LIMIT_MS(milliseconds) ((((milliseconds) / 80) << 4) & \
708 MASK_NO_ACP_LIMIT)
709 #define MASK_NO_AVI_LIMIT 0x0f
710 #define SET_NO_AVI_LIMIT_MS(milliseconds) (((milliseconds) / 80) & \
711 MASK_NO_AVI_LIMIT)
712
713 #define NO_PKT_CLR 0x870C
714 #define MASK_NO_VS_CLR 0x40
715 #define MASK_NO_SPD_CLR 0x20
716 #define MASK_NO_ACP_CLR 0x10
717 #define MASK_NO_AVI_CLR1 0x02
718 #define MASK_NO_AVI_CLR0 0x01
719
720 #define ERR_PK_LIMIT 0x870D
721 #define NO_PKT_LIMIT2 0x870E
722 #define PK_AVI_0HEAD 0x8710
723 #define PK_AVI_1HEAD 0x8711
724 #define PK_AVI_2HEAD 0x8712
725 #define PK_AVI_0BYTE 0x8713
726 #define PK_AVI_1BYTE 0x8714
727 #define PK_AVI_2BYTE 0x8715
728 #define PK_AVI_3BYTE 0x8716
729 #define PK_AVI_4BYTE 0x8717
730 #define PK_AVI_5BYTE 0x8718
731 #define PK_AVI_6BYTE 0x8719
732 #define PK_AVI_7BYTE 0x871A
733 #define PK_AVI_8BYTE 0x871B
734 #define PK_AVI_9BYTE 0x871C
735 #define PK_AVI_10BYTE 0x871D
736 #define PK_AVI_11BYTE 0x871E
737 #define PK_AVI_12BYTE 0x871F
738 #define PK_AVI_13BYTE 0x8720
739 #define PK_AVI_14BYTE 0x8721
740 #define PK_AVI_15BYTE 0x8722
741 #define PK_AVI_16BYTE 0x8723
742
743 #define BKSV 0x8800
744
745 #define BCAPS 0x8840
746 #define MASK_HDMI_RSVD 0x80
747 #define MASK_REPEATER 0x40
748 #define MASK_READY 0x20
749 #define MASK_FASTI2C 0x10
750 #define MASK_1_1_FEA 0x02
751 #define MASK_FAST_REAU 0x01
752
753 #define BSTATUS1 0x8842
754 #define MASK_MAX_EXCED 0x08
755
756 #define EDID_RAM 0x8C00
757 #define NO_GDB_LIMIT 0x9007
758
759 #endif