root/drivers/media/pci/cx88/cx88-reg.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * cx88x-hw.h - CX2388x register offsets
   4  *
   5  * Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de)
   6  *                2001 Michael Eskin
   7  *                2002 Yurij Sysoev <yurij@naturesoft.net>
   8  *                2003 Gerd Knorr <kraxel@bytesex.org>
   9  */
  10 
  11 #ifndef _CX88_REG_H_
  12 #define _CX88_REG_H_
  13 
  14 /*
  15  * PCI IDs and config space
  16  */
  17 
  18 #ifndef PCI_VENDOR_ID_CONEXANT
  19 # define PCI_VENDOR_ID_CONEXANT         0x14F1
  20 #endif
  21 #ifndef PCI_DEVICE_ID_CX2300_VID
  22 # define PCI_DEVICE_ID_CX2300_VID       0x8800
  23 #endif
  24 
  25 #define CX88X_DEVCTRL 0x40
  26 #define CX88X_EN_TBFX 0x02
  27 #define CX88X_EN_VSFX 0x04
  28 
  29 /*
  30  * PCI controller registers
  31  */
  32 
  33 /* Command and Status Register */
  34 #define F0_CMD_STAT_MM      0x2f0004
  35 #define F1_CMD_STAT_MM      0x2f0104
  36 #define F2_CMD_STAT_MM      0x2f0204
  37 #define F3_CMD_STAT_MM      0x2f0304
  38 #define F4_CMD_STAT_MM      0x2f0404
  39 
  40 /* Device Control #1 */
  41 #define F0_DEV_CNTRL1_MM    0x2f0040
  42 #define F1_DEV_CNTRL1_MM    0x2f0140
  43 #define F2_DEV_CNTRL1_MM    0x2f0240
  44 #define F3_DEV_CNTRL1_MM    0x2f0340
  45 #define F4_DEV_CNTRL1_MM    0x2f0440
  46 
  47 /* Device Control #1 */
  48 #define F0_BAR0_MM          0x2f0010
  49 #define F1_BAR0_MM          0x2f0110
  50 #define F2_BAR0_MM          0x2f0210
  51 #define F3_BAR0_MM          0x2f0310
  52 #define F4_BAR0_MM          0x2f0410
  53 
  54 /*
  55  * DMA Controller registers
  56  */
  57 
  58 #define MO_PDMA_STHRSH      0x200000 // Source threshold
  59 #define MO_PDMA_STADRS      0x200004 // Source target address
  60 #define MO_PDMA_SIADRS      0x200008 // Source internal address
  61 #define MO_PDMA_SCNTRL      0x20000C // Source control
  62 #define MO_PDMA_DTHRSH      0x200010 // Destination threshold
  63 #define MO_PDMA_DTADRS      0x200014 // Destination target address
  64 #define MO_PDMA_DIADRS      0x200018 // Destination internal address
  65 #define MO_PDMA_DCNTRL      0x20001C // Destination control
  66 #define MO_LD_SSID          0x200030 // Load subsystem ID
  67 #define MO_DEV_CNTRL2       0x200034 // Device control
  68 #define MO_PCI_INTMSK       0x200040 // PCI interrupt mask
  69 #define MO_PCI_INTSTAT      0x200044 // PCI interrupt status
  70 #define MO_PCI_INTMSTAT     0x200048 // PCI interrupt masked status
  71 #define MO_VID_INTMSK       0x200050 // Video interrupt mask
  72 #define MO_VID_INTSTAT      0x200054 // Video interrupt status
  73 #define MO_VID_INTMSTAT     0x200058 // Video interrupt masked status
  74 #define MO_VID_INTSSTAT     0x20005C // Video interrupt set status
  75 #define MO_AUD_INTMSK       0x200060 // Audio interrupt mask
  76 #define MO_AUD_INTSTAT      0x200064 // Audio interrupt status
  77 #define MO_AUD_INTMSTAT     0x200068 // Audio interrupt masked status
  78 #define MO_AUD_INTSSTAT     0x20006C // Audio interrupt set status
  79 #define MO_TS_INTMSK        0x200070 // Transport stream interrupt mask
  80 #define MO_TS_INTSTAT       0x200074 // Transport stream interrupt status
  81 #define MO_TS_INTMSTAT      0x200078 // Transport stream interrupt mask status
  82 #define MO_TS_INTSSTAT      0x20007C // Transport stream interrupt set status
  83 #define MO_VIP_INTMSK       0x200080 // VIP interrupt mask
  84 #define MO_VIP_INTSTAT      0x200084 // VIP interrupt status
  85 #define MO_VIP_INTMSTAT     0x200088 // VIP interrupt masked status
  86 #define MO_VIP_INTSSTAT     0x20008C // VIP interrupt set status
  87 #define MO_GPHST_INTMSK     0x200090 // Host interrupt mask
  88 #define MO_GPHST_INTSTAT    0x200094 // Host interrupt status
  89 #define MO_GPHST_INTMSTAT   0x200098 // Host interrupt masked status
  90 #define MO_GPHST_INTSSTAT   0x20009C // Host interrupt set status
  91 
  92 // DMA Channels 1-6 belong to SPIPE
  93 #define MO_DMA7_PTR1        0x300018 // {24}RW* DMA Current Ptr : Ch#7
  94 #define MO_DMA8_PTR1        0x30001C // {24}RW* DMA Current Ptr : Ch#8
  95 
  96 // DMA Channels 9-20 belong to SPIPE
  97 #define MO_DMA21_PTR1       0x300080 // {24}R0* DMA Current Ptr : Ch#21
  98 #define MO_DMA22_PTR1       0x300084 // {24}R0* DMA Current Ptr : Ch#22
  99 #define MO_DMA23_PTR1       0x300088 // {24}R0* DMA Current Ptr : Ch#23
 100 #define MO_DMA24_PTR1       0x30008C // {24}R0* DMA Current Ptr : Ch#24
 101 #define MO_DMA25_PTR1       0x300090 // {24}R0* DMA Current Ptr : Ch#25
 102 #define MO_DMA26_PTR1       0x300094 // {24}R0* DMA Current Ptr : Ch#26
 103 #define MO_DMA27_PTR1       0x300098 // {24}R0* DMA Current Ptr : Ch#27
 104 #define MO_DMA28_PTR1       0x30009C // {24}R0* DMA Current Ptr : Ch#28
 105 #define MO_DMA29_PTR1       0x3000A0 // {24}R0* DMA Current Ptr : Ch#29
 106 #define MO_DMA30_PTR1       0x3000A4 // {24}R0* DMA Current Ptr : Ch#30
 107 #define MO_DMA31_PTR1       0x3000A8 // {24}R0* DMA Current Ptr : Ch#31
 108 #define MO_DMA32_PTR1       0x3000AC // {24}R0* DMA Current Ptr : Ch#32
 109 
 110 #define MO_DMA21_PTR2       0x3000C0 // {24}RW* DMA Tab Ptr : Ch#21
 111 #define MO_DMA22_PTR2       0x3000C4 // {24}RW* DMA Tab Ptr : Ch#22
 112 #define MO_DMA23_PTR2       0x3000C8 // {24}RW* DMA Tab Ptr : Ch#23
 113 #define MO_DMA24_PTR2       0x3000CC // {24}RW* DMA Tab Ptr : Ch#24
 114 #define MO_DMA25_PTR2       0x3000D0 // {24}RW* DMA Tab Ptr : Ch#25
 115 #define MO_DMA26_PTR2       0x3000D4 // {24}RW* DMA Tab Ptr : Ch#26
 116 #define MO_DMA27_PTR2       0x3000D8 // {24}RW* DMA Tab Ptr : Ch#27
 117 #define MO_DMA28_PTR2       0x3000DC // {24}RW* DMA Tab Ptr : Ch#28
 118 #define MO_DMA29_PTR2       0x3000E0 // {24}RW* DMA Tab Ptr : Ch#29
 119 #define MO_DMA30_PTR2       0x3000E4 // {24}RW* DMA Tab Ptr : Ch#30
 120 #define MO_DMA31_PTR2       0x3000E8 // {24}RW* DMA Tab Ptr : Ch#31
 121 #define MO_DMA32_PTR2       0x3000EC // {24}RW* DMA Tab Ptr : Ch#32
 122 
 123 #define MO_DMA21_CNT1       0x300100 // {11}RW* DMA Buffer Size : Ch#21
 124 #define MO_DMA22_CNT1       0x300104 // {11}RW* DMA Buffer Size : Ch#22
 125 #define MO_DMA23_CNT1       0x300108 // {11}RW* DMA Buffer Size : Ch#23
 126 #define MO_DMA24_CNT1       0x30010C // {11}RW* DMA Buffer Size : Ch#24
 127 #define MO_DMA25_CNT1       0x300110 // {11}RW* DMA Buffer Size : Ch#25
 128 #define MO_DMA26_CNT1       0x300114 // {11}RW* DMA Buffer Size : Ch#26
 129 #define MO_DMA27_CNT1       0x300118 // {11}RW* DMA Buffer Size : Ch#27
 130 #define MO_DMA28_CNT1       0x30011C // {11}RW* DMA Buffer Size : Ch#28
 131 #define MO_DMA29_CNT1       0x300120 // {11}RW* DMA Buffer Size : Ch#29
 132 #define MO_DMA30_CNT1       0x300124 // {11}RW* DMA Buffer Size : Ch#30
 133 #define MO_DMA31_CNT1       0x300128 // {11}RW* DMA Buffer Size : Ch#31
 134 #define MO_DMA32_CNT1       0x30012C // {11}RW* DMA Buffer Size : Ch#32
 135 
 136 #define MO_DMA21_CNT2       0x300140 // {11}RW* DMA Table Size : Ch#21
 137 #define MO_DMA22_CNT2       0x300144 // {11}RW* DMA Table Size : Ch#22
 138 #define MO_DMA23_CNT2       0x300148 // {11}RW* DMA Table Size : Ch#23
 139 #define MO_DMA24_CNT2       0x30014C // {11}RW* DMA Table Size : Ch#24
 140 #define MO_DMA25_CNT2       0x300150 // {11}RW* DMA Table Size : Ch#25
 141 #define MO_DMA26_CNT2       0x300154 // {11}RW* DMA Table Size : Ch#26
 142 #define MO_DMA27_CNT2       0x300158 // {11}RW* DMA Table Size : Ch#27
 143 #define MO_DMA28_CNT2       0x30015C // {11}RW* DMA Table Size : Ch#28
 144 #define MO_DMA29_CNT2       0x300160 // {11}RW* DMA Table Size : Ch#29
 145 #define MO_DMA30_CNT2       0x300164 // {11}RW* DMA Table Size : Ch#30
 146 #define MO_DMA31_CNT2       0x300168 // {11}RW* DMA Table Size : Ch#31
 147 #define MO_DMA32_CNT2       0x30016C // {11}RW* DMA Table Size : Ch#32
 148 
 149 /*
 150  * Video registers
 151  */
 152 
 153 #define MO_VIDY_DMA         0x310000 // {64}RWp Video Y
 154 #define MO_VIDU_DMA         0x310008 // {64}RWp Video U
 155 #define MO_VIDV_DMA         0x310010 // {64}RWp Video V
 156 #define MO_VBI_DMA          0x310018 // {64}RWp VBI (Vertical blanking interval)
 157 
 158 #define MO_DEVICE_STATUS    0x310100
 159 #define MO_INPUT_FORMAT     0x310104
 160 #define MO_AGC_BURST        0x31010c
 161 #define MO_CONTR_BRIGHT     0x310110
 162 #define MO_UV_SATURATION    0x310114
 163 #define MO_HUE              0x310118
 164 #define MO_HTOTAL           0x310120
 165 #define MO_HDELAY_EVEN      0x310124
 166 #define MO_HDELAY_ODD       0x310128
 167 #define MO_VDELAY_ODD       0x31012c
 168 #define MO_VDELAY_EVEN      0x310130
 169 #define MO_HACTIVE_EVEN     0x31013c
 170 #define MO_HACTIVE_ODD      0x310140
 171 #define MO_VACTIVE_EVEN     0x310144
 172 #define MO_VACTIVE_ODD      0x310148
 173 #define MO_HSCALE_EVEN      0x31014c
 174 #define MO_HSCALE_ODD       0x310150
 175 #define MO_VSCALE_EVEN      0x310154
 176 #define MO_FILTER_EVEN      0x31015c
 177 #define MO_VSCALE_ODD       0x310158
 178 #define MO_FILTER_ODD       0x310160
 179 #define MO_OUTPUT_FORMAT    0x310164
 180 
 181 #define MO_PLL_REG          0x310168 // PLL register
 182 #define MO_PLL_ADJ_CTRL     0x31016c // PLL adjust control register
 183 #define MO_SCONV_REG        0x310170 // sample rate conversion register
 184 #define MO_SCONV_FIFO       0x310174 // sample rate conversion fifo
 185 #define MO_SUB_STEP         0x310178 // subcarrier step size
 186 #define MO_SUB_STEP_DR      0x31017c // subcarrier step size for DR line
 187 
 188 #define MO_CAPTURE_CTRL     0x310180 // capture control
 189 #define MO_COLOR_CTRL       0x310184
 190 #define MO_VBI_PACKET       0x310188 // vbi packet size / delay
 191 #define MO_FIELD_COUNT      0x310190 // field counter
 192 #define MO_VIP_CONFIG       0x310194
 193 #define MO_VBOS_CONTROL     0x3101a8
 194 
 195 #define MO_AGC_BACK_VBI     0x310200
 196 #define MO_AGC_SYNC_TIP1    0x310208
 197 
 198 #define MO_VIDY_GPCNT       0x31C020 // {16}RO Video Y general purpose counter
 199 #define MO_VIDU_GPCNT       0x31C024 // {16}RO Video U general purpose counter
 200 #define MO_VIDV_GPCNT       0x31C028 // {16}RO Video V general purpose counter
 201 #define MO_VBI_GPCNT        0x31C02C // {16}RO VBI general purpose counter
 202 #define MO_VIDY_GPCNTRL     0x31C030 // {2}WO Video Y general purpose control
 203 #define MO_VIDU_GPCNTRL     0x31C034 // {2}WO Video U general purpose control
 204 #define MO_VIDV_GPCNTRL     0x31C038 // {2}WO Video V general purpose control
 205 #define MO_VBI_GPCNTRL      0x31C03C // {2}WO VBI general purpose counter
 206 #define MO_VID_DMACNTRL     0x31C040 // {8}RW Video DMA control
 207 #define MO_VID_XFR_STAT     0x31C044 // {1}RO Video transfer status
 208 
 209 /*
 210  * audio registers
 211  */
 212 
 213 #define MO_AUDD_DMA         0x320000 // {64}RWp Audio downstream
 214 #define MO_AUDU_DMA         0x320008 // {64}RWp Audio upstream
 215 #define MO_AUDR_DMA         0x320010 // {64}RWp Audio RDS (downstream)
 216 #define MO_AUDD_GPCNT       0x32C020 // {16}RO Audio down general purpose counter
 217 #define MO_AUDU_GPCNT       0x32C024 // {16}RO Audio up general purpose counter
 218 #define MO_AUDR_GPCNT       0x32C028 // {16}RO Audio RDS general purpose counter
 219 #define MO_AUDD_GPCNTRL     0x32C030 // {2}WO Audio down general purpose control
 220 #define MO_AUDU_GPCNTRL     0x32C034 // {2}WO Audio up general purpose control
 221 #define MO_AUDR_GPCNTRL     0x32C038 // {2}WO Audio RDS general purpose control
 222 #define MO_AUD_DMACNTRL     0x32C040 // {6}RW Audio DMA control
 223 #define MO_AUD_XFR_STAT     0x32C044 // {1}RO Audio transfer status
 224 #define MO_AUDD_LNGTH       0x32C048 // {12}RW Audio down line length
 225 #define MO_AUDR_LNGTH       0x32C04C // {12}RW Audio RDS line length
 226 
 227 #define AUD_INIT                 0x320100
 228 #define AUD_INIT_LD              0x320104
 229 #define AUD_SOFT_RESET           0x320108
 230 #define AUD_I2SINPUTCNTL         0x320120
 231 #define AUD_BAUDRATE             0x320124
 232 #define AUD_I2SOUTPUTCNTL        0x320128
 233 #define AAGC_HYST                0x320134
 234 #define AAGC_GAIN                0x320138
 235 #define AAGC_DEF                 0x32013c
 236 #define AUD_IIR1_0_SEL           0x320150
 237 #define AUD_IIR1_0_SHIFT         0x320154
 238 #define AUD_IIR1_1_SEL           0x320158
 239 #define AUD_IIR1_1_SHIFT         0x32015c
 240 #define AUD_IIR1_2_SEL           0x320160
 241 #define AUD_IIR1_2_SHIFT         0x320164
 242 #define AUD_IIR1_3_SEL           0x320168
 243 #define AUD_IIR1_3_SHIFT         0x32016c
 244 #define AUD_IIR1_4_SEL           0x320170
 245 #define AUD_IIR1_4_SHIFT         0x32017c
 246 #define AUD_IIR1_5_SEL           0x320180
 247 #define AUD_IIR1_5_SHIFT         0x320184
 248 #define AUD_IIR2_0_SEL           0x320190
 249 #define AUD_IIR2_0_SHIFT         0x320194
 250 #define AUD_IIR2_1_SEL           0x320198
 251 #define AUD_IIR2_1_SHIFT         0x32019c
 252 #define AUD_IIR2_2_SEL           0x3201a0
 253 #define AUD_IIR2_2_SHIFT         0x3201a4
 254 #define AUD_IIR2_3_SEL           0x3201a8
 255 #define AUD_IIR2_3_SHIFT         0x3201ac
 256 #define AUD_IIR3_0_SEL           0x3201c0
 257 #define AUD_IIR3_0_SHIFT         0x3201c4
 258 #define AUD_IIR3_1_SEL           0x3201c8
 259 #define AUD_IIR3_1_SHIFT         0x3201cc
 260 #define AUD_IIR3_2_SEL           0x3201d0
 261 #define AUD_IIR3_2_SHIFT         0x3201d4
 262 #define AUD_IIR4_0_SEL           0x3201e0
 263 #define AUD_IIR4_0_SHIFT         0x3201e4
 264 #define AUD_IIR4_1_SEL           0x3201e8
 265 #define AUD_IIR4_1_SHIFT         0x3201ec
 266 #define AUD_IIR4_2_SEL           0x3201f0
 267 #define AUD_IIR4_2_SHIFT         0x3201f4
 268 #define AUD_IIR4_0_CA0           0x320200
 269 #define AUD_IIR4_0_CA1           0x320204
 270 #define AUD_IIR4_0_CA2           0x320208
 271 #define AUD_IIR4_0_CB0           0x32020c
 272 #define AUD_IIR4_0_CB1           0x320210
 273 #define AUD_IIR4_1_CA0           0x320214
 274 #define AUD_IIR4_1_CA1           0x320218
 275 #define AUD_IIR4_1_CA2           0x32021c
 276 #define AUD_IIR4_1_CB0           0x320220
 277 #define AUD_IIR4_1_CB1           0x320224
 278 #define AUD_IIR4_2_CA0           0x320228
 279 #define AUD_IIR4_2_CA1           0x32022c
 280 #define AUD_IIR4_2_CA2           0x320230
 281 #define AUD_IIR4_2_CB0           0x320234
 282 #define AUD_IIR4_2_CB1           0x320238
 283 #define AUD_HP_MD_IIR4_1         0x320250
 284 #define AUD_HP_PROG_IIR4_1       0x320254
 285 #define AUD_FM_MODE_ENABLE       0x320258
 286 #define AUD_POLY0_DDS_CONSTANT   0x320270
 287 #define AUD_DN0_FREQ             0x320274
 288 #define AUD_DN1_FREQ             0x320278
 289 #define AUD_DN1_FREQ_SHIFT       0x32027c
 290 #define AUD_DN1_AFC              0x320280
 291 #define AUD_DN1_SRC_SEL          0x320284
 292 #define AUD_DN1_SHFT             0x320288
 293 #define AUD_DN2_FREQ             0x32028c
 294 #define AUD_DN2_FREQ_SHIFT       0x320290
 295 #define AUD_DN2_AFC              0x320294
 296 #define AUD_DN2_SRC_SEL          0x320298
 297 #define AUD_DN2_SHFT             0x32029c
 298 #define AUD_CRDC0_SRC_SEL        0x320300
 299 #define AUD_CRDC0_SHIFT          0x320304
 300 #define AUD_CORDIC_SHIFT_0       0x320308
 301 #define AUD_CRDC1_SRC_SEL        0x32030c
 302 #define AUD_CRDC1_SHIFT          0x320310
 303 #define AUD_CORDIC_SHIFT_1       0x320314
 304 #define AUD_DCOC_0_SRC           0x320320
 305 #define AUD_DCOC0_SHIFT          0x320324
 306 #define AUD_DCOC_0_SHIFT_IN0     0x320328
 307 #define AUD_DCOC_0_SHIFT_IN1     0x32032c
 308 #define AUD_DCOC_1_SRC           0x320330
 309 #define AUD_DCOC1_SHIFT          0x320334
 310 #define AUD_DCOC_1_SHIFT_IN0     0x320338
 311 #define AUD_DCOC_1_SHIFT_IN1     0x32033c
 312 #define AUD_DCOC_2_SRC           0x320340
 313 #define AUD_DCOC2_SHIFT          0x320344
 314 #define AUD_DCOC_2_SHIFT_IN0     0x320348
 315 #define AUD_DCOC_2_SHIFT_IN1     0x32034c
 316 #define AUD_DCOC_PASS_IN         0x320350
 317 #define AUD_PDET_SRC             0x320370
 318 #define AUD_PDET_SHIFT           0x320374
 319 #define AUD_PILOT_BQD_1_K0       0x320380
 320 #define AUD_PILOT_BQD_1_K1       0x320384
 321 #define AUD_PILOT_BQD_1_K2       0x320388
 322 #define AUD_PILOT_BQD_1_K3       0x32038c
 323 #define AUD_PILOT_BQD_1_K4       0x320390
 324 #define AUD_PILOT_BQD_2_K0       0x320394
 325 #define AUD_PILOT_BQD_2_K1       0x320398
 326 #define AUD_PILOT_BQD_2_K2       0x32039c
 327 #define AUD_PILOT_BQD_2_K3       0x3203a0
 328 #define AUD_PILOT_BQD_2_K4       0x3203a4
 329 #define AUD_THR_FR               0x3203c0
 330 #define AUD_X_PROG               0x3203c4
 331 #define AUD_Y_PROG               0x3203c8
 332 #define AUD_HARMONIC_MULT        0x3203cc
 333 #define AUD_C1_UP_THR            0x3203d0
 334 #define AUD_C1_LO_THR            0x3203d4
 335 #define AUD_C2_UP_THR            0x3203d8
 336 #define AUD_C2_LO_THR            0x3203dc
 337 #define AUD_PLL_EN               0x320400
 338 #define AUD_PLL_SRC              0x320404
 339 #define AUD_PLL_SHIFT            0x320408
 340 #define AUD_PLL_IF_SEL           0x32040c
 341 #define AUD_PLL_IF_SHIFT         0x320410
 342 #define AUD_BIQUAD_PLL_K0        0x320414
 343 #define AUD_BIQUAD_PLL_K1        0x320418
 344 #define AUD_BIQUAD_PLL_K2        0x32041c
 345 #define AUD_BIQUAD_PLL_K3        0x320420
 346 #define AUD_BIQUAD_PLL_K4        0x320424
 347 #define AUD_DEEMPH0_SRC_SEL      0x320440
 348 #define AUD_DEEMPH0_SHIFT        0x320444
 349 #define AUD_DEEMPH0_G0           0x320448
 350 #define AUD_DEEMPH0_A0           0x32044c
 351 #define AUD_DEEMPH0_B0           0x320450
 352 #define AUD_DEEMPH0_A1           0x320454
 353 #define AUD_DEEMPH0_B1           0x320458
 354 #define AUD_DEEMPH1_SRC_SEL      0x32045c
 355 #define AUD_DEEMPH1_SHIFT        0x320460
 356 #define AUD_DEEMPH1_G0           0x320464
 357 #define AUD_DEEMPH1_A0           0x320468
 358 #define AUD_DEEMPH1_B0           0x32046c
 359 #define AUD_DEEMPH1_A1           0x320470
 360 #define AUD_DEEMPH1_B1           0x320474
 361 #define AUD_OUT0_SEL             0x320490
 362 #define AUD_OUT0_SHIFT           0x320494
 363 #define AUD_OUT1_SEL             0x320498
 364 #define AUD_OUT1_SHIFT           0x32049c
 365 #define AUD_RDSI_SEL             0x3204a0
 366 #define AUD_RDSI_SHIFT           0x3204a4
 367 #define AUD_RDSQ_SEL             0x3204a8
 368 #define AUD_RDSQ_SHIFT           0x3204ac
 369 #define AUD_DBX_IN_GAIN          0x320500
 370 #define AUD_DBX_WBE_GAIN         0x320504
 371 #define AUD_DBX_SE_GAIN          0x320508
 372 #define AUD_DBX_RMS_WBE          0x32050c
 373 #define AUD_DBX_RMS_SE           0x320510
 374 #define AUD_DBX_SE_BYPASS        0x320514
 375 #define AUD_FAWDETCTL            0x320530
 376 #define AUD_FAWDETWINCTL         0x320534
 377 #define AUD_DEEMPHGAIN_R         0x320538
 378 #define AUD_DEEMPHNUMER1_R       0x32053c
 379 #define AUD_DEEMPHNUMER2_R       0x320540
 380 #define AUD_DEEMPHDENOM1_R       0x320544
 381 #define AUD_DEEMPHDENOM2_R       0x320548
 382 #define AUD_ERRLOGPERIOD_R       0x32054c
 383 #define AUD_ERRINTRPTTHSHLD1_R   0x320550
 384 #define AUD_ERRINTRPTTHSHLD2_R   0x320554
 385 #define AUD_ERRINTRPTTHSHLD3_R   0x320558
 386 #define AUD_NICAM_STATUS1        0x32055c
 387 #define AUD_NICAM_STATUS2        0x320560
 388 #define AUD_ERRLOG1              0x320564
 389 #define AUD_ERRLOG2              0x320568
 390 #define AUD_ERRLOG3              0x32056c
 391 #define AUD_DAC_BYPASS_L         0x320580
 392 #define AUD_DAC_BYPASS_R         0x320584
 393 #define AUD_DAC_BYPASS_CTL       0x320588
 394 #define AUD_CTL                  0x32058c
 395 #define AUD_STATUS               0x320590
 396 #define AUD_VOL_CTL              0x320594
 397 #define AUD_BAL_CTL              0x320598
 398 #define AUD_START_TIMER          0x3205b0
 399 #define AUD_MODE_CHG_TIMER       0x3205b4
 400 #define AUD_POLYPH80SCALEFAC     0x3205b8
 401 #define AUD_DMD_RA_DDS           0x3205bc
 402 #define AUD_I2S_RA_DDS           0x3205c0
 403 #define AUD_RATE_THRES_DMD       0x3205d0
 404 #define AUD_RATE_THRES_I2S       0x3205d4
 405 #define AUD_RATE_ADJ1            0x3205d8
 406 #define AUD_RATE_ADJ2            0x3205dc
 407 #define AUD_RATE_ADJ3            0x3205e0
 408 #define AUD_RATE_ADJ4            0x3205e4
 409 #define AUD_RATE_ADJ5            0x3205e8
 410 #define AUD_APB_IN_RATE_ADJ      0x3205ec
 411 #define AUD_I2SCNTL              0x3205ec
 412 #define AUD_PHASE_FIX_CTL        0x3205f0
 413 #define AUD_PLL_PRESCALE         0x320600
 414 #define AUD_PLL_DDS              0x320604
 415 #define AUD_PLL_INT              0x320608
 416 #define AUD_PLL_FRAC             0x32060c
 417 #define AUD_PLL_JTAG             0x320620
 418 #define AUD_PLL_SPMP             0x320624
 419 #define AUD_AFE_12DB_EN          0x320628
 420 
 421 // Audio QAM Register Addresses
 422 #define AUD_PDF_DDS_CNST_BYTE2   0x320d01
 423 #define AUD_PDF_DDS_CNST_BYTE1   0x320d02
 424 #define AUD_PDF_DDS_CNST_BYTE0   0x320d03
 425 #define AUD_PHACC_FREQ_8MSB      0x320d2a
 426 #define AUD_PHACC_FREQ_8LSB      0x320d2b
 427 #define AUD_QAM_MODE             0x320d04
 428 
 429 /*
 430  * transport stream registers
 431  */
 432 
 433 #define MO_TS_DMA           0x330000 // {64}RWp Transport stream downstream
 434 #define MO_TS_GPCNT         0x33C020 // {16}RO TS general purpose counter
 435 #define MO_TS_GPCNTRL       0x33C030 // {2}WO TS general purpose control
 436 #define MO_TS_DMACNTRL      0x33C040 // {6}RW TS DMA control
 437 #define MO_TS_XFR_STAT      0x33C044 // {1}RO TS transfer status
 438 #define MO_TS_LNGTH         0x33C048 // {12}RW TS line length
 439 
 440 #define TS_HW_SOP_CNTRL     0x33C04C
 441 #define TS_GEN_CNTRL        0x33C050
 442 #define TS_BD_PKT_STAT      0x33C054
 443 #define TS_SOP_STAT         0x33C058
 444 #define TS_FIFO_OVFL_STAT   0x33C05C
 445 #define TS_VALERR_CNTRL     0x33C060
 446 
 447 /*
 448  * VIP registers
 449  */
 450 
 451 #define MO_VIPD_DMA         0x340000 // {64}RWp VIP downstream
 452 #define MO_VIPU_DMA         0x340008 // {64}RWp VIP upstream
 453 #define MO_VIPD_GPCNT       0x34C020 // {16}RO VIP down general purpose counter
 454 #define MO_VIPU_GPCNT       0x34C024 // {16}RO VIP up general purpose counter
 455 #define MO_VIPD_GPCNTRL     0x34C030 // {2}WO VIP down general purpose control
 456 #define MO_VIPU_GPCNTRL     0x34C034 // {2}WO VIP up general purpose control
 457 #define MO_VIP_DMACNTRL     0x34C040 // {6}RW VIP DMA control
 458 #define MO_VIP_XFR_STAT     0x34C044 // {1}RO VIP transfer status
 459 #define MO_VIP_CFG          0x340048 // VIP configuration
 460 #define MO_VIPU_CNTRL       0x34004C // VIP upstream control #1
 461 #define MO_VIPD_CNTRL       0x340050 // VIP downstream control #2
 462 #define MO_VIPD_LNGTH       0x340054 // VIP downstream line length
 463 #define MO_VIP_BRSTLN       0x340058 // VIP burst length
 464 #define MO_VIP_INTCNTRL     0x34C05C // VIP Interrupt Control
 465 #define MO_VIP_XFTERM       0x340060 // VIP transfer terminate
 466 
 467 /*
 468  * misc registers
 469  */
 470 
 471 #define MO_M2M_DMA          0x350000 // {64}RWp Mem2Mem DMA Bfr
 472 #define MO_GP0_IO           0x350010 // {32}RW* GPIOoutput enablesdata I/O
 473 #define MO_GP1_IO           0x350014 // {32}RW* GPIOoutput enablesdata I/O
 474 #define MO_GP2_IO           0x350018 // {32}RW* GPIOoutput enablesdata I/O
 475 #define MO_GP3_IO           0x35001C // {32}RW* GPIO Mode/Ctrloutput enables
 476 #define MO_GPIO             0x350020 // {32}RW* GPIO I2C Ctrldata I/O
 477 #define MO_GPOE             0x350024 // {32}RW  GPIO I2C Ctrloutput enables
 478 #define MO_GP_ISM           0x350028 // {16}WO  GPIO Intr Sens/Pol
 479 
 480 #define MO_PLL_B            0x35C008 // {32}RW* PLL Control for ASB bus clks
 481 #define MO_M2M_CNT          0x35C024 // {32}RW  Mem2Mem DMA Cnt
 482 #define MO_M2M_XSUM         0x35C028 // {32}RO  M2M XOR-Checksum
 483 #define MO_CRC              0x35C02C // {16}RW  CRC16 init/result
 484 #define MO_CRC_D            0x35C030 // {32}WO  CRC16 new data in
 485 #define MO_TM_CNT_LDW       0x35C034 // {32}RO  Timer : Counter low dword
 486 #define MO_TM_CNT_UW        0x35C038 // {16}RO  Timer : Counter high word
 487 #define MO_TM_LMT_LDW       0x35C03C // {32}RW  Timer : Limit low dword
 488 #define MO_TM_LMT_UW        0x35C040 // {32}RW  Timer : Limit high word
 489 #define MO_PINMUX_IO        0x35C044 // {8}RW  Pin Mux Control
 490 #define MO_TSTSEL_IO        0x35C048 // {2}RW  Pin Mux Control
 491 #define MO_AFECFG_IO        0x35C04C // AFE configuration reg
 492 #define MO_DDS_IO           0x35C050 // DDS Increment reg
 493 #define MO_DDSCFG_IO        0x35C054 // DDS Configuration reg
 494 #define MO_SAMPLE_IO        0x35C058 // IRIn sample reg
 495 #define MO_SRST_IO          0x35C05C // Output system reset reg
 496 
 497 #define MO_INT1_MSK         0x35C060 // DMA RISC interrupt mask
 498 #define MO_INT1_STAT        0x35C064 // DMA RISC interrupt status
 499 #define MO_INT1_MSTAT       0x35C068 // DMA RISC interrupt masked status
 500 
 501 /*
 502  * i2c bus registers
 503  */
 504 
 505 #define MO_I2C              0x368000 // I2C data/control
 506 #define MO_I2C_DIV          (0xf<<4)
 507 #define MO_I2C_SYNC         (1<<3)
 508 #define MO_I2C_W3B          (1<<2)
 509 #define MO_I2C_SCL          (1<<1)
 510 #define MO_I2C_SDA          (1<<0)
 511 
 512 
 513 /*
 514  * general purpose host registers
 515  *
 516  * FIXME: tyops?  s/0x35/0x38/ ??
 517  */
 518 
 519 #define MO_GPHSTD_DMA       0x350000 // {64}RWp Host downstream
 520 #define MO_GPHSTU_DMA       0x350008 // {64}RWp Host upstream
 521 #define MO_GPHSTU_CNTRL     0x380048 // Host upstream control #1
 522 #define MO_GPHSTD_CNTRL     0x38004C // Host downstream control #2
 523 #define MO_GPHSTD_LNGTH     0x380050 // Host downstream line length
 524 #define MO_GPHST_WSC        0x380054 // Host wait state control
 525 #define MO_GPHST_XFR        0x380058 // Host transfer control
 526 #define MO_GPHST_WDTH       0x38005C // Host interface width
 527 #define MO_GPHST_HDSHK      0x380060 // Host peripheral handshake
 528 #define MO_GPHST_MUX16      0x380064 // Host muxed 16-bit transfer parameters
 529 #define MO_GPHST_MODE       0x380068 // Host mode select
 530 
 531 #define MO_GPHSTD_GPCNT     0x35C020 // Host down general purpose counter
 532 #define MO_GPHSTU_GPCNT     0x35C024 // Host up general purpose counter
 533 #define MO_GPHSTD_GPCNTRL   0x38C030 // Host down general purpose control
 534 #define MO_GPHSTU_GPCNTRL   0x38C034 // Host up general purpose control
 535 #define MO_GPHST_DMACNTRL   0x38C040 // Host DMA control
 536 #define MO_GPHST_XFR_STAT   0x38C044 // Host transfer status
 537 #define MO_GPHST_SOFT_RST   0x38C06C // Host software reset
 538 
 539 /*
 540  * RISC instructions
 541  */
 542 
 543 #define RISC_SYNC                0x80000000
 544 #define RISC_SYNC_ODD            0x80000000
 545 #define RISC_SYNC_EVEN           0x80000200
 546 #define RISC_RESYNC              0x80008000
 547 #define RISC_RESYNC_ODD          0x80008000
 548 #define RISC_RESYNC_EVEN         0x80008200
 549 #define RISC_WRITE               0x10000000
 550 #define RISC_WRITEC              0x50000000
 551 #define RISC_READ                0x90000000
 552 #define RISC_READC               0xA0000000
 553 #define RISC_JUMP                0x70000000
 554 #define RISC_SKIP                0x20000000
 555 #define RISC_WRITERM             0xB0000000
 556 #define RISC_WRITECM             0xC0000000
 557 #define RISC_WRITECR             0xD0000000
 558 #define RISC_IMM                 0x00000001
 559 
 560 #define RISC_SOL                 0x08000000
 561 #define RISC_EOL                 0x04000000
 562 
 563 #define RISC_IRQ2                0x02000000
 564 #define RISC_IRQ1                0x01000000
 565 
 566 #define RISC_CNT_NONE            0x00000000
 567 #define RISC_CNT_INC             0x00010000
 568 #define RISC_CNT_RSVR            0x00020000
 569 #define RISC_CNT_RESET           0x00030000
 570 #define RISC_JMP_SRP             0x01
 571 
 572 /*
 573  * various constants
 574  */
 575 
 576 // DMA
 577 /* Interrupt mask/status */
 578 #define PCI_INT_VIDINT          (1 <<  0)
 579 #define PCI_INT_AUDINT          (1 <<  1)
 580 #define PCI_INT_TSINT           (1 <<  2)
 581 #define PCI_INT_VIPINT          (1 <<  3)
 582 #define PCI_INT_HSTINT          (1 <<  4)
 583 #define PCI_INT_TM1INT          (1 <<  5)
 584 #define PCI_INT_SRCDMAINT       (1 <<  6)
 585 #define PCI_INT_DSTDMAINT       (1 <<  7)
 586 #define PCI_INT_RISC_RD_BERRINT (1 << 10)
 587 #define PCI_INT_RISC_WR_BERRINT (1 << 11)
 588 #define PCI_INT_BRDG_BERRINT    (1 << 12)
 589 #define PCI_INT_SRC_DMA_BERRINT (1 << 13)
 590 #define PCI_INT_DST_DMA_BERRINT (1 << 14)
 591 #define PCI_INT_IPB_DMA_BERRINT (1 << 15)
 592 #define PCI_INT_I2CDONE         (1 << 16)
 593 #define PCI_INT_I2CRACK         (1 << 17)
 594 #define PCI_INT_IR_SMPINT       (1 << 18)
 595 #define PCI_INT_GPIO_INT0       (1 << 19)
 596 #define PCI_INT_GPIO_INT1       (1 << 20)
 597 
 598 #define SEL_BTSC     0x01
 599 #define SEL_EIAJ     0x02
 600 #define SEL_A2       0x04
 601 #define SEL_SAP      0x08
 602 #define SEL_NICAM    0x10
 603 #define SEL_FMRADIO  0x20
 604 
 605 // AUD_CTL
 606 #define AUD_INT_DN_RISCI1       (1 <<  0)
 607 #define AUD_INT_UP_RISCI1       (1 <<  1)
 608 #define AUD_INT_RDS_DN_RISCI1   (1 <<  2)
 609 #define AUD_INT_DN_RISCI2       (1 <<  4) /* yes, 3 is skipped */
 610 #define AUD_INT_UP_RISCI2       (1 <<  5)
 611 #define AUD_INT_RDS_DN_RISCI2   (1 <<  6)
 612 #define AUD_INT_DN_SYNC         (1 << 12)
 613 #define AUD_INT_UP_SYNC         (1 << 13)
 614 #define AUD_INT_RDS_DN_SYNC     (1 << 14)
 615 #define AUD_INT_OPC_ERR         (1 << 16)
 616 #define AUD_INT_BER_IRQ         (1 << 20)
 617 #define AUD_INT_MCHG_IRQ        (1 << 21)
 618 
 619 #define EN_BTSC_FORCE_MONO      0
 620 #define EN_BTSC_FORCE_STEREO    1
 621 #define EN_BTSC_FORCE_SAP       2
 622 #define EN_BTSC_AUTO_STEREO     3
 623 #define EN_BTSC_AUTO_SAP        4
 624 
 625 #define EN_A2_FORCE_MONO1       8
 626 #define EN_A2_FORCE_MONO2       9
 627 #define EN_A2_FORCE_STEREO      10
 628 #define EN_A2_AUTO_MONO2        11
 629 #define EN_A2_AUTO_STEREO       12
 630 
 631 #define EN_EIAJ_FORCE_MONO1     16
 632 #define EN_EIAJ_FORCE_MONO2     17
 633 #define EN_EIAJ_FORCE_STEREO    18
 634 #define EN_EIAJ_AUTO_MONO2      19
 635 #define EN_EIAJ_AUTO_STEREO     20
 636 
 637 #define EN_NICAM_FORCE_MONO1    32
 638 #define EN_NICAM_FORCE_MONO2    33
 639 #define EN_NICAM_FORCE_STEREO   34
 640 #define EN_NICAM_AUTO_MONO2     35
 641 #define EN_NICAM_AUTO_STEREO    36
 642 
 643 #define EN_FMRADIO_FORCE_MONO   24
 644 #define EN_FMRADIO_FORCE_STEREO 25
 645 #define EN_FMRADIO_AUTO_STEREO  26
 646 
 647 #define EN_NICAM_AUTO_FALLBACK  0x00000040
 648 #define EN_FMRADIO_EN_RDS       0x00000200
 649 #define EN_NICAM_TRY_AGAIN_BIT  0x00000400
 650 #define EN_DAC_ENABLE           0x00001000
 651 #define EN_I2SOUT_ENABLE        0x00002000
 652 #define EN_I2SIN_STR2DAC        0x00004000
 653 #define EN_I2SIN_ENABLE         0x00008000
 654 
 655 #define EN_DMTRX_SUMDIFF        (0 << 7)
 656 #define EN_DMTRX_SUMR           (1 << 7)
 657 #define EN_DMTRX_LR             (2 << 7)
 658 #define EN_DMTRX_MONO           (3 << 7)
 659 #define EN_DMTRX_BYPASS         (1 << 11)
 660 
 661 // Video
 662 #define VID_CAPTURE_CONTROL             0x310180
 663 
 664 #define CX23880_CAP_CTL_CAPTURE_VBI_ODD  (1<<3)
 665 #define CX23880_CAP_CTL_CAPTURE_VBI_EVEN (1<<2)
 666 #define CX23880_CAP_CTL_CAPTURE_ODD      (1<<1)
 667 #define CX23880_CAP_CTL_CAPTURE_EVEN     (1<<0)
 668 
 669 #define VideoInputMux0           0x0
 670 #define VideoInputMux1           0x1
 671 #define VideoInputMux2           0x2
 672 #define VideoInputMux3           0x3
 673 #define VideoInputTuner          0x0
 674 #define VideoInputComposite      0x1
 675 #define VideoInputSVideo         0x2
 676 #define VideoInputOther          0x3
 677 
 678 #define Xtal0            0x1
 679 #define Xtal1            0x2
 680 #define XtalAuto         0x3
 681 
 682 #define VideoFormatAuto          0x0
 683 #define VideoFormatNTSC          0x1
 684 #define VideoFormatNTSCJapan     0x2
 685 #define VideoFormatNTSC443       0x3
 686 #define VideoFormatPAL           0x4
 687 #define VideoFormatPALB          0x4
 688 #define VideoFormatPALD          0x4
 689 #define VideoFormatPALG          0x4
 690 #define VideoFormatPALH          0x4
 691 #define VideoFormatPALI          0x4
 692 #define VideoFormatPALBDGHI      0x4
 693 #define VideoFormatPALM          0x5
 694 #define VideoFormatPALN          0x6
 695 #define VideoFormatPALNC         0x7
 696 #define VideoFormatPAL60         0x8
 697 #define VideoFormatSECAM         0x9
 698 
 699 #define VideoFormatAuto27MHz             0x10
 700 #define VideoFormatNTSC27MHz             0x11
 701 #define VideoFormatNTSCJapan27MHz        0x12
 702 #define VideoFormatNTSC44327MHz          0x13
 703 #define VideoFormatPAL27MHz              0x14
 704 #define VideoFormatPALB27MHz             0x14
 705 #define VideoFormatPALD27MHz             0x14
 706 #define VideoFormatPALG27MHz             0x14
 707 #define VideoFormatPALH27MHz             0x14
 708 #define VideoFormatPALI27MHz             0x14
 709 #define VideoFormatPALBDGHI27MHz         0x14
 710 #define VideoFormatPALM27MHz             0x15
 711 #define VideoFormatPALN27MHz             0x16
 712 #define VideoFormatPALNC27MHz            0x17
 713 #define VideoFormatPAL6027MHz            0x18
 714 #define VideoFormatSECAM27MHz            0x19
 715 
 716 #define NominalUSECAM    0x87
 717 #define NominalVSECAM    0x85
 718 #define NominalUNTSC     0xFE
 719 #define NominalVNTSC     0xB4
 720 
 721 #define NominalContrast  0xD8
 722 
 723 #define HFilterAutoFormat        0x0
 724 #define HFilterCIF               0x1
 725 #define HFilterQCIF              0x2
 726 #define HFilterICON              0x3
 727 
 728 #define VFilter2TapInterpolate  0
 729 #define VFilter3TapInterpolate  1
 730 #define VFilter4TapInterpolate  2
 731 #define VFilter5TapInterpolate  3
 732 #define VFilter2TapNoInterpolate  4
 733 #define VFilter3TapNoInterpolate  5
 734 #define VFilter4TapNoInterpolate  6
 735 #define VFilter5TapNoInterpolate  7
 736 
 737 #define ColorFormatRGB32         0x0000
 738 #define ColorFormatRGB24         0x0011
 739 #define ColorFormatRGB16         0x0022
 740 #define ColorFormatRGB15         0x0033
 741 #define ColorFormatYUY2          0x0044
 742 #define ColorFormatBTYUV         0x0055
 743 #define ColorFormatY8            0x0066
 744 #define ColorFormatRGB8          0x0077
 745 #define ColorFormatPL422         0x0088
 746 #define ColorFormatPL411         0x0099
 747 #define ColorFormatYUV12         0x00AA
 748 #define ColorFormatYUV9          0x00BB
 749 #define ColorFormatRAW           0x00EE
 750 #define ColorFormatBSWAP         0x0300
 751 #define ColorFormatWSWAP         0x0c00
 752 #define ColorFormatEvenMask      0x050f
 753 #define ColorFormatOddMask       0x0af0
 754 #define ColorFormatGamma         0x1000
 755 
 756 #define Interlaced               0x1
 757 #define NonInterlaced            0x0
 758 
 759 #define FieldEven                0x1
 760 #define FieldOdd                 0x0
 761 
 762 #define TGReadWriteMode          0x0
 763 #define TGEnableMode             0x1
 764 
 765 #define DV_CbAlign               0x0
 766 #define DV_Y0Align               0x1
 767 #define DV_CrAlign               0x2
 768 #define DV_Y1Align               0x3
 769 
 770 #define DVF_Analog               0x0
 771 #define DVF_CCIR656              0x1
 772 #define DVF_ByteStream           0x2
 773 #define DVF_ExtVSYNC             0x4
 774 #define DVF_ExtField             0x5
 775 
 776 #define CHANNEL_VID_Y            0x1
 777 #define CHANNEL_VID_U            0x2
 778 #define CHANNEL_VID_V            0x3
 779 #define CHANNEL_VID_VBI          0x4
 780 #define CHANNEL_AUD_DN           0x5
 781 #define CHANNEL_AUD_UP           0x6
 782 #define CHANNEL_AUD_RDS_DN       0x7
 783 #define CHANNEL_MPEG_DN          0x8
 784 #define CHANNEL_VIP_DN           0x9
 785 #define CHANNEL_VIP_UP           0xA
 786 #define CHANNEL_HOST_DN          0xB
 787 #define CHANNEL_HOST_UP          0xC
 788 #define CHANNEL_FIRST            0x1
 789 #define CHANNEL_LAST             0xC
 790 
 791 #define GP_COUNT_CONTROL_NONE            0x0
 792 #define GP_COUNT_CONTROL_INC             0x1
 793 #define GP_COUNT_CONTROL_RESERVED        0x2
 794 #define GP_COUNT_CONTROL_RESET           0x3
 795 
 796 #define PLL_PRESCALE_BY_2  2
 797 #define PLL_PRESCALE_BY_3  3
 798 #define PLL_PRESCALE_BY_4  4
 799 #define PLL_PRESCALE_BY_5  5
 800 
 801 #define HLNotchFilter4xFsc       0
 802 #define HLNotchFilterSquare      1
 803 #define HLNotchFilter135NTSC     2
 804 #define HLNotchFilter135PAL      3
 805 
 806 #define NTSC_8x_SUB_CARRIER  28.63636E6
 807 #define PAL_8x_SUB_CARRIER  35.46895E6
 808 
 809 // Default analog settings
 810 #define DEFAULT_HUE_NTSC                        0x00
 811 #define DEFAULT_BRIGHTNESS_NTSC                 0x00
 812 #define DEFAULT_CONTRAST_NTSC                   0x39
 813 #define DEFAULT_SAT_U_NTSC                      0x7F
 814 #define DEFAULT_SAT_V_NTSC                      0x5A
 815 
 816 #endif /* _CX88_REG_H_ */