root/arch/mips/include/asm/mach-rc32434/dma.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright 2002 Integrated Device Technology, Inc.
   4  *              All rights reserved.
   5  *
   6  * DMA register definition.
   7  *
   8  * Author : ryan.holmQVist@idt.com
   9  * Date   : 20011005
  10  */
  11 
  12 #ifndef __ASM_RC32434_DMA_H
  13 #define __ASM_RC32434_DMA_H
  14 
  15 #include <asm/mach-rc32434/rb.h>
  16 
  17 #define DMA0_BASE_ADDR                  0x18040000
  18 
  19 /*
  20  * DMA descriptor (in physical memory).
  21  */
  22 
  23 struct dma_desc {
  24         u32 control;                    /* Control. use DMAD_* */
  25         u32 ca;                         /* Current Address. */
  26         u32 devcs;                      /* Device control and status. */
  27         u32 link;                       /* Next descriptor in chain. */
  28 };
  29 
  30 #define DMA_DESC_SIZ                    sizeof(struct dma_desc)
  31 #define DMA_DESC_COUNT_BIT              0
  32 #define DMA_DESC_COUNT_MSK              0x0003ffff
  33 #define DMA_DESC_DS_BIT                 20
  34 #define DMA_DESC_DS_MSK                 0x00300000
  35 
  36 #define DMA_DESC_DEV_CMD_BIT            22
  37 #define DMA_DESC_DEV_CMD_MSK            0x01c00000
  38 
  39 /* DMA command sizes */
  40 #define DMA_DESC_DEV_CMD_BYTE           0
  41 #define DMA_DESC_DEV_CMD_HLF_WD         1
  42 #define DMA_DESC_DEV_CMD_WORD           2
  43 #define DMA_DESC_DEV_CMD_2WORDS         3
  44 #define DMA_DESC_DEV_CMD_4WORDS         4
  45 #define DMA_DESC_DEV_CMD_6WORDS         5
  46 #define DMA_DESC_DEV_CMD_8WORDS         6
  47 #define DMA_DESC_DEV_CMD_16WORDS        7
  48 
  49 /* DMA descriptors interrupts */
  50 #define DMA_DESC_COF                    (1 << 25) /* Chain on finished */
  51 #define DMA_DESC_COD                    (1 << 26) /* Chain on done */
  52 #define DMA_DESC_IOF                    (1 << 27) /* Interrupt on finished */
  53 #define DMA_DESC_IOD                    (1 << 28) /* Interrupt on done */
  54 #define DMA_DESC_TERM                   (1 << 29) /* Terminated */
  55 #define DMA_DESC_DONE                   (1 << 30) /* Done */
  56 #define DMA_DESC_FINI                   (1 << 31) /* Finished */
  57 
  58 /*
  59  * DMA register (within Internal Register Map).
  60  */
  61 
  62 struct dma_reg {
  63         u32 dmac;               /* Control. */
  64         u32 dmas;               /* Status. */
  65         u32 dmasm;              /* Mask. */
  66         u32 dmadptr;            /* Descriptor pointer. */
  67         u32 dmandptr;           /* Next descriptor pointer. */
  68 };
  69 
  70 /* DMA channels specific registers */
  71 #define DMA_CHAN_RUN_BIT                (1 << 0)
  72 #define DMA_CHAN_DONE_BIT               (1 << 1)
  73 #define DMA_CHAN_MODE_BIT               (1 << 2)
  74 #define DMA_CHAN_MODE_MSK               0x0000000c
  75 #define  DMA_CHAN_MODE_AUTO             0
  76 #define  DMA_CHAN_MODE_BURST            1
  77 #define  DMA_CHAN_MODE_XFRT             2
  78 #define  DMA_CHAN_MODE_RSVD             3
  79 #define DMA_CHAN_ACT_BIT                (1 << 4)
  80 
  81 /* DMA status registers */
  82 #define DMA_STAT_FINI                   (1 << 0)
  83 #define DMA_STAT_DONE                   (1 << 1)
  84 #define DMA_STAT_CHAIN                  (1 << 2)
  85 #define DMA_STAT_ERR                    (1 << 3)
  86 #define DMA_STAT_HALT                   (1 << 4)
  87 
  88 /*
  89  * DMA channel definitions
  90  */
  91 
  92 #define DMA_CHAN_ETH_RCV                0
  93 #define DMA_CHAN_ETH_XMT                1
  94 #define DMA_CHAN_MEM_TO_FIFO            2
  95 #define DMA_CHAN_FIFO_TO_MEM            3
  96 #define DMA_CHAN_PCI_TO_MEM             4
  97 #define DMA_CHAN_MEM_TO_PCI             5
  98 #define DMA_CHAN_COUNT                  6
  99 
 100 struct dma_channel {
 101         struct dma_reg ch[DMA_CHAN_COUNT];
 102 };
 103 
 104 #endif  /* __ASM_RC32434_DMA_H */