This source file includes following definitions.
- file_to_cio2_queue
- vb2q_to_cio2_queue
1
2
3
4 #ifndef __IPU3_CIO2_H
5 #define __IPU3_CIO2_H
6
7 #define CIO2_NAME "ipu3-cio2"
8 #define CIO2_DEVICE_NAME "Intel IPU3 CIO2"
9 #define CIO2_ENTITY_NAME "ipu3-csi2"
10 #define CIO2_PCI_ID 0x9d32
11 #define CIO2_PCI_BAR 0
12 #define CIO2_DMA_MASK DMA_BIT_MASK(39)
13
14 #define CIO2_IMAGE_MAX_WIDTH 4224
15 #define CIO2_IMAGE_MAX_LENGTH 3136
16
17
18 #define CIO2_MAX_LOPS 8
19 #define CIO2_MAX_BUFFERS (PAGE_SIZE / 16 / CIO2_MAX_LOPS)
20
21 #define CIO2_PAD_SINK 0
22 #define CIO2_PAD_SOURCE 1
23 #define CIO2_PADS 2
24
25 #define CIO2_NUM_DMA_CHAN 20
26 #define CIO2_NUM_PORTS 4
27
28
29 #define CIO2_QUEUES CIO2_NUM_PORTS
30
31
32 #define CIO2_REG_PIPE_BASE(n) ((n) * 0x0400)
33 #define CIO2_REG_CSIRX_BASE 0x000
34 #define CIO2_REG_MIPIBE_BASE 0x100
35 #define CIO2_REG_PIXELGEN_BAS 0x200
36 #define CIO2_REG_IRQCTRL_BASE 0x300
37 #define CIO2_REG_GPREG_BASE 0x1000
38
39
40 #define CIO2_REG_CSIRX_ENABLE (CIO2_REG_CSIRX_BASE + 0x0)
41 #define CIO2_REG_CSIRX_NOF_ENABLED_LANES (CIO2_REG_CSIRX_BASE + 0x4)
42 #define CIO2_REG_CSIRX_SP_IF_CONFIG (CIO2_REG_CSIRX_BASE + 0x10)
43 #define CIO2_REG_CSIRX_LP_IF_CONFIG (CIO2_REG_CSIRX_BASE + 0x14)
44 #define CIO2_CSIRX_IF_CONFIG_FILTEROUT 0x00
45 #define CIO2_CSIRX_IF_CONFIG_FILTEROUT_VC_INACTIVE 0x01
46 #define CIO2_CSIRX_IF_CONFIG_PASS 0x02
47 #define CIO2_CSIRX_IF_CONFIG_FLAG_ERROR BIT(2)
48 #define CIO2_REG_CSIRX_STATUS (CIO2_REG_CSIRX_BASE + 0x18)
49 #define CIO2_REG_CSIRX_STATUS_DLANE_HS (CIO2_REG_CSIRX_BASE + 0x1c)
50 #define CIO2_CSIRX_STATUS_DLANE_HS_MASK 0xff
51 #define CIO2_REG_CSIRX_STATUS_DLANE_LP (CIO2_REG_CSIRX_BASE + 0x20)
52 #define CIO2_CSIRX_STATUS_DLANE_LP_MASK 0xffffff
53
54 #define CIO2_REG_CSIRX_DLY_CNT_TERMEN(lane) \
55 (CIO2_REG_CSIRX_BASE + 0x2c + 8 * (lane))
56 #define CIO2_REG_CSIRX_DLY_CNT_SETTLE(lane) \
57 (CIO2_REG_CSIRX_BASE + 0x30 + 8 * (lane))
58
59 #define CIO2_REG_MIPIBE_ENABLE (CIO2_REG_MIPIBE_BASE + 0x0)
60 #define CIO2_REG_MIPIBE_STATUS (CIO2_REG_MIPIBE_BASE + 0x4)
61 #define CIO2_REG_MIPIBE_COMP_FORMAT(vc) \
62 (CIO2_REG_MIPIBE_BASE + 0x8 + 0x4 * (vc))
63 #define CIO2_REG_MIPIBE_FORCE_RAW8 (CIO2_REG_MIPIBE_BASE + 0x20)
64 #define CIO2_REG_MIPIBE_FORCE_RAW8_ENABLE BIT(0)
65 #define CIO2_REG_MIPIBE_FORCE_RAW8_USE_TYPEID BIT(1)
66 #define CIO2_REG_MIPIBE_FORCE_RAW8_TYPEID_SHIFT 2
67
68 #define CIO2_REG_MIPIBE_IRQ_STATUS (CIO2_REG_MIPIBE_BASE + 0x24)
69 #define CIO2_REG_MIPIBE_IRQ_CLEAR (CIO2_REG_MIPIBE_BASE + 0x28)
70 #define CIO2_REG_MIPIBE_GLOBAL_LUT_DISREGARD (CIO2_REG_MIPIBE_BASE + 0x68)
71 #define CIO2_MIPIBE_GLOBAL_LUT_DISREGARD 1
72 #define CIO2_REG_MIPIBE_PKT_STALL_STATUS (CIO2_REG_MIPIBE_BASE + 0x6c)
73 #define CIO2_REG_MIPIBE_PARSE_GSP_THROUGH_LP_LUT_REG_IDX \
74 (CIO2_REG_MIPIBE_BASE + 0x70)
75 #define CIO2_REG_MIPIBE_SP_LUT_ENTRY(vc) \
76 (CIO2_REG_MIPIBE_BASE + 0x74 + 4 * (vc))
77 #define CIO2_REG_MIPIBE_LP_LUT_ENTRY(m) \
78 (CIO2_REG_MIPIBE_BASE + 0x84 + 4 * (m))
79 #define CIO2_MIPIBE_LP_LUT_ENTRY_DISREGARD 1
80 #define CIO2_MIPIBE_LP_LUT_ENTRY_SID_SHIFT 1
81 #define CIO2_MIPIBE_LP_LUT_ENTRY_VC_SHIFT 5
82 #define CIO2_MIPIBE_LP_LUT_ENTRY_FORMAT_TYPE_SHIFT 7
83
84
85
86 #define CIO2_REG_IRQCTRL_EDGE (CIO2_REG_IRQCTRL_BASE + 0x00)
87 #define CIO2_REG_IRQCTRL_MASK (CIO2_REG_IRQCTRL_BASE + 0x04)
88 #define CIO2_REG_IRQCTRL_STATUS (CIO2_REG_IRQCTRL_BASE + 0x08)
89 #define CIO2_REG_IRQCTRL_CLEAR (CIO2_REG_IRQCTRL_BASE + 0x0c)
90 #define CIO2_REG_IRQCTRL_ENABLE (CIO2_REG_IRQCTRL_BASE + 0x10)
91 #define CIO2_REG_IRQCTRL_LEVEL_NOT_PULSE (CIO2_REG_IRQCTRL_BASE + 0x14)
92
93 #define CIO2_REG_GPREG_SRST (CIO2_REG_GPREG_BASE + 0x0)
94 #define CIO2_GPREG_SRST_ALL 0xffff
95 #define CIO2_REG_FB_HPLL_FREQ (CIO2_REG_GPREG_BASE + 0x08)
96 #define CIO2_REG_ISCLK_RATIO (CIO2_REG_GPREG_BASE + 0xc)
97
98 #define CIO2_REG_CGC 0x1400
99 #define CIO2_CGC_CSI2_TGE BIT(0)
100 #define CIO2_CGC_PRIM_TGE BIT(1)
101 #define CIO2_CGC_SIDE_TGE BIT(2)
102 #define CIO2_CGC_XOSC_TGE BIT(3)
103 #define CIO2_CGC_MPLL_SHUTDOWN_EN BIT(4)
104 #define CIO2_CGC_D3I3_TGE BIT(5)
105 #define CIO2_CGC_CSI2_INTERFRAME_TGE BIT(6)
106 #define CIO2_CGC_CSI2_PORT_DCGE BIT(8)
107 #define CIO2_CGC_CSI2_DCGE BIT(9)
108 #define CIO2_CGC_SIDE_DCGE BIT(10)
109 #define CIO2_CGC_PRIM_DCGE BIT(11)
110 #define CIO2_CGC_ROSC_DCGE BIT(12)
111 #define CIO2_CGC_XOSC_DCGE BIT(13)
112 #define CIO2_CGC_FLIS_DCGE BIT(14)
113 #define CIO2_CGC_CLKGATE_HOLDOFF_SHIFT 20
114 #define CIO2_CGC_CSI_CLKGATE_HOLDOFF_SHIFT 24
115 #define CIO2_REG_D0I3C 0x1408
116 #define CIO2_D0I3C_I3 BIT(2)
117 #define CIO2_D0I3C_RR BIT(3)
118 #define CIO2_REG_SWRESET 0x140c
119 #define CIO2_SWRESET_SWRESET 1
120 #define CIO2_REG_SENSOR_ACTIVE 0x1410
121 #define CIO2_REG_INT_STS 0x1414
122 #define CIO2_REG_INT_STS_EXT_OE 0x1418
123 #define CIO2_INT_EXT_OE_DMAOE_SHIFT 0
124 #define CIO2_INT_EXT_OE_DMAOE_MASK 0x7ffff
125 #define CIO2_INT_EXT_OE_OES_SHIFT 24
126 #define CIO2_INT_EXT_OE_OES_MASK (0xf << CIO2_INT_EXT_OE_OES_SHIFT)
127 #define CIO2_REG_INT_EN 0x1420
128 #define CIO2_REG_INT_EN_IRQ (1 << 24)
129 #define CIO2_REG_INT_EN_IOS(dma) (1 << (((dma) >> 1) + 12))
130
131
132
133
134 #define CIO2_INT_IOC(dma) (1 << ((dma) < 4 ? (dma) : ((dma) >> 1) + 2))
135 #define CIO2_INT_IOC_SHIFT 0
136 #define CIO2_INT_IOC_MASK (0x7ff << CIO2_INT_IOC_SHIFT)
137 #define CIO2_INT_IOS_IOLN(dma) (1 << (((dma) >> 1) + 12))
138 #define CIO2_INT_IOS_IOLN_SHIFT 12
139 #define CIO2_INT_IOS_IOLN_MASK (0x3ff << CIO2_INT_IOS_IOLN_SHIFT)
140 #define CIO2_INT_IOIE BIT(22)
141 #define CIO2_INT_IOOE BIT(23)
142 #define CIO2_INT_IOIRQ BIT(24)
143 #define CIO2_REG_INT_EN_EXT_OE 0x1424
144 #define CIO2_REG_DMA_DBG 0x1448
145 #define CIO2_REG_DMA_DBG_DMA_INDEX_SHIFT 0
146 #define CIO2_REG_PBM_ARB_CTRL 0x1460
147 #define CIO2_PBM_ARB_CTRL_LANES_DIV 0
148 #define CIO2_PBM_ARB_CTRL_LANES_DIV_SHIFT 0
149 #define CIO2_PBM_ARB_CTRL_LE_EN BIT(7)
150 #define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN 2
151 #define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN_SHIFT 8
152 #define CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP 480
153 #define CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP_SHIFT 16
154 #define CIO2_REG_PBM_WMCTRL1 0x1464
155 #define CIO2_PBM_WMCTRL1_MIN_2CK_SHIFT 0
156 #define CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT 8
157 #define CIO2_PBM_WMCTRL1_MID2_2CK_SHIFT 16
158 #define CIO2_PBM_WMCTRL1_TS_COUNT_DISABLE BIT(31)
159 #define CIO2_PBM_WMCTRL1_MIN_2CK (4 << CIO2_PBM_WMCTRL1_MIN_2CK_SHIFT)
160 #define CIO2_PBM_WMCTRL1_MID1_2CK (16 << CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT)
161 #define CIO2_PBM_WMCTRL1_MID2_2CK (21 << CIO2_PBM_WMCTRL1_MID2_2CK_SHIFT)
162 #define CIO2_REG_PBM_WMCTRL2 0x1468
163 #define CIO2_PBM_WMCTRL2_HWM_2CK 40
164 #define CIO2_PBM_WMCTRL2_HWM_2CK_SHIFT 0
165 #define CIO2_PBM_WMCTRL2_LWM_2CK 22
166 #define CIO2_PBM_WMCTRL2_LWM_2CK_SHIFT 8
167 #define CIO2_PBM_WMCTRL2_OBFFWM_2CK 2
168 #define CIO2_PBM_WMCTRL2_OBFFWM_2CK_SHIFT 16
169 #define CIO2_PBM_WMCTRL2_TRANSDYN 1
170 #define CIO2_PBM_WMCTRL2_TRANSDYN_SHIFT 24
171 #define CIO2_PBM_WMCTRL2_DYNWMEN BIT(28)
172 #define CIO2_PBM_WMCTRL2_OBFF_MEM_EN BIT(29)
173 #define CIO2_PBM_WMCTRL2_OBFF_CPU_EN BIT(30)
174 #define CIO2_PBM_WMCTRL2_DRAINNOW BIT(31)
175 #define CIO2_REG_PBM_TS_COUNT 0x146c
176 #define CIO2_REG_PBM_FOPN_ABORT 0x1474
177
178 #define CIO2_PBM_FOPN_ABORT(n) (0x1 << 8 * (n))
179 #define CIO2_PBM_FOPN_FORCE_ABORT(n) (0x2 << 8 * (n))
180 #define CIO2_PBM_FOPN_FRAMEOPEN(n) (0x8 << 8 * (n))
181 #define CIO2_REG_LTRCTRL 0x1480
182 #define CIO2_LTRCTRL_LTRDYNEN BIT(16)
183 #define CIO2_LTRCTRL_LTRSTABLETIME_SHIFT 8
184 #define CIO2_LTRCTRL_LTRSTABLETIME_MASK 0xff
185 #define CIO2_LTRCTRL_LTRSEL1S3 BIT(7)
186 #define CIO2_LTRCTRL_LTRSEL1S2 BIT(6)
187 #define CIO2_LTRCTRL_LTRSEL1S1 BIT(5)
188 #define CIO2_LTRCTRL_LTRSEL1S0 BIT(4)
189 #define CIO2_LTRCTRL_LTRSEL2S3 BIT(3)
190 #define CIO2_LTRCTRL_LTRSEL2S2 BIT(2)
191 #define CIO2_LTRCTRL_LTRSEL2S1 BIT(1)
192 #define CIO2_LTRCTRL_LTRSEL2S0 BIT(0)
193 #define CIO2_REG_LTRVAL23 0x1484
194 #define CIO2_REG_LTRVAL01 0x1488
195 #define CIO2_LTRVAL02_VAL_SHIFT 0
196 #define CIO2_LTRVAL02_SCALE_SHIFT 10
197 #define CIO2_LTRVAL13_VAL_SHIFT 16
198 #define CIO2_LTRVAL13_SCALE_SHIFT 26
199
200 #define CIO2_LTRVAL0_VAL 175
201
202 #define CIO2_LTRVAL0_SCALE 2
203 #define CIO2_LTRVAL1_VAL 90
204 #define CIO2_LTRVAL1_SCALE 2
205 #define CIO2_LTRVAL2_VAL 90
206 #define CIO2_LTRVAL2_SCALE 2
207 #define CIO2_LTRVAL3_VAL 90
208 #define CIO2_LTRVAL3_SCALE 2
209
210 #define CIO2_REG_CDMABA(n) (0x1500 + 0x10 * (n))
211 #define CIO2_REG_CDMARI(n) (0x1504 + 0x10 * (n))
212 #define CIO2_CDMARI_FBPT_RP_SHIFT 0
213 #define CIO2_CDMARI_FBPT_RP_MASK 0xff
214 #define CIO2_REG_CDMAC0(n) (0x1508 + 0x10 * (n))
215 #define CIO2_CDMAC0_FBPT_LEN_SHIFT 0
216 #define CIO2_CDMAC0_FBPT_WIDTH_SHIFT 8
217 #define CIO2_CDMAC0_FBPT_NS BIT(25)
218 #define CIO2_CDMAC0_DMA_INTR_ON_FS BIT(26)
219 #define CIO2_CDMAC0_DMA_INTR_ON_FE BIT(27)
220 #define CIO2_CDMAC0_FBPT_UPDATE_FIFO_FULL BIT(28)
221 #define CIO2_CDMAC0_FBPT_FIFO_FULL_FIX_DIS BIT(29)
222 #define CIO2_CDMAC0_DMA_EN BIT(30)
223 #define CIO2_CDMAC0_DMA_HALTED BIT(31)
224 #define CIO2_REG_CDMAC1(n) (0x150c + 0x10 * (n))
225 #define CIO2_CDMAC1_LINENUMINT_SHIFT 0
226 #define CIO2_CDMAC1_LINENUMUPDATE_SHIFT 16
227
228 #define CIO2_REG_PXM_PXF_FMT_CFG0(n) (0x1700 + 0x30 * (n))
229 #define CIO2_PXM_PXF_FMT_CFG_SID0_SHIFT 0
230 #define CIO2_PXM_PXF_FMT_CFG_SID1_SHIFT 16
231 #define CIO2_PXM_PXF_FMT_CFG_PCK_64B (0 << 0)
232 #define CIO2_PXM_PXF_FMT_CFG_PCK_32B (1 << 0)
233 #define CIO2_PXM_PXF_FMT_CFG_BPP_08 (0 << 2)
234 #define CIO2_PXM_PXF_FMT_CFG_BPP_10 (1 << 2)
235 #define CIO2_PXM_PXF_FMT_CFG_BPP_12 (2 << 2)
236 #define CIO2_PXM_PXF_FMT_CFG_BPP_14 (3 << 2)
237 #define CIO2_PXM_PXF_FMT_CFG_SPEC_4PPC (0 << 4)
238 #define CIO2_PXM_PXF_FMT_CFG_SPEC_3PPC_RGBA (1 << 4)
239 #define CIO2_PXM_PXF_FMT_CFG_SPEC_3PPC_ARGB (2 << 4)
240 #define CIO2_PXM_PXF_FMT_CFG_SPEC_PLANAR2 (3 << 4)
241 #define CIO2_PXM_PXF_FMT_CFG_SPEC_PLANAR3 (4 << 4)
242 #define CIO2_PXM_PXF_FMT_CFG_SPEC_NV16 (5 << 4)
243 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_1ST_AB (1 << 7)
244 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_1ST_CD (1 << 8)
245 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_2ND_AC (1 << 9)
246 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_2ND_BD (1 << 10)
247 #define CIO2_REG_INT_STS_EXT_IE 0x17e4
248 #define CIO2_REG_INT_EN_EXT_IE 0x17e8
249 #define CIO2_INT_EXT_IE_ECC_RE(n) (0x01 << (8 * (n)))
250 #define CIO2_INT_EXT_IE_DPHY_NR(n) (0x02 << (8 * (n)))
251 #define CIO2_INT_EXT_IE_ECC_NR(n) (0x04 << (8 * (n)))
252 #define CIO2_INT_EXT_IE_CRCERR(n) (0x08 << (8 * (n)))
253 #define CIO2_INT_EXT_IE_INTERFRAMEDATA(n) (0x10 << (8 * (n)))
254 #define CIO2_INT_EXT_IE_PKT2SHORT(n) (0x20 << (8 * (n)))
255 #define CIO2_INT_EXT_IE_PKT2LONG(n) (0x40 << (8 * (n)))
256 #define CIO2_INT_EXT_IE_IRQ(n) (0x80 << (8 * (n)))
257 #define CIO2_REG_PXM_FRF_CFG(n) (0x1720 + 0x30 * (n))
258 #define CIO2_PXM_FRF_CFG_FNSEL BIT(0)
259 #define CIO2_PXM_FRF_CFG_FN_RST BIT(1)
260 #define CIO2_PXM_FRF_CFG_ABORT BIT(2)
261 #define CIO2_PXM_FRF_CFG_CRC_TH_SHIFT 3
262 #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NR BIT(8)
263 #define CIO2_PXM_FRF_CFG_MSK_ECC_RE BIT(9)
264 #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NE BIT(10)
265 #define CIO2_PXM_FRF_CFG_EVEN_ODD_MODE_SHIFT 11
266 #define CIO2_PXM_FRF_CFG_MASK_CRC_THRES BIT(13)
267 #define CIO2_PXM_FRF_CFG_MASK_CSI_ACCEPT BIT(14)
268 #define CIO2_PXM_FRF_CFG_CIOHC_FS_MODE BIT(15)
269 #define CIO2_PXM_FRF_CFG_CIOHC_FRST_FRM_SHIFT 16
270 #define CIO2_REG_PXM_SID2BID0(n) (0x1724 + 0x30 * (n))
271 #define CIO2_FB_HPLL_FREQ 0x2
272 #define CIO2_ISCLK_RATIO 0xc
273
274 #define CIO2_IRQCTRL_MASK 0x3ffff
275
276 #define CIO2_INT_EN_EXT_OE_MASK 0x8f0fffff
277
278 #define CIO2_CGC_CLKGATE_HOLDOFF 3
279 #define CIO2_CGC_CSI_CLKGATE_HOLDOFF 5
280
281 #define CIO2_PXM_FRF_CFG_CRC_TH 16
282
283 #define CIO2_INT_EN_EXT_IE_MASK 0xffffffff
284
285 #define CIO2_DMA_CHAN 0
286
287 #define CIO2_CSIRX_DLY_CNT_CLANE_IDX -1
288
289 #define CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_A 0
290 #define CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_B 0
291 #define CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_A 95
292 #define CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_B -8
293
294 #define CIO2_CSIRX_DLY_CNT_TERMEN_DLANE_A 0
295 #define CIO2_CSIRX_DLY_CNT_TERMEN_DLANE_B 0
296 #define CIO2_CSIRX_DLY_CNT_SETTLE_DLANE_A 85
297 #define CIO2_CSIRX_DLY_CNT_SETTLE_DLANE_B -2
298
299 #define CIO2_CSIRX_DLY_CNT_TERMEN_DEFAULT 0x4
300 #define CIO2_CSIRX_DLY_CNT_SETTLE_DEFAULT 0x570
301
302 #define CIO2_PMCSR_OFFSET 4
303 #define CIO2_PMCSR_D0D3_SHIFT 2
304 #define CIO2_PMCSR_D3 0x3
305
306 struct cio2_csi2_timing {
307 s32 clk_termen;
308 s32 clk_settle;
309 s32 dat_termen;
310 s32 dat_settle;
311 };
312
313 struct cio2_buffer {
314 struct vb2_v4l2_buffer vbb;
315 u32 *lop[CIO2_MAX_LOPS];
316 dma_addr_t lop_bus_addr[CIO2_MAX_LOPS];
317 unsigned int offset;
318 };
319
320 struct csi2_bus_info {
321 u32 port;
322 u32 lanes;
323 };
324
325 struct cio2_queue {
326
327 struct mutex lock;
328 struct media_pipeline pipe;
329 struct csi2_bus_info csi2;
330 struct v4l2_subdev *sensor;
331 void __iomem *csi_rx_base;
332
333
334 struct v4l2_subdev subdev;
335 struct media_pad subdev_pads[CIO2_PADS];
336 struct v4l2_mbus_framefmt subdev_fmt;
337 atomic_t frame_sequence;
338
339
340 struct video_device vdev;
341 struct media_pad vdev_pad;
342 struct v4l2_pix_format_mplane format;
343 struct vb2_queue vbq;
344
345
346 struct cio2_fbpt_entry *fbpt;
347 dma_addr_t fbpt_bus_addr;
348 struct cio2_buffer *bufs[CIO2_MAX_BUFFERS];
349 unsigned int bufs_first;
350 unsigned int bufs_next;
351 atomic_t bufs_queued;
352 };
353
354 struct cio2_device {
355 struct pci_dev *pci_dev;
356 void __iomem *base;
357 struct v4l2_device v4l2_dev;
358 struct cio2_queue queue[CIO2_QUEUES];
359 struct cio2_queue *cur_queue;
360
361 struct mutex lock;
362
363 bool streaming;
364 struct v4l2_async_notifier notifier;
365 struct media_device media_dev;
366
367
368
369
370
371 void *dummy_page;
372
373 dma_addr_t dummy_page_bus_addr;
374
375 u32 *dummy_lop;
376
377 dma_addr_t dummy_lop_bus_addr;
378 };
379
380
381
382
383
384
385 #define SENSOR_VIR_CH_DFLT 0
386
387
388 #define CIO2_FBPT_SIZE (CIO2_MAX_BUFFERS * CIO2_MAX_LOPS * \
389 sizeof(struct cio2_fbpt_entry))
390
391 #define CIO2_FBPT_SUBENTRY_UNIT 4
392 #define CIO2_PAGE_SIZE 4096
393
394
395 #define CIO2_FBPT_CTRL_VALID BIT(0)
396 #define CIO2_FBPT_CTRL_IOC BIT(1)
397 #define CIO2_FBPT_CTRL_IOS BIT(2)
398 #define CIO2_FBPT_CTRL_SUCCXFAIL BIT(3)
399 #define CIO2_FBPT_CTRL_CMPLCODE_SHIFT 4
400
401
402
403
404
405
406 struct __packed cio2_fbpt_entry {
407 union {
408 struct __packed {
409 u32 ctrl;
410 u16 cur_line_num;
411 u16 frame_num;
412 u32 first_page_offset;
413 } first_entry;
414
415 struct __packed {
416 u32 timestamp;
417 u32 num_of_bytes;
418
419 u16 last_page_available_bytes;
420
421 u16 num_of_pages;
422 } second_entry;
423 };
424 u32 lop_page_addr;
425 };
426
427 static inline struct cio2_queue *file_to_cio2_queue(struct file *file)
428 {
429 return container_of(video_devdata(file), struct cio2_queue, vdev);
430 }
431
432 static inline struct cio2_queue *vb2q_to_cio2_queue(struct vb2_queue *vq)
433 {
434 return container_of(vq, struct cio2_queue, vbq);
435 }
436
437 #endif