drivers/media/pci/cx23885/cx23888-ir.c

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This source file includes following definitions.
to_state
cx23888_ir_write4
cx23888_ir_read4
cx23888_ir_and_or4
count_to_clock_divider
ns_to_clock_divider
clock_divider_to_ns
carrier_freq_to_clock_divider
clock_divider_to_carrier_freq
freq_to_clock_divider
clock_divider_to_freq
count_to_lpf_count
ns_to_lpf_count
lpf_count_to_ns
lpf_count_to_us
clock_divider_to_resolution
pulse_width_count_to_ns
pulse_width_count_to_us
ns_to_pulse_clocks
pulse_clocks_to_clock_divider
control_tx_irq_watermark
control_rx_irq_watermark
control_tx_enable
control_rx_enable
control_tx_modulation_enable
control_rx_demodulation_enable
control_rx_s_edge_detection
control_rx_s_carrier_window
control_tx_polarity_invert
control_tx_level_invert
txclk_tx_s_carrier
rxclk_rx_s_carrier
txclk_tx_s_max_pulse_width
rxclk_rx_s_max_pulse_width
cduty_tx_s_duty_cycle
filter_rx_s_min_width
irqenable_rx
irqenable_tx
cx23888_ir_irq_handler
cx23888_ir_rx_read
cx23888_ir_rx_g_parameters
cx23888_ir_rx_shutdown
cx23888_ir_rx_s_parameters
cx23888_ir_tx_write
cx23888_ir_tx_g_parameters
cx23888_ir_tx_shutdown
cx23888_ir_tx_s_parameters
cx23888_ir_log_status
cx23888_ir_g_register
cx23888_ir_s_register
cx23888_ir_probe
cx23888_ir_remove
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  Driver for the Conexant CX23885/7/8 PCIe bridge
   4  *
   5  *  CX23888 Integrated Consumer Infrared Controller
   6  *
   7  *  Copyright (C) 2009  Andy Walls <awalls@md.metrocast.net>
   8  */
   9 
  10 #include "cx23885.h"
  11 #include "cx23888-ir.h"
  12 
  13 #include <linux/kfifo.h>
  14 #include <linux/slab.h>
  15 
  16 #include <media/v4l2-device.h>
  17 #include <media/rc-core.h>
  18 
  19 static unsigned int ir_888_debug;
  20 module_param(ir_888_debug, int, 0644);
  21 MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]");
  22 
  23 #define CX23888_IR_REG_BASE     0x170000
  24 /*
  25  * These CX23888 register offsets have a straightforward one to one mapping
  26  * to the CX23885 register offsets of 0x200 through 0x218
  27  */
  28 #define CX23888_IR_CNTRL_REG    0x170000
  29 #define CNTRL_WIN_3_3   0x00000000
  30 #define CNTRL_WIN_4_3   0x00000001
  31 #define CNTRL_WIN_3_4   0x00000002
  32 #define CNTRL_WIN_4_4   0x00000003
  33 #define CNTRL_WIN       0x00000003
  34 #define CNTRL_EDG_NONE  0x00000000
  35 #define CNTRL_EDG_FALL  0x00000004
  36 #define CNTRL_EDG_RISE  0x00000008
  37 #define CNTRL_EDG_BOTH  0x0000000C
  38 #define CNTRL_EDG       0x0000000C
  39 #define CNTRL_DMD       0x00000010
  40 #define CNTRL_MOD       0x00000020
  41 #define CNTRL_RFE       0x00000040
  42 #define CNTRL_TFE       0x00000080
  43 #define CNTRL_RXE       0x00000100
  44 #define CNTRL_TXE       0x00000200
  45 #define CNTRL_RIC       0x00000400
  46 #define CNTRL_TIC       0x00000800
  47 #define CNTRL_CPL       0x00001000
  48 #define CNTRL_LBM       0x00002000
  49 #define CNTRL_R         0x00004000
  50 /* CX23888 specific control flag */
  51 #define CNTRL_IVO       0x00008000
  52 
  53 #define CX23888_IR_TXCLK_REG    0x170004
  54 #define TXCLK_TCD       0x0000FFFF
  55 
  56 #define CX23888_IR_RXCLK_REG    0x170008
  57 #define RXCLK_RCD       0x0000FFFF
  58 
  59 #define CX23888_IR_CDUTY_REG    0x17000C
  60 #define CDUTY_CDC       0x0000000F
  61 
  62 #define CX23888_IR_STATS_REG    0x170010
  63 #define STATS_RTO       0x00000001
  64 #define STATS_ROR       0x00000002
  65 #define STATS_RBY       0x00000004
  66 #define STATS_TBY       0x00000008
  67 #define STATS_RSR       0x00000010
  68 #define STATS_TSR       0x00000020
  69 
  70 #define CX23888_IR_IRQEN_REG    0x170014
  71 #define IRQEN_RTE       0x00000001
  72 #define IRQEN_ROE       0x00000002
  73 #define IRQEN_RSE       0x00000010
  74 #define IRQEN_TSE       0x00000020
  75 
  76 #define CX23888_IR_FILTR_REG    0x170018
  77 #define FILTR_LPF       0x0000FFFF
  78 
  79 /* This register doesn't follow the pattern; it's 0x23C on a CX23885 */
  80 #define CX23888_IR_FIFO_REG     0x170040
  81 #define FIFO_RXTX       0x0000FFFF
  82 #define FIFO_RXTX_LVL   0x00010000
  83 #define FIFO_RXTX_RTO   0x0001FFFF
  84 #define FIFO_RX_NDV     0x00020000
  85 #define FIFO_RX_DEPTH   8
  86 #define FIFO_TX_DEPTH   8
  87 
  88 /* CX23888 unique registers */
  89 #define CX23888_IR_SEEDP_REG    0x17001C
  90 #define CX23888_IR_TIMOL_REG    0x170020
  91 #define CX23888_IR_WAKE0_REG    0x170024
  92 #define CX23888_IR_WAKE1_REG    0x170028
  93 #define CX23888_IR_WAKE2_REG    0x17002C
  94 #define CX23888_IR_MASK0_REG    0x170030
  95 #define CX23888_IR_MASK1_REG    0x170034
  96 #define CX23888_IR_MAKS2_REG    0x170038
  97 #define CX23888_IR_DPIPG_REG    0x17003C
  98 #define CX23888_IR_LEARN_REG    0x170044
  99 
 100 #define CX23888_VIDCLK_FREQ     108000000 /* 108 MHz, BT.656 */
 101 #define CX23888_IR_REFCLK_FREQ  (CX23888_VIDCLK_FREQ / 2)
 102 
 103 /*
 104  * We use this union internally for convenience, but callers to tx_write
 105  * and rx_read will be expecting records of type struct ir_raw_event.
 106  * Always ensure the size of this union is dictated by struct ir_raw_event.
 107  */
 108 union cx23888_ir_fifo_rec {
 109         u32 hw_fifo_data;
 110         struct ir_raw_event ir_core_data;
 111 };
 112 
 113 #define CX23888_IR_RX_KFIFO_SIZE    (256 * sizeof(union cx23888_ir_fifo_rec))
 114 #define CX23888_IR_TX_KFIFO_SIZE    (256 * sizeof(union cx23888_ir_fifo_rec))
 115 
 116 struct cx23888_ir_state {
 117         struct v4l2_subdev sd;
 118         struct cx23885_dev *dev;
 119 
 120         struct v4l2_subdev_ir_parameters rx_params;
 121         struct mutex rx_params_lock;
 122         atomic_t rxclk_divider;
 123         atomic_t rx_invert;
 124 
 125         struct kfifo rx_kfifo;
 126         spinlock_t rx_kfifo_lock;
 127 
 128         struct v4l2_subdev_ir_parameters tx_params;
 129         struct mutex tx_params_lock;
 130         atomic_t txclk_divider;
 131 };
 132 
 133 static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd)
 134 {
 135         return v4l2_get_subdevdata(sd);
 136 }
 137 
 138 /*
 139  * IR register block read and write functions
 140  */
 141 static
 142 inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value)
 143 {
 144         cx_write(addr, value);
 145         return 0;
 146 }
 147 
 148 static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr)
 149 {
 150         return cx_read(addr);
 151 }
 152 
 153 static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr,
 154                                      u32 and_mask, u32 or_value)
 155 {
 156         cx_andor(addr, ~and_mask, or_value);
 157         return 0;
 158 }
 159 
 160 /*
 161  * Rx and Tx Clock Divider register computations
 162  *
 163  * Note the largest clock divider value of 0xffff corresponds to:
 164  *      (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
 165  * which fits in 21 bits, so we'll use unsigned int for time arguments.
 166  */
 167 static inline u16 count_to_clock_divider(unsigned int d)
 168 {
 169         if (d > RXCLK_RCD + 1)
 170                 d = RXCLK_RCD;
 171         else if (d < 2)
 172                 d = 1;
 173         else
 174                 d--;
 175         return (u16) d;
 176 }
 177 
 178 static inline u16 ns_to_clock_divider(unsigned int ns)
 179 {
 180         return count_to_clock_divider(
 181                 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
 182 }
 183 
 184 static inline unsigned int clock_divider_to_ns(unsigned int divider)
 185 {
 186         /* Period of the Rx or Tx clock in ns */
 187         return DIV_ROUND_CLOSEST((divider + 1) * 1000,
 188                                  CX23888_IR_REFCLK_FREQ / 1000000);
 189 }
 190 
 191 static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
 192 {
 193         return count_to_clock_divider(
 194                           DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * 16));
 195 }
 196 
 197 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
 198 {
 199         return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
 200 }
 201 
 202 static inline u16 freq_to_clock_divider(unsigned int freq,
 203                                         unsigned int rollovers)
 204 {
 205         return count_to_clock_divider(
 206                    DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * rollovers));
 207 }
 208 
 209 static inline unsigned int clock_divider_to_freq(unsigned int divider,
 210                                                  unsigned int rollovers)
 211 {
 212         return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ,
 213                                  (divider + 1) * rollovers);
 214 }
 215 
 216 /*
 217  * Low Pass Filter register calculations
 218  *
 219  * Note the largest count value of 0xffff corresponds to:
 220  *      0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
 221  * which fits in 21 bits, so we'll use unsigned int for time arguments.
 222  */
 223 static inline u16 count_to_lpf_count(unsigned int d)
 224 {
 225         if (d > FILTR_LPF)
 226                 d = FILTR_LPF;
 227         else if (d < 4)
 228                 d = 0;
 229         return (u16) d;
 230 }
 231 
 232 static inline u16 ns_to_lpf_count(unsigned int ns)
 233 {
 234         return count_to_lpf_count(
 235                 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
 236 }
 237 
 238 static inline unsigned int lpf_count_to_ns(unsigned int count)
 239 {
 240         /* Duration of the Low Pass Filter rejection window in ns */
 241         return DIV_ROUND_CLOSEST(count * 1000,
 242                                  CX23888_IR_REFCLK_FREQ / 1000000);
 243 }
 244 
 245 static inline unsigned int lpf_count_to_us(unsigned int count)
 246 {
 247         /* Duration of the Low Pass Filter rejection window in us */
 248         return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000);
 249 }
 250 
 251 /*
 252  * FIFO register pulse width count computations
 253  */
 254 static u32 clock_divider_to_resolution(u16 divider)
 255 {
 256         /*
 257          * Resolution is the duration of 1 tick of the readable portion of
 258          * of the pulse width counter as read from the FIFO.  The two lsb's are
 259          * not readable, hence the << 2.  This function returns ns.
 260          */
 261         return DIV_ROUND_CLOSEST((1 << 2)  * ((u32) divider + 1) * 1000,
 262                                  CX23888_IR_REFCLK_FREQ / 1000000);
 263 }
 264 
 265 static u64 pulse_width_count_to_ns(u16 count, u16 divider)
 266 {
 267         u64 n;
 268         u32 rem;
 269 
 270         /*
 271          * The 2 lsb's of the pulse width timer count are not readable, hence
 272          * the (count << 2) | 0x3
 273          */
 274         n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
 275         rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000);     /* / MHz => ns */
 276         if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
 277                 n++;
 278         return n;
 279 }
 280 
 281 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
 282 {
 283         u64 n;
 284         u32 rem;
 285 
 286         /*
 287          * The 2 lsb's of the pulse width timer count are not readable, hence
 288          * the (count << 2) | 0x3
 289          */
 290         n = (((u64) count << 2) | 0x3) * (divider + 1);    /* cycles      */
 291         rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
 292         if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
 293                 n++;
 294         return (unsigned int) n;
 295 }
 296 
 297 /*
 298  * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
 299  *
 300  * The total pulse clock count is an 18 bit pulse width timer count as the most
 301  * significant part and (up to) 16 bit clock divider count as a modulus.
 302  * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
 303  * width timer count's least significant bit.
 304  */
 305 static u64 ns_to_pulse_clocks(u32 ns)
 306 {
 307         u64 clocks;
 308         u32 rem;
 309         clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles  */
 310         rem = do_div(clocks, 1000);                         /* /1000 = cycles */
 311         if (rem >= 1000 / 2)
 312                 clocks++;
 313         return clocks;
 314 }
 315 
 316 static u16 pulse_clocks_to_clock_divider(u64 count)
 317 {
 318         do_div(count, (FIFO_RXTX << 2) | 0x3);
 319 
 320         /* net result needs to be rounded down and decremented by 1 */
 321         if (count > RXCLK_RCD + 1)
 322                 count = RXCLK_RCD;
 323         else if (count < 2)
 324                 count = 1;
 325         else
 326                 count--;
 327         return (u16) count;
 328 }
 329 
 330 /*
 331  * IR Control Register helpers
 332  */
 333 enum tx_fifo_watermark {
 334         TX_FIFO_HALF_EMPTY = 0,
 335         TX_FIFO_EMPTY      = CNTRL_TIC,
 336 };
 337 
 338 enum rx_fifo_watermark {
 339         RX_FIFO_HALF_FULL = 0,
 340         RX_FIFO_NOT_EMPTY = CNTRL_RIC,
 341 };
 342 
 343 static inline void control_tx_irq_watermark(struct cx23885_dev *dev,
 344                                             enum tx_fifo_watermark level)
 345 {
 346         cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_TIC, level);
 347 }
 348 
 349 static inline void control_rx_irq_watermark(struct cx23885_dev *dev,
 350                                             enum rx_fifo_watermark level)
 351 {
 352         cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_RIC, level);
 353 }
 354 
 355 static inline void control_tx_enable(struct cx23885_dev *dev, bool enable)
 356 {
 357         cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
 358                            enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
 359 }
 360 
 361 static inline void control_rx_enable(struct cx23885_dev *dev, bool enable)
 362 {
 363         cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
 364                            enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
 365 }
 366 
 367 static inline void control_tx_modulation_enable(struct cx23885_dev *dev,
 368                                                 bool enable)
 369 {
 370         cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_MOD,
 371                            enable ? CNTRL_MOD : 0);
 372 }
 373 
 374 static inline void control_rx_demodulation_enable(struct cx23885_dev *dev,
 375                                                   bool enable)
 376 {
 377         cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_DMD,
 378                            enable ? CNTRL_DMD : 0);
 379 }
 380 
 381 static inline void control_rx_s_edge_detection(struct cx23885_dev *dev,
 382                                                u32 edge_types)
 383 {
 384         cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
 385                            edge_types & CNTRL_EDG_BOTH);
 386 }
 387 
 388 static void control_rx_s_carrier_window(struct cx23885_dev *dev,
 389                                         unsigned int carrier,
 390                                         unsigned int *carrier_range_low,
 391                                         unsigned int *carrier_range_high)
 392 {
 393         u32 v;
 394         unsigned int c16 = carrier * 16;
 395 
 396         if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
 397                 v = CNTRL_WIN_3_4;
 398                 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
 399         } else {
 400                 v = CNTRL_WIN_3_3;
 401                 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
 402         }
 403 
 404         if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
 405                 v |= CNTRL_WIN_4_3;
 406                 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
 407         } else {
 408                 v |= CNTRL_WIN_3_3;
 409                 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
 410         }
 411         cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v);
 412 }
 413 
 414 static inline void control_tx_polarity_invert(struct cx23885_dev *dev,
 415                                               bool invert)
 416 {
 417         cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_CPL,
 418                            invert ? CNTRL_CPL : 0);
 419 }
 420 
 421 static inline void control_tx_level_invert(struct cx23885_dev *dev,
 422                                           bool invert)
 423 {
 424         cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_IVO,
 425                            invert ? CNTRL_IVO : 0);
 426 }
 427 
 428 /*
 429  * IR Rx & Tx Clock Register helpers
 430  */
 431 static unsigned int txclk_tx_s_carrier(struct cx23885_dev *dev,
 432                                        unsigned int freq,
 433                                        u16 *divider)
 434 {
 435         *divider = carrier_freq_to_clock_divider(freq);
 436         cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
 437         return clock_divider_to_carrier_freq(*divider);
 438 }
 439 
 440 static unsigned int rxclk_rx_s_carrier(struct cx23885_dev *dev,
 441                                        unsigned int freq,
 442                                        u16 *divider)
 443 {
 444         *divider = carrier_freq_to_clock_divider(freq);
 445         cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
 446         return clock_divider_to_carrier_freq(*divider);
 447 }
 448 
 449 static u32 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
 450                                       u16 *divider)
 451 {
 452         u64 pulse_clocks;
 453 
 454         if (ns > IR_MAX_DURATION)
 455                 ns = IR_MAX_DURATION;
 456         pulse_clocks = ns_to_pulse_clocks(ns);
 457         *divider = pulse_clocks_to_clock_divider(pulse_clocks);
 458         cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
 459         return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
 460 }
 461 
 462 static u32 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
 463                                       u16 *divider)
 464 {
 465         u64 pulse_clocks;
 466 
 467         if (ns > IR_MAX_DURATION)
 468                 ns = IR_MAX_DURATION;
 469         pulse_clocks = ns_to_pulse_clocks(ns);
 470         *divider = pulse_clocks_to_clock_divider(pulse_clocks);
 471         cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
 472         return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
 473 }
 474 
 475 /*
 476  * IR Tx Carrier Duty Cycle register helpers
 477  */
 478 static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev,
 479                                           unsigned int duty_cycle)
 480 {
 481         u32 n;
 482         n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
 483         if (n != 0)
 484                 n--;
 485         if (n > 15)
 486                 n = 15;
 487         cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n);
 488         return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
 489 }
 490 
 491 /*
 492  * IR Filter Register helpers
 493  */
 494 static u32 filter_rx_s_min_width(struct cx23885_dev *dev, u32 min_width_ns)
 495 {
 496         u32 count = ns_to_lpf_count(min_width_ns);
 497         cx23888_ir_write4(dev, CX23888_IR_FILTR_REG, count);
 498         return lpf_count_to_ns(count);
 499 }
 500 
 501 /*
 502  * IR IRQ Enable Register helpers
 503  */
 504 static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask)
 505 {
 506         mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
 507         cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG,
 508                            ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
 509 }
 510 
 511 static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask)
 512 {
 513         mask &= IRQEN_TSE;
 514         cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask);
 515 }
 516 
 517 /*
 518  * V4L2 Subdevice IR Ops
 519  */
 520 static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status,
 521                                   bool *handled)
 522 {
 523         struct cx23888_ir_state *state = to_state(sd);
 524         struct cx23885_dev *dev = state->dev;
 525         unsigned long flags;
 526 
 527         u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
 528         u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
 529         u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
 530 
 531         union cx23888_ir_fifo_rec rx_data[FIFO_RX_DEPTH];
 532         unsigned int i, j, k;
 533         u32 events, v;
 534         int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
 535 
 536         tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
 537         rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
 538         rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
 539         ror = stats & STATS_ROR; /* Rx FIFO Over Run */
 540 
 541         tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
 542         rse = irqen & IRQEN_RSE; /* Rx FIFO Service Request IRQ Enable */
 543         rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
 544         roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
 545 
 546         *handled = false;
 547         v4l2_dbg(2, ir_888_debug, sd, "IRQ Status:  %s %s %s %s %s %s\n",
 548                  tsr ? "tsr" : "   ", rsr ? "rsr" : "   ",
 549                  rto ? "rto" : "   ", ror ? "ror" : "   ",
 550                  stats & STATS_TBY ? "tby" : "   ",
 551                  stats & STATS_RBY ? "rby" : "   ");
 552 
 553         v4l2_dbg(2, ir_888_debug, sd, "IRQ Enables: %s %s %s %s\n",
 554                  tse ? "tse" : "   ", rse ? "rse" : "   ",
 555                  rte ? "rte" : "   ", roe ? "roe" : "   ");
 556 
 557         /*
 558          * Transmitter interrupt service
 559          */
 560         if (tse && tsr) {
 561                 /*
 562                  * TODO:
 563                  * Check the watermark threshold setting
 564                  * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
 565                  * Push the data to the hardware FIFO.
 566                  * If there was nothing more to send in the tx_kfifo, disable
 567                  *      the TSR IRQ and notify the v4l2_device.
 568                  * If there was something in the tx_kfifo, check the tx_kfifo
 569                  *      level and notify the v4l2_device, if it is low.
 570                  */
 571                 /* For now, inhibit TSR interrupt until Tx is implemented */
 572                 irqenable_tx(dev, 0);
 573                 events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
 574                 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
 575                 *handled = true;
 576         }
 577 
 578         /*
 579          * Receiver interrupt service
 580          */
 581         kror = 0;
 582         if ((rse && rsr) || (rte && rto)) {
 583                 /*
 584                  * Receive data on RSR to clear the STATS_RSR.
 585                  * Receive data on RTO, since we may not have yet hit the RSR
 586                  * watermark when we receive the RTO.
 587                  */
 588                 for (i = 0, v = FIFO_RX_NDV;
 589                      (v & FIFO_RX_NDV) && !kror; i = 0) {
 590                         for (j = 0;
 591                              (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
 592                                 v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG);
 593                                 rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
 594                                 i++;
 595                         }
 596                         if (i == 0)
 597                                 break;
 598                         j = i * sizeof(union cx23888_ir_fifo_rec);
 599                         k = kfifo_in_locked(&state->rx_kfifo,
 600                                       (unsigned char *) rx_data, j,
 601                                       &state->rx_kfifo_lock);
 602                         if (k != j)
 603                                 kror++; /* rx_kfifo over run */
 604                 }
 605                 *handled = true;
 606         }
 607 
 608         events = 0;
 609         v = 0;
 610         if (kror) {
 611                 events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
 612                 v4l2_err(sd, "IR receiver software FIFO overrun\n");
 613         }
 614         if (roe && ror) {
 615                 /*
 616                  * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
 617                  * the Rx FIFO Over Run status (STATS_ROR)
 618                  */
 619                 v |= CNTRL_RFE;
 620                 events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
 621                 v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
 622         }
 623         if (rte && rto) {
 624                 /*
 625                  * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
 626                  * the Rx Pulse Width Timer Time Out (STATS_RTO)
 627                  */
 628                 v |= CNTRL_RXE;
 629                 events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
 630         }
 631         if (v) {
 632                 /* Clear STATS_ROR & STATS_RTO as needed by resetting hardware */
 633                 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v);
 634                 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl);
 635                 *handled = true;
 636         }
 637 
 638         spin_lock_irqsave(&state->rx_kfifo_lock, flags);
 639         if (kfifo_len(&state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2)
 640                 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
 641         spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
 642 
 643         if (events)
 644                 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
 645         return 0;
 646 }
 647 
 648 /* Receiver */
 649 static int cx23888_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
 650                               ssize_t *num)
 651 {
 652         struct cx23888_ir_state *state = to_state(sd);
 653         bool invert = (bool) atomic_read(&state->rx_invert);
 654         u16 divider = (u16) atomic_read(&state->rxclk_divider);
 655 
 656         unsigned int i, n;
 657         union cx23888_ir_fifo_rec *p;
 658         unsigned u, v, w;
 659 
 660         n = count / sizeof(union cx23888_ir_fifo_rec)
 661                 * sizeof(union cx23888_ir_fifo_rec);
 662         if (n == 0) {
 663                 *num = 0;
 664                 return 0;
 665         }
 666 
 667         n = kfifo_out_locked(&state->rx_kfifo, buf, n, &state->rx_kfifo_lock);
 668 
 669         n /= sizeof(union cx23888_ir_fifo_rec);
 670         *num = n * sizeof(union cx23888_ir_fifo_rec);
 671 
 672         for (p = (union cx23888_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) {
 673 
 674                 if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
 675                         /* Assume RTO was because of no IR light input */
 676                         u = 0;
 677                         w = 1;
 678                 } else {
 679                         u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0;
 680                         if (invert)
 681                                 u = u ? 0 : 1;
 682                         w = 0;
 683                 }
 684 
 685                 v = (unsigned) pulse_width_count_to_ns(
 686                                   (u16) (p->hw_fifo_data & FIFO_RXTX), divider);
 687                 if (v > IR_MAX_DURATION)
 688                         v = IR_MAX_DURATION;
 689 
 690                 p->ir_core_data = (struct ir_raw_event)
 691                         { .pulse = u, .duration = v, .timeout = w };
 692 
 693                 v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns  %s  %s\n",
 694                          v, u ? "mark" : "space", w ? "(timed out)" : "");
 695                 if (w)
 696                         v4l2_dbg(2, ir_888_debug, sd, "rx read: end of rx\n");
 697         }
 698         return 0;
 699 }
 700 
 701 static int cx23888_ir_rx_g_parameters(struct v4l2_subdev *sd,
 702                                       struct v4l2_subdev_ir_parameters *p)
 703 {
 704         struct cx23888_ir_state *state = to_state(sd);
 705         mutex_lock(&state->rx_params_lock);
 706         memcpy(p, &state->rx_params, sizeof(struct v4l2_subdev_ir_parameters));
 707         mutex_unlock(&state->rx_params_lock);
 708         return 0;
 709 }
 710 
 711 static int cx23888_ir_rx_shutdown(struct v4l2_subdev *sd)
 712 {
 713         struct cx23888_ir_state *state = to_state(sd);
 714         struct cx23885_dev *dev = state->dev;
 715 
 716         mutex_lock(&state->rx_params_lock);
 717 
 718         /* Disable or slow down all IR Rx circuits and counters */
 719         irqenable_rx(dev, 0);
 720         control_rx_enable(dev, false);
 721         control_rx_demodulation_enable(dev, false);
 722         control_rx_s_edge_detection(dev, CNTRL_EDG_NONE);
 723         filter_rx_s_min_width(dev, 0);
 724         cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, RXCLK_RCD);
 725 
 726         state->rx_params.shutdown = true;
 727 
 728         mutex_unlock(&state->rx_params_lock);
 729         return 0;
 730 }
 731 
 732 static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd,
 733                                       struct v4l2_subdev_ir_parameters *p)
 734 {
 735         struct cx23888_ir_state *state = to_state(sd);
 736         struct cx23885_dev *dev = state->dev;
 737         struct v4l2_subdev_ir_parameters *o = &state->rx_params;
 738         u16 rxclk_divider;
 739 
 740         if (p->shutdown)
 741                 return cx23888_ir_rx_shutdown(sd);
 742 
 743         if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
 744                 return -ENOSYS;
 745 
 746         mutex_lock(&state->rx_params_lock);
 747 
 748         o->shutdown = p->shutdown;
 749 
 750         o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
 751 
 752         o->bytes_per_data_element = p->bytes_per_data_element
 753                                   = sizeof(union cx23888_ir_fifo_rec);
 754 
 755         /* Before we tweak the hardware, we have to disable the receiver */
 756         irqenable_rx(dev, 0);
 757         control_rx_enable(dev, false);
 758 
 759         control_rx_demodulation_enable(dev, p->modulation);
 760         o->modulation = p->modulation;
 761 
 762         if (p->modulation) {
 763                 p->carrier_freq = rxclk_rx_s_carrier(dev, p->carrier_freq,
 764                                                      &rxclk_divider);
 765 
 766                 o->carrier_freq = p->carrier_freq;
 767 
 768                 o->duty_cycle = p->duty_cycle = 50;
 769 
 770                 control_rx_s_carrier_window(dev, p->carrier_freq,
 771                                             &p->carrier_range_lower,
 772                                             &p->carrier_range_upper);
 773                 o->carrier_range_lower = p->carrier_range_lower;
 774                 o->carrier_range_upper = p->carrier_range_upper;
 775 
 776                 p->max_pulse_width =
 777                         (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
 778         } else {
 779                 p->max_pulse_width =
 780                             rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width,
 781                                                        &rxclk_divider);
 782         }
 783         o->max_pulse_width = p->max_pulse_width;
 784         atomic_set(&state->rxclk_divider, rxclk_divider);
 785 
 786         p->noise_filter_min_width =
 787                           filter_rx_s_min_width(dev, p->noise_filter_min_width);
 788         o->noise_filter_min_width = p->noise_filter_min_width;
 789 
 790         p->resolution = clock_divider_to_resolution(rxclk_divider);
 791         o->resolution = p->resolution;
 792 
 793         /* FIXME - make this dependent on resolution for better performance */
 794         control_rx_irq_watermark(dev, RX_FIFO_HALF_FULL);
 795 
 796         control_rx_s_edge_detection(dev, CNTRL_EDG_BOTH);
 797 
 798         o->invert_level = p->invert_level;
 799         atomic_set(&state->rx_invert, p->invert_level);
 800 
 801         o->interrupt_enable = p->interrupt_enable;
 802         o->enable = p->enable;
 803         if (p->enable) {
 804                 unsigned long flags;
 805 
 806                 spin_lock_irqsave(&state->rx_kfifo_lock, flags);
 807                 kfifo_reset(&state->rx_kfifo);
 808                 /* reset tx_fifo too if there is one... */
 809                 spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
 810                 if (p->interrupt_enable)
 811                         irqenable_rx(dev, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
 812                 control_rx_enable(dev, p->enable);
 813         }
 814 
 815         mutex_unlock(&state->rx_params_lock);
 816         return 0;
 817 }
 818 
 819 /* Transmitter */
 820 static int cx23888_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
 821                                ssize_t *num)
 822 {
 823         struct cx23888_ir_state *state = to_state(sd);
 824         struct cx23885_dev *dev = state->dev;
 825         /* For now enable the Tx FIFO Service interrupt & pretend we did work */
 826         irqenable_tx(dev, IRQEN_TSE);
 827         *num = count;
 828         return 0;
 829 }
 830 
 831 static int cx23888_ir_tx_g_parameters(struct v4l2_subdev *sd,
 832                                       struct v4l2_subdev_ir_parameters *p)
 833 {
 834         struct cx23888_ir_state *state = to_state(sd);
 835         mutex_lock(&state->tx_params_lock);
 836         memcpy(p, &state->tx_params, sizeof(struct v4l2_subdev_ir_parameters));
 837         mutex_unlock(&state->tx_params_lock);
 838         return 0;
 839 }
 840 
 841 static int cx23888_ir_tx_shutdown(struct v4l2_subdev *sd)
 842 {
 843         struct cx23888_ir_state *state = to_state(sd);
 844         struct cx23885_dev *dev = state->dev;
 845 
 846         mutex_lock(&state->tx_params_lock);
 847 
 848         /* Disable or slow down all IR Tx circuits and counters */
 849         irqenable_tx(dev, 0);
 850         control_tx_enable(dev, false);
 851         control_tx_modulation_enable(dev, false);
 852         cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, TXCLK_TCD);
 853 
 854         state->tx_params.shutdown = true;
 855 
 856         mutex_unlock(&state->tx_params_lock);
 857         return 0;
 858 }
 859 
 860 static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd,
 861                                       struct v4l2_subdev_ir_parameters *p)
 862 {
 863         struct cx23888_ir_state *state = to_state(sd);
 864         struct cx23885_dev *dev = state->dev;
 865         struct v4l2_subdev_ir_parameters *o = &state->tx_params;
 866         u16 txclk_divider;
 867 
 868         if (p->shutdown)
 869                 return cx23888_ir_tx_shutdown(sd);
 870 
 871         if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
 872                 return -ENOSYS;
 873 
 874         mutex_lock(&state->tx_params_lock);
 875 
 876         o->shutdown = p->shutdown;
 877 
 878         o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
 879 
 880         o->bytes_per_data_element = p->bytes_per_data_element
 881                                   = sizeof(union cx23888_ir_fifo_rec);
 882 
 883         /* Before we tweak the hardware, we have to disable the transmitter */
 884         irqenable_tx(dev, 0);
 885         control_tx_enable(dev, false);
 886 
 887         control_tx_modulation_enable(dev, p->modulation);
 888         o->modulation = p->modulation;
 889 
 890         if (p->modulation) {
 891                 p->carrier_freq = txclk_tx_s_carrier(dev, p->carrier_freq,
 892                                                      &txclk_divider);
 893                 o->carrier_freq = p->carrier_freq;
 894 
 895                 p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle);
 896                 o->duty_cycle = p->duty_cycle;
 897 
 898                 p->max_pulse_width =
 899                         (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
 900         } else {
 901                 p->max_pulse_width =
 902                             txclk_tx_s_max_pulse_width(dev, p->max_pulse_width,
 903                                                        &txclk_divider);
 904         }
 905         o->max_pulse_width = p->max_pulse_width;
 906         atomic_set(&state->txclk_divider, txclk_divider);
 907 
 908         p->resolution = clock_divider_to_resolution(txclk_divider);
 909         o->resolution = p->resolution;
 910 
 911         /* FIXME - make this dependent on resolution for better performance */
 912         control_tx_irq_watermark(dev, TX_FIFO_HALF_EMPTY);
 913 
 914         control_tx_polarity_invert(dev, p->invert_carrier_sense);
 915         o->invert_carrier_sense = p->invert_carrier_sense;
 916 
 917         control_tx_level_invert(dev, p->invert_level);
 918         o->invert_level = p->invert_level;
 919 
 920         o->interrupt_enable = p->interrupt_enable;
 921         o->enable = p->enable;
 922         if (p->enable) {
 923                 if (p->interrupt_enable)
 924                         irqenable_tx(dev, IRQEN_TSE);
 925                 control_tx_enable(dev, p->enable);
 926         }
 927 
 928         mutex_unlock(&state->tx_params_lock);
 929         return 0;
 930 }
 931 
 932 
 933 /*
 934  * V4L2 Subdevice Core Ops
 935  */
 936 static int cx23888_ir_log_status(struct v4l2_subdev *sd)
 937 {
 938         struct cx23888_ir_state *state = to_state(sd);
 939         struct cx23885_dev *dev = state->dev;
 940         char *s;
 941         int i, j;
 942 
 943         u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
 944         u32 txclk = cx23888_ir_read4(dev, CX23888_IR_TXCLK_REG) & TXCLK_TCD;
 945         u32 rxclk = cx23888_ir_read4(dev, CX23888_IR_RXCLK_REG) & RXCLK_RCD;
 946         u32 cduty = cx23888_ir_read4(dev, CX23888_IR_CDUTY_REG) & CDUTY_CDC;
 947         u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
 948         u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
 949         u32 filtr = cx23888_ir_read4(dev, CX23888_IR_FILTR_REG) & FILTR_LPF;
 950 
 951         v4l2_info(sd, "IR Receiver:\n");
 952         v4l2_info(sd, "\tEnabled:                           %s\n",
 953                   cntrl & CNTRL_RXE ? "yes" : "no");
 954         v4l2_info(sd, "\tDemodulation from a carrier:       %s\n",
 955                   cntrl & CNTRL_DMD ? "enabled" : "disabled");
 956         v4l2_info(sd, "\tFIFO:                              %s\n",
 957                   cntrl & CNTRL_RFE ? "enabled" : "disabled");
 958         switch (cntrl & CNTRL_EDG) {
 959         case CNTRL_EDG_NONE:
 960                 s = "disabled";
 961                 break;
 962         case CNTRL_EDG_FALL:
 963                 s = "falling edge";
 964                 break;
 965         case CNTRL_EDG_RISE:
 966                 s = "rising edge";
 967                 break;
 968         case CNTRL_EDG_BOTH:
 969                 s = "rising & falling edges";
 970                 break;
 971         default:
 972                 s = "??? edge";
 973                 break;
 974         }
 975         v4l2_info(sd, "\tPulse timers' start/stop trigger:  %s\n", s);
 976         v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
 977                   cntrl & CNTRL_R ? "not loaded" : "overflow marker");
 978         v4l2_info(sd, "\tFIFO interrupt watermark:          %s\n",
 979                   cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
 980         v4l2_info(sd, "\tLoopback mode:                     %s\n",
 981                   cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
 982         if (cntrl & CNTRL_DMD) {
 983                 v4l2_info(sd, "\tExpected carrier (16 clocks):      %u Hz\n",
 984                           clock_divider_to_carrier_freq(rxclk));
 985                 switch (cntrl & CNTRL_WIN) {
 986                 case CNTRL_WIN_3_3:
 987                         i = 3;
 988                         j = 3;
 989                         break;
 990                 case CNTRL_WIN_4_3:
 991                         i = 4;
 992                         j = 3;
 993                         break;
 994                 case CNTRL_WIN_3_4:
 995                         i = 3;
 996                         j = 4;
 997                         break;
 998                 case CNTRL_WIN_4_4:
 999                         i = 4;
1000                         j = 4;
1001                         break;
1002                 default:
1003                         i = 0;
1004                         j = 0;
1005                         break;
1006                 }
1007                 v4l2_info(sd, "\tNext carrier edge window:          16 clocks -%1d/+%1d, %u to %u Hz\n",
1008                           i, j,
1009                           clock_divider_to_freq(rxclk, 16 + j),
1010                           clock_divider_to_freq(rxclk, 16 - i));
1011         }
1012         v4l2_info(sd, "\tMax measurable pulse width:        %u us, %llu ns\n",
1013                   pulse_width_count_to_us(FIFO_RXTX, rxclk),
1014                   pulse_width_count_to_ns(FIFO_RXTX, rxclk));
1015         v4l2_info(sd, "\tLow pass filter:                   %s\n",
1016                   filtr ? "enabled" : "disabled");
1017         if (filtr)
1018                 v4l2_info(sd, "\tMin acceptable pulse width (LPF):  %u us, %u ns\n",
1019                           lpf_count_to_us(filtr),
1020                           lpf_count_to_ns(filtr));
1021         v4l2_info(sd, "\tPulse width timer timed-out:       %s\n",
1022                   stats & STATS_RTO ? "yes" : "no");
1023         v4l2_info(sd, "\tPulse width timer time-out intr:   %s\n",
1024                   irqen & IRQEN_RTE ? "enabled" : "disabled");
1025         v4l2_info(sd, "\tFIFO overrun:                      %s\n",
1026                   stats & STATS_ROR ? "yes" : "no");
1027         v4l2_info(sd, "\tFIFO overrun interrupt:            %s\n",
1028                   irqen & IRQEN_ROE ? "enabled" : "disabled");
1029         v4l2_info(sd, "\tBusy:                              %s\n",
1030                   stats & STATS_RBY ? "yes" : "no");
1031         v4l2_info(sd, "\tFIFO service requested:            %s\n",
1032                   stats & STATS_RSR ? "yes" : "no");
1033         v4l2_info(sd, "\tFIFO service request interrupt:    %s\n",
1034                   irqen & IRQEN_RSE ? "enabled" : "disabled");
1035 
1036         v4l2_info(sd, "IR Transmitter:\n");
1037         v4l2_info(sd, "\tEnabled:                           %s\n",
1038                   cntrl & CNTRL_TXE ? "yes" : "no");
1039         v4l2_info(sd, "\tModulation onto a carrier:         %s\n",
1040                   cntrl & CNTRL_MOD ? "enabled" : "disabled");
1041         v4l2_info(sd, "\tFIFO:                              %s\n",
1042                   cntrl & CNTRL_TFE ? "enabled" : "disabled");
1043         v4l2_info(sd, "\tFIFO interrupt watermark:          %s\n",
1044                   cntrl & CNTRL_TIC ? "not empty" : "half full or less");
1045         v4l2_info(sd, "\tOutput pin level inversion         %s\n",
1046                   cntrl & CNTRL_IVO ? "yes" : "no");
1047         v4l2_info(sd, "\tCarrier polarity:                  %s\n",
1048                   cntrl & CNTRL_CPL ? "space:burst mark:noburst"
1049                                     : "space:noburst mark:burst");
1050         if (cntrl & CNTRL_MOD) {
1051                 v4l2_info(sd, "\tCarrier (16 clocks):               %u Hz\n",
1052                           clock_divider_to_carrier_freq(txclk));
1053                 v4l2_info(sd, "\tCarrier duty cycle:                %2u/16\n",
1054                           cduty + 1);
1055         }
1056         v4l2_info(sd, "\tMax pulse width:                   %u us, %llu ns\n",
1057                   pulse_width_count_to_us(FIFO_RXTX, txclk),
1058                   pulse_width_count_to_ns(FIFO_RXTX, txclk));
1059         v4l2_info(sd, "\tBusy:                              %s\n",
1060                   stats & STATS_TBY ? "yes" : "no");
1061         v4l2_info(sd, "\tFIFO service requested:            %s\n",
1062                   stats & STATS_TSR ? "yes" : "no");
1063         v4l2_info(sd, "\tFIFO service request interrupt:    %s\n",
1064                   irqen & IRQEN_TSE ? "enabled" : "disabled");
1065 
1066         return 0;
1067 }
1068 
1069 #ifdef CONFIG_VIDEO_ADV_DEBUG
1070 static int cx23888_ir_g_register(struct v4l2_subdev *sd,
1071                                  struct v4l2_dbg_register *reg)
1072 {
1073         struct cx23888_ir_state *state = to_state(sd);
1074         u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1075 
1076         if ((addr & 0x3) != 0)
1077                 return -EINVAL;
1078         if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1079                 return -EINVAL;
1080         reg->size = 4;
1081         reg->val = cx23888_ir_read4(state->dev, addr);
1082         return 0;
1083 }
1084 
1085 static int cx23888_ir_s_register(struct v4l2_subdev *sd,
1086                                  const struct v4l2_dbg_register *reg)
1087 {
1088         struct cx23888_ir_state *state = to_state(sd);
1089         u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1090 
1091         if ((addr & 0x3) != 0)
1092                 return -EINVAL;
1093         if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1094                 return -EINVAL;
1095         cx23888_ir_write4(state->dev, addr, reg->val);
1096         return 0;
1097 }
1098 #endif
1099 
1100 static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = {
1101         .log_status = cx23888_ir_log_status,
1102 #ifdef CONFIG_VIDEO_ADV_DEBUG
1103         .g_register = cx23888_ir_g_register,
1104         .s_register = cx23888_ir_s_register,
1105 #endif
1106         .interrupt_service_routine = cx23888_ir_irq_handler,
1107 };
1108 
1109 static const struct v4l2_subdev_ir_ops cx23888_ir_ir_ops = {
1110         .rx_read = cx23888_ir_rx_read,
1111         .rx_g_parameters = cx23888_ir_rx_g_parameters,
1112         .rx_s_parameters = cx23888_ir_rx_s_parameters,
1113 
1114         .tx_write = cx23888_ir_tx_write,
1115         .tx_g_parameters = cx23888_ir_tx_g_parameters,
1116         .tx_s_parameters = cx23888_ir_tx_s_parameters,
1117 };
1118 
1119 static const struct v4l2_subdev_ops cx23888_ir_controller_ops = {
1120         .core = &cx23888_ir_core_ops,
1121         .ir = &cx23888_ir_ir_ops,
1122 };
1123 
1124 static const struct v4l2_subdev_ir_parameters default_rx_params = {
1125         .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec),
1126         .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1127 
1128         .enable = false,
1129         .interrupt_enable = false,
1130         .shutdown = true,
1131 
1132         .modulation = true,
1133         .carrier_freq = 36000, /* 36 kHz - RC-5, RC-6, and RC-6A carrier */
1134 
1135         /* RC-5:    666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1136         /* RC-6A:   333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1137         .noise_filter_min_width = 333333, /* ns */
1138         .carrier_range_lower = 35000,
1139         .carrier_range_upper = 37000,
1140         .invert_level = false,
1141 };
1142 
1143 static const struct v4l2_subdev_ir_parameters default_tx_params = {
1144         .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec),
1145         .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1146 
1147         .enable = false,
1148         .interrupt_enable = false,
1149         .shutdown = true,
1150 
1151         .modulation = true,
1152         .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
1153         .duty_cycle = 25,      /* 25 %   - RC-5 carrier */
1154         .invert_level = false,
1155         .invert_carrier_sense = false,
1156 };
1157 
1158 int cx23888_ir_probe(struct cx23885_dev *dev)
1159 {
1160         struct cx23888_ir_state *state;
1161         struct v4l2_subdev *sd;
1162         struct v4l2_subdev_ir_parameters default_params;
1163         int ret;
1164 
1165         state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL);
1166         if (state == NULL)
1167                 return -ENOMEM;
1168 
1169         spin_lock_init(&state->rx_kfifo_lock);
1170         if (kfifo_alloc(&state->rx_kfifo, CX23888_IR_RX_KFIFO_SIZE, GFP_KERNEL))
1171                 return -ENOMEM;
1172 
1173         state->dev = dev;
1174         sd = &state->sd;
1175 
1176         v4l2_subdev_init(sd, &cx23888_ir_controller_ops);
1177         v4l2_set_subdevdata(sd, state);
1178         /* FIXME - fix the formatting of dev->v4l2_dev.name and use it */
1179         snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name);
1180         sd->grp_id = CX23885_HW_888_IR;
1181 
1182         ret = v4l2_device_register_subdev(&dev->v4l2_dev, sd);
1183         if (ret == 0) {
1184                 /*
1185                  * Ensure no interrupts arrive from '888 specific conditions,
1186                  * since we ignore them in this driver to have commonality with
1187                  * similar IR controller cores.
1188                  */
1189                 cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0);
1190 
1191                 mutex_init(&state->rx_params_lock);
1192                 default_params = default_rx_params;
1193                 v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1194 
1195                 mutex_init(&state->tx_params_lock);
1196                 default_params = default_tx_params;
1197                 v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1198         } else {
1199                 kfifo_free(&state->rx_kfifo);
1200         }
1201         return ret;
1202 }
1203 
1204 int cx23888_ir_remove(struct cx23885_dev *dev)
1205 {
1206         struct v4l2_subdev *sd;
1207         struct cx23888_ir_state *state;
1208 
1209         sd = cx23885_find_hw(dev, CX23885_HW_888_IR);
1210         if (sd == NULL)
1211                 return -ENODEV;
1212 
1213         cx23888_ir_rx_shutdown(sd);
1214         cx23888_ir_tx_shutdown(sd);
1215 
1216         state = to_state(sd);
1217         v4l2_device_unregister_subdev(sd);
1218         kfifo_free(&state->rx_kfifo);
1219         kfree(state);
1220         /* Nothing more to free() as state held the actual v4l2_subdev object */
1221         return 0;
1222 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/media/pci/cx23885/cx23888-ir.c

DEFINITIONS
