root/drivers/media/pci/cx18/cx18-io.c

DEFINITIONS

1. cx18_memset_io
2. cx18_sw1_irq_enable
3. cx18_sw1_irq_disable
4. cx18_sw2_irq_enable
5. cx18_sw2_irq_disable
6. cx18_sw2_irq_disable_cpu
7. cx18_setup_page

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  cx18 driver PCI memory mapped IO access routines
   4  *
   5  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   6  *  Copyright (C) 2008  Andy Walls <awalls@md.metrocast.net>
   7  */
   8 
   9 #include "cx18-driver.h"
  10 #include "cx18-io.h"
  11 #include "cx18-irq.h"
  12 
  13 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
  14 {
  15         u8 __iomem *dst = addr;
  16         u16 val2 = val | (val << 8);
  17         u32 val4 = val2 | (val2 << 16);
  18 
  19         /* Align writes on the CX23418's addresses */
  20         if ((count > 0) && ((unsigned long)dst & 1)) {
  21                 cx18_writeb(cx, (u8) val, dst);
  22                 count--;
  23                 dst++;
  24         }
  25         if ((count > 1) && ((unsigned long)dst & 2)) {
  26                 cx18_writew(cx, val2, dst);
  27                 count -= 2;
  28                 dst += 2;
  29         }
  30         while (count > 3) {
  31                 cx18_writel(cx, val4, dst);
  32                 count -= 4;
  33                 dst += 4;
  34         }
  35         if (count > 1) {
  36                 cx18_writew(cx, val2, dst);
  37                 count -= 2;
  38                 dst += 2;
  39         }
  40         if (count > 0)
  41                 cx18_writeb(cx, (u8) val, dst);
  42 }
  43 
  44 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
  45 {
  46         cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
  47         cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;
  48         cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
  49 }
  50 
  51 void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
  52 {
  53         cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;
  54         cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
  55 }
  56 
  57 void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
  58 {
  59         cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
  60         cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val;
  61         cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
  62 }
  63 
  64 void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
  65 {
  66         cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;
  67         cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
  68 }
  69 
  70 void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
  71 {
  72         u32 r;
  73         r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
  74         cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
  75 }
  76 
  77 void cx18_setup_page(struct cx18 *cx, u32 addr)
  78 {
  79         u32 val;
  80         val = cx18_read_reg(cx, 0xD000F8);
  81         val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
  82         cx18_write_reg(cx, val, 0xD000F8);
  83 }