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8 #ifndef _LGDT330X_PRIV_
9 #define _LGDT330X_PRIV_
10
11
12 enum I2C_REG {
13 TOP_CONTROL= 0x00,
14 IRQ_MASK= 0x01,
15 IRQ_STATUS= 0x02,
16 VSB_CARRIER_FREQ0= 0x16,
17 VSB_CARRIER_FREQ1= 0x17,
18 VSB_CARRIER_FREQ2= 0x18,
19 VSB_CARRIER_FREQ3= 0x19,
20 CARRIER_MSEQAM1= 0x1a,
21 CARRIER_MSEQAM2= 0x1b,
22 CARRIER_LOCK= 0x1c,
23 TIMING_RECOVERY= 0x1d,
24 AGC_DELAY0= 0x2a,
25 AGC_DELAY1= 0x2b,
26 AGC_DELAY2= 0x2c,
27 AGC_RF_BANDWIDTH0= 0x2d,
28 AGC_RF_BANDWIDTH1= 0x2e,
29 AGC_RF_BANDWIDTH2= 0x2f,
30 AGC_LOOP_BANDWIDTH0= 0x30,
31 AGC_LOOP_BANDWIDTH1= 0x31,
32 AGC_FUNC_CTRL1= 0x32,
33 AGC_FUNC_CTRL2= 0x33,
34 AGC_FUNC_CTRL3= 0x34,
35 AGC_RFIF_ACC0= 0x39,
36 AGC_RFIF_ACC1= 0x3a,
37 AGC_RFIF_ACC2= 0x3b,
38 AGC_STATUS= 0x3f,
39 SYNC_STATUS_VSB= 0x43,
40 DEMUX_CONTROL= 0x66,
41 LGDT3302_EQPH_ERR0= 0x47,
42 LGDT3302_EQ_ERR1= 0x48,
43 LGDT3302_EQ_ERR2= 0x49,
44 LGDT3302_PH_ERR1= 0x4a,
45 LGDT3302_PH_ERR2= 0x4b,
46 LGDT3302_PACKET_ERR_COUNTER1= 0x6a,
47 LGDT3302_PACKET_ERR_COUNTER2= 0x6b,
48 LGDT3303_EQPH_ERR0= 0x6e,
49 LGDT3303_EQ_ERR1= 0x6f,
50 LGDT3303_EQ_ERR2= 0x70,
51 LGDT3303_PH_ERR1= 0x71,
52 LGDT3303_PH_ERR2= 0x72,
53 LGDT3303_PACKET_ERR_COUNTER1= 0x8b,
54 LGDT3303_PACKET_ERR_COUNTER2= 0x8c,
55 };
56
57 #endif