1
2
3
4
5
6 #ifndef GP8PSK_FE_H
7 #define GP8PSK_FE_H
8
9 #include <linux/types.h>
10
11
12
13 #define GET_8PSK_CONFIG 0x80
14 #define SET_8PSK_CONFIG 0x81
15 #define I2C_WRITE 0x83
16 #define I2C_READ 0x84
17 #define ARM_TRANSFER 0x85
18 #define TUNE_8PSK 0x86
19 #define GET_SIGNAL_STRENGTH 0x87
20 #define LOAD_BCM4500 0x88
21 #define BOOT_8PSK 0x89
22 #define START_INTERSIL 0x8A
23 #define SET_LNB_VOLTAGE 0x8B
24 #define SET_22KHZ_TONE 0x8C
25 #define SEND_DISEQC_COMMAND 0x8D
26 #define SET_DVB_MODE 0x8E
27 #define SET_DN_SWITCH 0x8F
28 #define GET_SIGNAL_LOCK 0x90
29 #define GET_FW_VERS 0x92
30 #define GET_SERIAL_NUMBER 0x93
31 #define USE_EXTRA_VOLT 0x94
32 #define GET_FPGA_VERS 0x95
33 #define CW3K_INIT 0x9d
34
35
36 #define bm8pskStarted 0x01
37 #define bm8pskFW_Loaded 0x02
38 #define bmIntersilOn 0x04
39 #define bmDVBmode 0x08
40 #define bm22kHz 0x10
41 #define bmSEL18V 0x20
42 #define bmDCtuned 0x40
43 #define bmArmed 0x80
44
45
46 #define ADV_MOD_DVB_QPSK 0
47 #define ADV_MOD_TURBO_QPSK 1
48 #define ADV_MOD_TURBO_8PSK 2
49 #define ADV_MOD_TURBO_16QAM 3
50
51 #define ADV_MOD_DCII_C_QPSK 4
52 #define ADV_MOD_DCII_I_QPSK 5
53 #define ADV_MOD_DCII_Q_QPSK 6
54 #define ADV_MOD_DCII_C_OQPSK 7
55 #define ADV_MOD_DSS_QPSK 8
56 #define ADV_MOD_DVB_BPSK 9
57
58
59 #define GP8PSK_FW_REV1 0x020604
60 #define GP8PSK_FW_REV2 0x020704
61 #define GP8PSK_FW_VERS(_fw_vers) \
62 ((_fw_vers)[2]<<0x10 | (_fw_vers)[1]<<0x08 | (_fw_vers)[0])
63
64 struct gp8psk_fe_ops {
65 int (*in)(void *priv, u8 req, u16 value, u16 index, u8 *b, int blen);
66 int (*out)(void *priv, u8 req, u16 value, u16 index, u8 *b, int blen);
67 int (*reload)(void *priv);
68 };
69
70 struct dvb_frontend *gp8psk_fe_attach(const struct gp8psk_fe_ops *ops,
71 void *priv, bool is_rev1);
72
73 #endif