root/drivers/media/dvb-frontends/mxl5xx_defs.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Defines for the Maxlinear MX58x family of tuners/demods
   4  *
   5  * Copyright (C) 2014 Digital Devices GmbH
   6  *
   7  * based on code:
   8  * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
   9  * which was released under GPL V2
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License
  13  * version 2, as published by the Free Software Foundation.
  14  */
  15 
  16 enum MXL_BOOL_E {
  17         MXL_DISABLE = 0,
  18         MXL_ENABLE  = 1,
  19 
  20         MXL_FALSE = 0,
  21         MXL_TRUE  = 1,
  22 
  23         MXL_INVALID = 0,
  24         MXL_VALID   = 1,
  25 
  26         MXL_NO      = 0,
  27         MXL_YES     = 1,
  28 
  29         MXL_OFF     = 0,
  30         MXL_ON      = 1
  31 };
  32 
  33 /* Firmware-Host Command IDs */
  34 enum MXL_HYDRA_HOST_CMD_ID_E {
  35         /* --Device command IDs-- */
  36         MXL_HYDRA_DEV_NO_OP_CMD = 0, /* No OP */
  37 
  38         MXL_HYDRA_DEV_SET_POWER_MODE_CMD = 1,
  39         MXL_HYDRA_DEV_SET_OVERWRITE_DEF_CMD = 2,
  40 
  41         /* Host-used CMD, not used by firmware */
  42         MXL_HYDRA_DEV_FIRMWARE_DOWNLOAD_CMD = 3,
  43 
  44         /* Additional CONTROL types from DTV */
  45         MXL_HYDRA_DEV_SET_BROADCAST_PID_STB_ID_CMD = 4,
  46         MXL_HYDRA_DEV_GET_PMM_SLEEP_CMD = 5,
  47 
  48         /* --Tuner command IDs-- */
  49         MXL_HYDRA_TUNER_TUNE_CMD = 6,
  50         MXL_HYDRA_TUNER_GET_STATUS_CMD = 7,
  51 
  52         /* --Demod command IDs-- */
  53         MXL_HYDRA_DEMOD_SET_PARAM_CMD = 8,
  54         MXL_HYDRA_DEMOD_GET_STATUS_CMD = 9,
  55 
  56         MXL_HYDRA_DEMOD_RESET_FEC_COUNTER_CMD = 10,
  57 
  58         MXL_HYDRA_DEMOD_SET_PKT_NUM_CMD = 11,
  59 
  60         MXL_HYDRA_DEMOD_SET_IQ_SOURCE_CMD = 12,
  61         MXL_HYDRA_DEMOD_GET_IQ_DATA_CMD = 13,
  62 
  63         MXL_HYDRA_DEMOD_GET_M68HC05_VER_CMD = 14,
  64 
  65         MXL_HYDRA_DEMOD_SET_ERROR_COUNTER_MODE_CMD = 15,
  66 
  67         /* --- ABORT channel tune */
  68         MXL_HYDRA_ABORT_TUNE_CMD = 16, /* Abort current tune command. */
  69 
  70         /* --SWM/FSK command IDs-- */
  71         MXL_HYDRA_FSK_RESET_CMD = 17,
  72         MXL_HYDRA_FSK_MSG_CMD = 18,
  73         MXL_HYDRA_FSK_SET_OP_MODE_CMD = 19,
  74 
  75         /* --DiSeqC command IDs-- */
  76         MXL_HYDRA_DISEQC_MSG_CMD = 20,
  77         MXL_HYDRA_DISEQC_COPY_MSG_TO_MAILBOX = 21,
  78         MXL_HYDRA_DISEQC_CFG_MSG_CMD = 22,
  79 
  80         /* --- FFT Debug Command IDs-- */
  81         MXL_HYDRA_REQ_FFT_SPECTRUM_CMD = 23,
  82 
  83         /* -- Demod scramblle code */
  84         MXL_HYDRA_DEMOD_SCRAMBLE_CODE_CMD = 24,
  85 
  86         /* ---For host to know how many commands in total */
  87         MXL_HYDRA_LAST_HOST_CMD = 25,
  88 
  89         MXL_HYDRA_DEMOD_INTR_TYPE_CMD = 47,
  90         MXL_HYDRA_DEV_INTR_CLEAR_CMD = 48,
  91         MXL_HYDRA_TUNER_SPECTRUM_REQ_CMD = 53,
  92         MXL_HYDRA_TUNER_ACTIVATE_CMD = 55,
  93         MXL_HYDRA_DEV_CFG_POWER_MODE_CMD = 56,
  94         MXL_HYDRA_DEV_XTAL_CAP_CMD = 57,
  95         MXL_HYDRA_DEV_CFG_SKU_CMD = 58,
  96         MXL_HYDRA_TUNER_SPECTRUM_MIN_GAIN_CMD = 59,
  97         MXL_HYDRA_DISEQC_CONT_TONE_CFG = 60,
  98         MXL_HYDRA_DEV_RF_WAKE_UP_CMD = 61,
  99         MXL_HYDRA_DEMOD_CFG_EQ_CTRL_PARAM_CMD = 62,
 100         MXL_HYDRA_DEMOD_FREQ_OFFSET_SEARCH_RANGE_CMD = 63,
 101         MXL_HYDRA_DEV_REQ_PWR_FROM_ADCRSSI_CMD = 64,
 102 
 103         MXL_XCPU_PID_FLT_CFG_CMD = 65,
 104         MXL_XCPU_SHMEM_TEST_CMD = 66,
 105         MXL_XCPU_ABORT_TUNE_CMD = 67,
 106         MXL_XCPU_CHAN_TUNE_CMD = 68,
 107         MXL_XCPU_FLT_BOND_HDRS_CMD = 69,
 108 
 109         MXL_HYDRA_DEV_BROADCAST_WAKE_UP_CMD = 70,
 110         MXL_HYDRA_FSK_CFG_FSK_FREQ_CMD = 71,
 111         MXL_HYDRA_FSK_POWER_DOWN_CMD = 72,
 112         MXL_XCPU_CLEAR_CB_STATS_CMD = 73,
 113         MXL_XCPU_CHAN_BOND_RESTART_CMD = 74
 114 };
 115 
 116 #define MXL_ENABLE_BIG_ENDIAN        (0)
 117 
 118 #define MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH   248
 119 
 120 #define MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN        (248)
 121 
 122 #define MXL_HYDRA_CAP_MIN     10
 123 #define MXL_HYDRA_CAP_MAX     33
 124 
 125 #define MXL_HYDRA_PLID_REG_READ       0xFB   /* Read register PLID */
 126 #define MXL_HYDRA_PLID_REG_WRITE      0xFC   /* Write register PLID */
 127 
 128 #define MXL_HYDRA_PLID_CMD_READ       0xFD   /* Command Read PLID */
 129 #define MXL_HYDRA_PLID_CMD_WRITE      0xFE   /* Command Write PLID */
 130 
 131 #define MXL_HYDRA_REG_SIZE_IN_BYTES   4      /* Hydra register size in bytes */
 132 #define MXL_HYDRA_I2C_HDR_SIZE        (2 * sizeof(u8)) /* PLID + LEN(0xFF) */
 133 #define MXL_HYDRA_CMD_HEADER_SIZE     (MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE)
 134 
 135 #define MXL_HYDRA_SKU_ID_581 0
 136 #define MXL_HYDRA_SKU_ID_584 1
 137 #define MXL_HYDRA_SKU_ID_585 2
 138 #define MXL_HYDRA_SKU_ID_544 3
 139 #define MXL_HYDRA_SKU_ID_561 4
 140 #define MXL_HYDRA_SKU_ID_582 5
 141 #define MXL_HYDRA_SKU_ID_568 6
 142 
 143 /* macro for register write data buffer size
 144  * (PLID + LEN (0xFF) + RegAddr + RegData)
 145  */
 146 #define MXL_HYDRA_REG_WRITE_LEN       (MXL_HYDRA_I2C_HDR_SIZE + (2 * MXL_HYDRA_REG_SIZE_IN_BYTES))
 147 
 148 /* macro to extract a single byte from 4-byte(32-bit) data */
 149 #define GET_BYTE(x, n)  (((x) >> (8*(n))) & 0xFF)
 150 
 151 #define MAX_CMD_DATA 512
 152 
 153 #define MXL_GET_REG_MASK_32(lsb_loc, num_of_bits) ((0xFFFFFFFF >> (32 - (num_of_bits))) << (lsb_loc))
 154 
 155 #define FW_DL_SIGN (0xDEADBEEF)
 156 
 157 #define MBIN_FORMAT_VERSION               '1'
 158 #define MBIN_FILE_HEADER_ID               'M'
 159 #define MBIN_SEGMENT_HEADER_ID            'S'
 160 #define MBIN_MAX_FILE_LENGTH              (1<<23)
 161 
 162 struct MBIN_FILE_HEADER_T {
 163         u8 id;
 164         u8 fmt_version;
 165         u8 header_len;
 166         u8 num_segments;
 167         u8 entry_address[4];
 168         u8 image_size24[3];
 169         u8 image_checksum;
 170         u8 reserved[4];
 171 };
 172 
 173 struct MBIN_FILE_T {
 174         struct MBIN_FILE_HEADER_T header;
 175         u8 data[1];
 176 };
 177 
 178 struct MBIN_SEGMENT_HEADER_T {
 179         u8 id;
 180         u8 len24[3];
 181         u8 address[4];
 182 };
 183 
 184 struct MBIN_SEGMENT_T {
 185         struct MBIN_SEGMENT_HEADER_T header;
 186         u8 data[1];
 187 };
 188 
 189 enum MXL_CMD_TYPE_E { MXL_CMD_WRITE = 0, MXL_CMD_READ };
 190 
 191 #define BUILD_HYDRA_CMD(cmd_id, req_type, size, data_ptr, cmd_buff)             \
 192         do {                                                            \
 193                 cmd_buff[0] = ((req_type == MXL_CMD_WRITE) ? MXL_HYDRA_PLID_CMD_WRITE : MXL_HYDRA_PLID_CMD_READ); \
 194                 cmd_buff[1] = (size > 251) ? 0xff : (u8) (size + 4);    \
 195                 cmd_buff[2] = size;                                     \
 196                 cmd_buff[3] = cmd_id;                                   \
 197                 cmd_buff[4] = 0x00;                                     \
 198                 cmd_buff[5] = 0x00;                                     \
 199                 convert_endian(MXL_ENABLE_BIG_ENDIAN, size, (u8 *)data_ptr); \
 200                 memcpy((void *)&cmd_buff[6], data_ptr, size);           \
 201         } while (0)
 202 
 203 struct MXL_REG_FIELD_T {
 204         u32 reg_addr;
 205         u8 lsb_pos;
 206         u8 num_of_bits;
 207 };
 208 
 209 struct MXL_DEV_CMD_DATA_T {
 210         u32 data_size;
 211         u8 data[MAX_CMD_DATA];
 212 };
 213 
 214 enum MXL_HYDRA_SKU_TYPE_E {
 215         MXL_HYDRA_SKU_TYPE_MIN = 0x00,
 216         MXL_HYDRA_SKU_TYPE_581 = 0x00,
 217         MXL_HYDRA_SKU_TYPE_584 = 0x01,
 218         MXL_HYDRA_SKU_TYPE_585 = 0x02,
 219         MXL_HYDRA_SKU_TYPE_544 = 0x03,
 220         MXL_HYDRA_SKU_TYPE_561 = 0x04,
 221         MXL_HYDRA_SKU_TYPE_5XX = 0x05,
 222         MXL_HYDRA_SKU_TYPE_5YY = 0x06,
 223         MXL_HYDRA_SKU_TYPE_511 = 0x07,
 224         MXL_HYDRA_SKU_TYPE_561_DE = 0x08,
 225         MXL_HYDRA_SKU_TYPE_582 = 0x09,
 226         MXL_HYDRA_SKU_TYPE_541 = 0x0A,
 227         MXL_HYDRA_SKU_TYPE_568 = 0x0B,
 228         MXL_HYDRA_SKU_TYPE_542 = 0x0C,
 229         MXL_HYDRA_SKU_TYPE_MAX = 0x0D,
 230 };
 231 
 232 struct MXL_HYDRA_SKU_COMMAND_T {
 233         enum MXL_HYDRA_SKU_TYPE_E sku_type;
 234 };
 235 
 236 enum MXL_HYDRA_DEMOD_ID_E {
 237         MXL_HYDRA_DEMOD_ID_0 = 0,
 238         MXL_HYDRA_DEMOD_ID_1,
 239         MXL_HYDRA_DEMOD_ID_2,
 240         MXL_HYDRA_DEMOD_ID_3,
 241         MXL_HYDRA_DEMOD_ID_4,
 242         MXL_HYDRA_DEMOD_ID_5,
 243         MXL_HYDRA_DEMOD_ID_6,
 244         MXL_HYDRA_DEMOD_ID_7,
 245         MXL_HYDRA_DEMOD_MAX
 246 };
 247 
 248 #define MXL_DEMOD_SCRAMBLE_SEQ_LEN  12
 249 
 250 #define MAX_STEP_SIZE_24_XTAL_102_05_KHZ  195
 251 #define MAX_STEP_SIZE_24_XTAL_204_10_KHZ  215
 252 #define MAX_STEP_SIZE_24_XTAL_306_15_KHZ  203
 253 #define MAX_STEP_SIZE_24_XTAL_408_20_KHZ  177
 254 
 255 #define MAX_STEP_SIZE_27_XTAL_102_05_KHZ  195
 256 #define MAX_STEP_SIZE_27_XTAL_204_10_KHZ  215
 257 #define MAX_STEP_SIZE_27_XTAL_306_15_KHZ  203
 258 #define MAX_STEP_SIZE_27_XTAL_408_20_KHZ  177
 259 
 260 #define MXL_HYDRA_SPECTRUM_MIN_FREQ_KHZ  300000
 261 #define MXL_HYDRA_SPECTRUM_MAX_FREQ_KHZ 2350000
 262 
 263 enum MXL_DEMOD_CHAN_PARAMS_OFFSET_E {
 264         DMD_STANDARD_ADDR = 0,
 265         DMD_SPECTRUM_INVERSION_ADDR,
 266         DMD_SPECTRUM_ROLL_OFF_ADDR,
 267         DMD_SYMBOL_RATE_ADDR,
 268         DMD_MODULATION_SCHEME_ADDR,
 269         DMD_FEC_CODE_RATE_ADDR,
 270         DMD_SNR_ADDR,
 271         DMD_FREQ_OFFSET_ADDR,
 272         DMD_CTL_FREQ_OFFSET_ADDR,
 273         DMD_STR_FREQ_OFFSET_ADDR,
 274         DMD_FTL_FREQ_OFFSET_ADDR,
 275         DMD_STR_NBC_SYNC_LOCK_ADDR,
 276         DMD_CYCLE_SLIP_COUNT_ADDR,
 277         DMD_DISPLAY_IQ_ADDR,
 278         DMD_DVBS2_CRC_ERRORS_ADDR,
 279         DMD_DVBS2_PER_COUNT_ADDR,
 280         DMD_DVBS2_PER_WINDOW_ADDR,
 281         DMD_DVBS_CORR_RS_ERRORS_ADDR,
 282         DMD_DVBS_UNCORR_RS_ERRORS_ADDR,
 283         DMD_DVBS_BER_COUNT_ADDR,
 284         DMD_DVBS_BER_WINDOW_ADDR,
 285         DMD_TUNER_ID_ADDR,
 286         DMD_DVBS2_PILOT_ON_OFF_ADDR,
 287         DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR,
 288 
 289         MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE,
 290 };
 291 
 292 enum MXL_HYDRA_TUNER_ID_E {
 293         MXL_HYDRA_TUNER_ID_0 = 0,
 294         MXL_HYDRA_TUNER_ID_1,
 295         MXL_HYDRA_TUNER_ID_2,
 296         MXL_HYDRA_TUNER_ID_3,
 297         MXL_HYDRA_TUNER_MAX
 298 };
 299 
 300 enum MXL_HYDRA_BCAST_STD_E {
 301         MXL_HYDRA_DSS = 0,
 302         MXL_HYDRA_DVBS,
 303         MXL_HYDRA_DVBS2,
 304 };
 305 
 306 enum MXL_HYDRA_FEC_E {
 307         MXL_HYDRA_FEC_AUTO = 0,
 308         MXL_HYDRA_FEC_1_2,
 309         MXL_HYDRA_FEC_3_5,
 310         MXL_HYDRA_FEC_2_3,
 311         MXL_HYDRA_FEC_3_4,
 312         MXL_HYDRA_FEC_4_5,
 313         MXL_HYDRA_FEC_5_6,
 314         MXL_HYDRA_FEC_6_7,
 315         MXL_HYDRA_FEC_7_8,
 316         MXL_HYDRA_FEC_8_9,
 317         MXL_HYDRA_FEC_9_10,
 318 };
 319 
 320 enum MXL_HYDRA_MODULATION_E {
 321         MXL_HYDRA_MOD_AUTO = 0,
 322         MXL_HYDRA_MOD_QPSK,
 323         MXL_HYDRA_MOD_8PSK
 324 };
 325 
 326 enum MXL_HYDRA_SPECTRUM_E {
 327         MXL_HYDRA_SPECTRUM_AUTO = 0,
 328         MXL_HYDRA_SPECTRUM_INVERTED,
 329         MXL_HYDRA_SPECTRUM_NON_INVERTED,
 330 };
 331 
 332 enum MXL_HYDRA_ROLLOFF_E {
 333         MXL_HYDRA_ROLLOFF_AUTO  = 0,
 334         MXL_HYDRA_ROLLOFF_0_20,
 335         MXL_HYDRA_ROLLOFF_0_25,
 336         MXL_HYDRA_ROLLOFF_0_35
 337 };
 338 
 339 enum MXL_HYDRA_PILOTS_E {
 340         MXL_HYDRA_PILOTS_OFF  = 0,
 341         MXL_HYDRA_PILOTS_ON,
 342         MXL_HYDRA_PILOTS_AUTO
 343 };
 344 
 345 enum MXL_HYDRA_CONSTELLATION_SRC_E {
 346         MXL_HYDRA_FORMATTER = 0,
 347         MXL_HYDRA_LEGACY_FEC,
 348         MXL_HYDRA_FREQ_RECOVERY,
 349         MXL_HYDRA_NBC,
 350         MXL_HYDRA_CTL,
 351         MXL_HYDRA_EQ,
 352 };
 353 
 354 struct MXL_HYDRA_DEMOD_LOCK_T {
 355         int agc_lock; /* AGC lock info */
 356         int fec_lock; /* Demod FEC block lock info */
 357 };
 358 
 359 struct MXL_HYDRA_DEMOD_STATUS_DVBS_T {
 360         u32 rs_errors;        /* RS decoder err counter */
 361         u32 ber_window;       /* Ber Windows */
 362         u32 ber_count;        /* BER count */
 363         u32 ber_window_iter1; /* Ber Windows - post viterbi */
 364         u32 ber_count_iter1;  /* BER count - post viterbi */
 365 };
 366 
 367 struct MXL_HYDRA_DEMOD_STATUS_DSS_T {
 368         u32 rs_errors;  /* RS decoder err counter */
 369         u32 ber_window; /* Ber Windows */
 370         u32 ber_count;  /* BER count */
 371 };
 372 
 373 struct MXL_HYDRA_DEMOD_STATUS_DVBS2_T {
 374         u32 crc_errors;        /* CRC error counter */
 375         u32 packet_error_count; /* Number of packet errors */
 376         u32 total_packets;     /* Total packets */
 377 };
 378 
 379 struct MXL_HYDRA_DEMOD_STATUS_T {
 380         enum MXL_HYDRA_BCAST_STD_E standard_mask; /* Standard DVB-S, DVB-S2 or DSS */
 381 
 382         union {
 383                 struct MXL_HYDRA_DEMOD_STATUS_DVBS_T demod_status_dvbs;   /* DVB-S demod status */
 384                 struct MXL_HYDRA_DEMOD_STATUS_DVBS2_T demod_status_dvbs2; /* DVB-S2 demod status */
 385                 struct MXL_HYDRA_DEMOD_STATUS_DSS_T demod_status_dss;     /* DSS demod status */
 386         } u;
 387 };
 388 
 389 struct MXL_HYDRA_DEMOD_SIG_OFFSET_INFO_T {
 390         s32 carrier_offset_in_hz; /* CRL offset info */
 391         s32 symbol_offset_in_symbol; /* SRL offset info */
 392 };
 393 
 394 struct MXL_HYDRA_DEMOD_SCRAMBLE_INFO_T {
 395         u8 scramble_sequence[MXL_DEMOD_SCRAMBLE_SEQ_LEN]; /* scramble sequence */
 396         u32 scramble_code; /* scramble gold code */
 397 };
 398 
 399 enum MXL_HYDRA_SPECTRUM_STEP_SIZE_E {
 400         MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
 401         MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
 402         MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
 403         MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
 404 
 405         MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
 406         MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
 407         MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
 408         MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
 409 };
 410 
 411 enum MXL_HYDRA_SPECTRUM_RESOLUTION_E {
 412         MXL_HYDRA_SPECTRUM_RESOLUTION_00_1_DB, /* 0.1 dB */
 413         MXL_HYDRA_SPECTRUM_RESOLUTION_01_0_DB, /* 1.0 dB */
 414         MXL_HYDRA_SPECTRUM_RESOLUTION_05_0_DB, /* 5.0 dB */
 415         MXL_HYDRA_SPECTRUM_RESOLUTION_10_0_DB, /* 10 dB */
 416 };
 417 
 418 enum MXL_HYDRA_SPECTRUM_ERROR_CODE_E {
 419         MXL_SPECTRUM_NO_ERROR,
 420         MXL_SPECTRUM_INVALID_PARAMETER,
 421         MXL_SPECTRUM_INVALID_STEP_SIZE,
 422         MXL_SPECTRUM_BW_CANNOT_BE_COVERED,
 423         MXL_SPECTRUM_DEMOD_BUSY,
 424         MXL_SPECTRUM_TUNER_NOT_ENABLED,
 425 };
 426 
 427 struct MXL_HYDRA_SPECTRUM_REQ_T {
 428         u32 tuner_index; /* TUNER Ctrl: one of MXL58x_TUNER_ID_E */
 429         u32 demod_index; /* DEMOD Ctrl: one of MXL58x_DEMOD_ID_E */
 430         enum MXL_HYDRA_SPECTRUM_STEP_SIZE_E step_size_in_khz;
 431         u32 starting_freq_ink_hz;
 432         u32 total_steps;
 433         enum MXL_HYDRA_SPECTRUM_RESOLUTION_E spectrum_division;
 434 };
 435 
 436 enum MXL_HYDRA_SEARCH_FREQ_OFFSET_TYPE_E {
 437         MXL_HYDRA_SEARCH_MAX_OFFSET = 0, /* DMD searches for max freq offset (i.e. 5MHz) */
 438         MXL_HYDRA_SEARCH_BW_PLUS_ROLLOFF, /* DMD searches for BW + ROLLOFF/2 */
 439 };
 440 
 441 struct MXL58X_CFG_FREQ_OFF_SEARCH_RANGE_T {
 442         u32 demod_index;
 443         enum MXL_HYDRA_SEARCH_FREQ_OFFSET_TYPE_E search_type;
 444 };
 445 
 446 /* there are two slices
 447  * slice0 - TS0, TS1, TS2 & TS3
 448  * slice1 - TS4, TS5, TS6 & TS7
 449  */
 450 #define MXL_HYDRA_TS_SLICE_MAX  2
 451 
 452 #define MAX_FIXED_PID_NUM   32
 453 
 454 #define MXL_HYDRA_NCO_CLK   418 /* 418 MHz */
 455 
 456 #define MXL_HYDRA_MAX_TS_CLOCK  139 /* 139 MHz */
 457 
 458 #define MXL_HYDRA_TS_FIXED_PID_FILT_SIZE          32
 459 
 460 #define MXL_HYDRA_SHARED_PID_FILT_SIZE_DEFAULT    33   /* Shared PID filter size in 1-1 mux mode */
 461 #define MXL_HYDRA_SHARED_PID_FILT_SIZE_2_TO_1     66   /* Shared PID filter size in 2-1 mux mode */
 462 #define MXL_HYDRA_SHARED_PID_FILT_SIZE_4_TO_1     132  /* Shared PID filter size in 4-1 mux mode */
 463 
 464 enum MXL_HYDRA_PID_BANK_TYPE_E {
 465         MXL_HYDRA_SOFTWARE_PID_BANK = 0,
 466         MXL_HYDRA_HARDWARE_PID_BANK,
 467 };
 468 
 469 enum MXL_HYDRA_TS_MUX_MODE_E {
 470         MXL_HYDRA_TS_MUX_PID_REMAP = 0,
 471         MXL_HYDRA_TS_MUX_PREFIX_EXTRA_HEADER = 1,
 472 };
 473 
 474 enum MXL_HYDRA_TS_MUX_TYPE_E {
 475         MXL_HYDRA_TS_MUX_DISABLE = 0, /* No Mux ( 1 TSIF to 1 TSIF) */
 476         MXL_HYDRA_TS_MUX_2_TO_1, /* Mux 2 TSIF to 1 TSIF */
 477         MXL_HYDRA_TS_MUX_4_TO_1, /* Mux 4 TSIF to 1 TSIF */
 478 };
 479 
 480 enum MXL_HYDRA_TS_GROUP_E {
 481         MXL_HYDRA_TS_GROUP_0_3 = 0, /* TS group 0 to 3 (TS0, TS1, TS2 & TS3) */
 482         MXL_HYDRA_TS_GROUP_4_7,     /* TS group 0 to 3 (TS4, TS5, TS6 & TS7) */
 483 };
 484 
 485 enum MXL_HYDRA_TS_PID_FLT_CTRL_E {
 486         MXL_HYDRA_TS_PIDS_ALLOW_ALL = 0, /* Allow all pids */
 487         MXL_HYDRA_TS_PIDS_DROP_ALL,      /* Drop all pids */
 488         MXL_HYDRA_TS_INVALIDATE_PID_FILTER, /* Delete current PD filter in the device */
 489 };
 490 
 491 enum MXL_HYDRA_TS_PID_TYPE_E {
 492         MXL_HYDRA_TS_PID_FIXED = 0,
 493         MXL_HYDRA_TS_PID_REGULAR,
 494 };
 495 
 496 struct MXL_HYDRA_TS_PID_T {
 497         u16 original_pid;           /* pid from TS */
 498         u16 remapped_pid;           /* remapped pid */
 499         enum MXL_BOOL_E enable;         /* enable or disable pid */
 500         enum MXL_BOOL_E allow_or_drop;    /* allow or drop pid */
 501         enum MXL_BOOL_E enable_pid_remap; /* enable or disable pid remap */
 502         u8 bond_id;                 /* Bond ID in A0 always 0 - Only for 568 Sku */
 503         u8 dest_id;                 /* Output port ID for the PID - Only for 568 Sku */
 504 };
 505 
 506 struct MXL_HYDRA_TS_MUX_PREFIX_HEADER_T {
 507         enum MXL_BOOL_E enable;
 508         u8 num_byte;
 509         u8 header[12];
 510 };
 511 
 512 enum MXL_HYDRA_PID_FILTER_BANK_E {
 513         MXL_HYDRA_PID_BANK_A = 0,
 514         MXL_HYDRA_PID_BANK_B,
 515 };
 516 
 517 enum MXL_HYDRA_MPEG_DATA_FMT_E {
 518         MXL_HYDRA_MPEG_SERIAL_MSB_1ST = 0,
 519         MXL_HYDRA_MPEG_SERIAL_LSB_1ST,
 520 
 521         MXL_HYDRA_MPEG_SYNC_WIDTH_BIT = 0,
 522         MXL_HYDRA_MPEG_SYNC_WIDTH_BYTE
 523 };
 524 
 525 enum MXL_HYDRA_MPEG_MODE_E {
 526         MXL_HYDRA_MPEG_MODE_SERIAL_4_WIRE = 0, /* MPEG 4 Wire serial mode */
 527         MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE,     /* MPEG 3 Wire serial mode */
 528         MXL_HYDRA_MPEG_MODE_SERIAL_2_WIRE,     /* MPEG 2 Wire serial mode */
 529         MXL_HYDRA_MPEG_MODE_PARALLEL           /* MPEG parallel mode - valid only for MxL581 */
 530 };
 531 
 532 enum MXL_HYDRA_MPEG_CLK_TYPE_E {
 533         MXL_HYDRA_MPEG_CLK_CONTINUOUS = 0, /* Continuous MPEG clock */
 534         MXL_HYDRA_MPEG_CLK_GAPPED,         /* Gapped (gated) MPEG clock */
 535 };
 536 
 537 enum MXL_HYDRA_MPEG_CLK_FMT_E {
 538         MXL_HYDRA_MPEG_ACTIVE_LOW = 0,
 539         MXL_HYDRA_MPEG_ACTIVE_HIGH,
 540 
 541         MXL_HYDRA_MPEG_CLK_NEGATIVE = 0,
 542         MXL_HYDRA_MPEG_CLK_POSITIVE,
 543 
 544         MXL_HYDRA_MPEG_CLK_IN_PHASE = 0,
 545         MXL_HYDRA_MPEG_CLK_INVERTED,
 546 };
 547 
 548 enum MXL_HYDRA_MPEG_CLK_PHASE_E {
 549         MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG = 0,
 550         MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_90_DEG,
 551         MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_180_DEG,
 552         MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_270_DEG
 553 };
 554 
 555 enum MXL_HYDRA_MPEG_ERR_INDICATION_E {
 556         MXL_HYDRA_MPEG_ERR_REPLACE_SYNC = 0,
 557         MXL_HYDRA_MPEG_ERR_REPLACE_VALID,
 558         MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED
 559 };
 560 
 561 struct MXL_HYDRA_MPEGOUT_PARAM_T {
 562         int                                  enable;               /* Enable or Disable MPEG OUT */
 563         enum MXL_HYDRA_MPEG_CLK_TYPE_E       mpeg_clk_type;          /* Continuous or gapped */
 564         enum MXL_HYDRA_MPEG_CLK_FMT_E        mpeg_clk_pol;           /* MPEG Clk polarity */
 565         u8                                   max_mpeg_clk_rate;       /* Max MPEG Clk rate (0 - 104 MHz, 139 MHz) */
 566         enum MXL_HYDRA_MPEG_CLK_PHASE_E      mpeg_clk_phase;         /* MPEG Clk phase */
 567         enum MXL_HYDRA_MPEG_DATA_FMT_E       lsb_or_msb_first;        /* LSB first or MSB first in TS transmission */
 568         enum MXL_HYDRA_MPEG_DATA_FMT_E       mpeg_sync_pulse_width;   /* MPEG SYNC pulse width (1-bit or 1-byte) */
 569         enum MXL_HYDRA_MPEG_CLK_FMT_E        mpeg_valid_pol;         /* MPEG VALID polarity */
 570         enum MXL_HYDRA_MPEG_CLK_FMT_E        mpeg_sync_pol;          /* MPEG SYNC polarity */
 571         enum MXL_HYDRA_MPEG_MODE_E           mpeg_mode;             /* config 4/3/2-wire serial or parallel TS out */
 572         enum MXL_HYDRA_MPEG_ERR_INDICATION_E mpeg_error_indication;  /* Enable or Disable MPEG error indication */
 573 };
 574 
 575 enum MXL_HYDRA_EXT_TS_IN_ID_E {
 576         MXL_HYDRA_EXT_TS_IN_0 = 0,
 577         MXL_HYDRA_EXT_TS_IN_1,
 578         MXL_HYDRA_EXT_TS_IN_2,
 579         MXL_HYDRA_EXT_TS_IN_3,
 580         MXL_HYDRA_EXT_TS_IN_MAX
 581 };
 582 
 583 enum MXL_HYDRA_TS_OUT_ID_E {
 584         MXL_HYDRA_TS_OUT_0 = 0,
 585         MXL_HYDRA_TS_OUT_1,
 586         MXL_HYDRA_TS_OUT_2,
 587         MXL_HYDRA_TS_OUT_3,
 588         MXL_HYDRA_TS_OUT_4,
 589         MXL_HYDRA_TS_OUT_5,
 590         MXL_HYDRA_TS_OUT_6,
 591         MXL_HYDRA_TS_OUT_7,
 592         MXL_HYDRA_TS_OUT_MAX
 593 };
 594 
 595 enum MXL_HYDRA_TS_DRIVE_STRENGTH_E {
 596         MXL_HYDRA_TS_DRIVE_STRENGTH_1X = 0,
 597         MXL_HYDRA_TS_DRIVE_STRENGTH_2X,
 598         MXL_HYDRA_TS_DRIVE_STRENGTH_3X,
 599         MXL_HYDRA_TS_DRIVE_STRENGTH_4X,
 600         MXL_HYDRA_TS_DRIVE_STRENGTH_5X,
 601         MXL_HYDRA_TS_DRIVE_STRENGTH_6X,
 602         MXL_HYDRA_TS_DRIVE_STRENGTH_7X,
 603         MXL_HYDRA_TS_DRIVE_STRENGTH_8X
 604 };
 605 
 606 enum MXL_HYDRA_DEVICE_E {
 607         MXL_HYDRA_DEVICE_581 = 0,
 608         MXL_HYDRA_DEVICE_584,
 609         MXL_HYDRA_DEVICE_585,
 610         MXL_HYDRA_DEVICE_544,
 611         MXL_HYDRA_DEVICE_561,
 612         MXL_HYDRA_DEVICE_TEST,
 613         MXL_HYDRA_DEVICE_582,
 614         MXL_HYDRA_DEVICE_541,
 615         MXL_HYDRA_DEVICE_568,
 616         MXL_HYDRA_DEVICE_542,
 617         MXL_HYDRA_DEVICE_541S,
 618         MXL_HYDRA_DEVICE_561S,
 619         MXL_HYDRA_DEVICE_581S,
 620         MXL_HYDRA_DEVICE_MAX
 621 };
 622 
 623 /* Demod IQ data */
 624 struct MXL_HYDRA_DEMOD_IQ_SRC_T {
 625         u32 demod_id;
 626         u32 source_of_iq; /* == 0, it means I/Q comes from Formatter
 627                          * == 1, Legacy FEC
 628                          * == 2, Frequency Recovery
 629                          * == 3, NBC
 630                          * == 4, CTL
 631                          * == 5, EQ
 632                          * == 6, FPGA
 633                          */
 634 };
 635 
 636 struct MXL_HYDRA_DEMOD_ABORT_TUNE_T {
 637         u32 demod_id;
 638 };
 639 
 640 struct MXL_HYDRA_TUNER_CMD {
 641         u8 tuner_id;
 642         u8 enable;
 643 };
 644 
 645 /* Demod Para for Channel Tune */
 646 struct MXL_HYDRA_DEMOD_PARAM_T {
 647         u32 tuner_index;
 648         u32 demod_index;
 649         u32 frequency_in_hz;     /* Frequency */
 650         u32 standard;          /* one of MXL_HYDRA_BCAST_STD_E */
 651         u32 spectrum_inversion; /* Input : Spectrum inversion. */
 652         u32 roll_off;           /* rollOff (alpha) factor */
 653         u32 symbol_rate_in_hz;    /* Symbol rate */
 654         u32 pilots;            /* TRUE = pilots enabled */
 655         u32 modulation_scheme;  /* Input : Modulation Scheme is one of MXL_HYDRA_MODULATION_E */
 656         u32 fec_code_rate;       /* Input : Forward error correction rate. Is one of MXL_HYDRA_FEC_E */
 657         u32 max_carrier_offset_in_mhz; /* Maximum carrier freq offset in MHz. Same as freqSearchRangeKHz, but in unit of MHz. */
 658 };
 659 
 660 struct MXL_HYDRA_DEMOD_SCRAMBLE_CODE_T {
 661         u32 demod_index;
 662         u8 scramble_sequence[12]; /* scramble sequence */
 663         u32 scramble_code; /* scramble gold code */
 664 };
 665 
 666 struct MXL_INTR_CFG_T {
 667         u32 intr_type;
 668         u32 intr_duration_in_nano_secs;
 669         u32 intr_mask;
 670 };
 671 
 672 struct MXL_HYDRA_POWER_MODE_CMD {
 673         u8 power_mode; /* enumeration values are defined in MXL_HYDRA_PWR_MODE_E (device API.h) */
 674 };
 675 
 676 struct MXL_HYDRA_RF_WAKEUP_PARAM_T {
 677         u32 time_interval_in_seconds; /* in seconds */
 678         u32 tuner_index;
 679         s32 rssi_threshold;
 680 };
 681 
 682 struct MXL_HYDRA_RF_WAKEUP_CFG_T {
 683         u32 tuner_count;
 684         struct MXL_HYDRA_RF_WAKEUP_PARAM_T params;
 685 };
 686 
 687 enum MXL_HYDRA_AUX_CTRL_MODE_E {
 688         MXL_HYDRA_AUX_CTRL_MODE_FSK = 0, /* Select FSK controller */
 689         MXL_HYDRA_AUX_CTRL_MODE_DISEQC,  /* Select DiSEqC controller */
 690 };
 691 
 692 enum MXL_HYDRA_DISEQC_OPMODE_E {
 693         MXL_HYDRA_DISEQC_ENVELOPE_MODE = 0,
 694         MXL_HYDRA_DISEQC_TONE_MODE,
 695 };
 696 
 697 enum MXL_HYDRA_DISEQC_VER_E {
 698         MXL_HYDRA_DISEQC_1_X = 0, /* Config DiSEqC 1.x mode */
 699         MXL_HYDRA_DISEQC_2_X, /* Config DiSEqC 2.x mode */
 700         MXL_HYDRA_DISEQC_DISABLE /* Disable DiSEqC */
 701 };
 702 
 703 enum MXL_HYDRA_DISEQC_CARRIER_FREQ_E {
 704         MXL_HYDRA_DISEQC_CARRIER_FREQ_22KHZ = 0, /* DiSEqC signal frequency of 22 KHz */
 705         MXL_HYDRA_DISEQC_CARRIER_FREQ_33KHZ,     /* DiSEqC signal frequency of 33 KHz */
 706         MXL_HYDRA_DISEQC_CARRIER_FREQ_44KHZ      /* DiSEqC signal frequency of 44 KHz */
 707 };
 708 
 709 enum MXL_HYDRA_DISEQC_ID_E {
 710         MXL_HYDRA_DISEQC_ID_0 = 0,
 711         MXL_HYDRA_DISEQC_ID_1,
 712         MXL_HYDRA_DISEQC_ID_2,
 713         MXL_HYDRA_DISEQC_ID_3
 714 };
 715 
 716 enum MXL_HYDRA_FSK_OP_MODE_E {
 717         MXL_HYDRA_FSK_CFG_TYPE_39KPBS = 0, /* 39.0kbps */
 718         MXL_HYDRA_FSK_CFG_TYPE_39_017KPBS, /* 39.017kbps */
 719         MXL_HYDRA_FSK_CFG_TYPE_115_2KPBS   /* 115.2kbps */
 720 };
 721 
 722 struct MXL58X_DSQ_OP_MODE_T {
 723         u32 diseqc_id; /* DSQ 0, 1, 2 or 3 */
 724         u32 op_mode; /* Envelope mode (0) or internal tone mode (1) */
 725         u32 version; /* 0: 1.0, 1: 1.1, 2: Disable */
 726         u32 center_freq; /* 0: 22KHz, 1: 33KHz and 2: 44 KHz */
 727 };
 728 
 729 struct MXL_HYDRA_DISEQC_CFG_CONT_TONE_T {
 730         u32 diseqc_id;
 731         u32 cont_tone_flag; /* 1: Enable , 0: Disable */
 732 };