1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III
3 * register descriptions
4 * see flexcop.c for copyright information
5 */
6 /* This file is automatically generated, do not edit things here. */
7 #ifndef __FLEXCOP_IBI_VALUE_INCLUDED__
8 #define __FLEXCOP_IBI_VALUE_INCLUDED__
9
10 typedef union {
11 u32 raw;
12
13 struct {
14 u32 dma_address0 :30;
15 u32 dma_0No_update : 1;
16 u32 dma_0start : 1;
17 } dma_0x0;
18
19 struct {
20 u32 dma_addr_size :24;
21 u32 DMA_maxpackets : 8;
22 } dma_0x4_remap;
23
24 struct {
25 u32 dma_addr_size :24;
26 u32 unused : 1;
27 u32 dma1timer : 7;
28 } dma_0x4_read;
29
30 struct {
31 u32 dma_addr_size :24;
32 u32 dmatimer : 7;
33 u32 unused : 1;
34 } dma_0x4_write;
35
36 struct {
37 u32 dma_cur_addr :30;
38 u32 unused : 2;
39 } dma_0x8;
40
41 struct {
42 u32 dma_address1 :30;
43 u32 remap_enable : 1;
44 u32 dma_1start : 1;
45 } dma_0xc;
46
47 struct {
48 u32 st_done : 1;
49 u32 no_base_addr_ack_error : 1;
50 u32 twoWS_port_reg : 2;
51 u32 total_bytes : 2;
52 u32 twoWS_rw : 1;
53 u32 working_start : 1;
54 u32 data1_reg : 8;
55 u32 baseaddr : 8;
56 u32 reserved1 : 1;
57 u32 chipaddr : 7;
58 } tw_sm_c_100;
59
60 struct {
61 u32 unused : 6;
62 u32 force_stop : 1;
63 u32 exlicit_stops : 1;
64 u32 data4_reg : 8;
65 u32 data3_reg : 8;
66 u32 data2_reg : 8;
67 } tw_sm_c_104;
68
69 struct {
70 u32 reserved2 :19;
71 u32 tlo1 : 5;
72 u32 reserved1 : 2;
73 u32 thi1 : 6;
74 } tw_sm_c_108;
75
76 struct {
77 u32 reserved2 :19;
78 u32 tlo1 : 5;
79 u32 reserved1 : 2;
80 u32 thi1 : 6;
81 } tw_sm_c_10c;
82
83 struct {
84 u32 reserved2 :19;
85 u32 tlo1 : 5;
86 u32 reserved1 : 2;
87 u32 thi1 : 6;
88 } tw_sm_c_110;
89
90 struct {
91 u32 LNB_CTLPrescaler_sig : 2;
92 u32 LNB_CTLLowCount_sig :15;
93 u32 LNB_CTLHighCount_sig :15;
94 } lnb_switch_freq_200;
95
96 struct {
97 u32 Rev_N_sig_reserved2 : 1;
98 u32 Rev_N_sig_caps : 1;
99 u32 Rev_N_sig_reserved1 : 2;
100 u32 Rev_N_sig_revision_hi : 4;
101 u32 reserved :20;
102 u32 Per_reset_sig : 1;
103 u32 LNB_L_H_sig : 1;
104 u32 ACPI3_sig : 1;
105 u32 ACPI1_sig : 1;
106 } misc_204;
107
108 struct {
109 u32 unused : 9;
110 u32 Mailbox_from_V8_Enable_sig : 1;
111 u32 DMA2_Size_IRQ_Enable_sig : 1;
112 u32 DMA1_Size_IRQ_Enable_sig : 1;
113 u32 DMA2_Timer_Enable_sig : 1;
114 u32 DMA2_IRQ_Enable_sig : 1;
115 u32 DMA1_Timer_Enable_sig : 1;
116 u32 DMA1_IRQ_Enable_sig : 1;
117 u32 Rcv_Data_sig : 1;
118 u32 MAC_filter_Mode_sig : 1;
119 u32 Multi2_Enable_sig : 1;
120 u32 Per_CA_Enable_sig : 1;
121 u32 SMC_Enable_sig : 1;
122 u32 CA_Enable_sig : 1;
123 u32 WAN_CA_Enable_sig : 1;
124 u32 WAN_Enable_sig : 1;
125 u32 Mask_filter_sig : 1;
126 u32 Null_filter_sig : 1;
127 u32 ECM_filter_sig : 1;
128 u32 EMM_filter_sig : 1;
129 u32 PMT_filter_sig : 1;
130 u32 PCR_filter_sig : 1;
131 u32 Stream2_filter_sig : 1;
132 u32 Stream1_filter_sig : 1;
133 } ctrl_208;
134
135 struct {
136 u32 reserved :21;
137 u32 Transport_Error : 1;
138 u32 LLC_SNAP_FLAG_set : 1;
139 u32 Continuity_error_flag : 1;
140 u32 Data_receiver_error : 1;
141 u32 Mailbox_from_V8_Status_sig : 1;
142 u32 DMA2_Size_IRQ_Status : 1;
143 u32 DMA1_Size_IRQ_Status : 1;
144 u32 DMA2_Timer_Status : 1;
145 u32 DMA2_IRQ_Status : 1;
146 u32 DMA1_Timer_Status : 1;
147 u32 DMA1_IRQ_Status : 1;
148 } irq_20c;
149
150 struct {
151 u32 Special_controls :16;
152 u32 Block_reset_enable : 8;
153 u32 reset_block_700 : 1;
154 u32 reset_block_600 : 1;
155 u32 reset_block_500 : 1;
156 u32 reset_block_400 : 1;
157 u32 reset_block_300 : 1;
158 u32 reset_block_200 : 1;
159 u32 reset_block_100 : 1;
160 u32 reset_block_000 : 1;
161 } sw_reset_210;
162
163 struct {
164 u32 unused2 :20;
165 u32 polarity_PS_ERR_sig : 1;
166 u32 polarity_PS_SYNC_sig : 1;
167 u32 polarity_PS_VALID_sig : 1;
168 u32 polarity_PS_CLK_sig : 1;
169 u32 unused1 : 3;
170 u32 s2p_sel_sig : 1;
171 u32 section_pkg_enable_sig : 1;
172 u32 halt_V8_sig : 1;
173 u32 v2WS_oe_sig : 1;
174 u32 vuart_oe_sig : 1;
175 } misc_214;
176
177 struct {
178 u32 Mailbox_from_V8 :32;
179 } mbox_v8_to_host_218;
180
181 struct {
182 u32 sysramaccess_busmuster : 1;
183 u32 sysramaccess_write : 1;
184 u32 unused : 7;
185 u32 sysramaccess_addr :15;
186 u32 sysramaccess_data : 8;
187 } mbox_host_to_v8_21c;
188
189 struct {
190 u32 debug_fifo_problem : 1;
191 u32 debug_flag_write_status00 : 1;
192 u32 Stream2_trans : 1;
193 u32 Stream2_PID :13;
194 u32 debug_flag_pid_saved : 1;
195 u32 MAC_Multicast_filter : 1;
196 u32 Stream1_trans : 1;
197 u32 Stream1_PID :13;
198 } pid_filter_300;
199
200 struct {
201 u32 reserved : 2;
202 u32 PMT_trans : 1;
203 u32 PMT_PID :13;
204 u32 debug_overrun2 : 1;
205 u32 debug_overrun3 : 1;
206 u32 PCR_trans : 1;
207 u32 PCR_PID :13;
208 } pid_filter_304;
209
210 struct {
211 u32 reserved : 2;
212 u32 ECM_trans : 1;
213 u32 ECM_PID :13;
214 u32 EMM_filter_6 : 1;
215 u32 EMM_filter_4 : 1;
216 u32 EMM_trans : 1;
217 u32 EMM_PID :13;
218 } pid_filter_308;
219
220 struct {
221 u32 unused2 : 3;
222 u32 Group_mask :13;
223 u32 unused1 : 2;
224 u32 Group_trans : 1;
225 u32 Group_PID :13;
226 } pid_filter_30c_ext_ind_0_7;
227
228 struct {
229 u32 unused :15;
230 u32 net_master_read :17;
231 } pid_filter_30c_ext_ind_1;
232
233 struct {
234 u32 unused :15;
235 u32 net_master_write :17;
236 } pid_filter_30c_ext_ind_2;
237
238 struct {
239 u32 unused :15;
240 u32 next_net_master_write :17;
241 } pid_filter_30c_ext_ind_3;
242
243 struct {
244 u32 reserved2 : 5;
245 u32 stack_read :10;
246 u32 reserved1 : 6;
247 u32 state_write :10;
248 u32 unused1 : 1;
249 } pid_filter_30c_ext_ind_4;
250
251 struct {
252 u32 unused :22;
253 u32 stack_cnt :10;
254 } pid_filter_30c_ext_ind_5;
255
256 struct {
257 u32 unused : 4;
258 u32 data_size_reg :12;
259 u32 write_status4 : 2;
260 u32 write_status1 : 2;
261 u32 pid_fsm_save_reg300 : 2;
262 u32 pid_fsm_save_reg4 : 2;
263 u32 pid_fsm_save_reg3 : 2;
264 u32 pid_fsm_save_reg2 : 2;
265 u32 pid_fsm_save_reg1 : 2;
266 u32 pid_fsm_save_reg0 : 2;
267 } pid_filter_30c_ext_ind_6;
268
269 struct {
270 u32 unused :22;
271 u32 pass_alltables : 1;
272 u32 AB_select : 1;
273 u32 extra_index_reg : 3;
274 u32 index_reg : 5;
275 } index_reg_310;
276
277 struct {
278 u32 reserved :17;
279 u32 PID_enable_bit : 1;
280 u32 PID_trans : 1;
281 u32 PID :13;
282 } pid_n_reg_314;
283
284 struct {
285 u32 reserved : 6;
286 u32 HighAB_bit : 1;
287 u32 Enable_bit : 1;
288 u32 A6_byte : 8;
289 u32 A5_byte : 8;
290 u32 A4_byte : 8;
291 } mac_low_reg_318;
292
293 struct {
294 u32 reserved : 8;
295 u32 A3_byte : 8;
296 u32 A2_byte : 8;
297 u32 A1_byte : 8;
298 } mac_high_reg_31c;
299
300 struct {
301 u32 data_Tag_ID :16;
302 u32 reserved :16;
303 } data_tag_400;
304
305 struct {
306 u32 Card_IDbyte3 : 8;
307 u32 Card_IDbyte4 : 8;
308 u32 Card_IDbyte5 : 8;
309 u32 Card_IDbyte6 : 8;
310 } card_id_408;
311
312 struct {
313 u32 Card_IDbyte1 : 8;
314 u32 Card_IDbyte2 : 8;
315 } card_id_40c;
316
317 struct {
318 u32 MAC6 : 8;
319 u32 MAC3 : 8;
320 u32 MAC2 : 8;
321 u32 MAC1 : 8;
322 } mac_address_418;
323
324 struct {
325 u32 reserved :16;
326 u32 MAC8 : 8;
327 u32 MAC7 : 8;
328 } mac_address_41c;
329
330 struct {
331 u32 reserved :21;
332 u32 txbuffempty : 1;
333 u32 ReceiveByteFrameError : 1;
334 u32 ReceiveDataReady : 1;
335 u32 transmitter_data_byte : 8;
336 } ci_600;
337
338 struct {
339 u32 pi_component_reg : 3;
340 u32 pi_rw : 1;
341 u32 pi_ha :20;
342 u32 pi_d : 8;
343 } pi_604;
344
345 struct {
346 u32 pi_busy_n : 1;
347 u32 pi_wait_n : 1;
348 u32 pi_timeout_status : 1;
349 u32 pi_CiMax_IRQ_n : 1;
350 u32 config_cclk : 1;
351 u32 config_cs_n : 1;
352 u32 config_wr_n : 1;
353 u32 config_Prog_n : 1;
354 u32 config_Init_stat : 1;
355 u32 config_Done_stat : 1;
356 u32 pcmcia_b_mod_pwr_n : 1;
357 u32 pcmcia_a_mod_pwr_n : 1;
358 u32 reserved : 3;
359 u32 Timer_addr : 5;
360 u32 unused : 1;
361 u32 timer_data : 7;
362 u32 Timer_Load_req : 1;
363 u32 Timer_Read_req : 1;
364 u32 oncecycle_read : 1;
365 u32 serialReset : 1;
366 } pi_608;
367
368 struct {
369 u32 reserved : 6;
370 u32 rw_flag : 1;
371 u32 dvb_en : 1;
372 u32 key_array_row : 5;
373 u32 key_array_col : 3;
374 u32 key_code : 2;
375 u32 key_enable : 1;
376 u32 PID :13;
377 } dvb_reg_60c;
378
379 struct {
380 u32 start_sram_ibi : 1;
381 u32 reserved2 : 1;
382 u32 ce_pin_reg : 1;
383 u32 oe_pin_reg : 1;
384 u32 reserved1 : 3;
385 u32 sc_xfer_bit : 1;
386 u32 sram_data : 8;
387 u32 sram_rw : 1;
388 u32 sram_addr :15;
389 } sram_ctrl_reg_700;
390
391 struct {
392 u32 net_addr_write :16;
393 u32 net_addr_read :16;
394 } net_buf_reg_704;
395
396 struct {
397 u32 cai_cnt : 4;
398 u32 reserved2 : 6;
399 u32 cai_write :11;
400 u32 reserved1 : 5;
401 u32 cai_read :11;
402 } cai_buf_reg_708;
403
404 struct {
405 u32 cao_cnt : 4;
406 u32 reserved2 : 6;
407 u32 cap_write :11;
408 u32 reserved1 : 5;
409 u32 cao_read :11;
410 } cao_buf_reg_70c;
411
412 struct {
413 u32 media_cnt : 4;
414 u32 reserved2 : 6;
415 u32 media_write :11;
416 u32 reserved1 : 5;
417 u32 media_read :11;
418 } media_buf_reg_710;
419
420 struct {
421 u32 reserved :17;
422 u32 ctrl_maximumfill : 1;
423 u32 ctrl_sramdma : 1;
424 u32 ctrl_usb_wan : 1;
425 u32 cao_ovflow_error : 1;
426 u32 cai_ovflow_error : 1;
427 u32 media_ovflow_error : 1;
428 u32 net_ovflow_error : 1;
429 u32 MEDIA_Dest : 2;
430 u32 CAO_Dest : 2;
431 u32 CAI_Dest : 2;
432 u32 NET_Dest : 2;
433 } sram_dest_reg_714;
434
435 struct {
436 u32 reserved3 :11;
437 u32 net_addr_write : 1;
438 u32 reserved2 : 3;
439 u32 net_addr_read : 1;
440 u32 reserved1 : 4;
441 u32 net_cnt :12;
442 } net_buf_reg_718;
443
444 struct {
445 u32 reserved3 : 4;
446 u32 wan_pkt_frame : 4;
447 u32 reserved2 : 4;
448 u32 sram_memmap : 2;
449 u32 sram_chip : 2;
450 u32 wan_wait_state : 8;
451 u32 reserved1 : 6;
452 u32 wan_speed_sig : 2;
453 } wan_ctrl_reg_71c;
454 } flexcop_ibi_value;
455
456 #endif