drivers/media/rc/nuvoton-cir.c

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This source file includes following definitions.
nvt_get_dev
is_w83667hg
nvt_cr_write
nvt_cr_read
nvt_set_reg_bit
nvt_clear_reg_bit
nvt_efm_enable
nvt_efm_disable
nvt_select_logical_dev
nvt_enable_logical_dev
nvt_disable_logical_dev
nvt_cir_reg_write
nvt_cir_reg_read
nvt_cir_wake_reg_write
nvt_cir_wake_reg_read
nvt_set_ioaddr
nvt_write_wakeup_codes
wakeup_data_show
wakeup_data_store
cir_dump_regs
cir_wake_dump_regs
nvt_find_chip
nvt_hw_detect
nvt_cir_ldev_init
nvt_cir_wake_ldev_init
nvt_clear_cir_fifo
nvt_clear_cir_wake_fifo
nvt_clear_tx_fifo
nvt_set_cir_iren
nvt_cir_regs_init
nvt_cir_wake_regs_init
nvt_enable_wake
nvt_rx_carrier_detect
nvt_set_tx_carrier
nvt_ir_raw_set_wakeup_filter
nvt_dump_rx_buf
nvt_process_rx_ir_data
nvt_handle_rx_fifo_overrun
nvt_get_rx_ir_data
nvt_cir_log_irqs
nvt_cir_isr
nvt_enable_cir
nvt_disable_cir
nvt_open
nvt_close
nvt_probe
nvt_remove
nvt_suspend
nvt_resume
nvt_shutdown
   1 /*
   2  * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
   3  *
   4  * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
   5  * Copyright (C) 2009 Nuvoton PS Team
   6  *
   7  * Special thanks to Nuvoton for providing hardware, spec sheets and
   8  * sample code upon which portions of this driver are based. Indirect
   9  * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
  10  * modeled after.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of the
  15  * License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful, but
  18  * WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  20  * General Public License for more details.
  21  */
  22 
  23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  24 
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/pnp.h>
  28 #include <linux/io.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/sched.h>
  31 #include <linux/slab.h>
  32 #include <media/rc-core.h>
  33 #include <linux/pci_ids.h>
  34 
  35 #include "nuvoton-cir.h"
  36 
  37 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt);
  38 
  39 static const struct nvt_chip nvt_chips[] = {
  40         { "w83667hg", NVT_W83667HG },
  41         { "NCT6775F", NVT_6775F },
  42         { "NCT6776F", NVT_6776F },
  43         { "NCT6779D", NVT_6779D },
  44 };
  45 
  46 static inline struct device *nvt_get_dev(const struct nvt_dev *nvt)
  47 {
  48         return nvt->rdev->dev.parent;
  49 }
  50 
  51 static inline bool is_w83667hg(struct nvt_dev *nvt)
  52 {
  53         return nvt->chip_ver == NVT_W83667HG;
  54 }
  55 
  56 /* write val to config reg */
  57 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
  58 {
  59         outb(reg, nvt->cr_efir);
  60         outb(val, nvt->cr_efdr);
  61 }
  62 
  63 /* read val from config reg */
  64 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
  65 {
  66         outb(reg, nvt->cr_efir);
  67         return inb(nvt->cr_efdr);
  68 }
  69 
  70 /* update config register bit without changing other bits */
  71 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
  72 {
  73         u8 tmp = nvt_cr_read(nvt, reg) | val;
  74         nvt_cr_write(nvt, tmp, reg);
  75 }
  76 
  77 /* clear config register bit without changing other bits */
  78 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
  79 {
  80         u8 tmp = nvt_cr_read(nvt, reg) & ~val;
  81         nvt_cr_write(nvt, tmp, reg);
  82 }
  83 
  84 /* enter extended function mode */
  85 static inline int nvt_efm_enable(struct nvt_dev *nvt)
  86 {
  87         if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME))
  88                 return -EBUSY;
  89 
  90         /* Enabling Extended Function Mode explicitly requires writing 2x */
  91         outb(EFER_EFM_ENABLE, nvt->cr_efir);
  92         outb(EFER_EFM_ENABLE, nvt->cr_efir);
  93 
  94         return 0;
  95 }
  96 
  97 /* exit extended function mode */
  98 static inline void nvt_efm_disable(struct nvt_dev *nvt)
  99 {
 100         outb(EFER_EFM_DISABLE, nvt->cr_efir);
 101 
 102         release_region(nvt->cr_efir, 2);
 103 }
 104 
 105 /*
 106  * When you want to address a specific logical device, write its logical
 107  * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
 108  * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
 109  */
 110 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
 111 {
 112         nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL);
 113 }
 114 
 115 /* select and enable logical device with setting EFM mode*/
 116 static inline void nvt_enable_logical_dev(struct nvt_dev *nvt, u8 ldev)
 117 {
 118         nvt_efm_enable(nvt);
 119         nvt_select_logical_dev(nvt, ldev);
 120         nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
 121         nvt_efm_disable(nvt);
 122 }
 123 
 124 /* select and disable logical device with setting EFM mode*/
 125 static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev)
 126 {
 127         nvt_efm_enable(nvt);
 128         nvt_select_logical_dev(nvt, ldev);
 129         nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
 130         nvt_efm_disable(nvt);
 131 }
 132 
 133 /* write val to cir config register */
 134 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
 135 {
 136         outb(val, nvt->cir_addr + offset);
 137 }
 138 
 139 /* read val from cir config register */
 140 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
 141 {
 142         return inb(nvt->cir_addr + offset);
 143 }
 144 
 145 /* write val to cir wake register */
 146 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
 147                                           u8 val, u8 offset)
 148 {
 149         outb(val, nvt->cir_wake_addr + offset);
 150 }
 151 
 152 /* read val from cir wake config register */
 153 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
 154 {
 155         return inb(nvt->cir_wake_addr + offset);
 156 }
 157 
 158 /* don't override io address if one is set already */
 159 static void nvt_set_ioaddr(struct nvt_dev *nvt, unsigned long *ioaddr)
 160 {
 161         unsigned long old_addr;
 162 
 163         old_addr = nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8;
 164         old_addr |= nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO);
 165 
 166         if (old_addr)
 167                 *ioaddr = old_addr;
 168         else {
 169                 nvt_cr_write(nvt, *ioaddr >> 8, CR_CIR_BASE_ADDR_HI);
 170                 nvt_cr_write(nvt, *ioaddr & 0xff, CR_CIR_BASE_ADDR_LO);
 171         }
 172 }
 173 
 174 static void nvt_write_wakeup_codes(struct rc_dev *dev,
 175                                    const u8 *wbuf, int count)
 176 {
 177         u8 tolerance, config;
 178         struct nvt_dev *nvt = dev->priv;
 179         unsigned long flags;
 180         int i;
 181 
 182         /* hardcode the tolerance to 10% */
 183         tolerance = DIV_ROUND_UP(count, 10);
 184 
 185         spin_lock_irqsave(&nvt->lock, flags);
 186 
 187         nvt_clear_cir_wake_fifo(nvt);
 188         nvt_cir_wake_reg_write(nvt, count, CIR_WAKE_FIFO_CMP_DEEP);
 189         nvt_cir_wake_reg_write(nvt, tolerance, CIR_WAKE_FIFO_CMP_TOL);
 190 
 191         config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
 192 
 193         /* enable writes to wake fifo */
 194         nvt_cir_wake_reg_write(nvt, config | CIR_WAKE_IRCON_MODE1,
 195                                CIR_WAKE_IRCON);
 196 
 197         if (count)
 198                 pr_info("Wake samples (%d) =", count);
 199         else
 200                 pr_info("Wake sample fifo cleared");
 201 
 202         for (i = 0; i < count; i++)
 203                 nvt_cir_wake_reg_write(nvt, wbuf[i], CIR_WAKE_WR_FIFO_DATA);
 204 
 205         nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
 206 
 207         spin_unlock_irqrestore(&nvt->lock, flags);
 208 }
 209 
 210 static ssize_t wakeup_data_show(struct device *dev,
 211                                 struct device_attribute *attr,
 212                                 char *buf)
 213 {
 214         struct rc_dev *rc_dev = to_rc_dev(dev);
 215         struct nvt_dev *nvt = rc_dev->priv;
 216         int fifo_len, duration;
 217         unsigned long flags;
 218         ssize_t buf_len = 0;
 219         int i;
 220 
 221         spin_lock_irqsave(&nvt->lock, flags);
 222 
 223         fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
 224         fifo_len = min(fifo_len, WAKEUP_MAX_SIZE);
 225 
 226         /* go to first element to be read */
 227         while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX))
 228                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
 229 
 230         for (i = 0; i < fifo_len; i++) {
 231                 duration = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
 232                 duration = (duration & BUF_LEN_MASK) * SAMPLE_PERIOD;
 233                 buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len,
 234                                     "%d ", duration);
 235         }
 236         buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len, "\n");
 237 
 238         spin_unlock_irqrestore(&nvt->lock, flags);
 239 
 240         return buf_len;
 241 }
 242 
 243 static ssize_t wakeup_data_store(struct device *dev,
 244                                  struct device_attribute *attr,
 245                                  const char *buf, size_t len)
 246 {
 247         struct rc_dev *rc_dev = to_rc_dev(dev);
 248         u8 wake_buf[WAKEUP_MAX_SIZE];
 249         char **argv;
 250         int i, count;
 251         unsigned int val;
 252         ssize_t ret;
 253 
 254         argv = argv_split(GFP_KERNEL, buf, &count);
 255         if (!argv)
 256                 return -ENOMEM;
 257         if (!count || count > WAKEUP_MAX_SIZE) {
 258                 ret = -EINVAL;
 259                 goto out;
 260         }
 261 
 262         for (i = 0; i < count; i++) {
 263                 ret = kstrtouint(argv[i], 10, &val);
 264                 if (ret)
 265                         goto out;
 266                 val = DIV_ROUND_CLOSEST(val, SAMPLE_PERIOD);
 267                 if (!val || val > 0x7f) {
 268                         ret = -EINVAL;
 269                         goto out;
 270                 }
 271                 wake_buf[i] = val;
 272                 /* sequence must start with a pulse */
 273                 if (i % 2 == 0)
 274                         wake_buf[i] |= BUF_PULSE_BIT;
 275         }
 276 
 277         nvt_write_wakeup_codes(rc_dev, wake_buf, count);
 278 
 279         ret = len;
 280 out:
 281         argv_free(argv);
 282         return ret;
 283 }
 284 static DEVICE_ATTR_RW(wakeup_data);
 285 
 286 /* dump current cir register contents */
 287 static void cir_dump_regs(struct nvt_dev *nvt)
 288 {
 289         nvt_efm_enable(nvt);
 290         nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
 291 
 292         pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
 293         pr_info(" * CR CIR ACTIVE :   0x%x\n",
 294                 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
 295         pr_info(" * CR CIR BASE ADDR: 0x%x\n",
 296                 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
 297                 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
 298         pr_info(" * CR CIR IRQ NUM:   0x%x\n",
 299                 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
 300 
 301         nvt_efm_disable(nvt);
 302 
 303         pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
 304         pr_info(" * IRCON:     0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
 305         pr_info(" * IRSTS:     0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
 306         pr_info(" * IREN:      0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
 307         pr_info(" * RXFCONT:   0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
 308         pr_info(" * CP:        0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
 309         pr_info(" * CC:        0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
 310         pr_info(" * SLCH:      0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
 311         pr_info(" * SLCL:      0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
 312         pr_info(" * FIFOCON:   0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
 313         pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
 314         pr_info(" * SRXFIFO:   0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
 315         pr_info(" * TXFCONT:   0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
 316         pr_info(" * STXFIFO:   0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
 317         pr_info(" * FCCH:      0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
 318         pr_info(" * FCCL:      0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
 319         pr_info(" * IRFSM:     0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
 320 }
 321 
 322 /* dump current cir wake register contents */
 323 static void cir_wake_dump_regs(struct nvt_dev *nvt)
 324 {
 325         u8 i, fifo_len;
 326 
 327         nvt_efm_enable(nvt);
 328         nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
 329 
 330         pr_info("%s: Dump CIR WAKE logical device registers:\n",
 331                 NVT_DRIVER_NAME);
 332         pr_info(" * CR CIR WAKE ACTIVE :   0x%x\n",
 333                 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
 334         pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
 335                 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
 336                 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
 337         pr_info(" * CR CIR WAKE IRQ NUM:   0x%x\n",
 338                 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
 339 
 340         nvt_efm_disable(nvt);
 341 
 342         pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
 343         pr_info(" * IRCON:          0x%x\n",
 344                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
 345         pr_info(" * IRSTS:          0x%x\n",
 346                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
 347         pr_info(" * IREN:           0x%x\n",
 348                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
 349         pr_info(" * FIFO CMP DEEP:  0x%x\n",
 350                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
 351         pr_info(" * FIFO CMP TOL:   0x%x\n",
 352                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
 353         pr_info(" * FIFO COUNT:     0x%x\n",
 354                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
 355         pr_info(" * SLCH:           0x%x\n",
 356                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
 357         pr_info(" * SLCL:           0x%x\n",
 358                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
 359         pr_info(" * FIFOCON:        0x%x\n",
 360                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
 361         pr_info(" * SRXFSTS:        0x%x\n",
 362                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
 363         pr_info(" * SAMPLE RX FIFO: 0x%x\n",
 364                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
 365         pr_info(" * WR FIFO DATA:   0x%x\n",
 366                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
 367         pr_info(" * RD FIFO ONLY:   0x%x\n",
 368                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
 369         pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
 370                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
 371         pr_info(" * FIFO IGNORE:    0x%x\n",
 372                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
 373         pr_info(" * IRFSM:          0x%x\n",
 374                 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
 375 
 376         fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
 377         pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
 378         pr_info("* Contents =");
 379         for (i = 0; i < fifo_len; i++)
 380                 pr_cont(" %02x",
 381                         nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
 382         pr_cont("\n");
 383 }
 384 
 385 static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id)
 386 {
 387         int i;
 388 
 389         for (i = 0; i < ARRAY_SIZE(nvt_chips); i++)
 390                 if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) {
 391                         nvt->chip_ver = nvt_chips[i].chip_ver;
 392                         return nvt_chips[i].name;
 393                 }
 394 
 395         return NULL;
 396 }
 397 
 398 
 399 /* detect hardware features */
 400 static int nvt_hw_detect(struct nvt_dev *nvt)
 401 {
 402         struct device *dev = nvt_get_dev(nvt);
 403         const char *chip_name;
 404         int chip_id;
 405 
 406         nvt_efm_enable(nvt);
 407 
 408         /* Check if we're wired for the alternate EFER setup */
 409         nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
 410         if (nvt->chip_major == 0xff) {
 411                 nvt_efm_disable(nvt);
 412                 nvt->cr_efir = CR_EFIR2;
 413                 nvt->cr_efdr = CR_EFDR2;
 414                 nvt_efm_enable(nvt);
 415                 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
 416         }
 417         nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
 418 
 419         nvt_efm_disable(nvt);
 420 
 421         chip_id = nvt->chip_major << 8 | nvt->chip_minor;
 422         if (chip_id == NVT_INVALID) {
 423                 dev_err(dev, "No device found on either EFM port\n");
 424                 return -ENODEV;
 425         }
 426 
 427         chip_name = nvt_find_chip(nvt, chip_id);
 428 
 429         /* warn, but still let the driver load, if we don't know this chip */
 430         if (!chip_name)
 431                 dev_warn(dev,
 432                          "unknown chip, id: 0x%02x 0x%02x, it may not work...",
 433                          nvt->chip_major, nvt->chip_minor);
 434         else
 435                 dev_info(dev, "found %s or compatible: chip id: 0x%02x 0x%02x",
 436                          chip_name, nvt->chip_major, nvt->chip_minor);
 437 
 438         return 0;
 439 }
 440 
 441 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
 442 {
 443         u8 val, psreg, psmask, psval;
 444 
 445         if (is_w83667hg(nvt)) {
 446                 psreg = CR_MULTIFUNC_PIN_SEL;
 447                 psmask = MULTIFUNC_PIN_SEL_MASK;
 448                 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
 449         } else {
 450                 psreg = CR_OUTPUT_PIN_SEL;
 451                 psmask = OUTPUT_PIN_SEL_MASK;
 452                 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
 453         }
 454 
 455         /* output pin selection: enable CIR, with WB sensor enabled */
 456         val = nvt_cr_read(nvt, psreg);
 457         val &= psmask;
 458         val |= psval;
 459         nvt_cr_write(nvt, val, psreg);
 460 
 461         /* Select CIR logical device */
 462         nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
 463 
 464         nvt_set_ioaddr(nvt, &nvt->cir_addr);
 465 
 466         nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
 467 
 468         nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
 469                 nvt->cir_addr, nvt->cir_irq);
 470 }
 471 
 472 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
 473 {
 474         /* Select ACPI logical device and anable it */
 475         nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
 476         nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
 477 
 478         /* Enable CIR Wake via PSOUT# (Pin60) */
 479         nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
 480 
 481         /* enable pme interrupt of cir wakeup event */
 482         nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
 483 
 484         /* Select CIR Wake logical device */
 485         nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
 486 
 487         nvt_set_ioaddr(nvt, &nvt->cir_wake_addr);
 488 
 489         nvt_dbg("CIR Wake initialized, base io port address: 0x%lx",
 490                 nvt->cir_wake_addr);
 491 }
 492 
 493 /* clear out the hardware's cir rx fifo */
 494 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
 495 {
 496         u8 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
 497         nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
 498 }
 499 
 500 /* clear out the hardware's cir wake rx fifo */
 501 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
 502 {
 503         u8 val, config;
 504 
 505         config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
 506 
 507         /* clearing wake fifo works in learning mode only */
 508         nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0,
 509                                CIR_WAKE_IRCON);
 510 
 511         val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
 512         nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
 513                                CIR_WAKE_FIFOCON);
 514 
 515         nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
 516 }
 517 
 518 /* clear out the hardware's cir tx fifo */
 519 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
 520 {
 521         u8 val;
 522 
 523         val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
 524         nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
 525 }
 526 
 527 /* enable RX Trigger Level Reach and Packet End interrupts */
 528 static void nvt_set_cir_iren(struct nvt_dev *nvt)
 529 {
 530         u8 iren;
 531 
 532         iren = CIR_IREN_RTR | CIR_IREN_PE | CIR_IREN_RFO;
 533         nvt_cir_reg_write(nvt, iren, CIR_IREN);
 534 }
 535 
 536 static void nvt_cir_regs_init(struct nvt_dev *nvt)
 537 {
 538         nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
 539 
 540         /* set sample limit count (PE interrupt raised when reached) */
 541         nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
 542         nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
 543 
 544         /* set fifo irq trigger levels */
 545         nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
 546                           CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
 547 
 548         /* clear hardware rx and tx fifos */
 549         nvt_clear_cir_fifo(nvt);
 550         nvt_clear_tx_fifo(nvt);
 551 
 552         nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
 553 }
 554 
 555 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
 556 {
 557         nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
 558 
 559         /*
 560          * Disable RX, set specific carrier on = low, off = high,
 561          * and sample period (currently 50us)
 562          */
 563         nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 |
 564                                CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
 565                                CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
 566                                CIR_WAKE_IRCON);
 567 
 568         /* clear any and all stray interrupts */
 569         nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
 570 }
 571 
 572 static void nvt_enable_wake(struct nvt_dev *nvt)
 573 {
 574         unsigned long flags;
 575 
 576         nvt_efm_enable(nvt);
 577 
 578         nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
 579         nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
 580         nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
 581 
 582         nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
 583         nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
 584 
 585         nvt_efm_disable(nvt);
 586 
 587         spin_lock_irqsave(&nvt->lock, flags);
 588 
 589         nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
 590                                CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
 591                                CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
 592                                CIR_WAKE_IRCON);
 593         nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
 594         nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
 595 
 596         spin_unlock_irqrestore(&nvt->lock, flags);
 597 }
 598 
 599 #if 0 /* Currently unused */
 600 /* rx carrier detect only works in learning mode, must be called w/lock */
 601 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
 602 {
 603         u32 count, carrier, duration = 0;
 604         int i;
 605 
 606         count = nvt_cir_reg_read(nvt, CIR_FCCL) |
 607                 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
 608 
 609         for (i = 0; i < nvt->pkts; i++) {
 610                 if (nvt->buf[i] & BUF_PULSE_BIT)
 611                         duration += nvt->buf[i] & BUF_LEN_MASK;
 612         }
 613 
 614         duration *= SAMPLE_PERIOD;
 615 
 616         if (!count || !duration) {
 617                 dev_notice(nvt_get_dev(nvt),
 618                            "Unable to determine carrier! (c:%u, d:%u)",
 619                            count, duration);
 620                 return 0;
 621         }
 622 
 623         carrier = MS_TO_NS(count) / duration;
 624 
 625         if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
 626                 nvt_dbg("WTF? Carrier frequency out of range!");
 627 
 628         nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
 629                 carrier, count, duration);
 630 
 631         return carrier;
 632 }
 633 #endif
 634 /*
 635  * set carrier frequency
 636  *
 637  * set carrier on 2 registers: CP & CC
 638  * always set CP as 0x81
 639  * set CC by SPEC, CC = 3MHz/carrier - 1
 640  */
 641 static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
 642 {
 643         struct nvt_dev *nvt = dev->priv;
 644         u16 val;
 645 
 646         if (carrier == 0)
 647                 return -EINVAL;
 648 
 649         nvt_cir_reg_write(nvt, 1, CIR_CP);
 650         val = 3000000 / (carrier) - 1;
 651         nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
 652 
 653         nvt_dbg("cp: 0x%x cc: 0x%x\n",
 654                 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
 655 
 656         return 0;
 657 }
 658 
 659 static int nvt_ir_raw_set_wakeup_filter(struct rc_dev *dev,
 660                                         struct rc_scancode_filter *sc_filter)
 661 {
 662         u8 buf_val;
 663         int i, ret, count;
 664         unsigned int val;
 665         struct ir_raw_event *raw;
 666         u8 wake_buf[WAKEUP_MAX_SIZE];
 667         bool complete;
 668 
 669         /* Require mask to be set */
 670         if (!sc_filter->mask)
 671                 return 0;
 672 
 673         raw = kmalloc_array(WAKEUP_MAX_SIZE, sizeof(*raw), GFP_KERNEL);
 674         if (!raw)
 675                 return -ENOMEM;
 676 
 677         ret = ir_raw_encode_scancode(dev->wakeup_protocol, sc_filter->data,
 678                                      raw, WAKEUP_MAX_SIZE);
 679         complete = (ret != -ENOBUFS);
 680         if (!complete)
 681                 ret = WAKEUP_MAX_SIZE;
 682         else if (ret < 0)
 683                 goto out_raw;
 684 
 685         /* Inspect the ir samples */
 686         for (i = 0, count = 0; i < ret && count < WAKEUP_MAX_SIZE; ++i) {
 687                 /* NS to US */
 688                 val = DIV_ROUND_UP(raw[i].duration, 1000L) / SAMPLE_PERIOD;
 689 
 690                 /* Split too large values into several smaller ones */
 691                 while (val > 0 && count < WAKEUP_MAX_SIZE) {
 692                         /* Skip last value for better comparison tolerance */
 693                         if (complete && i == ret - 1 && val < BUF_LEN_MASK)
 694                                 break;
 695 
 696                         /* Clamp values to BUF_LEN_MASK at most */
 697                         buf_val = (val > BUF_LEN_MASK) ? BUF_LEN_MASK : val;
 698 
 699                         wake_buf[count] = buf_val;
 700                         val -= buf_val;
 701                         if ((raw[i]).pulse)
 702                                 wake_buf[count] |= BUF_PULSE_BIT;
 703                         count++;
 704                 }
 705         }
 706 
 707         nvt_write_wakeup_codes(dev, wake_buf, count);
 708         ret = 0;
 709 out_raw:
 710         kfree(raw);
 711 
 712         return ret;
 713 }
 714 
 715 /* dump contents of the last rx buffer we got from the hw rx fifo */
 716 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
 717 {
 718         int i;
 719 
 720         printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
 721         for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
 722                 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
 723         printk(KERN_CONT "\n");
 724 }
 725 
 726 /*
 727  * Process raw data in rx driver buffer, store it in raw IR event kfifo,
 728  * trigger decode when appropriate.
 729  *
 730  * We get IR data samples one byte at a time. If the msb is set, its a pulse,
 731  * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
 732  * (default 50us) intervals for that pulse/space. A discrete signal is
 733  * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
 734  * to signal more IR coming (repeats) or end of IR, respectively. We store
 735  * sample data in the raw event kfifo until we see 0x7<something> (except f)
 736  * or 0x80, at which time, we trigger a decode operation.
 737  */
 738 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
 739 {
 740         struct ir_raw_event rawir = {};
 741         u8 sample;
 742         int i;
 743 
 744         nvt_dbg_verbose("%s firing", __func__);
 745 
 746         if (debug)
 747                 nvt_dump_rx_buf(nvt);
 748 
 749         nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
 750 
 751         for (i = 0; i < nvt->pkts; i++) {
 752                 sample = nvt->buf[i];
 753 
 754                 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
 755                 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
 756                                           * SAMPLE_PERIOD);
 757 
 758                 nvt_dbg("Storing %s with duration %d",
 759                         rawir.pulse ? "pulse" : "space", rawir.duration);
 760 
 761                 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
 762         }
 763 
 764         nvt->pkts = 0;
 765 
 766         nvt_dbg("Calling ir_raw_event_handle\n");
 767         ir_raw_event_handle(nvt->rdev);
 768 
 769         nvt_dbg_verbose("%s done", __func__);
 770 }
 771 
 772 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
 773 {
 774         dev_warn(nvt_get_dev(nvt), "RX FIFO overrun detected, flushing data!");
 775 
 776         nvt->pkts = 0;
 777         nvt_clear_cir_fifo(nvt);
 778         ir_raw_event_reset(nvt->rdev);
 779 }
 780 
 781 /* copy data from hardware rx fifo into driver buffer */
 782 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
 783 {
 784         u8 fifocount;
 785         int i;
 786 
 787         /* Get count of how many bytes to read from RX FIFO */
 788         fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
 789 
 790         nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
 791 
 792         /* Read fifocount bytes from CIR Sample RX FIFO register */
 793         for (i = 0; i < fifocount; i++)
 794                 nvt->buf[i] = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
 795 
 796         nvt->pkts = fifocount;
 797         nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
 798 
 799         nvt_process_rx_ir_data(nvt);
 800 }
 801 
 802 static void nvt_cir_log_irqs(u8 status, u8 iren)
 803 {
 804         nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
 805                 status, iren,
 806                 status & CIR_IRSTS_RDR  ? " RDR"        : "",
 807                 status & CIR_IRSTS_RTR  ? " RTR"        : "",
 808                 status & CIR_IRSTS_PE   ? " PE"         : "",
 809                 status & CIR_IRSTS_RFO  ? " RFO"        : "",
 810                 status & CIR_IRSTS_TE   ? " TE"         : "",
 811                 status & CIR_IRSTS_TTR  ? " TTR"        : "",
 812                 status & CIR_IRSTS_TFU  ? " TFU"        : "",
 813                 status & CIR_IRSTS_GH   ? " GH"         : "",
 814                 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
 815                            CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
 816                            CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
 817 }
 818 
 819 /* interrupt service routine for incoming and outgoing CIR data */
 820 static irqreturn_t nvt_cir_isr(int irq, void *data)
 821 {
 822         struct nvt_dev *nvt = data;
 823         u8 status, iren;
 824 
 825         nvt_dbg_verbose("%s firing", __func__);
 826 
 827         spin_lock(&nvt->lock);
 828 
 829         /*
 830          * Get IR Status register contents. Write 1 to ack/clear
 831          *
 832          * bit: reg name      - description
 833          *   7: CIR_IRSTS_RDR - RX Data Ready
 834          *   6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
 835          *   5: CIR_IRSTS_PE  - Packet End
 836          *   4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
 837          *   3: CIR_IRSTS_TE  - TX FIFO Empty
 838          *   2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
 839          *   1: CIR_IRSTS_TFU - TX FIFO Underrun
 840          *   0: CIR_IRSTS_GH  - Min Length Detected
 841          */
 842         status = nvt_cir_reg_read(nvt, CIR_IRSTS);
 843         iren = nvt_cir_reg_read(nvt, CIR_IREN);
 844 
 845         /* At least NCT6779D creates a spurious interrupt when the
 846          * logical device is being disabled.
 847          */
 848         if (status == 0xff && iren == 0xff) {
 849                 spin_unlock(&nvt->lock);
 850                 nvt_dbg_verbose("Spurious interrupt detected");
 851                 return IRQ_HANDLED;
 852         }
 853 
 854         /* IRQ may be shared with CIR WAKE, therefore check for each
 855          * status bit whether the related interrupt source is enabled
 856          */
 857         if (!(status & iren)) {
 858                 spin_unlock(&nvt->lock);
 859                 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
 860                 return IRQ_NONE;
 861         }
 862 
 863         /* ack/clear all irq flags we've got */
 864         nvt_cir_reg_write(nvt, status, CIR_IRSTS);
 865         nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
 866 
 867         nvt_cir_log_irqs(status, iren);
 868 
 869         if (status & CIR_IRSTS_RFO)
 870                 nvt_handle_rx_fifo_overrun(nvt);
 871         else if (status & (CIR_IRSTS_RTR | CIR_IRSTS_PE))
 872                 nvt_get_rx_ir_data(nvt);
 873 
 874         spin_unlock(&nvt->lock);
 875 
 876         nvt_dbg_verbose("%s done", __func__);
 877         return IRQ_HANDLED;
 878 }
 879 
 880 static void nvt_enable_cir(struct nvt_dev *nvt)
 881 {
 882         unsigned long flags;
 883 
 884         /* enable the CIR logical device */
 885         nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
 886 
 887         spin_lock_irqsave(&nvt->lock, flags);
 888 
 889         /*
 890          * Enable TX and RX, specify carrier on = low, off = high, and set
 891          * sample period (currently 50us)
 892          */
 893         nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
 894                           CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
 895                           CIR_IRCON);
 896 
 897         /* clear all pending interrupts */
 898         nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
 899 
 900         /* enable interrupts */
 901         nvt_set_cir_iren(nvt);
 902 
 903         spin_unlock_irqrestore(&nvt->lock, flags);
 904 }
 905 
 906 static void nvt_disable_cir(struct nvt_dev *nvt)
 907 {
 908         unsigned long flags;
 909 
 910         spin_lock_irqsave(&nvt->lock, flags);
 911 
 912         /* disable CIR interrupts */
 913         nvt_cir_reg_write(nvt, 0, CIR_IREN);
 914 
 915         /* clear any and all pending interrupts */
 916         nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
 917 
 918         /* clear all function enable flags */
 919         nvt_cir_reg_write(nvt, 0, CIR_IRCON);
 920 
 921         /* clear hardware rx and tx fifos */
 922         nvt_clear_cir_fifo(nvt);
 923         nvt_clear_tx_fifo(nvt);
 924 
 925         spin_unlock_irqrestore(&nvt->lock, flags);
 926 
 927         /* disable the CIR logical device */
 928         nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
 929 }
 930 
 931 static int nvt_open(struct rc_dev *dev)
 932 {
 933         struct nvt_dev *nvt = dev->priv;
 934 
 935         nvt_enable_cir(nvt);
 936 
 937         return 0;
 938 }
 939 
 940 static void nvt_close(struct rc_dev *dev)
 941 {
 942         struct nvt_dev *nvt = dev->priv;
 943 
 944         nvt_disable_cir(nvt);
 945 }
 946 
 947 /* Allocate memory, probe hardware, and initialize everything */
 948 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
 949 {
 950         struct nvt_dev *nvt;
 951         struct rc_dev *rdev;
 952         int ret;
 953 
 954         nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL);
 955         if (!nvt)
 956                 return -ENOMEM;
 957 
 958         /* input device for IR remote */
 959         nvt->rdev = devm_rc_allocate_device(&pdev->dev, RC_DRIVER_IR_RAW);
 960         if (!nvt->rdev)
 961                 return -ENOMEM;
 962         rdev = nvt->rdev;
 963 
 964         /* activate pnp device */
 965         ret = pnp_activate_dev(pdev);
 966         if (ret) {
 967                 dev_err(&pdev->dev, "Could not activate PNP device!\n");
 968                 return ret;
 969         }
 970 
 971         /* validate pnp resources */
 972         if (!pnp_port_valid(pdev, 0) ||
 973             pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
 974                 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
 975                 return -EINVAL;
 976         }
 977 
 978         if (!pnp_irq_valid(pdev, 0)) {
 979                 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
 980                 return -EINVAL;
 981         }
 982 
 983         if (!pnp_port_valid(pdev, 1) ||
 984             pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
 985                 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
 986                 return -EINVAL;
 987         }
 988 
 989         nvt->cir_addr = pnp_port_start(pdev, 0);
 990         nvt->cir_irq  = pnp_irq(pdev, 0);
 991 
 992         nvt->cir_wake_addr = pnp_port_start(pdev, 1);
 993 
 994         nvt->cr_efir = CR_EFIR;
 995         nvt->cr_efdr = CR_EFDR;
 996 
 997         spin_lock_init(&nvt->lock);
 998 
 999         pnp_set_drvdata(pdev, nvt);
1000 
1001         ret = nvt_hw_detect(nvt);
1002         if (ret)
1003                 return ret;
1004 
1005         /* Initialize CIR & CIR Wake Logical Devices */
1006         nvt_efm_enable(nvt);
1007         nvt_cir_ldev_init(nvt);
1008         nvt_cir_wake_ldev_init(nvt);
1009         nvt_efm_disable(nvt);
1010 
1011         /*
1012          * Initialize CIR & CIR Wake Config Registers
1013          * and enable logical devices
1014          */
1015         nvt_cir_regs_init(nvt);
1016         nvt_cir_wake_regs_init(nvt);
1017 
1018         /* Set up the rc device */
1019         rdev->priv = nvt;
1020         rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
1021         rdev->allowed_wakeup_protocols = RC_PROTO_BIT_ALL_IR_ENCODER;
1022         rdev->encode_wakeup = true;
1023         rdev->open = nvt_open;
1024         rdev->close = nvt_close;
1025         rdev->s_tx_carrier = nvt_set_tx_carrier;
1026         rdev->s_wakeup_filter = nvt_ir_raw_set_wakeup_filter;
1027         rdev->device_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1028         rdev->input_phys = "nuvoton/cir0";
1029         rdev->input_id.bustype = BUS_HOST;
1030         rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1031         rdev->input_id.product = nvt->chip_major;
1032         rdev->input_id.version = nvt->chip_minor;
1033         rdev->driver_name = NVT_DRIVER_NAME;
1034         rdev->map_name = RC_MAP_RC6_MCE;
1035         rdev->timeout = MS_TO_NS(100);
1036         /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1037         rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
1038 #if 0
1039         rdev->min_timeout = XYZ;
1040         rdev->max_timeout = XYZ;
1041 #endif
1042         ret = devm_rc_register_device(&pdev->dev, rdev);
1043         if (ret)
1044                 return ret;
1045 
1046         /* now claim resources */
1047         if (!devm_request_region(&pdev->dev, nvt->cir_addr,
1048                             CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1049                 return -EBUSY;
1050 
1051         ret = devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr,
1052                                IRQF_SHARED, NVT_DRIVER_NAME, nvt);
1053         if (ret)
1054                 return ret;
1055 
1056         if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr,
1057                             CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake"))
1058                 return -EBUSY;
1059 
1060         ret = device_create_file(&rdev->dev, &dev_attr_wakeup_data);
1061         if (ret)
1062                 return ret;
1063 
1064         device_init_wakeup(&pdev->dev, true);
1065 
1066         dev_notice(&pdev->dev, "driver has been successfully loaded\n");
1067         if (debug) {
1068                 cir_dump_regs(nvt);
1069                 cir_wake_dump_regs(nvt);
1070         }
1071 
1072         return 0;
1073 }
1074 
1075 static void nvt_remove(struct pnp_dev *pdev)
1076 {
1077         struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1078 
1079         device_remove_file(&nvt->rdev->dev, &dev_attr_wakeup_data);
1080 
1081         nvt_disable_cir(nvt);
1082 
1083         /* enable CIR Wake (for IR power-on) */
1084         nvt_enable_wake(nvt);
1085 }
1086 
1087 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1088 {
1089         struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1090 
1091         nvt_dbg("%s called", __func__);
1092 
1093         mutex_lock(&nvt->rdev->lock);
1094         if (nvt->rdev->users)
1095                 nvt_disable_cir(nvt);
1096         mutex_unlock(&nvt->rdev->lock);
1097 
1098         /* make sure wake is enabled */
1099         nvt_enable_wake(nvt);
1100 
1101         return 0;
1102 }
1103 
1104 static int nvt_resume(struct pnp_dev *pdev)
1105 {
1106         struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1107 
1108         nvt_dbg("%s called", __func__);
1109 
1110         nvt_cir_regs_init(nvt);
1111         nvt_cir_wake_regs_init(nvt);
1112 
1113         mutex_lock(&nvt->rdev->lock);
1114         if (nvt->rdev->users)
1115                 nvt_enable_cir(nvt);
1116         mutex_unlock(&nvt->rdev->lock);
1117 
1118         return 0;
1119 }
1120 
1121 static void nvt_shutdown(struct pnp_dev *pdev)
1122 {
1123         struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1124 
1125         nvt_enable_wake(nvt);
1126 }
1127 
1128 static const struct pnp_device_id nvt_ids[] = {
1129         { "WEC0530", 0 },   /* CIR */
1130         { "NTN0530", 0 },   /* CIR for new chip's pnp id*/
1131         { "", 0 },
1132 };
1133 
1134 static struct pnp_driver nvt_driver = {
1135         .name           = NVT_DRIVER_NAME,
1136         .id_table       = nvt_ids,
1137         .flags          = PNP_DRIVER_RES_DO_NOT_CHANGE,
1138         .probe          = nvt_probe,
1139         .remove         = nvt_remove,
1140         .suspend        = nvt_suspend,
1141         .resume         = nvt_resume,
1142         .shutdown       = nvt_shutdown,
1143 };
1144 
1145 module_param(debug, int, S_IRUGO | S_IWUSR);
1146 MODULE_PARM_DESC(debug, "Enable debugging output");
1147 
1148 MODULE_DEVICE_TABLE(pnp, nvt_ids);
1149 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1150 
1151 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1152 MODULE_LICENSE("GPL");
1153 
1154 module_pnp_driver(nvt_driver);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/media/rc/nuvoton-cir.c

DEFINITIONS
