1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Driver for ITE Tech Inc. IT8712F/IT8512F CIR
4 *
5 * Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com>
6 */
7
8 /* platform driver name to register */
9 #define ITE_DRIVER_NAME "ite-cir"
10
11 /* logging macros */
12 #define ite_pr(level, text, ...) \
13 printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
14 #define ite_dbg(text, ...) do { \
15 if (debug) \
16 printk(KERN_DEBUG \
17 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__); \
18 } while (0)
19
20 #define ite_dbg_verbose(text, ...) do {\
21 if (debug > 1) \
22 printk(KERN_DEBUG \
23 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__); \
24 } while (0)
25
26 /* FIFO sizes */
27 #define ITE_TX_FIFO_LEN 32
28 #define ITE_RX_FIFO_LEN 32
29
30 /* interrupt types */
31 #define ITE_IRQ_TX_FIFO 1
32 #define ITE_IRQ_RX_FIFO 2
33 #define ITE_IRQ_RX_FIFO_OVERRUN 4
34
35 /* forward declaration */
36 struct ite_dev;
37
38 /* struct for storing the parameters of different recognized devices */
39 struct ite_dev_params {
40 /* model of the device */
41 const char *model;
42
43 /* size of the I/O region */
44 int io_region_size;
45
46 /* IR pnp I/O resource number */
47 int io_rsrc_no;
48
49 /* true if the hardware supports transmission */
50 bool hw_tx_capable;
51
52 /* base sampling period, in ns */
53 u32 sample_period;
54
55 /* rx low carrier frequency, in Hz, 0 means no demodulation */
56 unsigned int rx_low_carrier_freq;
57
58 /* tx high carrier frequency, in Hz, 0 means no demodulation */
59 unsigned int rx_high_carrier_freq;
60
61 /* tx carrier frequency, in Hz */
62 unsigned int tx_carrier_freq;
63
64 /* duty cycle, 0-100 */
65 int tx_duty_cycle;
66
67 /* hw-specific operation function pointers; most of these must be
68 * called while holding the spin lock, except for the TX FIFO length
69 * one */
70 /* get pending interrupt causes */
71 int (*get_irq_causes) (struct ite_dev *dev);
72
73 /* enable rx */
74 void (*enable_rx) (struct ite_dev *dev);
75
76 /* make rx enter the idle state; keep listening for a pulse, but stop
77 * streaming space bytes */
78 void (*idle_rx) (struct ite_dev *dev);
79
80 /* disable rx completely */
81 void (*disable_rx) (struct ite_dev *dev);
82
83 /* read bytes from RX FIFO; return read count */
84 int (*get_rx_bytes) (struct ite_dev *dev, u8 *buf, int buf_size);
85
86 /* enable tx FIFO space available interrupt */
87 void (*enable_tx_interrupt) (struct ite_dev *dev);
88
89 /* disable tx FIFO space available interrupt */
90 void (*disable_tx_interrupt) (struct ite_dev *dev);
91
92 /* get number of full TX FIFO slots */
93 int (*get_tx_used_slots) (struct ite_dev *dev);
94
95 /* put a byte to the TX FIFO */
96 void (*put_tx_byte) (struct ite_dev *dev, u8 value);
97
98 /* disable hardware completely */
99 void (*disable) (struct ite_dev *dev);
100
101 /* initialize the hardware */
102 void (*init_hardware) (struct ite_dev *dev);
103
104 /* set the carrier parameters */
105 void (*set_carrier_params) (struct ite_dev *dev, bool high_freq,
106 bool use_demodulator, u8 carrier_freq_bits,
107 u8 allowance_bits, u8 pulse_width_bits);
108 };
109
110 /* ITE CIR device structure */
111 struct ite_dev {
112 struct pnp_dev *pdev;
113 struct rc_dev *rdev;
114 struct ir_raw_event rawir;
115
116 /* sync data */
117 spinlock_t lock;
118 bool in_use, transmitting;
119
120 /* transmit support */
121 int tx_fifo_allowance;
122 wait_queue_head_t tx_queue, tx_ended;
123
124 /* hardware I/O settings */
125 unsigned long cir_addr;
126 int cir_irq;
127
128 /* overridable copy of model parameters */
129 struct ite_dev_params params;
130 };
131
132 /* common values for all kinds of hardware */
133
134 /* baud rate divisor default */
135 #define ITE_BAUDRATE_DIVISOR 1
136
137 /* low-speed carrier frequency limits (Hz) */
138 #define ITE_LCF_MIN_CARRIER_FREQ 27000
139 #define ITE_LCF_MAX_CARRIER_FREQ 58000
140
141 /* high-speed carrier frequency limits (Hz) */
142 #define ITE_HCF_MIN_CARRIER_FREQ 400000
143 #define ITE_HCF_MAX_CARRIER_FREQ 500000
144
145 /* default carrier freq for when demodulator is off (Hz) */
146 #define ITE_DEFAULT_CARRIER_FREQ 38000
147
148 /* convert bits to us */
149 #define ITE_BITS_TO_NS(bits, sample_period) \
150 ((u32) ((bits) * ITE_BAUDRATE_DIVISOR * sample_period))
151
152 /*
153 * n in RDCR produces a tolerance of +/- n * 6.25% around the center
154 * carrier frequency...
155 *
156 * From two limit frequencies, L (low) and H (high), we can get both the
157 * center frequency F = (L + H) / 2 and the variation from the center
158 * frequency A = (H - L) / (H + L). We can use this in order to honor the
159 * s_rx_carrier_range() call in ir-core. We'll suppose that any request
160 * setting L=0 means we must shut down the demodulator.
161 */
162 #define ITE_RXDCR_PER_10000_STEP 625
163
164 /* high speed carrier freq values */
165 #define ITE_CFQ_400 0x03
166 #define ITE_CFQ_450 0x08
167 #define ITE_CFQ_480 0x0b
168 #define ITE_CFQ_500 0x0d
169
170 /* values for pulse widths */
171 #define ITE_TXMPW_A 0x02
172 #define ITE_TXMPW_B 0x03
173 #define ITE_TXMPW_C 0x04
174 #define ITE_TXMPW_D 0x05
175 #define ITE_TXMPW_E 0x06
176
177 /* values for demodulator carrier range allowance */
178 #define ITE_RXDCR_DEFAULT 0x01 /* default carrier range */
179 #define ITE_RXDCR_MAX 0x07 /* default carrier range */
180
181 /* DR TX bits */
182 #define ITE_TX_PULSE 0x00
183 #define ITE_TX_SPACE 0x80
184 #define ITE_TX_MAX_RLE 0x80
185 #define ITE_TX_RLE_MASK 0x7f
186
187 /*
188 * IT8712F
189 *
190 * hardware data obtained from:
191 *
192 * IT8712F
193 * Environment Control – Low Pin Count Input / Output
194 * (EC - LPC I/O)
195 * Preliminary Specification V0. 81
196 */
197
198 /* register offsets */
199 #define IT87_DR 0x00 /* data register */
200 #define IT87_IER 0x01 /* interrupt enable register */
201 #define IT87_RCR 0x02 /* receiver control register */
202 #define IT87_TCR1 0x03 /* transmitter control register 1 */
203 #define IT87_TCR2 0x04 /* transmitter control register 2 */
204 #define IT87_TSR 0x05 /* transmitter status register */
205 #define IT87_RSR 0x06 /* receiver status register */
206 #define IT87_BDLR 0x05 /* baud rate divisor low byte register */
207 #define IT87_BDHR 0x06 /* baud rate divisor high byte register */
208 #define IT87_IIR 0x07 /* interrupt identification register */
209
210 #define IT87_IOREG_LENGTH 0x08 /* length of register file */
211
212 /* IER bits */
213 #define IT87_TLDLIE 0x01 /* transmitter low data interrupt enable */
214 #define IT87_RDAIE 0x02 /* receiver data available interrupt enable */
215 #define IT87_RFOIE 0x04 /* receiver FIFO overrun interrupt enable */
216 #define IT87_IEC 0x08 /* interrupt enable control */
217 #define IT87_BR 0x10 /* baud rate register enable */
218 #define IT87_RESET 0x20 /* reset */
219
220 /* RCR bits */
221 #define IT87_RXDCR 0x07 /* receiver demodulation carrier range mask */
222 #define IT87_RXACT 0x08 /* receiver active */
223 #define IT87_RXEND 0x10 /* receiver demodulation enable */
224 #define IT87_RXEN 0x20 /* receiver enable */
225 #define IT87_HCFS 0x40 /* high-speed carrier frequency select */
226 #define IT87_RDWOS 0x80 /* receiver data without sync */
227
228 /* TCR1 bits */
229 #define IT87_TXMPM 0x03 /* transmitter modulation pulse mode mask */
230 #define IT87_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */
231 #define IT87_TXENDF 0x04 /* transmitter deferral */
232 #define IT87_TXRLE 0x08 /* transmitter run length enable */
233 #define IT87_FIFOTL 0x30 /* FIFO level threshold mask */
234 #define IT87_FIFOTL_DEFAULT 0x20 /* FIFO level threshold default
235 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
236 * 0x30 -> 25 */
237 #define IT87_ILE 0x40 /* internal loopback enable */
238 #define IT87_FIFOCLR 0x80 /* FIFO clear bit */
239
240 /* TCR2 bits */
241 #define IT87_TXMPW 0x07 /* transmitter modulation pulse width mask */
242 #define IT87_TXMPW_DEFAULT 0x04 /* default modulation pulse width */
243 #define IT87_CFQ 0xf8 /* carrier frequency mask */
244 #define IT87_CFQ_SHIFT 3 /* carrier frequency bit shift */
245
246 /* TSR bits */
247 #define IT87_TXFBC 0x3f /* transmitter FIFO byte count mask */
248
249 /* RSR bits */
250 #define IT87_RXFBC 0x3f /* receiver FIFO byte count mask */
251 #define IT87_RXFTO 0x80 /* receiver FIFO time-out */
252
253 /* IIR bits */
254 #define IT87_IP 0x01 /* interrupt pending */
255 #define IT87_II 0x06 /* interrupt identification mask */
256 #define IT87_II_NOINT 0x00 /* no interrupt */
257 #define IT87_II_TXLDL 0x02 /* transmitter low data level */
258 #define IT87_II_RXDS 0x04 /* receiver data stored */
259 #define IT87_II_RXFO 0x06 /* receiver FIFO overrun */
260
261 /*
262 * IT8512E/F
263 *
264 * Hardware data obtained from:
265 *
266 * IT8512E/F
267 * Embedded Controller
268 * Preliminary Specification V0.4.1
269 *
270 * Note that the CIR registers are not directly available to the host, because
271 * they only are accessible to the integrated microcontroller. Thus, in order
272 * use it, some kind of bridging is required. As the bridging may depend on
273 * the controller firmware in use, we are going to use the PNP ID in order to
274 * determine the strategy and ports available. See after these generic
275 * IT8512E/F register definitions for register definitions for those
276 * strategies.
277 */
278
279 /* register offsets */
280 #define IT85_C0DR 0x00 /* data register */
281 #define IT85_C0MSTCR 0x01 /* master control register */
282 #define IT85_C0IER 0x02 /* interrupt enable register */
283 #define IT85_C0IIR 0x03 /* interrupt identification register */
284 #define IT85_C0CFR 0x04 /* carrier frequency register */
285 #define IT85_C0RCR 0x05 /* receiver control register */
286 #define IT85_C0TCR 0x06 /* transmitter control register */
287 #define IT85_C0SCK 0x07 /* slow clock control register */
288 #define IT85_C0BDLR 0x08 /* baud rate divisor low byte register */
289 #define IT85_C0BDHR 0x09 /* baud rate divisor high byte register */
290 #define IT85_C0TFSR 0x0a /* transmitter FIFO status register */
291 #define IT85_C0RFSR 0x0b /* receiver FIFO status register */
292 #define IT85_C0WCL 0x0d /* wakeup code length register */
293 #define IT85_C0WCR 0x0e /* wakeup code read/write register */
294 #define IT85_C0WPS 0x0f /* wakeup power control/status register */
295
296 #define IT85_IOREG_LENGTH 0x10 /* length of register file */
297
298 /* C0MSTCR bits */
299 #define IT85_RESET 0x01 /* reset */
300 #define IT85_FIFOCLR 0x02 /* FIFO clear bit */
301 #define IT85_FIFOTL 0x0c /* FIFO level threshold mask */
302 #define IT85_FIFOTL_DEFAULT 0x08 /* FIFO level threshold default
303 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
304 * 0x0c -> 25 */
305 #define IT85_ILE 0x10 /* internal loopback enable */
306 #define IT85_ILSEL 0x20 /* internal loopback select */
307
308 /* C0IER bits */
309 #define IT85_TLDLIE 0x01 /* TX low data level interrupt enable */
310 #define IT85_RDAIE 0x02 /* RX data available interrupt enable */
311 #define IT85_RFOIE 0x04 /* RX FIFO overrun interrupt enable */
312 #define IT85_IEC 0x80 /* interrupt enable function control */
313
314 /* C0IIR bits */
315 #define IT85_TLDLI 0x01 /* transmitter low data level interrupt */
316 #define IT85_RDAI 0x02 /* receiver data available interrupt */
317 #define IT85_RFOI 0x04 /* receiver FIFO overrun interrupt */
318 #define IT85_NIP 0x80 /* no interrupt pending */
319
320 /* C0CFR bits */
321 #define IT85_CFQ 0x1f /* carrier frequency mask */
322 #define IT85_HCFS 0x20 /* high speed carrier frequency select */
323
324 /* C0RCR bits */
325 #define IT85_RXDCR 0x07 /* receiver demodulation carrier range mask */
326 #define IT85_RXACT 0x08 /* receiver active */
327 #define IT85_RXEND 0x10 /* receiver demodulation enable */
328 #define IT85_RDWOS 0x20 /* receiver data without sync */
329 #define IT85_RXEN 0x80 /* receiver enable */
330
331 /* C0TCR bits */
332 #define IT85_TXMPW 0x07 /* transmitter modulation pulse width mask */
333 #define IT85_TXMPW_DEFAULT 0x04 /* default modulation pulse width */
334 #define IT85_TXMPM 0x18 /* transmitter modulation pulse mode mask */
335 #define IT85_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */
336 #define IT85_TXENDF 0x20 /* transmitter deferral */
337 #define IT85_TXRLE 0x40 /* transmitter run length enable */
338
339 /* C0SCK bits */
340 #define IT85_SCKS 0x01 /* slow clock select */
341 #define IT85_TXDCKG 0x02 /* TXD clock gating */
342 #define IT85_DLL1P8E 0x04 /* DLL 1.8432M enable */
343 #define IT85_DLLTE 0x08 /* DLL test enable */
344 #define IT85_BRCM 0x70 /* baud rate count mode */
345 #define IT85_DLLOCK 0x80 /* DLL lock */
346
347 /* C0TFSR bits */
348 #define IT85_TXFBC 0x3f /* transmitter FIFO count mask */
349
350 /* C0RFSR bits */
351 #define IT85_RXFBC 0x3f /* receiver FIFO count mask */
352 #define IT85_RXFTO 0x80 /* receiver FIFO time-out */
353
354 /* C0WCL bits */
355 #define IT85_WCL 0x3f /* wakeup code length mask */
356
357 /* C0WPS bits */
358 #define IT85_CIRPOSIE 0x01 /* power on/off status interrupt enable */
359 #define IT85_CIRPOIS 0x02 /* power on/off interrupt status */
360 #define IT85_CIRPOII 0x04 /* power on/off interrupt identification */
361 #define IT85_RCRST 0x10 /* wakeup code reading counter reset bit */
362 #define IT85_WCRST 0x20 /* wakeup code writing counter reset bit */
363
364 /*
365 * ITE8708
366 *
367 * Hardware data obtained from hacked driver for IT8512 in this forum post:
368 *
369 * http://ubuntuforums.org/showthread.php?t=1028640
370 *
371 * Although there's no official documentation for that driver, analysis would
372 * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
373 * selectable by a single bank-select bit that's mapped onto both banks. The
374 * IT8512 registers are mapped in a different order, so that the first bank
375 * maps the ones that are used more often, and two registers that share a
376 * reserved high-order bit are placed at the same offset in both banks in
377 * order to reuse the reserved bit as the bank select bit.
378 */
379
380 /* register offsets */
381
382 /* mapped onto both banks */
383 #define IT8708_BANKSEL 0x07 /* bank select register */
384 #define IT8708_HRAE 0x80 /* high registers access enable */
385
386 /* mapped onto the low bank */
387 #define IT8708_C0DR 0x00 /* data register */
388 #define IT8708_C0MSTCR 0x01 /* master control register */
389 #define IT8708_C0IER 0x02 /* interrupt enable register */
390 #define IT8708_C0IIR 0x03 /* interrupt identification register */
391 #define IT8708_C0RFSR 0x04 /* receiver FIFO status register */
392 #define IT8708_C0RCR 0x05 /* receiver control register */
393 #define IT8708_C0TFSR 0x06 /* transmitter FIFO status register */
394 #define IT8708_C0TCR 0x07 /* transmitter control register */
395
396 /* mapped onto the high bank */
397 #define IT8708_C0BDLR 0x01 /* baud rate divisor low byte register */
398 #define IT8708_C0BDHR 0x02 /* baud rate divisor high byte register */
399 #define IT8708_C0CFR 0x04 /* carrier frequency register */
400
401 /* registers whose bank mapping we don't know, since they weren't being used
402 * in the hacked driver... most probably they belong to the high bank too,
403 * since they fit in the holes the other registers leave */
404 #define IT8708_C0SCK 0x03 /* slow clock control register */
405 #define IT8708_C0WCL 0x05 /* wakeup code length register */
406 #define IT8708_C0WCR 0x06 /* wakeup code read/write register */
407 #define IT8708_C0WPS 0x07 /* wakeup power control/status register */
408
409 #define IT8708_IOREG_LENGTH 0x08 /* length of register file */
410
411 /* two more registers that are defined in the hacked driver, but can't be
412 * found in the data sheets; no idea what they are or how they are accessed,
413 * since the hacked driver doesn't seem to use them */
414 #define IT8708_CSCRR 0x00
415 #define IT8708_CGPINTR 0x01
416
417 /* CSCRR bits */
418 #define IT8708_CSCRR_SCRB 0x3f
419 #define IT8708_CSCRR_PM 0x80
420
421 /* CGPINTR bits */
422 #define IT8708_CGPINT 0x01
423
424 /*
425 * ITE8709
426 *
427 * Hardware interfacing data obtained from the original lirc_ite8709 driver.
428 * Verbatim from its sources:
429 *
430 * The ITE8709 device seems to be the combination of IT8512 superIO chip and
431 * a specific firmware running on the IT8512's embedded micro-controller.
432 * In addition of the embedded micro-controller, the IT8512 chip contains a
433 * CIR module and several other modules. A few modules are directly accessible
434 * by the host CPU, but most of them are only accessible by the
435 * micro-controller. The CIR module is only accessible by the
436 * micro-controller.
437 *
438 * The battery-backed SRAM module is accessible by the host CPU and the
439 * micro-controller. So one of the MC's firmware role is to act as a bridge
440 * between the host CPU and the CIR module. The firmware implements a kind of
441 * communication protocol using the SRAM module as a shared memory. The IT8512
442 * specification is publicly available on ITE's web site, but the
443 * communication protocol is not, so it was reverse-engineered.
444 */
445
446 /* register offsets */
447 #define IT8709_RAM_IDX 0x00 /* index into the SRAM module bytes */
448 #define IT8709_RAM_VAL 0x01 /* read/write data to the indexed byte */
449
450 #define IT8709_IOREG_LENGTH 0x02 /* length of register file */
451
452 /* register offsets inside the SRAM module */
453 #define IT8709_MODE 0x1a /* request/ack byte */
454 #define IT8709_REG_IDX 0x1b /* index of the CIR register to access */
455 #define IT8709_REG_VAL 0x1c /* value read/to be written */
456 #define IT8709_IIR 0x1e /* interrupt identification register */
457 #define IT8709_RFSR 0x1f /* receiver FIFO status register */
458 #define IT8709_FIFO 0x20 /* start of in RAM RX FIFO copy */
459
460 /* MODE values */
461 #define IT8709_IDLE 0x00
462 #define IT8709_WRITE 0x01
463 #define IT8709_READ 0x02