1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * include/asm-mips/i8259.h
4 *
5 * i8259A interrupt definitions.
6 *
7 * Copyright (C) 2003 Maciej W. Rozycki
8 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
9 */
10 #ifndef _ASM_I8259_H
11 #define _ASM_I8259_H
12
13 #include <linux/compiler.h>
14 #include <linux/spinlock.h>
15
16 #include <asm/io.h>
17 #include <irq.h>
18
19 /* i8259A PIC registers */
20 #define PIC_MASTER_CMD 0x20
21 #define PIC_MASTER_IMR 0x21
22 #define PIC_MASTER_ISR PIC_MASTER_CMD
23 #define PIC_MASTER_POLL PIC_MASTER_ISR
24 #define PIC_MASTER_OCW3 PIC_MASTER_ISR
25 #define PIC_SLAVE_CMD 0xa0
26 #define PIC_SLAVE_IMR 0xa1
27
28 /* i8259A PIC related value */
29 #define PIC_CASCADE_IR 2
30 #define MASTER_ICW4_DEFAULT 0x01
31 #define SLAVE_ICW4_DEFAULT 0x01
32 #define PIC_ICW4_AEOI 2
33
34 extern raw_spinlock_t i8259A_lock;
35
36 extern void make_8259A_irq(unsigned int irq);
37
38 extern void init_i8259_irqs(void);
39
40 /**
41 * i8159_set_poll() - Override the i8259 polling function
42 * @poll: pointer to platform-specific polling function
43 *
44 * Call this to override the generic i8259 polling function, which directly
45 * accesses i8259 registers, with a platform specific one which may be faster
46 * in cases where hardware provides a more optimal means of polling for an
47 * interrupt.
48 */
49 extern void i8259_set_poll(int (*poll)(void));
50
51 /*
52 * Do the traditional i8259 interrupt polling thing. This is for the few
53 * cases where no better interrupt acknowledge method is available and we
54 * absolutely must touch the i8259.
55 */
56 static inline int i8259_irq(void)
57 {
58 int irq;
59
60 raw_spin_lock(&i8259A_lock);
61
62 /* Perform an interrupt acknowledge cycle on controller 1. */
63 outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */
64 irq = inb(PIC_MASTER_CMD) & 7;
65 if (irq == PIC_CASCADE_IR) {
66 /*
67 * Interrupt is cascaded so perform interrupt
68 * acknowledge on controller 2.
69 */
70 outb(0x0C, PIC_SLAVE_CMD); /* prepare for poll */
71 irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
72 }
73
74 if (unlikely(irq == 7)) {
75 /*
76 * This may be a spurious interrupt.
77 *
78 * Read the interrupt status register (ISR). If the most
79 * significant bit is not set then there is no valid
80 * interrupt.
81 */
82 outb(0x0B, PIC_MASTER_ISR); /* ISR register */
83 if(~inb(PIC_MASTER_ISR) & 0x80)
84 irq = -1;
85 }
86
87 raw_spin_unlock(&i8259A_lock);
88
89 return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
90 }
91
92 #endif /* _ASM_I8259_H */