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6 #ifndef __RGA_HW_H__
7 #define __RGA_HW_H__
8
9 #define RGA_CMDBUF_SIZE 0x20
10
11
12 #define MAX_WIDTH 8192
13 #define MAX_HEIGHT 8192
14
15 #define MIN_WIDTH 34
16 #define MIN_HEIGHT 34
17
18 #define DEFAULT_WIDTH 100
19 #define DEFAULT_HEIGHT 100
20
21 #define RGA_TIMEOUT 500
22
23
24 #define RGA_SYS_CTRL 0x0000
25 #define RGA_CMD_CTRL 0x0004
26 #define RGA_CMD_BASE 0x0008
27 #define RGA_INT 0x0010
28 #define RGA_MMU_CTRL0 0x0014
29 #define RGA_VERSION_INFO 0x0028
30
31 #define RGA_MODE_BASE_REG 0x0100
32 #define RGA_MODE_MAX_REG 0x017C
33
34 #define RGA_MODE_CTRL 0x0100
35 #define RGA_SRC_INFO 0x0104
36 #define RGA_SRC_Y_RGB_BASE_ADDR 0x0108
37 #define RGA_SRC_CB_BASE_ADDR 0x010c
38 #define RGA_SRC_CR_BASE_ADDR 0x0110
39 #define RGA_SRC1_RGB_BASE_ADDR 0x0114
40 #define RGA_SRC_VIR_INFO 0x0118
41 #define RGA_SRC_ACT_INFO 0x011c
42 #define RGA_SRC_X_FACTOR 0x0120
43 #define RGA_SRC_Y_FACTOR 0x0124
44 #define RGA_SRC_BG_COLOR 0x0128
45 #define RGA_SRC_FG_COLOR 0x012c
46 #define RGA_SRC_TR_COLOR0 0x0130
47 #define RGA_SRC_TR_COLOR1 0x0134
48
49 #define RGA_DST_INFO 0x0138
50 #define RGA_DST_Y_RGB_BASE_ADDR 0x013c
51 #define RGA_DST_CB_BASE_ADDR 0x0140
52 #define RGA_DST_CR_BASE_ADDR 0x0144
53 #define RGA_DST_VIR_INFO 0x0148
54 #define RGA_DST_ACT_INFO 0x014c
55
56 #define RGA_ALPHA_CTRL0 0x0150
57 #define RGA_ALPHA_CTRL1 0x0154
58 #define RGA_FADING_CTRL 0x0158
59 #define RGA_PAT_CON 0x015c
60 #define RGA_ROP_CON0 0x0160
61 #define RGA_ROP_CON1 0x0164
62 #define RGA_MASK_BASE 0x0168
63
64 #define RGA_MMU_CTRL1 0x016C
65 #define RGA_MMU_SRC_BASE 0x0170
66 #define RGA_MMU_SRC1_BASE 0x0174
67 #define RGA_MMU_DST_BASE 0x0178
68
69
70 #define RGA_MODE_RENDER_BITBLT 0
71 #define RGA_MODE_RENDER_COLOR_PALETTE 1
72 #define RGA_MODE_RENDER_RECTANGLE_FILL 2
73 #define RGA_MODE_RENDER_UPDATE_PALETTE_LUT_RAM 3
74
75 #define RGA_MODE_BITBLT_MODE_SRC_TO_DST 0
76 #define RGA_MODE_BITBLT_MODE_SRC_SRC1_TO_DST 1
77
78 #define RGA_MODE_CF_ROP4_SOLID 0
79 #define RGA_MODE_CF_ROP4_PATTERN 1
80
81 #define RGA_COLOR_FMT_ABGR8888 0
82 #define RGA_COLOR_FMT_XBGR8888 1
83 #define RGA_COLOR_FMT_RGB888 2
84 #define RGA_COLOR_FMT_BGR565 4
85 #define RGA_COLOR_FMT_ABGR1555 5
86 #define RGA_COLOR_FMT_ABGR4444 6
87 #define RGA_COLOR_FMT_YUV422SP 8
88 #define RGA_COLOR_FMT_YUV422P 9
89 #define RGA_COLOR_FMT_YUV420SP 10
90 #define RGA_COLOR_FMT_YUV420P 11
91
92 #define RGA_COLOR_FMT_CP_1BPP 12
93 #define RGA_COLOR_FMT_CP_2BPP 13
94 #define RGA_COLOR_FMT_CP_4BPP 14
95 #define RGA_COLOR_FMT_CP_8BPP 15
96 #define RGA_COLOR_FMT_MASK 15
97
98 #define RGA_COLOR_NONE_SWAP 0
99 #define RGA_COLOR_RB_SWAP 1
100 #define RGA_COLOR_ALPHA_SWAP 2
101 #define RGA_COLOR_UV_SWAP 4
102
103 #define RGA_SRC_CSC_MODE_BYPASS 0
104 #define RGA_SRC_CSC_MODE_BT601_R0 1
105 #define RGA_SRC_CSC_MODE_BT601_R1 2
106 #define RGA_SRC_CSC_MODE_BT709_R0 3
107 #define RGA_SRC_CSC_MODE_BT709_R1 4
108
109 #define RGA_SRC_ROT_MODE_0_DEGREE 0
110 #define RGA_SRC_ROT_MODE_90_DEGREE 1
111 #define RGA_SRC_ROT_MODE_180_DEGREE 2
112 #define RGA_SRC_ROT_MODE_270_DEGREE 3
113
114 #define RGA_SRC_MIRR_MODE_NO 0
115 #define RGA_SRC_MIRR_MODE_X 1
116 #define RGA_SRC_MIRR_MODE_Y 2
117 #define RGA_SRC_MIRR_MODE_X_Y 3
118
119 #define RGA_SRC_HSCL_MODE_NO 0
120 #define RGA_SRC_HSCL_MODE_DOWN 1
121 #define RGA_SRC_HSCL_MODE_UP 2
122
123 #define RGA_SRC_VSCL_MODE_NO 0
124 #define RGA_SRC_VSCL_MODE_DOWN 1
125 #define RGA_SRC_VSCL_MODE_UP 2
126
127 #define RGA_SRC_TRANS_ENABLE_R 1
128 #define RGA_SRC_TRANS_ENABLE_G 2
129 #define RGA_SRC_TRANS_ENABLE_B 4
130 #define RGA_SRC_TRANS_ENABLE_A 8
131
132 #define RGA_SRC_BIC_COE_SELEC_CATROM 0
133 #define RGA_SRC_BIC_COE_SELEC_MITCHELL 1
134 #define RGA_SRC_BIC_COE_SELEC_HERMITE 2
135 #define RGA_SRC_BIC_COE_SELEC_BSPLINE 3
136
137 #define RGA_DST_DITHER_MODE_888_TO_666 0
138 #define RGA_DST_DITHER_MODE_888_TO_565 1
139 #define RGA_DST_DITHER_MODE_888_TO_555 2
140 #define RGA_DST_DITHER_MODE_888_TO_444 3
141
142 #define RGA_DST_CSC_MODE_BYPASS 0
143 #define RGA_DST_CSC_MODE_BT601_R0 1
144 #define RGA_DST_CSC_MODE_BT601_R1 2
145 #define RGA_DST_CSC_MODE_BT709_R0 3
146
147 #define RGA_ALPHA_ROP_MODE_2 0
148 #define RGA_ALPHA_ROP_MODE_3 1
149 #define RGA_ALPHA_ROP_MODE_4 2
150
151 #define RGA_ALPHA_SELECT_ALPHA 0
152 #define RGA_ALPHA_SELECT_ROP 1
153
154 #define RGA_ALPHA_MASK_BIG_ENDIAN 0
155 #define RGA_ALPHA_MASK_LITTLE_ENDIAN 1
156
157 #define RGA_ALPHA_NORMAL 0
158 #define RGA_ALPHA_REVERSE 1
159
160 #define RGA_ALPHA_BLEND_GLOBAL 0
161 #define RGA_ALPHA_BLEND_NORMAL 1
162 #define RGA_ALPHA_BLEND_MULTIPLY 2
163
164 #define RGA_ALPHA_CAL_CUT 0
165 #define RGA_ALPHA_CAL_NORMAL 1
166
167 #define RGA_ALPHA_FACTOR_ZERO 0
168 #define RGA_ALPHA_FACTOR_ONE 1
169 #define RGA_ALPHA_FACTOR_OTHER 2
170 #define RGA_ALPHA_FACTOR_OTHER_REVERSE 3
171 #define RGA_ALPHA_FACTOR_SELF 4
172
173 #define RGA_ALPHA_COLOR_NORMAL 0
174 #define RGA_ALPHA_COLOR_MULTIPLY_CAL 1
175
176
177 union rga_mode_ctrl {
178 unsigned int val;
179 struct {
180
181 unsigned int render:3;
182
183 unsigned int bitblt:1;
184 unsigned int cf_rop4_pat:1;
185 unsigned int alpha_zero_key:1;
186 unsigned int gradient_sat:1;
187
188 unsigned int reserved:25;
189 } data;
190 };
191
192 union rga_src_info {
193 unsigned int val;
194 struct {
195
196 unsigned int format:4;
197
198 unsigned int swap:3;
199 unsigned int cp_endian:1;
200
201 unsigned int csc_mode:2;
202 unsigned int rot_mode:2;
203 unsigned int mir_mode:2;
204 unsigned int hscl_mode:2;
205 unsigned int vscl_mode:2;
206
207 unsigned int trans_mode:1;
208 unsigned int trans_enable:4;
209
210 unsigned int dither_up_en:1;
211 unsigned int bic_coe_sel:2;
212
213 unsigned int reserved:6;
214 } data;
215 };
216
217 union rga_src_vir_info {
218 unsigned int val;
219 struct {
220
221 unsigned int vir_width:15;
222 unsigned int reserved:1;
223
224 unsigned int vir_stride:10;
225
226 unsigned int reserved1:6;
227 } data;
228 };
229
230 union rga_src_act_info {
231 unsigned int val;
232 struct {
233
234 unsigned int act_width:13;
235 unsigned int reserved:3;
236
237 unsigned int act_height:13;
238 unsigned int reserved1:3;
239 } data;
240 };
241
242 union rga_src_x_factor {
243 unsigned int val;
244 struct {
245
246 unsigned int down_scale_factor:16;
247
248 unsigned int up_scale_factor:16;
249 } data;
250 };
251
252 union rga_src_y_factor {
253 unsigned int val;
254 struct {
255
256 unsigned int down_scale_factor:16;
257
258 unsigned int up_scale_factor:16;
259 } data;
260 };
261
262
263 union rga_src_cp_gr_color {
264 unsigned int val;
265 struct {
266
267 unsigned int gradient_x:16;
268
269 unsigned int gradient_y:16;
270 } data;
271 };
272
273 union rga_src_transparency_color0 {
274 unsigned int val;
275 struct {
276
277 unsigned int trans_rmin:8;
278
279 unsigned int trans_gmin:8;
280
281 unsigned int trans_bmin:8;
282
283 unsigned int trans_amin:8;
284 } data;
285 };
286
287 union rga_src_transparency_color1 {
288 unsigned int val;
289 struct {
290
291 unsigned int trans_rmax:8;
292
293 unsigned int trans_gmax:8;
294
295 unsigned int trans_bmax:8;
296
297 unsigned int trans_amax:8;
298 } data;
299 };
300
301 union rga_dst_info {
302 unsigned int val;
303 struct {
304
305 unsigned int format:4;
306
307 unsigned int swap:3;
308
309 unsigned int src1_format:3;
310
311 unsigned int src1_swap:2;
312
313 unsigned int dither_up_en:1;
314 unsigned int dither_down_en:1;
315 unsigned int dither_down_mode:2;
316
317 unsigned int csc_mode:2;
318 unsigned int csc_clip:1;
319
320 unsigned int reserved:13;
321 } data;
322 };
323
324 union rga_dst_vir_info {
325 unsigned int val;
326 struct {
327
328 unsigned int vir_stride:15;
329 unsigned int reserved:1;
330
331 unsigned int src1_vir_stride:15;
332 unsigned int reserved1:1;
333 } data;
334 };
335
336 union rga_dst_act_info {
337 unsigned int val;
338 struct {
339
340 unsigned int act_width:12;
341 unsigned int reserved:4;
342
343 unsigned int act_height:12;
344 unsigned int reserved1:4;
345 } data;
346 };
347
348 union rga_alpha_ctrl0 {
349 unsigned int val;
350 struct {
351
352 unsigned int rop_en:1;
353 unsigned int rop_select:1;
354 unsigned int rop_mode:2;
355
356 unsigned int src_fading_val:8;
357
358 unsigned int dst_fading_val:8;
359 unsigned int mask_endian:1;
360
361 unsigned int reserved:11;
362 } data;
363 };
364
365 union rga_alpha_ctrl1 {
366 unsigned int val;
367 struct {
368
369 unsigned int dst_color_m0:1;
370 unsigned int src_color_m0:1;
371
372 unsigned int dst_factor_m0:3;
373 unsigned int src_factor_m0:3;
374
375 unsigned int dst_alpha_cal_m0:1;
376 unsigned int src_alpha_cal_m0:1;
377
378 unsigned int dst_blend_m0:2;
379 unsigned int src_blend_m0:2;
380
381 unsigned int dst_alpha_m0:1;
382 unsigned int src_alpha_m0:1;
383
384 unsigned int dst_factor_m1:3;
385 unsigned int src_factor_m1:3;
386
387 unsigned int dst_alpha_cal_m1:1;
388 unsigned int src_alpha_cal_m1:1;
389
390 unsigned int dst_blend_m1:2;
391 unsigned int src_blend_m1:2;
392
393 unsigned int dst_alpha_m1:1;
394 unsigned int src_alpha_m1:1;
395
396 unsigned int reserved:2;
397 } data;
398 };
399
400 union rga_fading_ctrl {
401 unsigned int val;
402 struct {
403
404 unsigned int fading_offset_r:8;
405
406 unsigned int fading_offset_g:8;
407
408 unsigned int fading_offset_b:8;
409
410 unsigned int fading_en:1;
411 unsigned int reserved:7;
412 } data;
413 };
414
415 union rga_pat_con {
416 unsigned int val;
417 struct {
418
419 unsigned int width:8;
420
421 unsigned int height:8;
422
423 unsigned int offset_x:8;
424
425 unsigned int offset_y:8;
426 } data;
427 };
428
429 #endif