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5 #ifndef _VPBE_OSD_REGS_H
6 #define _VPBE_OSD_REGS_H
7
8
9 #define VPBE_PID 0x0
10 #define VPBE_PCR 0x4
11
12
13 #define VPSSCLK_PID 0x00
14 #define VPSSCLK_CLKCTRL 0x04
15
16
17 #define VPSSBL_PID 0x00
18 #define VPSSBL_PCR 0x04
19 #define VPSSBL_BCR 0x08
20 #define VPSSBL_INTSTAT 0x0C
21 #define VPSSBL_INTSEL 0x10
22 #define VPSSBL_EVTSEL 0x14
23 #define VPSSBL_MEMCTRL 0x18
24 #define VPSSBL_CCDCMUX 0x1C
25
26
27 #define ISP5_PID 0x0
28 #define ISP5_PCCR 0x4
29 #define ISP5_BCR 0x8
30 #define ISP5_INTSTAT 0xC
31 #define ISP5_INTSEL1 0x10
32 #define ISP5_INTSEL2 0x14
33 #define ISP5_INTSEL3 0x18
34 #define ISP5_EVTSEL 0x1c
35 #define ISP5_CCDCMUX 0x20
36
37
38 #define OSD_MODE 0x00
39 #define OSD_VIDWINMD 0x04
40 #define OSD_OSDWIN0MD 0x08
41 #define OSD_OSDWIN1MD 0x0C
42 #define OSD_OSDATRMD 0x0C
43 #define OSD_RECTCUR 0x10
44 #define OSD_VIDWIN0OFST 0x18
45 #define OSD_VIDWIN1OFST 0x1C
46 #define OSD_OSDWIN0OFST 0x20
47 #define OSD_OSDWIN1OFST 0x24
48 #define OSD_VIDWINADH 0x28
49 #define OSD_VIDWIN0ADL 0x2C
50 #define OSD_VIDWIN0ADR 0x2C
51 #define OSD_VIDWIN1ADL 0x30
52 #define OSD_VIDWIN1ADR 0x30
53 #define OSD_OSDWINADH 0x34
54 #define OSD_OSDWIN0ADL 0x38
55 #define OSD_OSDWIN0ADR 0x38
56 #define OSD_OSDWIN1ADL 0x3C
57 #define OSD_OSDWIN1ADR 0x3C
58 #define OSD_BASEPX 0x40
59 #define OSD_BASEPY 0x44
60 #define OSD_VIDWIN0XP 0x48
61 #define OSD_VIDWIN0YP 0x4C
62 #define OSD_VIDWIN0XL 0x50
63 #define OSD_VIDWIN0YL 0x54
64 #define OSD_VIDWIN1XP 0x58
65 #define OSD_VIDWIN1YP 0x5C
66 #define OSD_VIDWIN1XL 0x60
67 #define OSD_VIDWIN1YL 0x64
68 #define OSD_OSDWIN0XP 0x68
69 #define OSD_OSDWIN0YP 0x6C
70 #define OSD_OSDWIN0XL 0x70
71 #define OSD_OSDWIN0YL 0x74
72 #define OSD_OSDWIN1XP 0x78
73 #define OSD_OSDWIN1YP 0x7C
74 #define OSD_OSDWIN1XL 0x80
75 #define OSD_OSDWIN1YL 0x84
76 #define OSD_CURXP 0x88
77 #define OSD_CURYP 0x8C
78 #define OSD_CURXL 0x90
79 #define OSD_CURYL 0x94
80 #define OSD_W0BMP01 0xA0
81 #define OSD_W0BMP23 0xA4
82 #define OSD_W0BMP45 0xA8
83 #define OSD_W0BMP67 0xAC
84 #define OSD_W0BMP89 0xB0
85 #define OSD_W0BMPAB 0xB4
86 #define OSD_W0BMPCD 0xB8
87 #define OSD_W0BMPEF 0xBC
88 #define OSD_W1BMP01 0xC0
89 #define OSD_W1BMP23 0xC4
90 #define OSD_W1BMP45 0xC8
91 #define OSD_W1BMP67 0xCC
92 #define OSD_W1BMP89 0xD0
93 #define OSD_W1BMPAB 0xD4
94 #define OSD_W1BMPCD 0xD8
95 #define OSD_W1BMPEF 0xDC
96 #define OSD_VBNDRY 0xE0
97 #define OSD_EXTMODE 0xE4
98 #define OSD_MISCCTL 0xE8
99 #define OSD_CLUTRAMYCB 0xEC
100 #define OSD_CLUTRAMCR 0xF0
101 #define OSD_TRANSPVAL 0xF4
102 #define OSD_TRANSPVALL 0xF4
103 #define OSD_TRANSPVALU 0xF8
104 #define OSD_TRANSPBMPIDX 0xFC
105 #define OSD_PPVWIN0ADR 0xFC
106
107
108 #define VPBE_PCR_VENC_DIV (1 << 1)
109 #define VPBE_PCR_CLK_OFF (1 << 0)
110
111 #define VPSSBL_INTSTAT_HSSIINT (1 << 14)
112 #define VPSSBL_INTSTAT_CFALDINT (1 << 13)
113 #define VPSSBL_INTSTAT_IPIPE_INT5 (1 << 12)
114 #define VPSSBL_INTSTAT_IPIPE_INT4 (1 << 11)
115 #define VPSSBL_INTSTAT_IPIPE_INT3 (1 << 10)
116 #define VPSSBL_INTSTAT_IPIPE_INT2 (1 << 9)
117 #define VPSSBL_INTSTAT_IPIPE_INT1 (1 << 8)
118 #define VPSSBL_INTSTAT_IPIPE_INT0 (1 << 7)
119 #define VPSSBL_INTSTAT_IPIPEIFINT (1 << 6)
120 #define VPSSBL_INTSTAT_OSDINT (1 << 5)
121 #define VPSSBL_INTSTAT_VENCINT (1 << 4)
122 #define VPSSBL_INTSTAT_H3AINT (1 << 3)
123 #define VPSSBL_INTSTAT_CCDC_VDINT2 (1 << 2)
124 #define VPSSBL_INTSTAT_CCDC_VDINT1 (1 << 1)
125 #define VPSSBL_INTSTAT_CCDC_VDINT0 (1 << 0)
126
127
128 #define ISP5_INTSTAT_VENCINT (1 << 21)
129 #define ISP5_INTSTAT_OSDINT (1 << 20)
130
131
132 #define SDTV_NTSC 0
133 #define SDTV_PAL 1
134
135 #define HDTV_525P 0
136 #define HDTV_625P 1
137 #define HDTV_1080I 2
138 #define HDTV_720P 3
139
140 #define OSD_MODE_CS (1 << 15)
141 #define OSD_MODE_OVRSZ (1 << 14)
142 #define OSD_MODE_OHRSZ (1 << 13)
143 #define OSD_MODE_EF (1 << 12)
144 #define OSD_MODE_VVRSZ (1 << 11)
145 #define OSD_MODE_VHRSZ (1 << 10)
146 #define OSD_MODE_FSINV (1 << 9)
147 #define OSD_MODE_BCLUT (1 << 8)
148 #define OSD_MODE_CABG_SHIFT 0
149 #define OSD_MODE_CABG (0xff << 0)
150
151 #define OSD_VIDWINMD_VFINV (1 << 15)
152 #define OSD_VIDWINMD_V1EFC (1 << 14)
153 #define OSD_VIDWINMD_VHZ1_SHIFT 12
154 #define OSD_VIDWINMD_VHZ1 (3 << 12)
155 #define OSD_VIDWINMD_VVZ1_SHIFT 10
156 #define OSD_VIDWINMD_VVZ1 (3 << 10)
157 #define OSD_VIDWINMD_VFF1 (1 << 9)
158 #define OSD_VIDWINMD_ACT1 (1 << 8)
159 #define OSD_VIDWINMD_V0EFC (1 << 6)
160 #define OSD_VIDWINMD_VHZ0_SHIFT 4
161 #define OSD_VIDWINMD_VHZ0 (3 << 4)
162 #define OSD_VIDWINMD_VVZ0_SHIFT 2
163 #define OSD_VIDWINMD_VVZ0 (3 << 2)
164 #define OSD_VIDWINMD_VFF0 (1 << 1)
165 #define OSD_VIDWINMD_ACT0 (1 << 0)
166
167 #define OSD_OSDWIN0MD_ATN0E (1 << 14)
168 #define OSD_OSDWIN0MD_RGB0E (1 << 13)
169 #define OSD_OSDWIN0MD_BMP0MD_SHIFT 13
170 #define OSD_OSDWIN0MD_BMP0MD (3 << 13)
171 #define OSD_OSDWIN0MD_CLUTS0 (1 << 12)
172 #define OSD_OSDWIN0MD_OHZ0_SHIFT 10
173 #define OSD_OSDWIN0MD_OHZ0 (3 << 10)
174 #define OSD_OSDWIN0MD_OVZ0_SHIFT 8
175 #define OSD_OSDWIN0MD_OVZ0 (3 << 8)
176 #define OSD_OSDWIN0MD_BMW0_SHIFT 6
177 #define OSD_OSDWIN0MD_BMW0 (3 << 6)
178 #define OSD_OSDWIN0MD_BLND0_SHIFT 3
179 #define OSD_OSDWIN0MD_BLND0 (7 << 3)
180 #define OSD_OSDWIN0MD_TE0 (1 << 2)
181 #define OSD_OSDWIN0MD_OFF0 (1 << 1)
182 #define OSD_OSDWIN0MD_OACT0 (1 << 0)
183
184 #define OSD_OSDWIN1MD_OASW (1 << 15)
185 #define OSD_OSDWIN1MD_ATN1E (1 << 14)
186 #define OSD_OSDWIN1MD_RGB1E (1 << 13)
187 #define OSD_OSDWIN1MD_BMP1MD_SHIFT 13
188 #define OSD_OSDWIN1MD_BMP1MD (3 << 13)
189 #define OSD_OSDWIN1MD_CLUTS1 (1 << 12)
190 #define OSD_OSDWIN1MD_OHZ1_SHIFT 10
191 #define OSD_OSDWIN1MD_OHZ1 (3 << 10)
192 #define OSD_OSDWIN1MD_OVZ1_SHIFT 8
193 #define OSD_OSDWIN1MD_OVZ1 (3 << 8)
194 #define OSD_OSDWIN1MD_BMW1_SHIFT 6
195 #define OSD_OSDWIN1MD_BMW1 (3 << 6)
196 #define OSD_OSDWIN1MD_BLND1_SHIFT 3
197 #define OSD_OSDWIN1MD_BLND1 (7 << 3)
198 #define OSD_OSDWIN1MD_TE1 (1 << 2)
199 #define OSD_OSDWIN1MD_OFF1 (1 << 1)
200 #define OSD_OSDWIN1MD_OACT1 (1 << 0)
201
202 #define OSD_OSDATRMD_OASW (1 << 15)
203 #define OSD_OSDATRMD_OHZA_SHIFT 10
204 #define OSD_OSDATRMD_OHZA (3 << 10)
205 #define OSD_OSDATRMD_OVZA_SHIFT 8
206 #define OSD_OSDATRMD_OVZA (3 << 8)
207 #define OSD_OSDATRMD_BLNKINT_SHIFT 6
208 #define OSD_OSDATRMD_BLNKINT (3 << 6)
209 #define OSD_OSDATRMD_OFFA (1 << 1)
210 #define OSD_OSDATRMD_BLNK (1 << 0)
211
212 #define OSD_RECTCUR_RCAD_SHIFT 8
213 #define OSD_RECTCUR_RCAD (0xff << 8)
214 #define OSD_RECTCUR_CLUTSR (1 << 7)
215 #define OSD_RECTCUR_RCHW_SHIFT 4
216 #define OSD_RECTCUR_RCHW (7 << 4)
217 #define OSD_RECTCUR_RCVW_SHIFT 1
218 #define OSD_RECTCUR_RCVW (7 << 1)
219 #define OSD_RECTCUR_RCACT (1 << 0)
220
221 #define OSD_VIDWIN0OFST_V0LO (0x1ff << 0)
222
223 #define OSD_VIDWIN1OFST_V1LO (0x1ff << 0)
224
225 #define OSD_OSDWIN0OFST_O0LO (0x1ff << 0)
226
227 #define OSD_OSDWIN1OFST_O1LO (0x1ff << 0)
228
229 #define OSD_WINOFST_AH_SHIFT 9
230
231 #define OSD_VIDWIN0OFST_V0AH (0xf << 9)
232 #define OSD_VIDWIN1OFST_V1AH (0xf << 9)
233 #define OSD_OSDWIN0OFST_O0AH (0xf << 9)
234 #define OSD_OSDWIN1OFST_O1AH (0xf << 9)
235
236 #define OSD_VIDWINADH_V1AH_SHIFT 8
237 #define OSD_VIDWINADH_V1AH (0x7f << 8)
238 #define OSD_VIDWINADH_V0AH_SHIFT 0
239 #define OSD_VIDWINADH_V0AH (0x7f << 0)
240
241 #define OSD_VIDWIN0ADL_V0AL (0xffff << 0)
242
243 #define OSD_VIDWIN1ADL_V1AL (0xffff << 0)
244
245 #define OSD_OSDWINADH_O1AH_SHIFT 8
246 #define OSD_OSDWINADH_O1AH (0x7f << 8)
247 #define OSD_OSDWINADH_O0AH_SHIFT 0
248 #define OSD_OSDWINADH_O0AH (0x7f << 0)
249
250 #define OSD_OSDWIN0ADL_O0AL (0xffff << 0)
251
252 #define OSD_OSDWIN1ADL_O1AL (0xffff << 0)
253
254 #define OSD_BASEPX_BPX (0x3ff << 0)
255
256 #define OSD_BASEPY_BPY (0x1ff << 0)
257
258 #define OSD_VIDWIN0XP_V0X (0x7ff << 0)
259
260 #define OSD_VIDWIN0YP_V0Y (0x7ff << 0)
261
262 #define OSD_VIDWIN0XL_V0W (0x7ff << 0)
263
264 #define OSD_VIDWIN0YL_V0H (0x7ff << 0)
265
266 #define OSD_VIDWIN1XP_V1X (0x7ff << 0)
267
268 #define OSD_VIDWIN1YP_V1Y (0x7ff << 0)
269
270 #define OSD_VIDWIN1XL_V1W (0x7ff << 0)
271
272 #define OSD_VIDWIN1YL_V1H (0x7ff << 0)
273
274 #define OSD_OSDWIN0XP_W0X (0x7ff << 0)
275
276 #define OSD_OSDWIN0YP_W0Y (0x7ff << 0)
277
278 #define OSD_OSDWIN0XL_W0W (0x7ff << 0)
279
280 #define OSD_OSDWIN0YL_W0H (0x7ff << 0)
281
282 #define OSD_OSDWIN1XP_W1X (0x7ff << 0)
283
284 #define OSD_OSDWIN1YP_W1Y (0x7ff << 0)
285
286 #define OSD_OSDWIN1XL_W1W (0x7ff << 0)
287
288 #define OSD_OSDWIN1YL_W1H (0x7ff << 0)
289
290 #define OSD_CURXP_RCSX (0x7ff << 0)
291
292 #define OSD_CURYP_RCSY (0x7ff << 0)
293
294 #define OSD_CURXL_RCSW (0x7ff << 0)
295
296 #define OSD_CURYL_RCSH (0x7ff << 0)
297
298 #define OSD_EXTMODE_EXPMDSEL (1 << 15)
299 #define OSD_EXTMODE_SCRNHEXP_SHIFT 13
300 #define OSD_EXTMODE_SCRNHEXP (3 << 13)
301 #define OSD_EXTMODE_SCRNVEXP (1 << 12)
302 #define OSD_EXTMODE_OSD1BLDCHR (1 << 11)
303 #define OSD_EXTMODE_OSD0BLDCHR (1 << 10)
304 #define OSD_EXTMODE_ATNOSD1EN (1 << 9)
305 #define OSD_EXTMODE_ATNOSD0EN (1 << 8)
306 #define OSD_EXTMODE_OSDHRSZ15 (1 << 7)
307 #define OSD_EXTMODE_VIDHRSZ15 (1 << 6)
308 #define OSD_EXTMODE_ZMFILV1HEN (1 << 5)
309 #define OSD_EXTMODE_ZMFILV1VEN (1 << 4)
310 #define OSD_EXTMODE_ZMFILV0HEN (1 << 3)
311 #define OSD_EXTMODE_ZMFILV0VEN (1 << 2)
312 #define OSD_EXTMODE_EXPFILHEN (1 << 1)
313 #define OSD_EXTMODE_EXPFILVEN (1 << 0)
314
315 #define OSD_MISCCTL_BLDSEL (1 << 15)
316 #define OSD_MISCCTL_S420D (1 << 14)
317 #define OSD_MISCCTL_BMAPT (1 << 13)
318 #define OSD_MISCCTL_DM365M (1 << 12)
319 #define OSD_MISCCTL_RGBEN (1 << 7)
320 #define OSD_MISCCTL_RGBWIN (1 << 6)
321 #define OSD_MISCCTL_DMANG (1 << 6)
322 #define OSD_MISCCTL_TMON (1 << 5)
323 #define OSD_MISCCTL_RSEL (1 << 4)
324 #define OSD_MISCCTL_CPBSY (1 << 3)
325 #define OSD_MISCCTL_PPSW (1 << 2)
326 #define OSD_MISCCTL_PPRV (1 << 1)
327
328 #define OSD_CLUTRAMYCB_Y_SHIFT 8
329 #define OSD_CLUTRAMYCB_Y (0xff << 8)
330 #define OSD_CLUTRAMYCB_CB_SHIFT 0
331 #define OSD_CLUTRAMYCB_CB (0xff << 0)
332
333 #define OSD_CLUTRAMCR_CR_SHIFT 8
334 #define OSD_CLUTRAMCR_CR (0xff << 8)
335 #define OSD_CLUTRAMCR_CADDR_SHIFT 0
336 #define OSD_CLUTRAMCR_CADDR (0xff << 0)
337
338 #define OSD_TRANSPVAL_RGBTRANS (0xffff << 0)
339
340 #define OSD_TRANSPVALL_RGBL (0xffff << 0)
341
342 #define OSD_TRANSPVALU_Y_SHIFT 8
343 #define OSD_TRANSPVALU_Y (0xff << 8)
344 #define OSD_TRANSPVALU_RGBU_SHIFT 0
345 #define OSD_TRANSPVALU_RGBU (0xff << 0)
346
347 #define OSD_TRANSPBMPIDX_BMP1_SHIFT 8
348 #define OSD_TRANSPBMPIDX_BMP1 (0xff << 8)
349 #define OSD_TRANSPBMPIDX_BMP0_SHIFT 0
350 #define OSD_TRANSPBMPIDX_BMP0 0xff
351
352 #endif