root/drivers/media/platform/davinci/dm355_ccdc_regs.h

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INCLUDED FROM


   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright (C) 2005-2009 Texas Instruments Inc
   4  */
   5 #ifndef _DM355_CCDC_REGS_H
   6 #define _DM355_CCDC_REGS_H
   7 
   8 /**************************************************************************\
   9 * Register OFFSET Definitions
  10 \**************************************************************************/
  11 #define SYNCEN                          0x00
  12 #define MODESET                         0x04
  13 #define HDWIDTH                         0x08
  14 #define VDWIDTH                         0x0c
  15 #define PPLN                            0x10
  16 #define LPFR                            0x14
  17 #define SPH                             0x18
  18 #define NPH                             0x1c
  19 #define SLV0                            0x20
  20 #define SLV1                            0x24
  21 #define NLV                             0x28
  22 #define CULH                            0x2c
  23 #define CULV                            0x30
  24 #define HSIZE                           0x34
  25 #define SDOFST                          0x38
  26 #define STADRH                          0x3c
  27 #define STADRL                          0x40
  28 #define CLAMP                           0x44
  29 #define DCSUB                           0x48
  30 #define COLPTN                          0x4c
  31 #define BLKCMP0                         0x50
  32 #define BLKCMP1                         0x54
  33 #define MEDFILT                         0x58
  34 #define RYEGAIN                         0x5c
  35 #define GRCYGAIN                        0x60
  36 #define GBGGAIN                         0x64
  37 #define BMGGAIN                         0x68
  38 #define OFFSET                          0x6c
  39 #define OUTCLIP                         0x70
  40 #define VDINT0                          0x74
  41 #define VDINT1                          0x78
  42 #define RSV0                            0x7c
  43 #define GAMMAWD                         0x80
  44 #define REC656IF                        0x84
  45 #define CCDCFG                          0x88
  46 #define FMTCFG                          0x8c
  47 #define FMTPLEN                         0x90
  48 #define FMTSPH                          0x94
  49 #define FMTLNH                          0x98
  50 #define FMTSLV                          0x9c
  51 #define FMTLNV                          0xa0
  52 #define FMTRLEN                         0xa4
  53 #define FMTHCNT                         0xa8
  54 #define FMT_ADDR_PTR_B                  0xac
  55 #define FMT_ADDR_PTR(i)                 (FMT_ADDR_PTR_B + (i * 4))
  56 #define FMTPGM_VF0                      0xcc
  57 #define FMTPGM_VF1                      0xd0
  58 #define FMTPGM_AP0                      0xd4
  59 #define FMTPGM_AP1                      0xd8
  60 #define FMTPGM_AP2                      0xdc
  61 #define FMTPGM_AP3                      0xe0
  62 #define FMTPGM_AP4                      0xe4
  63 #define FMTPGM_AP5                      0xe8
  64 #define FMTPGM_AP6                      0xec
  65 #define FMTPGM_AP7                      0xf0
  66 #define LSCCFG1                         0xf4
  67 #define LSCCFG2                         0xf8
  68 #define LSCH0                           0xfc
  69 #define LSCV0                           0x100
  70 #define LSCKH                           0x104
  71 #define LSCKV                           0x108
  72 #define LSCMEMCTL                       0x10c
  73 #define LSCMEMD                         0x110
  74 #define LSCMEMQ                         0x114
  75 #define DFCCTL                          0x118
  76 #define DFCVSAT                         0x11c
  77 #define DFCMEMCTL                       0x120
  78 #define DFCMEM0                         0x124
  79 #define DFCMEM1                         0x128
  80 #define DFCMEM2                         0x12c
  81 #define DFCMEM3                         0x130
  82 #define DFCMEM4                         0x134
  83 #define CSCCTL                          0x138
  84 #define CSCM0                           0x13c
  85 #define CSCM1                           0x140
  86 #define CSCM2                           0x144
  87 #define CSCM3                           0x148
  88 #define CSCM4                           0x14c
  89 #define CSCM5                           0x150
  90 #define CSCM6                           0x154
  91 #define CSCM7                           0x158
  92 #define DATAOFST                        0x15c
  93 #define CCDC_REG_LAST                   DATAOFST
  94 /**************************************************************
  95 *       Define for various register bit mask and shifts for CCDC
  96 *
  97 **************************************************************/
  98 #define CCDC_RAW_IP_MODE                        0
  99 #define CCDC_VDHDOUT_INPUT                      0
 100 #define CCDC_YCINSWP_RAW                        (0 << 4)
 101 #define CCDC_EXWEN_DISABLE                      0
 102 #define CCDC_DATAPOL_NORMAL                     0
 103 #define CCDC_CCDCFG_FIDMD_LATCH_VSYNC           0
 104 #define CCDC_CCDCFG_FIDMD_NO_LATCH_VSYNC        (1 << 6)
 105 #define CCDC_CCDCFG_WENLOG_AND                  0
 106 #define CCDC_CCDCFG_TRGSEL_WEN                  0
 107 #define CCDC_CCDCFG_EXTRG_DISABLE               0
 108 #define CCDC_CFA_MOSAIC                         0
 109 #define CCDC_Y8POS_SHIFT                        11
 110 
 111 #define CCDC_VDC_DFCVSAT_MASK                   0x3fff
 112 #define CCDC_DATAOFST_MASK                      0x0ff
 113 #define CCDC_DATAOFST_H_SHIFT                   0
 114 #define CCDC_DATAOFST_V_SHIFT                   8
 115 #define CCDC_GAMMAWD_CFA_MASK                   1
 116 #define CCDC_GAMMAWD_CFA_SHIFT                  5
 117 #define CCDC_GAMMAWD_INPUT_SHIFT                2
 118 #define CCDC_FID_POL_MASK                       1
 119 #define CCDC_FID_POL_SHIFT                      4
 120 #define CCDC_HD_POL_MASK                        1
 121 #define CCDC_HD_POL_SHIFT                       3
 122 #define CCDC_VD_POL_MASK                        1
 123 #define CCDC_VD_POL_SHIFT                       2
 124 #define CCDC_VD_POL_NEGATIVE                    (1 << 2)
 125 #define CCDC_FRM_FMT_MASK                       1
 126 #define CCDC_FRM_FMT_SHIFT                      7
 127 #define CCDC_DATA_SZ_MASK                       7
 128 #define CCDC_DATA_SZ_SHIFT                      8
 129 #define CCDC_VDHDOUT_MASK                       1
 130 #define CCDC_VDHDOUT_SHIFT                      0
 131 #define CCDC_EXWEN_MASK                         1
 132 #define CCDC_EXWEN_SHIFT                        5
 133 #define CCDC_INPUT_MODE_MASK                    3
 134 #define CCDC_INPUT_MODE_SHIFT                   12
 135 #define CCDC_PIX_FMT_MASK                       3
 136 #define CCDC_PIX_FMT_SHIFT                      12
 137 #define CCDC_DATAPOL_MASK                       1
 138 #define CCDC_DATAPOL_SHIFT                      6
 139 #define CCDC_WEN_ENABLE                         (1 << 1)
 140 #define CCDC_VDHDEN_ENABLE                      (1 << 16)
 141 #define CCDC_LPF_ENABLE                         (1 << 14)
 142 #define CCDC_ALAW_ENABLE                        1
 143 #define CCDC_ALAW_GAMMA_WD_MASK                 7
 144 #define CCDC_REC656IF_BT656_EN                  3
 145 
 146 #define CCDC_FMTCFG_FMTMODE_MASK                3
 147 #define CCDC_FMTCFG_FMTMODE_SHIFT               1
 148 #define CCDC_FMTCFG_LNUM_MASK                   3
 149 #define CCDC_FMTCFG_LNUM_SHIFT                  4
 150 #define CCDC_FMTCFG_ADDRINC_MASK                7
 151 #define CCDC_FMTCFG_ADDRINC_SHIFT               8
 152 
 153 #define CCDC_CCDCFG_FIDMD_SHIFT                 6
 154 #define CCDC_CCDCFG_WENLOG_SHIFT                8
 155 #define CCDC_CCDCFG_TRGSEL_SHIFT                9
 156 #define CCDC_CCDCFG_EXTRG_SHIFT                 10
 157 #define CCDC_CCDCFG_MSBINVI_SHIFT               13
 158 
 159 #define CCDC_HSIZE_FLIP_SHIFT                   12
 160 #define CCDC_HSIZE_FLIP_MASK                    1
 161 #define CCDC_HSIZE_VAL_MASK                     0xFFF
 162 #define CCDC_SDOFST_FIELD_INTERLEAVED           0x249
 163 #define CCDC_SDOFST_INTERLACE_INVERSE           0x4B6D
 164 #define CCDC_SDOFST_INTERLACE_NORMAL            0x0B6D
 165 #define CCDC_SDOFST_PROGRESSIVE_INVERSE         0x4000
 166 #define CCDC_SDOFST_PROGRESSIVE_NORMAL          0
 167 #define CCDC_START_PX_HOR_MASK                  0x7FFF
 168 #define CCDC_NUM_PX_HOR_MASK                    0x7FFF
 169 #define CCDC_START_VER_ONE_MASK                 0x7FFF
 170 #define CCDC_START_VER_TWO_MASK                 0x7FFF
 171 #define CCDC_NUM_LINES_VER                      0x7FFF
 172 
 173 #define CCDC_BLK_CLAMP_ENABLE                   (1 << 15)
 174 #define CCDC_BLK_SGAIN_MASK                     0x1F
 175 #define CCDC_BLK_ST_PXL_MASK                    0x1FFF
 176 #define CCDC_BLK_SAMPLE_LN_MASK                 3
 177 #define CCDC_BLK_SAMPLE_LN_SHIFT                13
 178 
 179 #define CCDC_NUM_LINE_CALC_MASK                 3
 180 #define CCDC_NUM_LINE_CALC_SHIFT                14
 181 
 182 #define CCDC_BLK_DC_SUB_MASK                    0x3FFF
 183 #define CCDC_BLK_COMP_MASK                      0xFF
 184 #define CCDC_BLK_COMP_GB_COMP_SHIFT             8
 185 #define CCDC_BLK_COMP_GR_COMP_SHIFT             0
 186 #define CCDC_BLK_COMP_R_COMP_SHIFT              8
 187 #define CCDC_LATCH_ON_VSYNC_DISABLE             (1 << 15)
 188 #define CCDC_LATCH_ON_VSYNC_ENABLE              (0 << 15)
 189 #define CCDC_FPC_ENABLE                         (1 << 15)
 190 #define CCDC_FPC_FPC_NUM_MASK                   0x7FFF
 191 #define CCDC_DATA_PACK_ENABLE                   (1 << 11)
 192 #define CCDC_FMT_HORZ_FMTLNH_MASK               0x1FFF
 193 #define CCDC_FMT_HORZ_FMTSPH_MASK               0x1FFF
 194 #define CCDC_FMT_HORZ_FMTSPH_SHIFT              16
 195 #define CCDC_FMT_VERT_FMTLNV_MASK               0x1FFF
 196 #define CCDC_FMT_VERT_FMTSLV_MASK               0x1FFF
 197 #define CCDC_FMT_VERT_FMTSLV_SHIFT              16
 198 #define CCDC_VP_OUT_VERT_NUM_MASK               0x3FFF
 199 #define CCDC_VP_OUT_VERT_NUM_SHIFT              17
 200 #define CCDC_VP_OUT_HORZ_NUM_MASK               0x1FFF
 201 #define CCDC_VP_OUT_HORZ_NUM_SHIFT              4
 202 #define CCDC_VP_OUT_HORZ_ST_MASK                0xF
 203 
 204 #define CCDC_CSC_COEF_INTEG_MASK                7
 205 #define CCDC_CSC_COEF_DECIMAL_MASK              0x1f
 206 #define CCDC_CSC_COEF_INTEG_SHIFT               5
 207 #define CCDC_CSCM_MSB_SHIFT                     8
 208 #define CCDC_CSC_ENABLE                         1
 209 #define CCDC_CSC_DEC_MAX                        32
 210 
 211 #define CCDC_MFILT1_SHIFT                       10
 212 #define CCDC_MFILT2_SHIFT                       8
 213 #define CCDC_MED_FILT_THRESH                    0x3FFF
 214 #define CCDC_LPF_MASK                           1
 215 #define CCDC_LPF_SHIFT                          14
 216 #define CCDC_OFFSET_MASK                        0x3FF
 217 #define CCDC_DATASFT_MASK                       7
 218 #define CCDC_DATASFT_SHIFT                      8
 219 
 220 #define CCDC_DF_ENABLE                          1
 221 
 222 #define CCDC_FMTPLEN_P0_MASK                    0xF
 223 #define CCDC_FMTPLEN_P1_MASK                    0xF
 224 #define CCDC_FMTPLEN_P2_MASK                    7
 225 #define CCDC_FMTPLEN_P3_MASK                    7
 226 #define CCDC_FMTPLEN_P0_SHIFT                   0
 227 #define CCDC_FMTPLEN_P1_SHIFT                   4
 228 #define CCDC_FMTPLEN_P2_SHIFT                   8
 229 #define CCDC_FMTPLEN_P3_SHIFT                   12
 230 
 231 #define CCDC_FMTSPH_MASK                        0x1FFF
 232 #define CCDC_FMTLNH_MASK                        0x1FFF
 233 #define CCDC_FMTSLV_MASK                        0x1FFF
 234 #define CCDC_FMTLNV_MASK                        0x7FFF
 235 #define CCDC_FMTRLEN_MASK                       0x1FFF
 236 #define CCDC_FMTHCNT_MASK                       0x1FFF
 237 
 238 #define CCDC_ADP_INIT_MASK                      0x1FFF
 239 #define CCDC_ADP_LINE_SHIFT                     13
 240 #define CCDC_ADP_LINE_MASK                      3
 241 #define CCDC_FMTPGN_APTR_MASK                   7
 242 
 243 #define CCDC_DFCCTL_GDFCEN_MASK                 1
 244 #define CCDC_DFCCTL_VDFCEN_MASK                 1
 245 #define CCDC_DFCCTL_VDFC_DISABLE                (0 << 4)
 246 #define CCDC_DFCCTL_VDFCEN_SHIFT                4
 247 #define CCDC_DFCCTL_VDFCSL_MASK                 3
 248 #define CCDC_DFCCTL_VDFCSL_SHIFT                5
 249 #define CCDC_DFCCTL_VDFCUDA_MASK                1
 250 #define CCDC_DFCCTL_VDFCUDA_SHIFT               7
 251 #define CCDC_DFCCTL_VDFLSFT_MASK                3
 252 #define CCDC_DFCCTL_VDFLSFT_SHIFT               8
 253 #define CCDC_DFCMEMCTL_DFCMARST_MASK            1
 254 #define CCDC_DFCMEMCTL_DFCMARST_SHIFT           2
 255 #define CCDC_DFCMEMCTL_DFCMWR_MASK              1
 256 #define CCDC_DFCMEMCTL_DFCMWR_SHIFT             0
 257 #define CCDC_DFCMEMCTL_INC_ADDR                 (0 << 2)
 258 
 259 #define CCDC_LSCCFG_GFTSF_MASK                  7
 260 #define CCDC_LSCCFG_GFTSF_SHIFT                 1
 261 #define CCDC_LSCCFG_GFTINV_MASK                 0xf
 262 #define CCDC_LSCCFG_GFTINV_SHIFT                4
 263 #define CCDC_LSC_GFTABLE_SEL_MASK               3
 264 #define CCDC_LSC_GFTABLE_EPEL_SHIFT             8
 265 #define CCDC_LSC_GFTABLE_OPEL_SHIFT             10
 266 #define CCDC_LSC_GFTABLE_EPOL_SHIFT             12
 267 #define CCDC_LSC_GFTABLE_OPOL_SHIFT             14
 268 #define CCDC_LSC_GFMODE_MASK                    3
 269 #define CCDC_LSC_GFMODE_SHIFT                   4
 270 #define CCDC_LSC_DISABLE                        0
 271 #define CCDC_LSC_ENABLE                         1
 272 #define CCDC_LSC_TABLE1_SLC                     0
 273 #define CCDC_LSC_TABLE2_SLC                     1
 274 #define CCDC_LSC_TABLE3_SLC                     2
 275 #define CCDC_LSC_MEMADDR_RESET                  (1 << 2)
 276 #define CCDC_LSC_MEMADDR_INCR                   (0 << 2)
 277 #define CCDC_LSC_FRAC_MASK_T1                   0xFF
 278 #define CCDC_LSC_INT_MASK                       3
 279 #define CCDC_LSC_FRAC_MASK                      0x3FFF
 280 #define CCDC_LSC_CENTRE_MASK                    0x3FFF
 281 #define CCDC_LSC_COEF_MASK                      0xff
 282 #define CCDC_LSC_COEFL_SHIFT                    0
 283 #define CCDC_LSC_COEFU_SHIFT                    8
 284 #define CCDC_GAIN_MASK                          0x7FF
 285 #define CCDC_SYNCEN_VDHDEN_MASK                 (1 << 0)
 286 #define CCDC_SYNCEN_WEN_MASK                    (1 << 1)
 287 #define CCDC_SYNCEN_WEN_SHIFT                   1
 288 
 289 /* Power on Defaults in hardware */
 290 #define MODESET_DEFAULT                         0x200
 291 #define CULH_DEFAULT                            0xFFFF
 292 #define CULV_DEFAULT                            0xFF
 293 #define GAIN_DEFAULT                            256
 294 #define OUTCLIP_DEFAULT                         0x3FFF
 295 #define LSCCFG2_DEFAULT                         0xE
 296 
 297 #endif

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