root/drivers/media/platform/s5p-mfc/regs-mfc-v8.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Register definition file for Samsung MFC V8.x Interface (FIMV) driver
   4  *
   5  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com/
   7  */
   8 
   9 #ifndef _REGS_MFC_V8_H
  10 #define _REGS_MFC_V8_H
  11 
  12 #include <linux/sizes.h>
  13 #include "regs-mfc-v7.h"
  14 
  15 /* Additional registers for v8 */
  16 #define S5P_FIMV_D_MVC_NUM_VIEWS_V8             0xf104
  17 #define S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8   0xf108
  18 #define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8      0xf144
  19 #define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8     0xf148
  20 #define S5P_FIMV_D_MV_BUFFER_SIZE_V8            0xf150
  21 
  22 #define S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8       0xf138
  23 #define S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8      0xf13c
  24 
  25 #define S5P_FIMV_D_FIRST_PLANE_DPB_V8           0xf160
  26 #define S5P_FIMV_D_SECOND_PLANE_DPB_V8          0xf260
  27 #define S5P_FIMV_D_MV_BUFFER_V8                 0xf460
  28 
  29 #define S5P_FIMV_D_NUM_MV_V8                    0xf134
  30 #define S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8       0xf154
  31 
  32 #define S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8       0xf560
  33 #define S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8       0xf564
  34 
  35 #define S5P_FIMV_D_CPB_BUFFER_ADDR_V8           0xf5b0
  36 #define S5P_FIMV_D_CPB_BUFFER_SIZE_V8           0xf5b4
  37 #define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8  0xf5bc
  38 #define S5P_FIMV_D_CPB_BUFFER_OFFSET_V8         0xf5c0
  39 #define S5P_FIMV_D_SLICE_IF_ENABLE_V8           0xf5c4
  40 #define S5P_FIMV_D_STREAM_DATA_SIZE_V8          0xf5d0
  41 
  42 /* Display information register */
  43 #define S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8       0xf600
  44 #define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8      0xf604
  45 
  46 /* Display status */
  47 #define S5P_FIMV_D_DISPLAY_STATUS_V8            0xf608
  48 
  49 #define S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8  0xf60c
  50 #define S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8 0xf610
  51 
  52 #define S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8        0xf618
  53 #define S5P_FIMV_D_DISPLAY_CROP_INFO1_V8        0xf61c
  54 #define S5P_FIMV_D_DISPLAY_CROP_INFO2_V8        0xf620
  55 #define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE_V8   0xf624
  56 
  57 /* Decoded picture information register */
  58 #define S5P_FIMV_D_DECODED_STATUS_V8            0xf644
  59 #define S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8  0xf648
  60 #define S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8 0xf64c
  61 #define S5P_FIMV_D_DECODED_THIRD_PLANE_ADDR_V8  0xf650
  62 #define S5P_FIMV_D_DECODED_FRAME_TYPE_V8        0xf654
  63 #define S5P_FIMV_D_DECODED_NAL_SIZE_V8          0xf664
  64 
  65 /* Returned value register for specific setting */
  66 #define S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8       0xf674
  67 #define S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8       0xf678
  68 #define S5P_FIMV_D_MVC_VIEW_ID_V8               0xf6d8
  69 
  70 /* SEI related information */
  71 #define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8      0xf6dc
  72 
  73 /* Encoder Registers */
  74 #define S5P_FIMV_E_FIXED_PICTURE_QP_V8          0xf794
  75 #define S5P_FIMV_E_RC_CONFIG_V8                 0xf798
  76 #define S5P_FIMV_E_RC_QP_BOUND_V8               0xf79c
  77 #define S5P_FIMV_E_RC_RPARAM_V8                 0xf7a4
  78 #define S5P_FIMV_E_MB_RC_CONFIG_V8              0xf7a8
  79 #define S5P_FIMV_E_PADDING_CTRL_V8              0xf7ac
  80 #define S5P_FIMV_E_MV_HOR_RANGE_V8              0xf7b4
  81 #define S5P_FIMV_E_MV_VER_RANGE_V8              0xf7b8
  82 
  83 #define S5P_FIMV_E_VBV_BUFFER_SIZE_V8           0xf78c
  84 #define S5P_FIMV_E_VBV_INIT_DELAY_V8            0xf790
  85 #define S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8   0xf894
  86 
  87 #define S5P_FIMV_E_ASPECT_RATIO_V8              0xfb4c
  88 #define S5P_FIMV_E_EXTENDED_SAR_V8              0xfb50
  89 #define S5P_FIMV_E_H264_OPTIONS_V8              0xfb54
  90 
  91 /* MFCv8 Context buffer sizes */
  92 #define MFC_CTX_BUF_SIZE_V8             (36 * SZ_1K)    /*  36KB */
  93 #define MFC_H264_DEC_CTX_BUF_SIZE_V8    (2 * SZ_1M)     /*  2MB */
  94 #define MFC_OTHER_DEC_CTX_BUF_SIZE_V8   (20 * SZ_1K)    /*  20KB */
  95 #define MFC_H264_ENC_CTX_BUF_SIZE_V8    (100 * SZ_1K)   /* 100KB */
  96 #define MFC_OTHER_ENC_CTX_BUF_SIZE_V8   (10 * SZ_1K)    /*  10KB */
  97 
  98 /* Buffer size defines */
  99 #define S5P_FIMV_TMV_BUFFER_SIZE_V8(w, h)       (((w) + 1) * ((h) + 1) * 8)
 100 
 101 #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(w, h)     (((w) * 704) + 2176)
 102 #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(w, h) \
 103                 (((w) * 576 + (h) * 128)  + 4128)
 104 
 105 #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(w, h) \
 106                         (((w) * 592) + 2336)
 107 #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(w, h) \
 108                         (((w) * 576) + 10512 + \
 109                         ((((((w) * 16) * ((h) * 16)) * 3) / 2) * 4))
 110 #define S5P_FIMV_ME_BUFFER_SIZE_V8(imw, imh, mbw, mbh) \
 111         ((DIV_ROUND_UP((mbw * 16), 64) *  DIV_ROUND_UP((mbh * 16), 64) * 256) \
 112          + (DIV_ROUND_UP((mbw) * (mbh), 32) * 16))
 113 
 114 /* BUffer alignment defines */
 115 #define S5P_FIMV_D_ALIGN_PLANE_SIZE_V8  64
 116 
 117 /* MFCv8 variant defines */
 118 #define MAX_FW_SIZE_V8                  (SZ_512K)       /* 512KB */
 119 #define MAX_CPB_SIZE_V8                 (3 * SZ_1M)     /* 3MB */
 120 #define MFC_VERSION_V8                  0x80
 121 #define MFC_NUM_PORTS_V8                1
 122 
 123 #endif /*_REGS_MFC_V8_H*/