drivers/media/platform/pxa

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This source file includes following definitions.
pxa_mbus_bytes_per_line
pxa_mbus_image_size
pxa_mbus_find_fmtdesc
pxa_mbus_get_fmtdesc
pxa_mbus_config_compatible
pxa_mbus_xlate_by_fourcc
pxa_mbus_build_fmts_xlate
vb2_to_pxa_buffer
pcdev_to_dev
v4l2_dev_to_pcdev
pxa_camera_dma_irq_y
pxa_camera_dma_irq_u
pxa_camera_dma_irq_v
pxa_init_dma_channel
pxa_videobuf_set_actdma
pxa_dma_start_channels
pxa_dma_stop_channels
pxa_dma_add_tail_buf
pxa_camera_start_capture
pxa_camera_stop_capture
pxa_camera_wakeup
pxa_camera_check_link_miss
pxa_camera_dma_irq
mclk_get_divisor
recalculate_fifo_timeout
pxa_camera_activate
pxa_camera_deactivate
pxa_camera_eof
pxa_camera_irq
test_platform_param
pxa_camera_setup_cicr
pxa_buffer_cleanup
pxa_buffer_init
pxac_vb2_cleanup
pxac_vb2_queue
pxac_vb2_prepare
pxac_vb2_init
pxac_vb2_queue_setup
pxac_vb2_start_streaming
pxac_vb2_stop_streaming
pxa_camera_init_videobuf2
pxa_camera_set_bus_param
pxa_camera_try_bus_param
pxa_camera_packing_supported
pxa_camera_get_formats
pxa_camera_build_formats
pxa_camera_destroy_formats
pxa_camera_check_frame
pxac_vidioc_g_register
pxac_vidioc_s_register
pxac_vidioc_enum_fmt_vid_cap
pxac_vidioc_g_fmt_vid_cap
pxac_vidioc_try_fmt_vid_cap
pxac_vidioc_s_fmt_vid_cap
pxac_vidioc_querycap
pxac_vidioc_enum_input
pxac_vidioc_g_input
pxac_vidioc_s_input
pxac_sensor_set_power
pxac_fops_camera_open
pxac_fops_camera_release
pxa_camera_sensor_bound
pxa_camera_sensor_unbind
pxa_camera_suspend
pxa_camera_resume
pxa_camera_pdata_from_dt
pxa_camera_probe
pxa_camera_remove
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * V4L2 Driver for PXA camera host
   4  *
   5  * Copyright (C) 2006, Sascha Hauer, Pengutronix
   6  * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
   7  * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr>
   8  */
   9 
  10 #include <linux/init.h>
  11 #include <linux/module.h>
  12 #include <linux/io.h>
  13 #include <linux/delay.h>
  14 #include <linux/device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/errno.h>
  18 #include <linux/fs.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/kernel.h>
  21 #include <linux/mm.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/of.h>
  24 #include <linux/of_graph.h>
  25 #include <linux/time.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/clk.h>
  28 #include <linux/sched.h>
  29 #include <linux/slab.h>
  30 #include <linux/dmaengine.h>
  31 #include <linux/dma/pxa-dma.h>
  32 
  33 #include <media/v4l2-async.h>
  34 #include <media/v4l2-clk.h>
  35 #include <media/v4l2-common.h>
  36 #include <media/v4l2-ctrls.h>
  37 #include <media/v4l2-device.h>
  38 #include <media/v4l2-event.h>
  39 #include <media/v4l2-ioctl.h>
  40 #include <media/v4l2-fwnode.h>
  41 
  42 #include <media/videobuf2-dma-sg.h>
  43 
  44 #include <linux/videodev2.h>
  45 
  46 #include <linux/platform_data/media/camera-pxa.h>
  47 
  48 #define PXA_CAM_VERSION "0.0.6"
  49 #define PXA_CAM_DRV_NAME "pxa27x-camera"
  50 
  51 #define DEFAULT_WIDTH   640
  52 #define DEFAULT_HEIGHT  480
  53 
  54 /* Camera Interface */
  55 #define CICR0           0x0000
  56 #define CICR1           0x0004
  57 #define CICR2           0x0008
  58 #define CICR3           0x000C
  59 #define CICR4           0x0010
  60 #define CISR            0x0014
  61 #define CIFR            0x0018
  62 #define CITOR           0x001C
  63 #define CIBR0           0x0028
  64 #define CIBR1           0x0030
  65 #define CIBR2           0x0038
  66 
  67 #define CICR0_DMAEN     (1UL << 31)     /* DMA request enable */
  68 #define CICR0_PAR_EN    (1 << 30)       /* Parity enable */
  69 #define CICR0_SL_CAP_EN (1 << 29)       /* Capture enable for slave mode */
  70 #define CICR0_ENB       (1 << 28)       /* Camera interface enable */
  71 #define CICR0_DIS       (1 << 27)       /* Camera interface disable */
  72 #define CICR0_SIM       (0x7 << 24)     /* Sensor interface mode mask */
  73 #define CICR0_TOM       (1 << 9)        /* Time-out mask */
  74 #define CICR0_RDAVM     (1 << 8)        /* Receive-data-available mask */
  75 #define CICR0_FEM       (1 << 7)        /* FIFO-empty mask */
  76 #define CICR0_EOLM      (1 << 6)        /* End-of-line mask */
  77 #define CICR0_PERRM     (1 << 5)        /* Parity-error mask */
  78 #define CICR0_QDM       (1 << 4)        /* Quick-disable mask */
  79 #define CICR0_CDM       (1 << 3)        /* Disable-done mask */
  80 #define CICR0_SOFM      (1 << 2)        /* Start-of-frame mask */
  81 #define CICR0_EOFM      (1 << 1)        /* End-of-frame mask */
  82 #define CICR0_FOM       (1 << 0)        /* FIFO-overrun mask */
  83 
  84 #define CICR1_TBIT      (1UL << 31)     /* Transparency bit */
  85 #define CICR1_RGBT_CONV (0x3 << 29)     /* RGBT conversion mask */
  86 #define CICR1_PPL       (0x7ff << 15)   /* Pixels per line mask */
  87 #define CICR1_RGB_CONV  (0x7 << 12)     /* RGB conversion mask */
  88 #define CICR1_RGB_F     (1 << 11)       /* RGB format */
  89 #define CICR1_YCBCR_F   (1 << 10)       /* YCbCr format */
  90 #define CICR1_RGB_BPP   (0x7 << 7)      /* RGB bis per pixel mask */
  91 #define CICR1_RAW_BPP   (0x3 << 5)      /* Raw bis per pixel mask */
  92 #define CICR1_COLOR_SP  (0x3 << 3)      /* Color space mask */
  93 #define CICR1_DW        (0x7 << 0)      /* Data width mask */
  94 
  95 #define CICR2_BLW       (0xff << 24)    /* Beginning-of-line pixel clock
  96                                            wait count mask */
  97 #define CICR2_ELW       (0xff << 16)    /* End-of-line pixel clock
  98                                            wait count mask */
  99 #define CICR2_HSW       (0x3f << 10)    /* Horizontal sync pulse width mask */
 100 #define CICR2_BFPW      (0x3f << 3)     /* Beginning-of-frame pixel clock
 101                                            wait count mask */
 102 #define CICR2_FSW       (0x7 << 0)      /* Frame stabilization
 103                                            wait count mask */
 104 
 105 #define CICR3_BFW       (0xff << 24)    /* Beginning-of-frame line clock
 106                                            wait count mask */
 107 #define CICR3_EFW       (0xff << 16)    /* End-of-frame line clock
 108                                            wait count mask */
 109 #define CICR3_VSW       (0x3f << 10)    /* Vertical sync pulse width mask */
 110 #define CICR3_BFPW      (0x3f << 3)     /* Beginning-of-frame pixel clock
 111                                            wait count mask */
 112 #define CICR3_LPF       (0x7ff << 0)    /* Lines per frame mask */
 113 
 114 #define CICR4_MCLK_DLY  (0x3 << 24)     /* MCLK Data Capture Delay mask */
 115 #define CICR4_PCLK_EN   (1 << 23)       /* Pixel clock enable */
 116 #define CICR4_PCP       (1 << 22)       /* Pixel clock polarity */
 117 #define CICR4_HSP       (1 << 21)       /* Horizontal sync polarity */
 118 #define CICR4_VSP       (1 << 20)       /* Vertical sync polarity */
 119 #define CICR4_MCLK_EN   (1 << 19)       /* MCLK enable */
 120 #define CICR4_FR_RATE   (0x7 << 8)      /* Frame rate mask */
 121 #define CICR4_DIV       (0xff << 0)     /* Clock divisor mask */
 122 
 123 #define CISR_FTO        (1 << 15)       /* FIFO time-out */
 124 #define CISR_RDAV_2     (1 << 14)       /* Channel 2 receive data available */
 125 #define CISR_RDAV_1     (1 << 13)       /* Channel 1 receive data available */
 126 #define CISR_RDAV_0     (1 << 12)       /* Channel 0 receive data available */
 127 #define CISR_FEMPTY_2   (1 << 11)       /* Channel 2 FIFO empty */
 128 #define CISR_FEMPTY_1   (1 << 10)       /* Channel 1 FIFO empty */
 129 #define CISR_FEMPTY_0   (1 << 9)        /* Channel 0 FIFO empty */
 130 #define CISR_EOL        (1 << 8)        /* End of line */
 131 #define CISR_PAR_ERR    (1 << 7)        /* Parity error */
 132 #define CISR_CQD        (1 << 6)        /* Camera interface quick disable */
 133 #define CISR_CDD        (1 << 5)        /* Camera interface disable done */
 134 #define CISR_SOF        (1 << 4)        /* Start of frame */
 135 #define CISR_EOF        (1 << 3)        /* End of frame */
 136 #define CISR_IFO_2      (1 << 2)        /* FIFO overrun for Channel 2 */
 137 #define CISR_IFO_1      (1 << 1)        /* FIFO overrun for Channel 1 */
 138 #define CISR_IFO_0      (1 << 0)        /* FIFO overrun for Channel 0 */
 139 
 140 #define CIFR_FLVL2      (0x7f << 23)    /* FIFO 2 level mask */
 141 #define CIFR_FLVL1      (0x7f << 16)    /* FIFO 1 level mask */
 142 #define CIFR_FLVL0      (0xff << 8)     /* FIFO 0 level mask */
 143 #define CIFR_THL_0      (0x3 << 4)      /* Threshold Level for Channel 0 FIFO */
 144 #define CIFR_RESET_F    (1 << 3)        /* Reset input FIFOs */
 145 #define CIFR_FEN2       (1 << 2)        /* FIFO enable for channel 2 */
 146 #define CIFR_FEN1       (1 << 1)        /* FIFO enable for channel 1 */
 147 #define CIFR_FEN0       (1 << 0)        /* FIFO enable for channel 0 */
 148 
 149 #define CICR0_SIM_MP    (0 << 24)
 150 #define CICR0_SIM_SP    (1 << 24)
 151 #define CICR0_SIM_MS    (2 << 24)
 152 #define CICR0_SIM_EP    (3 << 24)
 153 #define CICR0_SIM_ES    (4 << 24)
 154 
 155 #define CICR1_DW_VAL(x)   ((x) & CICR1_DW)          /* Data bus width */
 156 #define CICR1_PPL_VAL(x)  (((x) << 15) & CICR1_PPL) /* Pixels per line */
 157 #define CICR1_COLOR_SP_VAL(x)   (((x) << 3) & CICR1_COLOR_SP)   /* color space */
 158 #define CICR1_RGB_BPP_VAL(x)    (((x) << 7) & CICR1_RGB_BPP)    /* bpp for rgb */
 159 #define CICR1_RGBT_CONV_VAL(x)  (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
 160 
 161 #define CICR2_BLW_VAL(x)  (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
 162 #define CICR2_ELW_VAL(x)  (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
 163 #define CICR2_HSW_VAL(x)  (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
 164 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
 165 #define CICR2_FSW_VAL(x)  (((x) << 0) & CICR2_FSW)  /* Frame stabilization wait count */
 166 
 167 #define CICR3_BFW_VAL(x)  (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count  */
 168 #define CICR3_EFW_VAL(x)  (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
 169 #define CICR3_VSW_VAL(x)  (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
 170 #define CICR3_LPF_VAL(x)  (((x) << 0) & CICR3_LPF)  /* Lines per frame */
 171 
 172 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
 173                         CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
 174                         CICR0_EOFM | CICR0_FOM)
 175 
 176 #define sensor_call(cam, o, f, args...) \
 177         v4l2_subdev_call(cam->sensor, o, f, ##args)
 178 
 179 /*
 180  * Format handling
 181  */
 182 
 183 /**
 184  * enum pxa_mbus_packing - data packing types on the media-bus
 185  * @PXA_MBUS_PACKING_NONE:      no packing, bit-for-bit transfer to RAM, one
 186  *                              sample represents one pixel
 187  * @PXA_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
 188  *                              possibly incomplete byte high bits are padding
 189  * @PXA_MBUS_PACKING_EXTEND16:  sample width (e.g., 10 bits) has to be extended
 190  *                              to 16 bits
 191  */
 192 enum pxa_mbus_packing {
 193         PXA_MBUS_PACKING_NONE,
 194         PXA_MBUS_PACKING_2X8_PADHI,
 195         PXA_MBUS_PACKING_EXTEND16,
 196 };
 197 
 198 /**
 199  * enum pxa_mbus_order - sample order on the media bus
 200  * @PXA_MBUS_ORDER_LE:          least significant sample first
 201  * @PXA_MBUS_ORDER_BE:          most significant sample first
 202  */
 203 enum pxa_mbus_order {
 204         PXA_MBUS_ORDER_LE,
 205         PXA_MBUS_ORDER_BE,
 206 };
 207 
 208 /**
 209  * enum pxa_mbus_layout - planes layout in memory
 210  * @PXA_MBUS_LAYOUT_PACKED:             color components packed
 211  * @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V:      YUV components stored in 3 planes (4:2:2)
 212  * @PXA_MBUS_LAYOUT_PLANAR_2Y_C:        YUV components stored in a luma and a
 213  *                                      chroma plane (C plane is half the size
 214  *                                      of Y plane)
 215  * @PXA_MBUS_LAYOUT_PLANAR_Y_C:         YUV components stored in a luma and a
 216  *                                      chroma plane (C plane is the same size
 217  *                                      as Y plane)
 218  */
 219 enum pxa_mbus_layout {
 220         PXA_MBUS_LAYOUT_PACKED = 0,
 221         PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
 222         PXA_MBUS_LAYOUT_PLANAR_2Y_C,
 223         PXA_MBUS_LAYOUT_PLANAR_Y_C,
 224 };
 225 
 226 /**
 227  * struct pxa_mbus_pixelfmt - Data format on the media bus
 228  * @name:               Name of the format
 229  * @fourcc:             Fourcc code, that will be obtained if the data is
 230  *                      stored in memory in the following way:
 231  * @packing:            Type of sample-packing, that has to be used
 232  * @order:              Sample order when storing in memory
 233  * @layout:             Planes layout in memory
 234  * @bits_per_sample:    How many bits the bridge has to sample
 235  */
 236 struct pxa_mbus_pixelfmt {
 237         const char              *name;
 238         u32                     fourcc;
 239         enum pxa_mbus_packing   packing;
 240         enum pxa_mbus_order     order;
 241         enum pxa_mbus_layout    layout;
 242         u8                      bits_per_sample;
 243 };
 244 
 245 /**
 246  * struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
 247  * @code:       mediabus pixel-code
 248  * @fmt:        pixel format description
 249  */
 250 struct pxa_mbus_lookup {
 251         u32     code;
 252         struct pxa_mbus_pixelfmt        fmt;
 253 };
 254 
 255 static const struct pxa_mbus_lookup mbus_fmt[] = {
 256 {
 257         .code = MEDIA_BUS_FMT_YUYV8_2X8,
 258         .fmt = {
 259                 .fourcc                 = V4L2_PIX_FMT_YUYV,
 260                 .name                   = "YUYV",
 261                 .bits_per_sample        = 8,
 262                 .packing                = PXA_MBUS_PACKING_2X8_PADHI,
 263                 .order                  = PXA_MBUS_ORDER_LE,
 264                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 265         },
 266 }, {
 267         .code = MEDIA_BUS_FMT_YVYU8_2X8,
 268         .fmt = {
 269                 .fourcc                 = V4L2_PIX_FMT_YVYU,
 270                 .name                   = "YVYU",
 271                 .bits_per_sample        = 8,
 272                 .packing                = PXA_MBUS_PACKING_2X8_PADHI,
 273                 .order                  = PXA_MBUS_ORDER_LE,
 274                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 275         },
 276 }, {
 277         .code = MEDIA_BUS_FMT_UYVY8_2X8,
 278         .fmt = {
 279                 .fourcc                 = V4L2_PIX_FMT_UYVY,
 280                 .name                   = "UYVY",
 281                 .bits_per_sample        = 8,
 282                 .packing                = PXA_MBUS_PACKING_2X8_PADHI,
 283                 .order                  = PXA_MBUS_ORDER_LE,
 284                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 285         },
 286 }, {
 287         .code = MEDIA_BUS_FMT_VYUY8_2X8,
 288         .fmt = {
 289                 .fourcc                 = V4L2_PIX_FMT_VYUY,
 290                 .name                   = "VYUY",
 291                 .bits_per_sample        = 8,
 292                 .packing                = PXA_MBUS_PACKING_2X8_PADHI,
 293                 .order                  = PXA_MBUS_ORDER_LE,
 294                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 295         },
 296 }, {
 297         .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
 298         .fmt = {
 299                 .fourcc                 = V4L2_PIX_FMT_RGB555,
 300                 .name                   = "RGB555",
 301                 .bits_per_sample        = 8,
 302                 .packing                = PXA_MBUS_PACKING_2X8_PADHI,
 303                 .order                  = PXA_MBUS_ORDER_LE,
 304                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 305         },
 306 }, {
 307         .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
 308         .fmt = {
 309                 .fourcc                 = V4L2_PIX_FMT_RGB555X,
 310                 .name                   = "RGB555X",
 311                 .bits_per_sample        = 8,
 312                 .packing                = PXA_MBUS_PACKING_2X8_PADHI,
 313                 .order                  = PXA_MBUS_ORDER_BE,
 314                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 315         },
 316 }, {
 317         .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
 318         .fmt = {
 319                 .fourcc                 = V4L2_PIX_FMT_RGB565,
 320                 .name                   = "RGB565",
 321                 .bits_per_sample        = 8,
 322                 .packing                = PXA_MBUS_PACKING_2X8_PADHI,
 323                 .order                  = PXA_MBUS_ORDER_LE,
 324                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 325         },
 326 }, {
 327         .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
 328         .fmt = {
 329                 .fourcc                 = V4L2_PIX_FMT_RGB565X,
 330                 .name                   = "RGB565X",
 331                 .bits_per_sample        = 8,
 332                 .packing                = PXA_MBUS_PACKING_2X8_PADHI,
 333                 .order                  = PXA_MBUS_ORDER_BE,
 334                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 335         },
 336 }, {
 337         .code = MEDIA_BUS_FMT_SBGGR8_1X8,
 338         .fmt = {
 339                 .fourcc                 = V4L2_PIX_FMT_SBGGR8,
 340                 .name                   = "Bayer 8 BGGR",
 341                 .bits_per_sample        = 8,
 342                 .packing                = PXA_MBUS_PACKING_NONE,
 343                 .order                  = PXA_MBUS_ORDER_LE,
 344                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 345         },
 346 }, {
 347         .code = MEDIA_BUS_FMT_SGBRG8_1X8,
 348         .fmt = {
 349                 .fourcc                 = V4L2_PIX_FMT_SGBRG8,
 350                 .name                   = "Bayer 8 GBRG",
 351                 .bits_per_sample        = 8,
 352                 .packing                = PXA_MBUS_PACKING_NONE,
 353                 .order                  = PXA_MBUS_ORDER_LE,
 354                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 355         },
 356 }, {
 357         .code = MEDIA_BUS_FMT_SGRBG8_1X8,
 358         .fmt = {
 359                 .fourcc                 = V4L2_PIX_FMT_SGRBG8,
 360                 .name                   = "Bayer 8 GRBG",
 361                 .bits_per_sample        = 8,
 362                 .packing                = PXA_MBUS_PACKING_NONE,
 363                 .order                  = PXA_MBUS_ORDER_LE,
 364                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 365         },
 366 }, {
 367         .code = MEDIA_BUS_FMT_SRGGB8_1X8,
 368         .fmt = {
 369                 .fourcc                 = V4L2_PIX_FMT_SRGGB8,
 370                 .name                   = "Bayer 8 RGGB",
 371                 .bits_per_sample        = 8,
 372                 .packing                = PXA_MBUS_PACKING_NONE,
 373                 .order                  = PXA_MBUS_ORDER_LE,
 374                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 375         },
 376 }, {
 377         .code = MEDIA_BUS_FMT_SBGGR10_1X10,
 378         .fmt = {
 379                 .fourcc                 = V4L2_PIX_FMT_SBGGR10,
 380                 .name                   = "Bayer 10 BGGR",
 381                 .bits_per_sample        = 10,
 382                 .packing                = PXA_MBUS_PACKING_EXTEND16,
 383                 .order                  = PXA_MBUS_ORDER_LE,
 384                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 385         },
 386 }, {
 387         .code = MEDIA_BUS_FMT_Y8_1X8,
 388         .fmt = {
 389                 .fourcc                 = V4L2_PIX_FMT_GREY,
 390                 .name                   = "Grey",
 391                 .bits_per_sample        = 8,
 392                 .packing                = PXA_MBUS_PACKING_NONE,
 393                 .order                  = PXA_MBUS_ORDER_LE,
 394                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 395         },
 396 }, {
 397         .code = MEDIA_BUS_FMT_Y10_1X10,
 398         .fmt = {
 399                 .fourcc                 = V4L2_PIX_FMT_Y10,
 400                 .name                   = "Grey 10bit",
 401                 .bits_per_sample        = 10,
 402                 .packing                = PXA_MBUS_PACKING_EXTEND16,
 403                 .order                  = PXA_MBUS_ORDER_LE,
 404                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 405         },
 406 }, {
 407         .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
 408         .fmt = {
 409                 .fourcc                 = V4L2_PIX_FMT_SBGGR10,
 410                 .name                   = "Bayer 10 BGGR",
 411                 .bits_per_sample        = 8,
 412                 .packing                = PXA_MBUS_PACKING_2X8_PADHI,
 413                 .order                  = PXA_MBUS_ORDER_LE,
 414                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 415         },
 416 }, {
 417         .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE,
 418         .fmt = {
 419                 .fourcc                 = V4L2_PIX_FMT_SBGGR10,
 420                 .name                   = "Bayer 10 BGGR",
 421                 .bits_per_sample        = 8,
 422                 .packing                = PXA_MBUS_PACKING_2X8_PADHI,
 423                 .order                  = PXA_MBUS_ORDER_BE,
 424                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 425         },
 426 }, {
 427         .code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE,
 428         .fmt = {
 429                 .fourcc                 = V4L2_PIX_FMT_RGB444,
 430                 .name                   = "RGB444",
 431                 .bits_per_sample        = 8,
 432                 .packing                = PXA_MBUS_PACKING_2X8_PADHI,
 433                 .order                  = PXA_MBUS_ORDER_BE,
 434                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 435         },
 436 }, {
 437         .code = MEDIA_BUS_FMT_UYVY8_1X16,
 438         .fmt = {
 439                 .fourcc                 = V4L2_PIX_FMT_UYVY,
 440                 .name                   = "UYVY 16bit",
 441                 .bits_per_sample        = 16,
 442                 .packing                = PXA_MBUS_PACKING_EXTEND16,
 443                 .order                  = PXA_MBUS_ORDER_LE,
 444                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 445         },
 446 }, {
 447         .code = MEDIA_BUS_FMT_VYUY8_1X16,
 448         .fmt = {
 449                 .fourcc                 = V4L2_PIX_FMT_VYUY,
 450                 .name                   = "VYUY 16bit",
 451                 .bits_per_sample        = 16,
 452                 .packing                = PXA_MBUS_PACKING_EXTEND16,
 453                 .order                  = PXA_MBUS_ORDER_LE,
 454                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 455         },
 456 }, {
 457         .code = MEDIA_BUS_FMT_YUYV8_1X16,
 458         .fmt = {
 459                 .fourcc                 = V4L2_PIX_FMT_YUYV,
 460                 .name                   = "YUYV 16bit",
 461                 .bits_per_sample        = 16,
 462                 .packing                = PXA_MBUS_PACKING_EXTEND16,
 463                 .order                  = PXA_MBUS_ORDER_LE,
 464                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 465         },
 466 }, {
 467         .code = MEDIA_BUS_FMT_YVYU8_1X16,
 468         .fmt = {
 469                 .fourcc                 = V4L2_PIX_FMT_YVYU,
 470                 .name                   = "YVYU 16bit",
 471                 .bits_per_sample        = 16,
 472                 .packing                = PXA_MBUS_PACKING_EXTEND16,
 473                 .order                  = PXA_MBUS_ORDER_LE,
 474                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 475         },
 476 }, {
 477         .code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
 478         .fmt = {
 479                 .fourcc                 = V4L2_PIX_FMT_SGRBG10DPCM8,
 480                 .name                   = "Bayer 10 BGGR DPCM 8",
 481                 .bits_per_sample        = 8,
 482                 .packing                = PXA_MBUS_PACKING_NONE,
 483                 .order                  = PXA_MBUS_ORDER_LE,
 484                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 485         },
 486 }, {
 487         .code = MEDIA_BUS_FMT_SGBRG10_1X10,
 488         .fmt = {
 489                 .fourcc                 = V4L2_PIX_FMT_SGBRG10,
 490                 .name                   = "Bayer 10 GBRG",
 491                 .bits_per_sample        = 10,
 492                 .packing                = PXA_MBUS_PACKING_EXTEND16,
 493                 .order                  = PXA_MBUS_ORDER_LE,
 494                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 495         },
 496 }, {
 497         .code = MEDIA_BUS_FMT_SGRBG10_1X10,
 498         .fmt = {
 499                 .fourcc                 = V4L2_PIX_FMT_SGRBG10,
 500                 .name                   = "Bayer 10 GRBG",
 501                 .bits_per_sample        = 10,
 502                 .packing                = PXA_MBUS_PACKING_EXTEND16,
 503                 .order                  = PXA_MBUS_ORDER_LE,
 504                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 505         },
 506 }, {
 507         .code = MEDIA_BUS_FMT_SRGGB10_1X10,
 508         .fmt = {
 509                 .fourcc                 = V4L2_PIX_FMT_SRGGB10,
 510                 .name                   = "Bayer 10 RGGB",
 511                 .bits_per_sample        = 10,
 512                 .packing                = PXA_MBUS_PACKING_EXTEND16,
 513                 .order                  = PXA_MBUS_ORDER_LE,
 514                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 515         },
 516 }, {
 517         .code = MEDIA_BUS_FMT_SBGGR12_1X12,
 518         .fmt = {
 519                 .fourcc                 = V4L2_PIX_FMT_SBGGR12,
 520                 .name                   = "Bayer 12 BGGR",
 521                 .bits_per_sample        = 12,
 522                 .packing                = PXA_MBUS_PACKING_EXTEND16,
 523                 .order                  = PXA_MBUS_ORDER_LE,
 524                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 525         },
 526 }, {
 527         .code = MEDIA_BUS_FMT_SGBRG12_1X12,
 528         .fmt = {
 529                 .fourcc                 = V4L2_PIX_FMT_SGBRG12,
 530                 .name                   = "Bayer 12 GBRG",
 531                 .bits_per_sample        = 12,
 532                 .packing                = PXA_MBUS_PACKING_EXTEND16,
 533                 .order                  = PXA_MBUS_ORDER_LE,
 534                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 535         },
 536 }, {
 537         .code = MEDIA_BUS_FMT_SGRBG12_1X12,
 538         .fmt = {
 539                 .fourcc                 = V4L2_PIX_FMT_SGRBG12,
 540                 .name                   = "Bayer 12 GRBG",
 541                 .bits_per_sample        = 12,
 542                 .packing                = PXA_MBUS_PACKING_EXTEND16,
 543                 .order                  = PXA_MBUS_ORDER_LE,
 544                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 545         },
 546 }, {
 547         .code = MEDIA_BUS_FMT_SRGGB12_1X12,
 548         .fmt = {
 549                 .fourcc                 = V4L2_PIX_FMT_SRGGB12,
 550                 .name                   = "Bayer 12 RGGB",
 551                 .bits_per_sample        = 12,
 552                 .packing                = PXA_MBUS_PACKING_EXTEND16,
 553                 .order                  = PXA_MBUS_ORDER_LE,
 554                 .layout                 = PXA_MBUS_LAYOUT_PACKED,
 555         },
 556 },
 557 };
 558 
 559 static s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf)
 560 {
 561         if (mf->layout != PXA_MBUS_LAYOUT_PACKED)
 562                 return width * mf->bits_per_sample / 8;
 563 
 564         switch (mf->packing) {
 565         case PXA_MBUS_PACKING_NONE:
 566                 return width * mf->bits_per_sample / 8;
 567         case PXA_MBUS_PACKING_2X8_PADHI:
 568         case PXA_MBUS_PACKING_EXTEND16:
 569                 return width * 2;
 570         }
 571         return -EINVAL;
 572 }
 573 
 574 static s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf,
 575                         u32 bytes_per_line, u32 height)
 576 {
 577         if (mf->layout == PXA_MBUS_LAYOUT_PACKED)
 578                 return bytes_per_line * height;
 579 
 580         switch (mf->packing) {
 581         case PXA_MBUS_PACKING_2X8_PADHI:
 582                 return bytes_per_line * height * 2;
 583         default:
 584                 return -EINVAL;
 585         }
 586 }
 587 
 588 static const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc(
 589         u32 code,
 590         const struct pxa_mbus_lookup *lookup,
 591         int n)
 592 {
 593         int i;
 594 
 595         for (i = 0; i < n; i++)
 596                 if (lookup[i].code == code)
 597                         return &lookup[i].fmt;
 598 
 599         return NULL;
 600 }
 601 
 602 static const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc(
 603         u32 code)
 604 {
 605         return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
 606 }
 607 
 608 static unsigned int pxa_mbus_config_compatible(const struct v4l2_mbus_config *cfg,
 609                                         unsigned int flags)
 610 {
 611         unsigned long common_flags;
 612         bool hsync = true, vsync = true, pclk, data, mode;
 613         bool mipi_lanes, mipi_clock;
 614 
 615         common_flags = cfg->flags & flags;
 616 
 617         switch (cfg->type) {
 618         case V4L2_MBUS_PARALLEL:
 619                 hsync = common_flags & (V4L2_MBUS_HSYNC_ACTIVE_HIGH |
 620                                         V4L2_MBUS_HSYNC_ACTIVE_LOW);
 621                 vsync = common_flags & (V4L2_MBUS_VSYNC_ACTIVE_HIGH |
 622                                         V4L2_MBUS_VSYNC_ACTIVE_LOW);
 623                 /* fall through */
 624         case V4L2_MBUS_BT656:
 625                 pclk = common_flags & (V4L2_MBUS_PCLK_SAMPLE_RISING |
 626                                        V4L2_MBUS_PCLK_SAMPLE_FALLING);
 627                 data = common_flags & (V4L2_MBUS_DATA_ACTIVE_HIGH |
 628                                        V4L2_MBUS_DATA_ACTIVE_LOW);
 629                 mode = common_flags & (V4L2_MBUS_MASTER | V4L2_MBUS_SLAVE);
 630                 return (!hsync || !vsync || !pclk || !data || !mode) ?
 631                         0 : common_flags;
 632         case V4L2_MBUS_CSI2_DPHY:
 633                 mipi_lanes = common_flags & V4L2_MBUS_CSI2_LANES;
 634                 mipi_clock = common_flags & (V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK |
 635                                              V4L2_MBUS_CSI2_CONTINUOUS_CLOCK);
 636                 return (!mipi_lanes || !mipi_clock) ? 0 : common_flags;
 637         default:
 638                 WARN_ON(1);
 639                 return -EINVAL;
 640         }
 641         return 0;
 642 }
 643 
 644 /**
 645  * struct pxa_camera_format_xlate - match between host and sensor formats
 646  * @code: code of a sensor provided format
 647  * @host_fmt: host format after host translation from code
 648  *
 649  * Host and sensor translation structure. Used in table of host and sensor
 650  * formats matchings in pxa_camera_device. A host can override the generic list
 651  * generation by implementing get_formats(), and use it for format checks and
 652  * format setup.
 653  */
 654 struct pxa_camera_format_xlate {
 655         u32 code;
 656         const struct pxa_mbus_pixelfmt *host_fmt;
 657 };
 658 
 659 /*
 660  * Structures
 661  */
 662 enum pxa_camera_active_dma {
 663         DMA_Y = 0x1,
 664         DMA_U = 0x2,
 665         DMA_V = 0x4,
 666 };
 667 
 668 /* buffer for one video frame */
 669 struct pxa_buffer {
 670         /* common v4l buffer stuff -- must be first */
 671         struct vb2_v4l2_buffer          vbuf;
 672         struct list_head                queue;
 673         u32     code;
 674         int                             nb_planes;
 675         /* our descriptor lists for Y, U and V channels */
 676         struct dma_async_tx_descriptor  *descs[3];
 677         dma_cookie_t                    cookie[3];
 678         struct scatterlist              *sg[3];
 679         int                             sg_len[3];
 680         size_t                          plane_sizes[3];
 681         int                             inwork;
 682         enum pxa_camera_active_dma      active_dma;
 683 };
 684 
 685 struct pxa_camera_dev {
 686         struct v4l2_device      v4l2_dev;
 687         struct video_device     vdev;
 688         struct v4l2_async_notifier notifier;
 689         struct vb2_queue        vb2_vq;
 690         struct v4l2_subdev      *sensor;
 691         struct pxa_camera_format_xlate *user_formats;
 692         const struct pxa_camera_format_xlate *current_fmt;
 693         struct v4l2_pix_format  current_pix;
 694 
 695         struct v4l2_async_subdev asd;
 696 
 697         /*
 698          * PXA27x is only supposed to handle one camera on its Quick Capture
 699          * interface. If anyone ever builds hardware to enable more than
 700          * one camera, they will have to modify this driver too
 701          */
 702         struct clk              *clk;
 703 
 704         unsigned int            irq;
 705         void __iomem            *base;
 706 
 707         int                     channels;
 708         struct dma_chan         *dma_chans[3];
 709 
 710         struct pxacamera_platform_data *pdata;
 711         struct resource         *res;
 712         unsigned long           platform_flags;
 713         unsigned long           ciclk;
 714         unsigned long           mclk;
 715         u32                     mclk_divisor;
 716         struct v4l2_clk         *mclk_clk;
 717         u16                     width_flags;    /* max 10 bits */
 718 
 719         struct list_head        capture;
 720 
 721         spinlock_t              lock;
 722         struct mutex            mlock;
 723         unsigned int            buf_sequence;
 724 
 725         struct pxa_buffer       *active;
 726         struct tasklet_struct   task_eof;
 727 
 728         u32                     save_cicr[5];
 729 };
 730 
 731 struct pxa_cam {
 732         unsigned long flags;
 733 };
 734 
 735 static const char *pxa_cam_driver_description = "PXA_Camera";
 736 
 737 /*
 738  * Format translation functions
 739  */
 740 static const struct pxa_camera_format_xlate
 741 *pxa_mbus_xlate_by_fourcc(struct pxa_camera_format_xlate *user_formats,
 742                           unsigned int fourcc)
 743 {
 744         unsigned int i;
 745 
 746         for (i = 0; user_formats[i].code; i++)
 747                 if (user_formats[i].host_fmt->fourcc == fourcc)
 748                         return user_formats + i;
 749         return NULL;
 750 }
 751 
 752 static struct pxa_camera_format_xlate *pxa_mbus_build_fmts_xlate(
 753         struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev,
 754         int (*get_formats)(struct v4l2_device *, unsigned int,
 755                            struct pxa_camera_format_xlate *xlate))
 756 {
 757         unsigned int i, fmts = 0, raw_fmts = 0;
 758         int ret;
 759         struct v4l2_subdev_mbus_code_enum code = {
 760                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
 761         };
 762         struct pxa_camera_format_xlate *user_formats;
 763 
 764         while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
 765                 raw_fmts++;
 766                 code.index++;
 767         }
 768 
 769         /*
 770          * First pass - only count formats this host-sensor
 771          * configuration can provide
 772          */
 773         for (i = 0; i < raw_fmts; i++) {
 774                 ret = get_formats(v4l2_dev, i, NULL);
 775                 if (ret < 0)
 776                         return ERR_PTR(ret);
 777                 fmts += ret;
 778         }
 779 
 780         if (!fmts)
 781                 return ERR_PTR(-ENXIO);
 782 
 783         user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL);
 784         if (!user_formats)
 785                 return ERR_PTR(-ENOMEM);
 786 
 787         /* Second pass - actually fill data formats */
 788         fmts = 0;
 789         for (i = 0; i < raw_fmts; i++) {
 790                 ret = get_formats(v4l2_dev, i, user_formats + fmts);
 791                 if (ret < 0)
 792                         goto egfmt;
 793                 fmts += ret;
 794         }
 795         user_formats[fmts].code = 0;
 796 
 797         return user_formats;
 798 egfmt:
 799         kfree(user_formats);
 800         return ERR_PTR(ret);
 801 }
 802 
 803 /*
 804  *  Videobuf operations
 805  */
 806 static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
 807 {
 808         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 809 
 810         return container_of(vbuf, struct pxa_buffer, vbuf);
 811 }
 812 
 813 static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
 814 {
 815         return pcdev->v4l2_dev.dev;
 816 }
 817 
 818 static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
 819 {
 820         return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev);
 821 }
 822 
 823 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
 824                                enum pxa_camera_active_dma act_dma);
 825 
 826 static void pxa_camera_dma_irq_y(void *data)
 827 {
 828         struct pxa_camera_dev *pcdev = data;
 829 
 830         pxa_camera_dma_irq(pcdev, DMA_Y);
 831 }
 832 
 833 static void pxa_camera_dma_irq_u(void *data)
 834 {
 835         struct pxa_camera_dev *pcdev = data;
 836 
 837         pxa_camera_dma_irq(pcdev, DMA_U);
 838 }
 839 
 840 static void pxa_camera_dma_irq_v(void *data)
 841 {
 842         struct pxa_camera_dev *pcdev = data;
 843 
 844         pxa_camera_dma_irq(pcdev, DMA_V);
 845 }
 846 
 847 /**
 848  * pxa_init_dma_channel - init dma descriptors
 849  * @pcdev: pxa camera device
 850  * @buf: pxa camera buffer
 851  * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
 852  * @sg: dma scatter list
 853  * @sglen: dma scatter list length
 854  *
 855  * Prepares the pxa dma descriptors to transfer one camera channel.
 856  *
 857  * Returns 0 if success or -ENOMEM if no memory is available
 858  */
 859 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
 860                                 struct pxa_buffer *buf, int channel,
 861                                 struct scatterlist *sg, int sglen)
 862 {
 863         struct dma_chan *dma_chan = pcdev->dma_chans[channel];
 864         struct dma_async_tx_descriptor *tx;
 865 
 866         tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
 867                                      DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
 868         if (!tx) {
 869                 dev_err(pcdev_to_dev(pcdev),
 870                         "dmaengine_prep_slave_sg failed\n");
 871                 goto fail;
 872         }
 873 
 874         tx->callback_param = pcdev;
 875         switch (channel) {
 876         case 0:
 877                 tx->callback = pxa_camera_dma_irq_y;
 878                 break;
 879         case 1:
 880                 tx->callback = pxa_camera_dma_irq_u;
 881                 break;
 882         case 2:
 883                 tx->callback = pxa_camera_dma_irq_v;
 884                 break;
 885         }
 886 
 887         buf->descs[channel] = tx;
 888         return 0;
 889 fail:
 890         dev_dbg(pcdev_to_dev(pcdev),
 891                 "%s (vb=%p) dma_tx=%p\n",
 892                 __func__, buf, tx);
 893 
 894         return -ENOMEM;
 895 }
 896 
 897 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
 898                                     struct pxa_buffer *buf)
 899 {
 900         buf->active_dma = DMA_Y;
 901         if (buf->nb_planes == 3)
 902                 buf->active_dma |= DMA_U | DMA_V;
 903 }
 904 
 905 /**
 906  * pxa_dma_start_channels - start DMA channel for active buffer
 907  * @pcdev: pxa camera device
 908  *
 909  * Initialize DMA channels to the beginning of the active video buffer, and
 910  * start these channels.
 911  */
 912 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
 913 {
 914         int i;
 915 
 916         for (i = 0; i < pcdev->channels; i++) {
 917                 dev_dbg(pcdev_to_dev(pcdev),
 918                         "%s (channel=%d)\n", __func__, i);
 919                 dma_async_issue_pending(pcdev->dma_chans[i]);
 920         }
 921 }
 922 
 923 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
 924 {
 925         int i;
 926 
 927         for (i = 0; i < pcdev->channels; i++) {
 928                 dev_dbg(pcdev_to_dev(pcdev),
 929                         "%s (channel=%d)\n", __func__, i);
 930                 dmaengine_terminate_all(pcdev->dma_chans[i]);
 931         }
 932 }
 933 
 934 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
 935                                  struct pxa_buffer *buf)
 936 {
 937         int i;
 938 
 939         for (i = 0; i < pcdev->channels; i++) {
 940                 buf->cookie[i] = dmaengine_submit(buf->descs[i]);
 941                 dev_dbg(pcdev_to_dev(pcdev),
 942                         "%s (channel=%d) : submit vb=%p cookie=%d\n",
 943                         __func__, i, buf, buf->descs[i]->cookie);
 944         }
 945 }
 946 
 947 /**
 948  * pxa_camera_start_capture - start video capturing
 949  * @pcdev: camera device
 950  *
 951  * Launch capturing. DMA channels should not be active yet. They should get
 952  * activated at the end of frame interrupt, to capture only whole frames, and
 953  * never begin the capture of a partial frame.
 954  */
 955 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
 956 {
 957         unsigned long cicr0;
 958 
 959         dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
 960         __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
 961         /* Enable End-Of-Frame Interrupt */
 962         cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
 963         cicr0 &= ~CICR0_EOFM;
 964         __raw_writel(cicr0, pcdev->base + CICR0);
 965 }
 966 
 967 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
 968 {
 969         unsigned long cicr0;
 970 
 971         pxa_dma_stop_channels(pcdev);
 972 
 973         cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
 974         __raw_writel(cicr0, pcdev->base + CICR0);
 975 
 976         pcdev->active = NULL;
 977         dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
 978 }
 979 
 980 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
 981                               struct pxa_buffer *buf,
 982                               enum vb2_buffer_state state)
 983 {
 984         struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
 985         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 986 
 987         /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
 988         list_del_init(&buf->queue);
 989         vb->timestamp = ktime_get_ns();
 990         vbuf->sequence = pcdev->buf_sequence++;
 991         vbuf->field = V4L2_FIELD_NONE;
 992         vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
 993         dev_dbg(pcdev_to_dev(pcdev), "%s dequeued buffer (buf=0x%p)\n",
 994                 __func__, buf);
 995 
 996         if (list_empty(&pcdev->capture)) {
 997                 pxa_camera_stop_capture(pcdev);
 998                 return;
 999         }
1000 
1001         pcdev->active = list_entry(pcdev->capture.next,
1002                                    struct pxa_buffer, queue);
1003 }
1004 
1005 /**
1006  * pxa_camera_check_link_miss - check missed DMA linking
1007  * @pcdev: camera device
1008  * @last_submitted: an opaque DMA cookie for last submitted
1009  * @last_issued: an opaque DMA cookie for last issued
1010  *
1011  * The DMA chaining is done with DMA running. This means a tiny temporal window
1012  * remains, where a buffer is queued on the chain, while the chain is already
1013  * stopped. This means the tailed buffer would never be transferred by DMA.
1014  * This function restarts the capture for this corner case, where :
1015  *  - DADR() == DADDR_STOP
1016  *  - a videobuffer is queued on the pcdev->capture list
1017  *
1018  * Please check the "DMA hot chaining timeslice issue" in
1019  *   Documentation/media/v4l-drivers/pxa_camera.rst
1020  *
1021  * Context: should only be called within the dma irq handler
1022  */
1023 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
1024                                        dma_cookie_t last_submitted,
1025                                        dma_cookie_t last_issued)
1026 {
1027         bool is_dma_stopped = last_submitted != last_issued;
1028 
1029         dev_dbg(pcdev_to_dev(pcdev),
1030                 "%s : top queued buffer=%p, is_dma_stopped=%d\n",
1031                 __func__, pcdev->active, is_dma_stopped);
1032 
1033         if (pcdev->active && is_dma_stopped)
1034                 pxa_camera_start_capture(pcdev);
1035 }
1036 
1037 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
1038                                enum pxa_camera_active_dma act_dma)
1039 {
1040         struct pxa_buffer *buf, *last_buf;
1041         unsigned long flags;
1042         u32 camera_status, overrun;
1043         int chan;
1044         enum dma_status last_status;
1045         dma_cookie_t last_issued;
1046 
1047         spin_lock_irqsave(&pcdev->lock, flags);
1048 
1049         camera_status = __raw_readl(pcdev->base + CISR);
1050         dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
1051                 camera_status, act_dma);
1052         overrun = CISR_IFO_0;
1053         if (pcdev->channels == 3)
1054                 overrun |= CISR_IFO_1 | CISR_IFO_2;
1055 
1056         /*
1057          * pcdev->active should not be NULL in DMA irq handler.
1058          *
1059          * But there is one corner case : if capture was stopped due to an
1060          * overrun of channel 1, and at that same channel 2 was completed.
1061          *
1062          * When handling the overrun in DMA irq for channel 1, we'll stop the
1063          * capture and restart it (and thus set pcdev->active to NULL). But the
1064          * DMA irq handler will already be pending for channel 2. So on entering
1065          * the DMA irq handler for channel 2 there will be no active buffer, yet
1066          * that is normal.
1067          */
1068         if (!pcdev->active)
1069                 goto out;
1070 
1071         buf = pcdev->active;
1072         WARN_ON(buf->inwork || list_empty(&buf->queue));
1073 
1074         /*
1075          * It's normal if the last frame creates an overrun, as there
1076          * are no more DMA descriptors to fetch from QCI fifos
1077          */
1078         switch (act_dma) {
1079         case DMA_U:
1080                 chan = 1;
1081                 break;
1082         case DMA_V:
1083                 chan = 2;
1084                 break;
1085         default:
1086                 chan = 0;
1087                 break;
1088         }
1089         last_buf = list_entry(pcdev->capture.prev,
1090                               struct pxa_buffer, queue);
1091         last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
1092                                                last_buf->cookie[chan],
1093                                                NULL, &last_issued);
1094         if (camera_status & overrun &&
1095             last_status != DMA_COMPLETE) {
1096                 dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
1097                         camera_status);
1098                 pxa_camera_stop_capture(pcdev);
1099                 list_for_each_entry(buf, &pcdev->capture, queue)
1100                         pxa_dma_add_tail_buf(pcdev, buf);
1101                 pxa_camera_start_capture(pcdev);
1102                 goto out;
1103         }
1104         buf->active_dma &= ~act_dma;
1105         if (!buf->active_dma) {
1106                 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE);
1107                 pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
1108                                            last_issued);
1109         }
1110 
1111 out:
1112         spin_unlock_irqrestore(&pcdev->lock, flags);
1113 }
1114 
1115 static u32 mclk_get_divisor(struct platform_device *pdev,
1116                             struct pxa_camera_dev *pcdev)
1117 {
1118         unsigned long mclk = pcdev->mclk;
1119         u32 div;
1120         unsigned long lcdclk;
1121 
1122         lcdclk = clk_get_rate(pcdev->clk);
1123         pcdev->ciclk = lcdclk;
1124 
1125         /* mclk <= ciclk / 4 (27.4.2) */
1126         if (mclk > lcdclk / 4) {
1127                 mclk = lcdclk / 4;
1128                 dev_warn(&pdev->dev,
1129                          "Limiting master clock to %lu\n", mclk);
1130         }
1131 
1132         /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
1133         div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
1134 
1135         /* If we're not supplying MCLK, leave it at 0 */
1136         if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1137                 pcdev->mclk = lcdclk / (2 * (div + 1));
1138 
1139         dev_dbg(&pdev->dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
1140                 lcdclk, mclk, div);
1141 
1142         return div;
1143 }
1144 
1145 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
1146                                      unsigned long pclk)
1147 {
1148         /* We want a timeout > 1 pixel time, not ">=" */
1149         u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
1150 
1151         __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
1152 }
1153 
1154 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
1155 {
1156         u32 cicr4 = 0;
1157 
1158         /* disable all interrupts */
1159         __raw_writel(0x3ff, pcdev->base + CICR0);
1160 
1161         if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1162                 cicr4 |= CICR4_PCLK_EN;
1163         if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1164                 cicr4 |= CICR4_MCLK_EN;
1165         if (pcdev->platform_flags & PXA_CAMERA_PCP)
1166                 cicr4 |= CICR4_PCP;
1167         if (pcdev->platform_flags & PXA_CAMERA_HSP)
1168                 cicr4 |= CICR4_HSP;
1169         if (pcdev->platform_flags & PXA_CAMERA_VSP)
1170                 cicr4 |= CICR4_VSP;
1171 
1172         __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
1173 
1174         if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1175                 /* Initialise the timeout under the assumption pclk = mclk */
1176                 recalculate_fifo_timeout(pcdev, pcdev->mclk);
1177         else
1178                 /* "Safe default" - 13MHz */
1179                 recalculate_fifo_timeout(pcdev, 13000000);
1180 
1181         clk_prepare_enable(pcdev->clk);
1182 }
1183 
1184 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
1185 {
1186         clk_disable_unprepare(pcdev->clk);
1187 }
1188 
1189 static void pxa_camera_eof(unsigned long arg)
1190 {
1191         struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg;
1192         unsigned long cifr;
1193         struct pxa_buffer *buf;
1194 
1195         dev_dbg(pcdev_to_dev(pcdev),
1196                 "Camera interrupt status 0x%x\n",
1197                 __raw_readl(pcdev->base + CISR));
1198 
1199         /* Reset the FIFOs */
1200         cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1201         __raw_writel(cifr, pcdev->base + CIFR);
1202 
1203         pcdev->active = list_first_entry(&pcdev->capture,
1204                                          struct pxa_buffer, queue);
1205         buf = pcdev->active;
1206         pxa_videobuf_set_actdma(pcdev, buf);
1207 
1208         pxa_dma_start_channels(pcdev);
1209 }
1210 
1211 static irqreturn_t pxa_camera_irq(int irq, void *data)
1212 {
1213         struct pxa_camera_dev *pcdev = data;
1214         unsigned long status, cicr0;
1215 
1216         status = __raw_readl(pcdev->base + CISR);
1217         dev_dbg(pcdev_to_dev(pcdev),
1218                 "Camera interrupt status 0x%lx\n", status);
1219 
1220         if (!status)
1221                 return IRQ_NONE;
1222 
1223         __raw_writel(status, pcdev->base + CISR);
1224 
1225         if (status & CISR_EOF) {
1226                 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
1227                 __raw_writel(cicr0, pcdev->base + CICR0);
1228                 tasklet_schedule(&pcdev->task_eof);
1229         }
1230 
1231         return IRQ_HANDLED;
1232 }
1233 
1234 static int test_platform_param(struct pxa_camera_dev *pcdev,
1235                                unsigned char buswidth, unsigned long *flags)
1236 {
1237         /*
1238          * Platform specified synchronization and pixel clock polarities are
1239          * only a recommendation and are only used during probing. The PXA270
1240          * quick capture interface supports both.
1241          */
1242         *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1243                   V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
1244                 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1245                 V4L2_MBUS_HSYNC_ACTIVE_LOW |
1246                 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1247                 V4L2_MBUS_VSYNC_ACTIVE_LOW |
1248                 V4L2_MBUS_DATA_ACTIVE_HIGH |
1249                 V4L2_MBUS_PCLK_SAMPLE_RISING |
1250                 V4L2_MBUS_PCLK_SAMPLE_FALLING;
1251 
1252         /* If requested data width is supported by the platform, use it */
1253         if ((1 << (buswidth - 1)) & pcdev->width_flags)
1254                 return 0;
1255 
1256         return -EINVAL;
1257 }
1258 
1259 static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
1260                                   unsigned long flags, __u32 pixfmt)
1261 {
1262         unsigned long dw, bpp;
1263         u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1264         int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
1265 
1266         if (ret < 0)
1267                 y_skip_top = 0;
1268 
1269         /*
1270          * Datawidth is now guaranteed to be equal to one of the three values.
1271          * We fix bit-per-pixel equal to data-width...
1272          */
1273         switch (pcdev->current_fmt->host_fmt->bits_per_sample) {
1274         case 10:
1275                 dw = 4;
1276                 bpp = 0x40;
1277                 break;
1278         case 9:
1279                 dw = 3;
1280                 bpp = 0x20;
1281                 break;
1282         default:
1283                 /*
1284                  * Actually it can only be 8 now,
1285                  * default is just to silence compiler warnings
1286                  */
1287         case 8:
1288                 dw = 2;
1289                 bpp = 0;
1290         }
1291 
1292         if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1293                 cicr4 |= CICR4_PCLK_EN;
1294         if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1295                 cicr4 |= CICR4_MCLK_EN;
1296         if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1297                 cicr4 |= CICR4_PCP;
1298         if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1299                 cicr4 |= CICR4_HSP;
1300         if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1301                 cicr4 |= CICR4_VSP;
1302 
1303         cicr0 = __raw_readl(pcdev->base + CICR0);
1304         if (cicr0 & CICR0_ENB)
1305                 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1306 
1307         cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw;
1308 
1309         switch (pixfmt) {
1310         case V4L2_PIX_FMT_YUV422P:
1311                 pcdev->channels = 3;
1312                 cicr1 |= CICR1_YCBCR_F;
1313                 /*
1314                  * Normally, pxa bus wants as input UYVY format. We allow all
1315                  * reorderings of the YUV422 format, as no processing is done,
1316                  * and the YUV stream is just passed through without any
1317                  * transformation. Note that UYVY is the only format that
1318                  * should be used if pxa framebuffer Overlay2 is used.
1319                  */
1320                 /* fall through */
1321         case V4L2_PIX_FMT_UYVY:
1322         case V4L2_PIX_FMT_VYUY:
1323         case V4L2_PIX_FMT_YUYV:
1324         case V4L2_PIX_FMT_YVYU:
1325                 cicr1 |= CICR1_COLOR_SP_VAL(2);
1326                 break;
1327         case V4L2_PIX_FMT_RGB555:
1328                 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1329                         CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1330                 break;
1331         case V4L2_PIX_FMT_RGB565:
1332                 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1333                 break;
1334         }
1335 
1336         cicr2 = 0;
1337         cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) |
1338                 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1339         cicr4 |= pcdev->mclk_divisor;
1340 
1341         __raw_writel(cicr1, pcdev->base + CICR1);
1342         __raw_writel(cicr2, pcdev->base + CICR2);
1343         __raw_writel(cicr3, pcdev->base + CICR3);
1344         __raw_writel(cicr4, pcdev->base + CICR4);
1345 
1346         /* CIF interrupts are not used, only DMA */
1347         cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1348                 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1349         cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1350         __raw_writel(cicr0, pcdev->base + CICR0);
1351 }
1352 
1353 /*
1354  * Videobuf2 section
1355  */
1356 static void pxa_buffer_cleanup(struct pxa_buffer *buf)
1357 {
1358         int i;
1359 
1360         for (i = 0; i < 3 && buf->descs[i]; i++) {
1361                 dmaengine_desc_free(buf->descs[i]);
1362                 kfree(buf->sg[i]);
1363                 buf->descs[i] = NULL;
1364                 buf->sg[i] = NULL;
1365                 buf->sg_len[i] = 0;
1366                 buf->plane_sizes[i] = 0;
1367         }
1368         buf->nb_planes = 0;
1369 }
1370 
1371 static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
1372                            struct pxa_buffer *buf)
1373 {
1374         struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
1375         struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
1376         int nb_channels = pcdev->channels;
1377         int i, ret = 0;
1378         unsigned long size = vb2_plane_size(vb, 0);
1379 
1380         switch (nb_channels) {
1381         case 1:
1382                 buf->plane_sizes[0] = size;
1383                 break;
1384         case 3:
1385                 buf->plane_sizes[0] = size / 2;
1386                 buf->plane_sizes[1] = size / 4;
1387                 buf->plane_sizes[2] = size / 4;
1388                 break;
1389         default:
1390                 return -EINVAL;
1391         }
1392         buf->nb_planes = nb_channels;
1393 
1394         ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
1395                        buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
1396         if (ret < 0) {
1397                 dev_err(pcdev_to_dev(pcdev),
1398                         "sg_split failed: %d\n", ret);
1399                 return ret;
1400         }
1401         for (i = 0; i < nb_channels; i++) {
1402                 ret = pxa_init_dma_channel(pcdev, buf, i,
1403                                            buf->sg[i], buf->sg_len[i]);
1404                 if (ret) {
1405                         pxa_buffer_cleanup(buf);
1406                         return ret;
1407                 }
1408         }
1409         INIT_LIST_HEAD(&buf->queue);
1410 
1411         return ret;
1412 }
1413 
1414 static void pxac_vb2_cleanup(struct vb2_buffer *vb)
1415 {
1416         struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1417         struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1418 
1419         dev_dbg(pcdev_to_dev(pcdev),
1420                  "%s(vb=%p)\n", __func__, vb);
1421         pxa_buffer_cleanup(buf);
1422 }
1423 
1424 static void pxac_vb2_queue(struct vb2_buffer *vb)
1425 {
1426         struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1427         struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1428 
1429         dev_dbg(pcdev_to_dev(pcdev),
1430                  "%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
1431                 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
1432                 pcdev->active);
1433 
1434         list_add_tail(&buf->queue, &pcdev->capture);
1435 
1436         pxa_dma_add_tail_buf(pcdev, buf);
1437 }
1438 
1439 /*
1440  * Please check the DMA prepared buffer structure in :
1441  *   Documentation/media/v4l-drivers/pxa_camera.rst
1442  * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
1443  * modification while DMA chain is running will work anyway.
1444  */
1445 static int pxac_vb2_prepare(struct vb2_buffer *vb)
1446 {
1447         struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1448         struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1449         int ret = 0;
1450 
1451         switch (pcdev->channels) {
1452         case 1:
1453         case 3:
1454                 vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage);
1455                 break;
1456         default:
1457                 return -EINVAL;
1458         }
1459 
1460         dev_dbg(pcdev_to_dev(pcdev),
1461                  "%s (vb=%p) nb_channels=%d size=%lu\n",
1462                 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));
1463 
1464         WARN_ON(!pcdev->current_fmt);
1465 
1466 #ifdef DEBUG
1467         /*
1468          * This can be useful if you want to see if we actually fill
1469          * the buffer with something
1470          */
1471         for (i = 0; i < vb->num_planes; i++)
1472                 memset((void *)vb2_plane_vaddr(vb, i),
1473                        0xaa, vb2_get_plane_payload(vb, i));
1474 #endif
1475 
1476         /*
1477          * I think, in buf_prepare you only have to protect global data,
1478          * the actual buffer is yours
1479          */
1480         buf->inwork = 0;
1481         pxa_videobuf_set_actdma(pcdev, buf);
1482 
1483         return ret;
1484 }
1485 
1486 static int pxac_vb2_init(struct vb2_buffer *vb)
1487 {
1488         struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1489         struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1490 
1491         dev_dbg(pcdev_to_dev(pcdev),
1492                  "%s(nb_channels=%d)\n",
1493                 __func__, pcdev->channels);
1494 
1495         return pxa_buffer_init(pcdev, buf);
1496 }
1497 
1498 static int pxac_vb2_queue_setup(struct vb2_queue *vq,
1499                                 unsigned int *nbufs,
1500                                 unsigned int *num_planes, unsigned int sizes[],
1501                                 struct device *alloc_devs[])
1502 {
1503         struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1504         int size = pcdev->current_pix.sizeimage;
1505 
1506         dev_dbg(pcdev_to_dev(pcdev),
1507                  "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
1508                 __func__, vq, *nbufs, *num_planes, size);
1509         /*
1510          * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
1511          * format, even if there are 3 planes Y, U and V, we reply there is only
1512          * one plane, containing Y, U and V data, one after the other.
1513          */
1514         if (*num_planes)
1515                 return sizes[0] < size ? -EINVAL : 0;
1516 
1517         *num_planes = 1;
1518         switch (pcdev->channels) {
1519         case 1:
1520         case 3:
1521                 sizes[0] = size;
1522                 break;
1523         default:
1524                 return -EINVAL;
1525         }
1526 
1527         if (!*nbufs)
1528                 *nbufs = 1;
1529 
1530         return 0;
1531 }
1532 
1533 static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
1534 {
1535         struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1536 
1537         dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
1538                 __func__, count, pcdev->active);
1539 
1540         pcdev->buf_sequence = 0;
1541         if (!pcdev->active)
1542                 pxa_camera_start_capture(pcdev);
1543 
1544         return 0;
1545 }
1546 
1547 static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
1548 {
1549         struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1550         struct pxa_buffer *buf, *tmp;
1551 
1552         dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n",
1553                 __func__, pcdev->active);
1554         pxa_camera_stop_capture(pcdev);
1555 
1556         list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue)
1557                 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR);
1558 }
1559 
1560 static const struct vb2_ops pxac_vb2_ops = {
1561         .queue_setup            = pxac_vb2_queue_setup,
1562         .buf_init               = pxac_vb2_init,
1563         .buf_prepare            = pxac_vb2_prepare,
1564         .buf_queue              = pxac_vb2_queue,
1565         .buf_cleanup            = pxac_vb2_cleanup,
1566         .start_streaming        = pxac_vb2_start_streaming,
1567         .stop_streaming         = pxac_vb2_stop_streaming,
1568         .wait_prepare           = vb2_ops_wait_prepare,
1569         .wait_finish            = vb2_ops_wait_finish,
1570 };
1571 
1572 static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev)
1573 {
1574         int ret;
1575         struct vb2_queue *vq = &pcdev->vb2_vq;
1576 
1577         memset(vq, 0, sizeof(*vq));
1578         vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1579         vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1580         vq->drv_priv = pcdev;
1581         vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1582         vq->buf_struct_size = sizeof(struct pxa_buffer);
1583         vq->dev = pcdev->v4l2_dev.dev;
1584 
1585         vq->ops = &pxac_vb2_ops;
1586         vq->mem_ops = &vb2_dma_sg_memops;
1587         vq->lock = &pcdev->mlock;
1588 
1589         ret = vb2_queue_init(vq);
1590         dev_dbg(pcdev_to_dev(pcdev),
1591                  "vb2_queue_init(vq=%p): %d\n", vq, ret);
1592 
1593         return ret;
1594 }
1595 
1596 /*
1597  * Video ioctls section
1598  */
1599 static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev)
1600 {
1601         struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1602         u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc;
1603         unsigned long bus_flags, common_flags;
1604         int ret;
1605 
1606         ret = test_platform_param(pcdev,
1607                                   pcdev->current_fmt->host_fmt->bits_per_sample,
1608                                   &bus_flags);
1609         if (ret < 0)
1610                 return ret;
1611 
1612         ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1613         if (!ret) {
1614                 common_flags = pxa_mbus_config_compatible(&cfg,
1615                                                           bus_flags);
1616                 if (!common_flags) {
1617                         dev_warn(pcdev_to_dev(pcdev),
1618                                  "Flags incompatible: camera 0x%x, host 0x%lx\n",
1619                                  cfg.flags, bus_flags);
1620                         return -EINVAL;
1621                 }
1622         } else if (ret != -ENOIOCTLCMD) {
1623                 return ret;
1624         } else {
1625                 common_flags = bus_flags;
1626         }
1627 
1628         pcdev->channels = 1;
1629 
1630         /* Make choices, based on platform preferences */
1631         if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1632             (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1633                 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1634                         common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1635                 else
1636                         common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1637         }
1638 
1639         if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1640             (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1641                 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1642                         common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1643                 else
1644                         common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1645         }
1646 
1647         if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1648             (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1649                 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1650                         common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1651                 else
1652                         common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1653         }
1654 
1655         cfg.flags = common_flags;
1656         ret = sensor_call(pcdev, video, s_mbus_config, &cfg);
1657         if (ret < 0 && ret != -ENOIOCTLCMD) {
1658                 dev_dbg(pcdev_to_dev(pcdev),
1659                         "camera s_mbus_config(0x%lx) returned %d\n",
1660                         common_flags, ret);
1661                 return ret;
1662         }
1663 
1664         pxa_camera_setup_cicr(pcdev, common_flags, pixfmt);
1665 
1666         return 0;
1667 }
1668 
1669 static int pxa_camera_try_bus_param(struct pxa_camera_dev *pcdev,
1670                                     unsigned char buswidth)
1671 {
1672         struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1673         unsigned long bus_flags, common_flags;
1674         int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1675 
1676         if (ret < 0)
1677                 return ret;
1678 
1679         ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1680         if (!ret) {
1681                 common_flags = pxa_mbus_config_compatible(&cfg,
1682                                                           bus_flags);
1683                 if (!common_flags) {
1684                         dev_warn(pcdev_to_dev(pcdev),
1685                                  "Flags incompatible: camera 0x%x, host 0x%lx\n",
1686                                  cfg.flags, bus_flags);
1687                         return -EINVAL;
1688                 }
1689         } else if (ret == -ENOIOCTLCMD) {
1690                 ret = 0;
1691         }
1692 
1693         return ret;
1694 }
1695 
1696 static const struct pxa_mbus_pixelfmt pxa_camera_formats[] = {
1697         {
1698                 .fourcc                 = V4L2_PIX_FMT_YUV422P,
1699                 .name                   = "Planar YUV422 16 bit",
1700                 .bits_per_sample        = 8,
1701                 .packing                = PXA_MBUS_PACKING_2X8_PADHI,
1702                 .order                  = PXA_MBUS_ORDER_LE,
1703                 .layout                 = PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
1704         },
1705 };
1706 
1707 /* This will be corrected as we get more formats */
1708 static bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt)
1709 {
1710         return  fmt->packing == PXA_MBUS_PACKING_NONE ||
1711                 (fmt->bits_per_sample == 8 &&
1712                  fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) ||
1713                 (fmt->bits_per_sample > 8 &&
1714                  fmt->packing == PXA_MBUS_PACKING_EXTEND16);
1715 }
1716 
1717 static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
1718                                   unsigned int idx,
1719                                   struct pxa_camera_format_xlate *xlate)
1720 {
1721         struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
1722         int formats = 0, ret;
1723         struct v4l2_subdev_mbus_code_enum code = {
1724                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1725                 .index = idx,
1726         };
1727         const struct pxa_mbus_pixelfmt *fmt;
1728 
1729         ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
1730         if (ret < 0)
1731                 /* No more formats */
1732                 return 0;
1733 
1734         fmt = pxa_mbus_get_fmtdesc(code.code);
1735         if (!fmt) {
1736                 dev_err(pcdev_to_dev(pcdev),
1737                         "Invalid format code #%u: %d\n", idx, code.code);
1738                 return 0;
1739         }
1740 
1741         /* This also checks support for the requested bits-per-sample */
1742         ret = pxa_camera_try_bus_param(pcdev, fmt->bits_per_sample);
1743         if (ret < 0)
1744                 return 0;
1745 
1746         switch (code.code) {
1747         case MEDIA_BUS_FMT_UYVY8_2X8:
1748                 formats++;
1749                 if (xlate) {
1750                         xlate->host_fmt = &pxa_camera_formats[0];
1751                         xlate->code     = code.code;
1752                         xlate++;
1753                         dev_dbg(pcdev_to_dev(pcdev),
1754                                 "Providing format %s using code %d\n",
1755                                 pxa_camera_formats[0].name, code.code);
1756                 }
1757         /* fall through */
1758         case MEDIA_BUS_FMT_VYUY8_2X8:
1759         case MEDIA_BUS_FMT_YUYV8_2X8:
1760         case MEDIA_BUS_FMT_YVYU8_2X8:
1761         case MEDIA_BUS_FMT_RGB565_2X8_LE:
1762         case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1763                 if (xlate)
1764                         dev_dbg(pcdev_to_dev(pcdev),
1765                                 "Providing format %s packed\n",
1766                                 fmt->name);
1767                 break;
1768         default:
1769                 if (!pxa_camera_packing_supported(fmt))
1770                         return 0;
1771                 if (xlate)
1772                         dev_dbg(pcdev_to_dev(pcdev),
1773                                 "Providing format %s in pass-through mode\n",
1774                                 fmt->name);
1775                 break;
1776         }
1777 
1778         /* Generic pass-through */
1779         formats++;
1780         if (xlate) {
1781                 xlate->host_fmt = fmt;
1782                 xlate->code     = code.code;
1783                 xlate++;
1784         }
1785 
1786         return formats;
1787 }
1788 
1789 static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev)
1790 {
1791         struct pxa_camera_format_xlate *xlate;
1792 
1793         xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor,
1794                                           pxa_camera_get_formats);
1795         if (IS_ERR(xlate))
1796                 return PTR_ERR(xlate);
1797 
1798         pcdev->user_formats = xlate;
1799         return 0;
1800 }
1801 
1802 static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev)
1803 {
1804         kfree(pcdev->user_formats);
1805 }
1806 
1807 static int pxa_camera_check_frame(u32 width, u32 height)
1808 {
1809         /* limit to pxa hardware capabilities */
1810         return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1811                 (width & 0x01);
1812 }
1813 
1814 #ifdef CONFIG_VIDEO_ADV_DEBUG
1815 static int pxac_vidioc_g_register(struct file *file, void *priv,
1816                                   struct v4l2_dbg_register *reg)
1817 {
1818         struct pxa_camera_dev *pcdev = video_drvdata(file);
1819 
1820         if (reg->reg > CIBR2)
1821                 return -ERANGE;
1822 
1823         reg->val = __raw_readl(pcdev->base + reg->reg);
1824         reg->size = sizeof(__u32);
1825         return 0;
1826 }
1827 
1828 static int pxac_vidioc_s_register(struct file *file, void *priv,
1829                                   const struct v4l2_dbg_register *reg)
1830 {
1831         struct pxa_camera_dev *pcdev = video_drvdata(file);
1832 
1833         if (reg->reg > CIBR2)
1834                 return -ERANGE;
1835         if (reg->size != sizeof(__u32))
1836                 return -EINVAL;
1837         __raw_writel(reg->val, pcdev->base + reg->reg);
1838         return 0;
1839 }
1840 #endif
1841 
1842 static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void  *priv,
1843                                         struct v4l2_fmtdesc *f)
1844 {
1845         struct pxa_camera_dev *pcdev = video_drvdata(filp);
1846         const struct pxa_mbus_pixelfmt *format;
1847         unsigned int idx;
1848 
1849         for (idx = 0; pcdev->user_formats[idx].code; idx++);
1850         if (f->index >= idx)
1851                 return -EINVAL;
1852 
1853         format = pcdev->user_formats[f->index].host_fmt;
1854         f->pixelformat = format->fourcc;
1855         return 0;
1856 }
1857 
1858 static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1859                                     struct v4l2_format *f)
1860 {
1861         struct pxa_camera_dev *pcdev = video_drvdata(filp);
1862         struct v4l2_pix_format *pix = &f->fmt.pix;
1863 
1864         pix->width              = pcdev->current_pix.width;
1865         pix->height             = pcdev->current_pix.height;
1866         pix->bytesperline       = pcdev->current_pix.bytesperline;
1867         pix->sizeimage          = pcdev->current_pix.sizeimage;
1868         pix->field              = pcdev->current_pix.field;
1869         pix->pixelformat        = pcdev->current_fmt->host_fmt->fourcc;
1870         pix->colorspace         = pcdev->current_pix.colorspace;
1871         dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n",
1872                 pcdev->current_fmt->host_fmt->fourcc);
1873         return 0;
1874 }
1875 
1876 static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1877                                       struct v4l2_format *f)
1878 {
1879         struct pxa_camera_dev *pcdev = video_drvdata(filp);
1880         const struct pxa_camera_format_xlate *xlate;
1881         struct v4l2_pix_format *pix = &f->fmt.pix;
1882         struct v4l2_subdev_pad_config pad_cfg;
1883         struct v4l2_subdev_format format = {
1884                 .which = V4L2_SUBDEV_FORMAT_TRY,
1885         };
1886         struct v4l2_mbus_framefmt *mf = &format.format;
1887         __u32 pixfmt = pix->pixelformat;
1888         int ret;
1889 
1890         xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt);
1891         if (!xlate) {
1892                 dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
1893                 return -EINVAL;
1894         }
1895 
1896         /*
1897          * Limit to pxa hardware capabilities.  YUV422P planar format requires
1898          * images size to be a multiple of 16 bytes.  If not, zeros will be
1899          * inserted between Y and U planes, and U and V planes, which violates
1900          * the YUV422P standard.
1901          */
1902         v4l_bound_align_image(&pix->width, 48, 2048, 1,
1903                               &pix->height, 32, 2048, 0,
1904                               pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1905 
1906         v4l2_fill_mbus_format(mf, pix, xlate->code);
1907         ret = sensor_call(pcdev, pad, set_fmt, &pad_cfg, &format);
1908         if (ret < 0)
1909                 return ret;
1910 
1911         v4l2_fill_pix_format(pix, mf);
1912 
1913         /* Only progressive video supported so far */
1914         switch (mf->field) {
1915         case V4L2_FIELD_ANY:
1916         case V4L2_FIELD_NONE:
1917                 pix->field = V4L2_FIELD_NONE;
1918                 break;
1919         default:
1920                 /* TODO: support interlaced at least in pass-through mode */
1921                 dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
1922                         mf->field);
1923                 return -EINVAL;
1924         }
1925 
1926         ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt);
1927         if (ret < 0)
1928                 return ret;
1929 
1930         pix->bytesperline = ret;
1931         ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline,
1932                                   pix->height);
1933         if (ret < 0)
1934                 return ret;
1935 
1936         pix->sizeimage = ret;
1937         return 0;
1938 }
1939 
1940 static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1941                                     struct v4l2_format *f)
1942 {
1943         struct pxa_camera_dev *pcdev = video_drvdata(filp);
1944         const struct pxa_camera_format_xlate *xlate;
1945         struct v4l2_pix_format *pix = &f->fmt.pix;
1946         struct v4l2_subdev_format format = {
1947                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1948         };
1949         unsigned long flags;
1950         int ret, is_busy;
1951 
1952         dev_dbg(pcdev_to_dev(pcdev),
1953                 "s_fmt_vid_cap(pix=%dx%d:%x)\n",
1954                 pix->width, pix->height, pix->pixelformat);
1955 
1956         spin_lock_irqsave(&pcdev->lock, flags);
1957         is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq);
1958         spin_unlock_irqrestore(&pcdev->lock, flags);
1959 
1960         if (is_busy)
1961                 return -EBUSY;
1962 
1963         ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f);
1964         if (ret)
1965                 return ret;
1966 
1967         xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats,
1968                                          pix->pixelformat);
1969         v4l2_fill_mbus_format(&format.format, pix, xlate->code);
1970         ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
1971         if (ret < 0) {
1972                 dev_warn(pcdev_to_dev(pcdev),
1973                          "Failed to configure for format %x\n",
1974                          pix->pixelformat);
1975         } else if (pxa_camera_check_frame(pix->width, pix->height)) {
1976                 dev_warn(pcdev_to_dev(pcdev),
1977                          "Camera driver produced an unsupported frame %dx%d\n",
1978                          pix->width, pix->height);
1979                 return -EINVAL;
1980         }
1981 
1982         pcdev->current_fmt = xlate;
1983         pcdev->current_pix = *pix;
1984 
1985         ret = pxa_camera_set_bus_param(pcdev);
1986         return ret;
1987 }
1988 
1989 static int pxac_vidioc_querycap(struct file *file, void *priv,
1990                                 struct v4l2_capability *cap)
1991 {
1992         strscpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info));
1993         strscpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver));
1994         strscpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1995         return 0;
1996 }
1997 
1998 static int pxac_vidioc_enum_input(struct file *file, void *priv,
1999                                   struct v4l2_input *i)
2000 {
2001         if (i->index > 0)
2002                 return -EINVAL;
2003 
2004         i->type = V4L2_INPUT_TYPE_CAMERA;
2005         strscpy(i->name, "Camera", sizeof(i->name));
2006 
2007         return 0;
2008 }
2009 
2010 static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
2011 {
2012         *i = 0;
2013 
2014         return 0;
2015 }
2016 
2017 static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i)
2018 {
2019         if (i > 0)
2020                 return -EINVAL;
2021 
2022         return 0;
2023 }
2024 
2025 static int pxac_sensor_set_power(struct pxa_camera_dev *pcdev, int on)
2026 {
2027         int ret;
2028 
2029         ret = sensor_call(pcdev, core, s_power, on);
2030         if (ret == -ENOIOCTLCMD)
2031                 ret = 0;
2032         if (ret) {
2033                 dev_warn(pcdev_to_dev(pcdev),
2034                          "Failed to put subdevice in %s mode: %d\n",
2035                          on ? "normal operation" : "power saving", ret);
2036         }
2037 
2038         return ret;
2039 }
2040 
2041 static int pxac_fops_camera_open(struct file *filp)
2042 {
2043         struct pxa_camera_dev *pcdev = video_drvdata(filp);
2044         int ret;
2045 
2046         mutex_lock(&pcdev->mlock);
2047         ret = v4l2_fh_open(filp);
2048         if (ret < 0)
2049                 goto out;
2050 
2051         if (!v4l2_fh_is_singular_file(filp))
2052                 goto out;
2053 
2054         ret = pxac_sensor_set_power(pcdev, 1);
2055         if (ret)
2056                 v4l2_fh_release(filp);
2057 out:
2058         mutex_unlock(&pcdev->mlock);
2059         return ret;
2060 }
2061 
2062 static int pxac_fops_camera_release(struct file *filp)
2063 {
2064         struct pxa_camera_dev *pcdev = video_drvdata(filp);
2065         int ret;
2066         bool fh_singular;
2067 
2068         mutex_lock(&pcdev->mlock);
2069 
2070         fh_singular = v4l2_fh_is_singular_file(filp);
2071 
2072         ret = _vb2_fop_release(filp, NULL);
2073 
2074         if (fh_singular)
2075                 ret = pxac_sensor_set_power(pcdev, 0);
2076 
2077         mutex_unlock(&pcdev->mlock);
2078 
2079         return ret;
2080 }
2081 
2082 static const struct v4l2_file_operations pxa_camera_fops = {
2083         .owner          = THIS_MODULE,
2084         .open           = pxac_fops_camera_open,
2085         .release        = pxac_fops_camera_release,
2086         .read           = vb2_fop_read,
2087         .poll           = vb2_fop_poll,
2088         .mmap           = vb2_fop_mmap,
2089         .unlocked_ioctl = video_ioctl2,
2090 };
2091 
2092 static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = {
2093         .vidioc_querycap                = pxac_vidioc_querycap,
2094 
2095         .vidioc_enum_input              = pxac_vidioc_enum_input,
2096         .vidioc_g_input                 = pxac_vidioc_g_input,
2097         .vidioc_s_input                 = pxac_vidioc_s_input,
2098 
2099         .vidioc_enum_fmt_vid_cap        = pxac_vidioc_enum_fmt_vid_cap,
2100         .vidioc_g_fmt_vid_cap           = pxac_vidioc_g_fmt_vid_cap,
2101         .vidioc_s_fmt_vid_cap           = pxac_vidioc_s_fmt_vid_cap,
2102         .vidioc_try_fmt_vid_cap         = pxac_vidioc_try_fmt_vid_cap,
2103 
2104         .vidioc_reqbufs                 = vb2_ioctl_reqbufs,
2105         .vidioc_create_bufs             = vb2_ioctl_create_bufs,
2106         .vidioc_querybuf                = vb2_ioctl_querybuf,
2107         .vidioc_qbuf                    = vb2_ioctl_qbuf,
2108         .vidioc_dqbuf                   = vb2_ioctl_dqbuf,
2109         .vidioc_expbuf                  = vb2_ioctl_expbuf,
2110         .vidioc_streamon                = vb2_ioctl_streamon,
2111         .vidioc_streamoff               = vb2_ioctl_streamoff,
2112 #ifdef CONFIG_VIDEO_ADV_DEBUG
2113         .vidioc_g_register              = pxac_vidioc_g_register,
2114         .vidioc_s_register              = pxac_vidioc_s_register,
2115 #endif
2116         .vidioc_subscribe_event         = v4l2_ctrl_subscribe_event,
2117         .vidioc_unsubscribe_event       = v4l2_event_unsubscribe,
2118 };
2119 
2120 static const struct v4l2_clk_ops pxa_camera_mclk_ops = {
2121 };
2122 
2123 static const struct video_device pxa_camera_videodev_template = {
2124         .name = "pxa-camera",
2125         .minor = -1,
2126         .fops = &pxa_camera_fops,
2127         .ioctl_ops = &pxa_camera_ioctl_ops,
2128         .release = video_device_release_empty,
2129         .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
2130 };
2131 
2132 static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier,
2133                      struct v4l2_subdev *subdev,
2134                      struct v4l2_async_subdev *asd)
2135 {
2136         int err;
2137         struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
2138         struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
2139         struct video_device *vdev = &pcdev->vdev;
2140         struct v4l2_pix_format *pix = &pcdev->current_pix;
2141         struct v4l2_subdev_format format = {
2142                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2143         };
2144         struct v4l2_mbus_framefmt *mf = &format.format;
2145 
2146         dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n",
2147                  __func__);
2148         mutex_lock(&pcdev->mlock);
2149         *vdev = pxa_camera_videodev_template;
2150         vdev->v4l2_dev = v4l2_dev;
2151         vdev->lock = &pcdev->mlock;
2152         pcdev->sensor = subdev;
2153         pcdev->vdev.queue = &pcdev->vb2_vq;
2154         pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev;
2155         pcdev->vdev.ctrl_handler = subdev->ctrl_handler;
2156         video_set_drvdata(&pcdev->vdev, pcdev);
2157 
2158         err = pxa_camera_build_formats(pcdev);
2159         if (err) {
2160                 dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n",
2161                         err);
2162                 goto out;
2163         }
2164 
2165         pcdev->current_fmt = pcdev->user_formats;
2166         pix->field = V4L2_FIELD_NONE;
2167         pix->width = DEFAULT_WIDTH;
2168         pix->height = DEFAULT_HEIGHT;
2169         pix->bytesperline =
2170                 pxa_mbus_bytes_per_line(pix->width,
2171                                         pcdev->current_fmt->host_fmt);
2172         pix->sizeimage =
2173                 pxa_mbus_image_size(pcdev->current_fmt->host_fmt,
2174                                     pix->bytesperline, pix->height);
2175         pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
2176         v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code);
2177 
2178         err = pxac_sensor_set_power(pcdev, 1);
2179         if (err)
2180                 goto out;
2181 
2182         err = sensor_call(pcdev, pad, set_fmt, NULL, &format);
2183         if (err)
2184                 goto out_sensor_poweroff;
2185 
2186         v4l2_fill_pix_format(pix, mf);
2187         pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n",
2188                 __func__, pix->colorspace, pix->pixelformat);
2189 
2190         err = pxa_camera_init_videobuf2(pcdev);
2191         if (err)
2192                 goto out_sensor_poweroff;
2193 
2194         err = video_register_device(&pcdev->vdev, VFL_TYPE_GRABBER, -1);
2195         if (err) {
2196                 v4l2_err(v4l2_dev, "register video device failed: %d\n", err);
2197                 pcdev->sensor = NULL;
2198         } else {
2199                 dev_info(pcdev_to_dev(pcdev),
2200                          "PXA Camera driver attached to camera %s\n",
2201                          subdev->name);
2202         }
2203 
2204 out_sensor_poweroff:
2205         err = pxac_sensor_set_power(pcdev, 0);
2206 out:
2207         mutex_unlock(&pcdev->mlock);
2208         return err;
2209 }
2210 
2211 static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
2212                      struct v4l2_subdev *subdev,
2213                      struct v4l2_async_subdev *asd)
2214 {
2215         struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev);
2216 
2217         mutex_lock(&pcdev->mlock);
2218         dev_info(pcdev_to_dev(pcdev),
2219                  "PXA Camera driver detached from camera %s\n",
2220                  subdev->name);
2221 
2222         /* disable capture, disable interrupts */
2223         __raw_writel(0x3ff, pcdev->base + CICR0);
2224 
2225         /* Stop DMA engine */
2226         pxa_dma_stop_channels(pcdev);
2227 
2228         pxa_camera_destroy_formats(pcdev);
2229 
2230         if (pcdev->mclk_clk) {
2231                 v4l2_clk_unregister(pcdev->mclk_clk);
2232                 pcdev->mclk_clk = NULL;
2233         }
2234 
2235         video_unregister_device(&pcdev->vdev);
2236         pcdev->sensor = NULL;
2237 
2238         mutex_unlock(&pcdev->mlock);
2239 }
2240 
2241 static const struct v4l2_async_notifier_operations pxa_camera_sensor_ops = {
2242         .bound = pxa_camera_sensor_bound,
2243         .unbind = pxa_camera_sensor_unbind,
2244 };
2245 
2246 /*
2247  * Driver probe, remove, suspend and resume operations
2248  */
2249 static int pxa_camera_suspend(struct device *dev)
2250 {
2251         struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2252         int i = 0, ret = 0;
2253 
2254         pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
2255         pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
2256         pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
2257         pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
2258         pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
2259 
2260         if (pcdev->sensor)
2261                 ret = pxac_sensor_set_power(pcdev, 0);
2262 
2263         return ret;
2264 }
2265 
2266 static int pxa_camera_resume(struct device *dev)
2267 {
2268         struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2269         int i = 0, ret = 0;
2270 
2271         __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
2272         __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
2273         __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
2274         __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
2275         __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
2276 
2277         if (pcdev->sensor) {
2278                 ret = pxac_sensor_set_power(pcdev, 1);
2279         }
2280 
2281         /* Restart frame capture if active buffer exists */
2282         if (!ret && pcdev->active)
2283                 pxa_camera_start_capture(pcdev);
2284 
2285         return ret;
2286 }
2287 
2288 static int pxa_camera_pdata_from_dt(struct device *dev,
2289                                     struct pxa_camera_dev *pcdev,
2290                                     struct v4l2_async_subdev *asd)
2291 {
2292         u32 mclk_rate;
2293         struct device_node *remote, *np = dev->of_node;
2294         struct v4l2_fwnode_endpoint ep = { .bus_type = 0 };
2295         int err = of_property_read_u32(np, "clock-frequency",
2296                                        &mclk_rate);
2297         if (!err) {
2298                 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
2299                 pcdev->mclk = mclk_rate;
2300         }
2301 
2302         np = of_graph_get_next_endpoint(np, NULL);
2303         if (!np) {
2304                 dev_err(dev, "could not find endpoint\n");
2305                 return -EINVAL;
2306         }
2307 
2308         err = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep);
2309         if (err) {
2310                 dev_err(dev, "could not parse endpoint\n");
2311                 goto out;
2312         }
2313 
2314         switch (ep.bus.parallel.bus_width) {
2315         case 4:
2316                 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
2317                 break;
2318         case 5:
2319                 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
2320                 break;
2321         case 8:
2322                 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
2323                 break;
2324         case 9:
2325                 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
2326                 break;
2327         case 10:
2328                 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2329                 break;
2330         default:
2331                 break;
2332         }
2333 
2334         if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
2335                 pcdev->platform_flags |= PXA_CAMERA_MASTER;
2336         if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2337                 pcdev->platform_flags |= PXA_CAMERA_HSP;
2338         if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2339                 pcdev->platform_flags |= PXA_CAMERA_VSP;
2340         if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2341                 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
2342         if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
2343                 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
2344 
2345         asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
2346         remote = of_graph_get_remote_port_parent(np);
2347         if (remote)
2348                 asd->match.fwnode = of_fwnode_handle(remote);
2349         else
2350                 dev_notice(dev, "no remote for %pOF\n", np);
2351 
2352 out:
2353         of_node_put(np);
2354 
2355         return err;
2356 }
2357 
2358 static int pxa_camera_probe(struct platform_device *pdev)
2359 {
2360         struct pxa_camera_dev *pcdev;
2361         struct resource *res;
2362         void __iomem *base;
2363         struct dma_slave_config config = {
2364                 .src_addr_width = 0,
2365                 .src_maxburst = 8,
2366                 .direction = DMA_DEV_TO_MEM,
2367         };
2368         char clk_name[V4L2_CLK_NAME_SIZE];
2369         int irq;
2370         int err = 0, i;
2371 
2372         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2373         irq = platform_get_irq(pdev, 0);
2374         if (!res || irq < 0)
2375                 return -ENODEV;
2376 
2377         pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
2378         if (!pcdev) {
2379                 dev_err(&pdev->dev, "Could not allocate pcdev\n");
2380                 return -ENOMEM;
2381         }
2382 
2383         pcdev->clk = devm_clk_get(&pdev->dev, NULL);
2384         if (IS_ERR(pcdev->clk))
2385                 return PTR_ERR(pcdev->clk);
2386 
2387         pcdev->res = res;
2388 
2389         pcdev->pdata = pdev->dev.platform_data;
2390         if (pcdev->pdata) {
2391                 pcdev->platform_flags = pcdev->pdata->flags;
2392                 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
2393                 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2394                 pcdev->asd.match.i2c.adapter_id =
2395                         pcdev->pdata->sensor_i2c_adapter_id;
2396                 pcdev->asd.match.i2c.address = pcdev->pdata->sensor_i2c_address;
2397         } else if (pdev->dev.of_node) {
2398                 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev, &pcdev->asd);
2399         } else {
2400                 return -ENODEV;
2401         }
2402         if (err < 0)
2403                 return err;
2404 
2405         if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
2406                         PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
2407                 /*
2408                  * Platform hasn't set available data widths. This is bad.
2409                  * Warn and use a default.
2410                  */
2411                 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available data widths, using default 10 bit\n");
2412                 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2413         }
2414         if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
2415                 pcdev->width_flags = 1 << 7;
2416         if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
2417                 pcdev->width_flags |= 1 << 8;
2418         if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
2419                 pcdev->width_flags |= 1 << 9;
2420         if (!pcdev->mclk) {
2421                 dev_warn(&pdev->dev,
2422                          "mclk == 0! Please, fix your platform data. Using default 20MHz\n");
2423                 pcdev->mclk = 20000000;
2424         }
2425 
2426         pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
2427 
2428         INIT_LIST_HEAD(&pcdev->capture);
2429         spin_lock_init(&pcdev->lock);
2430         mutex_init(&pcdev->mlock);
2431 
2432         /*
2433          * Request the regions.
2434          */
2435         base = devm_ioremap_resource(&pdev->dev, res);
2436         if (IS_ERR(base))
2437                 return PTR_ERR(base);
2438 
2439         pcdev->irq = irq;
2440         pcdev->base = base;
2441 
2442         /* request dma */
2443         pcdev->dma_chans[0] = dma_request_slave_channel(&pdev->dev, "CI_Y");
2444         if (!pcdev->dma_chans[0]) {
2445                 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2446                 return -ENODEV;
2447         }
2448 
2449         pcdev->dma_chans[1] = dma_request_slave_channel(&pdev->dev, "CI_U");
2450         if (!pcdev->dma_chans[1]) {
2451                 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2452                 err = -ENODEV;
2453                 goto exit_free_dma_y;
2454         }
2455 
2456         pcdev->dma_chans[2] = dma_request_slave_channel(&pdev->dev, "CI_V");
2457         if (!pcdev->dma_chans[2]) {
2458                 dev_err(&pdev->dev, "Can't request DMA for V\n");
2459                 err = -ENODEV;
2460                 goto exit_free_dma_u;
2461         }
2462 
2463         for (i = 0; i < 3; i++) {
2464                 config.src_addr = pcdev->res->start + CIBR0 + i * 8;
2465                 err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
2466                 if (err < 0) {
2467                         dev_err(&pdev->dev, "dma slave config failed: %d\n",
2468                                 err);
2469                         goto exit_free_dma;
2470                 }
2471         }
2472 
2473         /* request irq */
2474         err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
2475                                PXA_CAM_DRV_NAME, pcdev);
2476         if (err) {
2477                 dev_err(&pdev->dev, "Camera interrupt register failed\n");
2478                 goto exit_free_dma;
2479         }
2480 
2481         tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev);
2482 
2483         pxa_camera_activate(pcdev);
2484 
2485         dev_set_drvdata(&pdev->dev, pcdev);
2486         err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
2487         if (err)
2488                 goto exit_deactivate;
2489 
2490         v4l2_async_notifier_init(&pcdev->notifier);
2491 
2492         err = v4l2_async_notifier_add_subdev(&pcdev->notifier, &pcdev->asd);
2493         if (err) {
2494                 fwnode_handle_put(pcdev->asd.match.fwnode);
2495                 goto exit_free_v4l2dev;
2496         }
2497 
2498         pcdev->notifier.ops = &pxa_camera_sensor_ops;
2499 
2500         if (!of_have_populated_dt())
2501                 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2502 
2503         err = pxa_camera_init_videobuf2(pcdev);
2504         if (err)
2505                 goto exit_notifier_cleanup;
2506 
2507         if (pcdev->mclk) {
2508                 v4l2_clk_name_i2c(clk_name, sizeof(clk_name),
2509                                   pcdev->asd.match.i2c.adapter_id,
2510                                   pcdev->asd.match.i2c.address);
2511 
2512                 pcdev->mclk_clk = v4l2_clk_register(&pxa_camera_mclk_ops,
2513                                                     clk_name, NULL);
2514                 if (IS_ERR(pcdev->mclk_clk)) {
2515                         err = PTR_ERR(pcdev->mclk_clk);
2516                         goto exit_notifier_cleanup;
2517                 }
2518         }
2519 
2520         err = v4l2_async_notifier_register(&pcdev->v4l2_dev, &pcdev->notifier);
2521         if (err)
2522                 goto exit_free_clk;
2523 
2524         return 0;
2525 exit_free_clk:
2526         v4l2_clk_unregister(pcdev->mclk_clk);
2527 exit_notifier_cleanup:
2528         v4l2_async_notifier_cleanup(&pcdev->notifier);
2529 exit_free_v4l2dev:
2530         v4l2_device_unregister(&pcdev->v4l2_dev);
2531 exit_deactivate:
2532         pxa_camera_deactivate(pcdev);
2533 exit_free_dma:
2534         dma_release_channel(pcdev->dma_chans[2]);
2535 exit_free_dma_u:
2536         dma_release_channel(pcdev->dma_chans[1]);
2537 exit_free_dma_y:
2538         dma_release_channel(pcdev->dma_chans[0]);
2539         return err;
2540 }
2541 
2542 static int pxa_camera_remove(struct platform_device *pdev)
2543 {
2544         struct pxa_camera_dev *pcdev = dev_get_drvdata(&pdev->dev);
2545 
2546         pxa_camera_deactivate(pcdev);
2547         dma_release_channel(pcdev->dma_chans[0]);
2548         dma_release_channel(pcdev->dma_chans[1]);
2549         dma_release_channel(pcdev->dma_chans[2]);
2550 
2551         v4l2_async_notifier_unregister(&pcdev->notifier);
2552         v4l2_async_notifier_cleanup(&pcdev->notifier);
2553 
2554         if (pcdev->mclk_clk) {
2555                 v4l2_clk_unregister(pcdev->mclk_clk);
2556                 pcdev->mclk_clk = NULL;
2557         }
2558 
2559         v4l2_device_unregister(&pcdev->v4l2_dev);
2560 
2561         dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
2562 
2563         return 0;
2564 }
2565 
2566 static const struct dev_pm_ops pxa_camera_pm = {
2567         .suspend        = pxa_camera_suspend,
2568         .resume         = pxa_camera_resume,
2569 };
2570 
2571 static const struct of_device_id pxa_camera_of_match[] = {
2572         { .compatible = "marvell,pxa270-qci", },
2573         {},
2574 };
2575 MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
2576 
2577 static struct platform_driver pxa_camera_driver = {
2578         .driver         = {
2579                 .name   = PXA_CAM_DRV_NAME,
2580                 .pm     = &pxa_camera_pm,
2581                 .of_match_table = of_match_ptr(pxa_camera_of_match),
2582         },
2583         .probe          = pxa_camera_probe,
2584         .remove         = pxa_camera_remove,
2585 };
2586 
2587 module_platform_driver(pxa_camera_driver);
2588 
2589 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
2590 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
2591 MODULE_LICENSE("GPL");
2592 MODULE_VERSION(PXA_CAM_VERSION);
2593 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/media/platform/pxa_camera.c

DEFINITIONS
