root/drivers/media/platform/ti-vpe/vpe_regs.h

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INCLUDED FROM


   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2013 Texas Instruments Inc.
   4  *
   5  * David Griego, <dagriego@biglakesoftware.com>
   6  * Dale Farnsworth, <dale@farnsworth.org>
   7  * Archit Taneja, <archit@ti.com>
   8  */
   9 
  10 #ifndef __TI_VPE_REGS_H
  11 #define __TI_VPE_REGS_H
  12 
  13 /* VPE register offsets and field selectors */
  14 
  15 /* VPE top level regs */
  16 #define VPE_PID                         0x0000
  17 #define VPE_PID_MINOR_MASK              0x3f
  18 #define VPE_PID_MINOR_SHIFT             0
  19 #define VPE_PID_CUSTOM_MASK             0x03
  20 #define VPE_PID_CUSTOM_SHIFT            6
  21 #define VPE_PID_MAJOR_MASK              0x07
  22 #define VPE_PID_MAJOR_SHIFT             8
  23 #define VPE_PID_RTL_MASK                0x1f
  24 #define VPE_PID_RTL_SHIFT               11
  25 #define VPE_PID_FUNC_MASK               0xfff
  26 #define VPE_PID_FUNC_SHIFT              16
  27 #define VPE_PID_SCHEME_MASK             0x03
  28 #define VPE_PID_SCHEME_SHIFT            30
  29 
  30 #define VPE_SYSCONFIG                   0x0010
  31 #define VPE_SYSCONFIG_IDLE_MASK         0x03
  32 #define VPE_SYSCONFIG_IDLE_SHIFT        2
  33 #define VPE_SYSCONFIG_STANDBY_MASK      0x03
  34 #define VPE_SYSCONFIG_STANDBY_SHIFT     4
  35 #define VPE_FORCE_IDLE_MODE             0
  36 #define VPE_NO_IDLE_MODE                1
  37 #define VPE_SMART_IDLE_MODE             2
  38 #define VPE_SMART_IDLE_WAKEUP_MODE      3
  39 #define VPE_FORCE_STANDBY_MODE          0
  40 #define VPE_NO_STANDBY_MODE             1
  41 #define VPE_SMART_STANDBY_MODE          2
  42 #define VPE_SMART_STANDBY_WAKEUP_MODE   3
  43 
  44 #define VPE_INT0_STATUS0_RAW_SET        0x0020
  45 #define VPE_INT0_STATUS0_RAW            VPE_INT0_STATUS0_RAW_SET
  46 #define VPE_INT0_STATUS0_CLR            0x0028
  47 #define VPE_INT0_STATUS0                VPE_INT0_STATUS0_CLR
  48 #define VPE_INT0_ENABLE0_SET            0x0030
  49 #define VPE_INT0_ENABLE0                VPE_INT0_ENABLE0_SET
  50 #define VPE_INT0_ENABLE0_CLR            0x0038
  51 #define VPE_INT0_LIST0_COMPLETE         BIT(0)
  52 #define VPE_INT0_LIST0_NOTIFY           BIT(1)
  53 #define VPE_INT0_LIST1_COMPLETE         BIT(2)
  54 #define VPE_INT0_LIST1_NOTIFY           BIT(3)
  55 #define VPE_INT0_LIST2_COMPLETE         BIT(4)
  56 #define VPE_INT0_LIST2_NOTIFY           BIT(5)
  57 #define VPE_INT0_LIST3_COMPLETE         BIT(6)
  58 #define VPE_INT0_LIST3_NOTIFY           BIT(7)
  59 #define VPE_INT0_LIST4_COMPLETE         BIT(8)
  60 #define VPE_INT0_LIST4_NOTIFY           BIT(9)
  61 #define VPE_INT0_LIST5_COMPLETE         BIT(10)
  62 #define VPE_INT0_LIST5_NOTIFY           BIT(11)
  63 #define VPE_INT0_LIST6_COMPLETE         BIT(12)
  64 #define VPE_INT0_LIST6_NOTIFY           BIT(13)
  65 #define VPE_INT0_LIST7_COMPLETE         BIT(14)
  66 #define VPE_INT0_LIST7_NOTIFY           BIT(15)
  67 #define VPE_INT0_DESCRIPTOR             BIT(16)
  68 #define VPE_DEI_FMD_INT                 BIT(18)
  69 
  70 #define VPE_INT0_STATUS1_RAW_SET        0x0024
  71 #define VPE_INT0_STATUS1_RAW            VPE_INT0_STATUS1_RAW_SET
  72 #define VPE_INT0_STATUS1_CLR            0x002c
  73 #define VPE_INT0_STATUS1                VPE_INT0_STATUS1_CLR
  74 #define VPE_INT0_ENABLE1_SET            0x0034
  75 #define VPE_INT0_ENABLE1                VPE_INT0_ENABLE1_SET
  76 #define VPE_INT0_ENABLE1_CLR            0x003c
  77 #define VPE_INT0_CHANNEL_GROUP0         BIT(0)
  78 #define VPE_INT0_CHANNEL_GROUP1         BIT(1)
  79 #define VPE_INT0_CHANNEL_GROUP2         BIT(2)
  80 #define VPE_INT0_CHANNEL_GROUP3         BIT(3)
  81 #define VPE_INT0_CHANNEL_GROUP4         BIT(4)
  82 #define VPE_INT0_CHANNEL_GROUP5         BIT(5)
  83 #define VPE_INT0_CLIENT                 BIT(7)
  84 #define VPE_DEI_ERROR_INT               BIT(16)
  85 #define VPE_DS1_UV_ERROR_INT            BIT(22)
  86 
  87 #define VPE_INTC_EOI                    0x00a0
  88 
  89 #define VPE_CLK_ENABLE                  0x0100
  90 #define VPE_VPEDMA_CLK_ENABLE           BIT(0)
  91 #define VPE_DATA_PATH_CLK_ENABLE        BIT(1)
  92 
  93 #define VPE_CLK_RESET                   0x0104
  94 #define VPE_VPDMA_CLK_RESET_MASK        0x1
  95 #define VPE_VPDMA_CLK_RESET_SHIFT       0
  96 #define VPE_DATA_PATH_CLK_RESET_MASK    0x1
  97 #define VPE_DATA_PATH_CLK_RESET_SHIFT   1
  98 #define VPE_MAIN_RESET_MASK             0x1
  99 #define VPE_MAIN_RESET_SHIFT            31
 100 
 101 #define VPE_CLK_FORMAT_SELECT           0x010c
 102 #define VPE_CSC_SRC_SELECT_MASK         0x03
 103 #define VPE_CSC_SRC_SELECT_SHIFT        0
 104 #define VPE_RGB_OUT_SELECT              BIT(8)
 105 #define VPE_DS_SRC_SELECT_MASK          0x07
 106 #define VPE_DS_SRC_SELECT_SHIFT         9
 107 #define VPE_DS_BYPASS                   BIT(16)
 108 #define VPE_COLOR_SEPARATE_422          BIT(18)
 109 
 110 #define VPE_DS_SRC_DEI_SCALER           (5 << VPE_DS_SRC_SELECT_SHIFT)
 111 #define VPE_CSC_SRC_DEI_SCALER          (3 << VPE_CSC_SRC_SELECT_SHIFT)
 112 
 113 #define VPE_CLK_RANGE_MAP               0x011c
 114 #define VPE_RANGE_RANGE_MAP_Y_MASK      0x07
 115 #define VPE_RANGE_RANGE_MAP_Y_SHIFT     0
 116 #define VPE_RANGE_RANGE_MAP_UV_MASK     0x07
 117 #define VPE_RANGE_RANGE_MAP_UV_SHIFT    3
 118 #define VPE_RANGE_MAP_ON                BIT(6)
 119 #define VPE_RANGE_REDUCTION_ON          BIT(28)
 120 
 121 /* VPE chrominance upsampler regs */
 122 #define VPE_US1_R0                      0x0304
 123 #define VPE_US2_R0                      0x0404
 124 #define VPE_US3_R0                      0x0504
 125 #define VPE_US_C1_MASK                  0x3fff
 126 #define VPE_US_C1_SHIFT                 2
 127 #define VPE_US_C0_MASK                  0x3fff
 128 #define VPE_US_C0_SHIFT                 18
 129 #define VPE_US_MODE_MASK                0x03
 130 #define VPE_US_MODE_SHIFT               16
 131 #define VPE_ANCHOR_FID0_C1_MASK         0x3fff
 132 #define VPE_ANCHOR_FID0_C1_SHIFT        2
 133 #define VPE_ANCHOR_FID0_C0_MASK         0x3fff
 134 #define VPE_ANCHOR_FID0_C0_SHIFT        18
 135 
 136 #define VPE_US1_R1                      0x0308
 137 #define VPE_US2_R1                      0x0408
 138 #define VPE_US3_R1                      0x0508
 139 #define VPE_ANCHOR_FID0_C3_MASK         0x3fff
 140 #define VPE_ANCHOR_FID0_C3_SHIFT        2
 141 #define VPE_ANCHOR_FID0_C2_MASK         0x3fff
 142 #define VPE_ANCHOR_FID0_C2_SHIFT        18
 143 
 144 #define VPE_US1_R2                      0x030c
 145 #define VPE_US2_R2                      0x040c
 146 #define VPE_US3_R2                      0x050c
 147 #define VPE_INTERP_FID0_C1_MASK         0x3fff
 148 #define VPE_INTERP_FID0_C1_SHIFT        2
 149 #define VPE_INTERP_FID0_C0_MASK         0x3fff
 150 #define VPE_INTERP_FID0_C0_SHIFT        18
 151 
 152 #define VPE_US1_R3                      0x0310
 153 #define VPE_US2_R3                      0x0410
 154 #define VPE_US3_R3                      0x0510
 155 #define VPE_INTERP_FID0_C3_MASK         0x3fff
 156 #define VPE_INTERP_FID0_C3_SHIFT        2
 157 #define VPE_INTERP_FID0_C2_MASK         0x3fff
 158 #define VPE_INTERP_FID0_C2_SHIFT        18
 159 
 160 #define VPE_US1_R4                      0x0314
 161 #define VPE_US2_R4                      0x0414
 162 #define VPE_US3_R4                      0x0514
 163 #define VPE_ANCHOR_FID1_C1_MASK         0x3fff
 164 #define VPE_ANCHOR_FID1_C1_SHIFT        2
 165 #define VPE_ANCHOR_FID1_C0_MASK         0x3fff
 166 #define VPE_ANCHOR_FID1_C0_SHIFT        18
 167 
 168 #define VPE_US1_R5                      0x0318
 169 #define VPE_US2_R5                      0x0418
 170 #define VPE_US3_R5                      0x0518
 171 #define VPE_ANCHOR_FID1_C3_MASK         0x3fff
 172 #define VPE_ANCHOR_FID1_C3_SHIFT        2
 173 #define VPE_ANCHOR_FID1_C2_MASK         0x3fff
 174 #define VPE_ANCHOR_FID1_C2_SHIFT        18
 175 
 176 #define VPE_US1_R6                      0x031c
 177 #define VPE_US2_R6                      0x041c
 178 #define VPE_US3_R6                      0x051c
 179 #define VPE_INTERP_FID1_C1_MASK         0x3fff
 180 #define VPE_INTERP_FID1_C1_SHIFT        2
 181 #define VPE_INTERP_FID1_C0_MASK         0x3fff
 182 #define VPE_INTERP_FID1_C0_SHIFT        18
 183 
 184 #define VPE_US1_R7                      0x0320
 185 #define VPE_US2_R7                      0x0420
 186 #define VPE_US3_R7                      0x0520
 187 #define VPE_INTERP_FID0_C3_MASK         0x3fff
 188 #define VPE_INTERP_FID0_C3_SHIFT        2
 189 #define VPE_INTERP_FID0_C2_MASK         0x3fff
 190 #define VPE_INTERP_FID0_C2_SHIFT        18
 191 
 192 /* VPE de-interlacer regs */
 193 #define VPE_DEI_FRAME_SIZE              0x0600
 194 #define VPE_DEI_WIDTH_MASK              0x07ff
 195 #define VPE_DEI_WIDTH_SHIFT             0
 196 #define VPE_DEI_HEIGHT_MASK             0x07ff
 197 #define VPE_DEI_HEIGHT_SHIFT            16
 198 #define VPE_DEI_INTERLACE_BYPASS        BIT(29)
 199 #define VPE_DEI_FIELD_FLUSH             BIT(30)
 200 #define VPE_DEI_PROGRESSIVE             BIT(31)
 201 
 202 #define VPE_MDT_BYPASS                  0x0604
 203 #define VPE_MDT_TEMPMAX_BYPASS          BIT(0)
 204 #define VPE_MDT_SPATMAX_BYPASS          BIT(1)
 205 
 206 #define VPE_MDT_SF_THRESHOLD            0x0608
 207 #define VPE_MDT_SF_SC_THR1_MASK         0xff
 208 #define VPE_MDT_SF_SC_THR1_SHIFT        0
 209 #define VPE_MDT_SF_SC_THR2_MASK         0xff
 210 #define VPE_MDT_SF_SC_THR2_SHIFT        0
 211 #define VPE_MDT_SF_SC_THR3_MASK         0xff
 212 #define VPE_MDT_SF_SC_THR3_SHIFT        0
 213 
 214 #define VPE_EDI_CONFIG                  0x060c
 215 #define VPE_EDI_INP_MODE_MASK           0x03
 216 #define VPE_EDI_INP_MODE_SHIFT          0
 217 #define VPE_EDI_ENABLE_3D               BIT(2)
 218 #define VPE_EDI_ENABLE_CHROMA_3D        BIT(3)
 219 #define VPE_EDI_CHROMA3D_COR_THR_MASK   0xff
 220 #define VPE_EDI_CHROMA3D_COR_THR_SHIFT  8
 221 #define VPE_EDI_DIR_COR_LOWER_THR_MASK  0xff
 222 #define VPE_EDI_DIR_COR_LOWER_THR_SHIFT 16
 223 #define VPE_EDI_COR_SCALE_FACTOR_MASK   0xff
 224 #define VPE_EDI_COR_SCALE_FACTOR_SHIFT  23
 225 
 226 #define VPE_DEI_EDI_LUT_R0              0x0610
 227 #define VPE_EDI_LUT0_MASK               0x1f
 228 #define VPE_EDI_LUT0_SHIFT              0
 229 #define VPE_EDI_LUT1_MASK               0x1f
 230 #define VPE_EDI_LUT1_SHIFT              8
 231 #define VPE_EDI_LUT2_MASK               0x1f
 232 #define VPE_EDI_LUT2_SHIFT              16
 233 #define VPE_EDI_LUT3_MASK               0x1f
 234 #define VPE_EDI_LUT3_SHIFT              24
 235 
 236 #define VPE_DEI_EDI_LUT_R1              0x0614
 237 #define VPE_EDI_LUT0_MASK               0x1f
 238 #define VPE_EDI_LUT0_SHIFT              0
 239 #define VPE_EDI_LUT1_MASK               0x1f
 240 #define VPE_EDI_LUT1_SHIFT              8
 241 #define VPE_EDI_LUT2_MASK               0x1f
 242 #define VPE_EDI_LUT2_SHIFT              16
 243 #define VPE_EDI_LUT3_MASK               0x1f
 244 #define VPE_EDI_LUT3_SHIFT              24
 245 
 246 #define VPE_DEI_EDI_LUT_R2              0x0618
 247 #define VPE_EDI_LUT4_MASK               0x1f
 248 #define VPE_EDI_LUT4_SHIFT              0
 249 #define VPE_EDI_LUT5_MASK               0x1f
 250 #define VPE_EDI_LUT5_SHIFT              8
 251 #define VPE_EDI_LUT6_MASK               0x1f
 252 #define VPE_EDI_LUT6_SHIFT              16
 253 #define VPE_EDI_LUT7_MASK               0x1f
 254 #define VPE_EDI_LUT7_SHIFT              24
 255 
 256 #define VPE_DEI_EDI_LUT_R3              0x061c
 257 #define VPE_EDI_LUT8_MASK               0x1f
 258 #define VPE_EDI_LUT8_SHIFT              0
 259 #define VPE_EDI_LUT9_MASK               0x1f
 260 #define VPE_EDI_LUT9_SHIFT              8
 261 #define VPE_EDI_LUT10_MASK              0x1f
 262 #define VPE_EDI_LUT10_SHIFT             16
 263 #define VPE_EDI_LUT11_MASK              0x1f
 264 #define VPE_EDI_LUT11_SHIFT             24
 265 
 266 #define VPE_DEI_FMD_WINDOW_R0           0x0620
 267 #define VPE_FMD_WINDOW_MINX_MASK        0x07ff
 268 #define VPE_FMD_WINDOW_MINX_SHIFT       0
 269 #define VPE_FMD_WINDOW_MAXX_MASK        0x07ff
 270 #define VPE_FMD_WINDOW_MAXX_SHIFT       16
 271 #define VPE_FMD_WINDOW_ENABLE           BIT(31)
 272 
 273 #define VPE_DEI_FMD_WINDOW_R1           0x0624
 274 #define VPE_FMD_WINDOW_MINY_MASK        0x07ff
 275 #define VPE_FMD_WINDOW_MINY_SHIFT       0
 276 #define VPE_FMD_WINDOW_MAXY_MASK        0x07ff
 277 #define VPE_FMD_WINDOW_MAXY_SHIFT       16
 278 
 279 #define VPE_DEI_FMD_CONTROL_R0          0x0628
 280 #define VPE_FMD_ENABLE                  BIT(0)
 281 #define VPE_FMD_LOCK                    BIT(1)
 282 #define VPE_FMD_JAM_DIR                 BIT(2)
 283 #define VPE_FMD_BED_ENABLE              BIT(3)
 284 #define VPE_FMD_CAF_FIELD_THR_MASK      0xff
 285 #define VPE_FMD_CAF_FIELD_THR_SHIFT     16
 286 #define VPE_FMD_CAF_LINE_THR_MASK       0xff
 287 #define VPE_FMD_CAF_LINE_THR_SHIFT      24
 288 
 289 #define VPE_DEI_FMD_CONTROL_R1          0x062c
 290 #define VPE_FMD_CAF_THR_MASK            0x000fffff
 291 #define VPE_FMD_CAF_THR_SHIFT           0
 292 
 293 #define VPE_DEI_FMD_STATUS_R0           0x0630
 294 #define VPE_FMD_CAF_MASK                0x000fffff
 295 #define VPE_FMD_CAF_SHIFT               0
 296 #define VPE_FMD_RESET                   BIT(24)
 297 
 298 #define VPE_DEI_FMD_STATUS_R1           0x0634
 299 #define VPE_FMD_FIELD_DIFF_MASK         0x0fffffff
 300 #define VPE_FMD_FIELD_DIFF_SHIFT        0
 301 
 302 #define VPE_DEI_FMD_STATUS_R2           0x0638
 303 #define VPE_FMD_FRAME_DIFF_MASK         0x000fffff
 304 #define VPE_FMD_FRAME_DIFF_SHIFT        0
 305 
 306 #endif

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