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10 #ifndef __TI_CAL_REGS_H
11 #define __TI_CAL_REGS_H
12
13 #define CAL_NUM_CSI2_PORTS 2
14
15
16
17 #define CAL_HL_REVISION 0x0000
18 #define CAL_HL_HWINFO 0x0004
19 #define CAL_HL_SYSCONFIG 0x0010
20 #define CAL_HL_IRQ_EOI 0x001c
21 #define CAL_HL_IRQSTATUS_RAW(m) (0x20U + ((m-1) * 0x10U))
22 #define CAL_HL_IRQSTATUS(m) (0x24U + ((m-1) * 0x10U))
23 #define CAL_HL_IRQENABLE_SET(m) (0x28U + ((m-1) * 0x10U))
24 #define CAL_HL_IRQENABLE_CLR(m) (0x2cU + ((m-1) * 0x10U))
25 #define CAL_PIX_PROC(m) (0xc0U + ((m-1) * 0x4U))
26 #define CAL_CTRL 0x100
27 #define CAL_CTRL1 0x104
28 #define CAL_LINE_NUMBER_EVT 0x108
29 #define CAL_VPORT_CTRL1 0x120
30 #define CAL_VPORT_CTRL2 0x124
31 #define CAL_BYS_CTRL1 0x130
32 #define CAL_BYS_CTRL2 0x134
33 #define CAL_RD_DMA_CTRL 0x140
34 #define CAL_RD_DMA_PIX_ADDR 0x144
35 #define CAL_RD_DMA_PIX_OFST 0x148
36 #define CAL_RD_DMA_XSIZE 0x14c
37 #define CAL_RD_DMA_YSIZE 0x150
38 #define CAL_RD_DMA_INIT_ADDR 0x154
39 #define CAL_RD_DMA_INIT_OFST 0x168
40 #define CAL_RD_DMA_CTRL2 0x16c
41 #define CAL_WR_DMA_CTRL(m) (0x200U + ((m-1) * 0x10U))
42 #define CAL_WR_DMA_ADDR(m) (0x204U + ((m-1) * 0x10U))
43 #define CAL_WR_DMA_OFST(m) (0x208U + ((m-1) * 0x10U))
44 #define CAL_WR_DMA_XSIZE(m) (0x20cU + ((m-1) * 0x10U))
45 #define CAL_CSI2_PPI_CTRL(m) (0x300U + ((m-1) * 0x80U))
46 #define CAL_CSI2_COMPLEXIO_CFG(m) (0x304U + ((m-1) * 0x80U))
47 #define CAL_CSI2_COMPLEXIO_IRQSTATUS(m) (0x308U + ((m-1) * 0x80U))
48 #define CAL_CSI2_SHORT_PACKET(m) (0x30cU + ((m-1) * 0x80U))
49 #define CAL_CSI2_COMPLEXIO_IRQENABLE(m) (0x310U + ((m-1) * 0x80U))
50 #define CAL_CSI2_TIMING(m) (0x314U + ((m-1) * 0x80U))
51 #define CAL_CSI2_VC_IRQENABLE(m) (0x318U + ((m-1) * 0x80U))
52 #define CAL_CSI2_VC_IRQSTATUS(m) (0x328U + ((m-1) * 0x80U))
53 #define CAL_CSI2_CTX0(m) (0x330U + ((m-1) * 0x80U))
54 #define CAL_CSI2_CTX1(m) (0x334U + ((m-1) * 0x80U))
55 #define CAL_CSI2_CTX2(m) (0x338U + ((m-1) * 0x80U))
56 #define CAL_CSI2_CTX3(m) (0x33cU + ((m-1) * 0x80U))
57 #define CAL_CSI2_CTX4(m) (0x340U + ((m-1) * 0x80U))
58 #define CAL_CSI2_CTX5(m) (0x344U + ((m-1) * 0x80U))
59 #define CAL_CSI2_CTX6(m) (0x348U + ((m-1) * 0x80U))
60 #define CAL_CSI2_CTX7(m) (0x34cU + ((m-1) * 0x80U))
61 #define CAL_CSI2_STATUS0(m) (0x350U + ((m-1) * 0x80U))
62 #define CAL_CSI2_STATUS1(m) (0x354U + ((m-1) * 0x80U))
63 #define CAL_CSI2_STATUS2(m) (0x358U + ((m-1) * 0x80U))
64 #define CAL_CSI2_STATUS3(m) (0x35cU + ((m-1) * 0x80U))
65 #define CAL_CSI2_STATUS4(m) (0x360U + ((m-1) * 0x80U))
66 #define CAL_CSI2_STATUS5(m) (0x364U + ((m-1) * 0x80U))
67 #define CAL_CSI2_STATUS6(m) (0x368U + ((m-1) * 0x80U))
68 #define CAL_CSI2_STATUS7(m) (0x36cU + ((m-1) * 0x80U))
69
70
71 #define CAL_CSI2_PHY_REG0 0x000
72 #define CAL_CSI2_PHY_REG1 0x004
73 #define CAL_CSI2_PHY_REG2 0x008
74
75
76 #define CM_CTRL_CORE_CAMERRX_CONTROL 0x000
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81
82 #define CAL_GEN_DISABLE 0
83 #define CAL_GEN_ENABLE 1
84 #define CAL_GEN_FALSE 0
85 #define CAL_GEN_TRUE 1
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90
91 #define CAL_HL_REVISION_MINOR_MASK GENMASK(5, 0)
92 #define CAL_HL_REVISION_CUSTOM_MASK GENMASK(7, 6)
93 #define CAL_HL_REVISION_MAJOR_MASK GENMASK(10, 8)
94 #define CAL_HL_REVISION_RTL_MASK GENMASK(15, 11)
95 #define CAL_HL_REVISION_FUNC_MASK GENMASK(27, 16)
96 #define CAL_HL_REVISION_SCHEME_MASK GENMASK(31, 30)
97 #define CAL_HL_REVISION_SCHEME_H08 1
98 #define CAL_HL_REVISION_SCHEME_LEGACY 0
99
100 #define CAL_HL_HWINFO_WFIFO_MASK GENMASK(3, 0)
101 #define CAL_HL_HWINFO_RFIFO_MASK GENMASK(7, 4)
102 #define CAL_HL_HWINFO_PCTX_MASK GENMASK(12, 8)
103 #define CAL_HL_HWINFO_WCTX_MASK GENMASK(18, 13)
104 #define CAL_HL_HWINFO_VFIFO_MASK GENMASK(22, 19)
105 #define CAL_HL_HWINFO_NCPORT_MASK GENMASK(27, 23)
106 #define CAL_HL_HWINFO_NPPI_CTXS0_MASK GENMASK(29, 28)
107 #define CAL_HL_HWINFO_NPPI_CTXS1_MASK GENMASK(31, 30)
108 #define CAL_HL_HWINFO_NPPI_CONTEXTS_ZERO 0
109 #define CAL_HL_HWINFO_NPPI_CONTEXTS_FOUR 1
110 #define CAL_HL_HWINFO_NPPI_CONTEXTS_EIGHT 2
111 #define CAL_HL_HWINFO_NPPI_CONTEXTS_RESERVED 3
112
113 #define CAL_HL_SYSCONFIG_SOFTRESET_MASK BIT_MASK(0)
114 #define CAL_HL_SYSCONFIG_SOFTRESET_DONE 0x0
115 #define CAL_HL_SYSCONFIG_SOFTRESET_PENDING 0x1
116 #define CAL_HL_SYSCONFIG_SOFTRESET_NOACTION 0x0
117 #define CAL_HL_SYSCONFIG_SOFTRESET_RESET 0x1
118 #define CAL_HL_SYSCONFIG_IDLE_MASK GENMASK(3, 2)
119 #define CAL_HL_SYSCONFIG_IDLEMODE_FORCE 0
120 #define CAL_HL_SYSCONFIG_IDLEMODE_NO 1
121 #define CAL_HL_SYSCONFIG_IDLEMODE_SMART1 2
122 #define CAL_HL_SYSCONFIG_IDLEMODE_SMART2 3
123
124 #define CAL_HL_IRQ_EOI_LINE_NUMBER_MASK BIT_MASK(0)
125 #define CAL_HL_IRQ_EOI_LINE_NUMBER_READ0 0
126 #define CAL_HL_IRQ_EOI_LINE_NUMBER_EOI0 0
127
128 #define CAL_HL_IRQ_MASK(m) BIT_MASK(m-1)
129 #define CAL_HL_IRQ_NOACTION 0x0
130 #define CAL_HL_IRQ_ENABLE 0x1
131 #define CAL_HL_IRQ_CLEAR 0x1
132 #define CAL_HL_IRQ_DISABLED 0x0
133 #define CAL_HL_IRQ_ENABLED 0x1
134 #define CAL_HL_IRQ_PENDING 0x1
135
136 #define CAL_PIX_PROC_EN_MASK BIT_MASK(0)
137 #define CAL_PIX_PROC_EXTRACT_MASK GENMASK(4, 1)
138 #define CAL_PIX_PROC_EXTRACT_B6 0x0
139 #define CAL_PIX_PROC_EXTRACT_B7 0x1
140 #define CAL_PIX_PROC_EXTRACT_B8 0x2
141 #define CAL_PIX_PROC_EXTRACT_B10 0x3
142 #define CAL_PIX_PROC_EXTRACT_B10_MIPI 0x4
143 #define CAL_PIX_PROC_EXTRACT_B12 0x5
144 #define CAL_PIX_PROC_EXTRACT_B12_MIPI 0x6
145 #define CAL_PIX_PROC_EXTRACT_B14 0x7
146 #define CAL_PIX_PROC_EXTRACT_B14_MIPI 0x8
147 #define CAL_PIX_PROC_EXTRACT_B16_BE 0x9
148 #define CAL_PIX_PROC_EXTRACT_B16_LE 0xa
149 #define CAL_PIX_PROC_DPCMD_MASK GENMASK(9, 5)
150 #define CAL_PIX_PROC_DPCMD_BYPASS 0x0
151 #define CAL_PIX_PROC_DPCMD_DPCM_10_8_1 0x2
152 #define CAL_PIX_PROC_DPCMD_DPCM_12_8_1 0x8
153 #define CAL_PIX_PROC_DPCMD_DPCM_10_7_1 0x4
154 #define CAL_PIX_PROC_DPCMD_DPCM_10_7_2 0x5
155 #define CAL_PIX_PROC_DPCMD_DPCM_10_6_1 0x6
156 #define CAL_PIX_PROC_DPCMD_DPCM_10_6_2 0x7
157 #define CAL_PIX_PROC_DPCMD_DPCM_12_7_1 0xa
158 #define CAL_PIX_PROC_DPCMD_DPCM_12_6_1 0xc
159 #define CAL_PIX_PROC_DPCMD_DPCM_14_10 0xe
160 #define CAL_PIX_PROC_DPCMD_DPCM_14_8_1 0x10
161 #define CAL_PIX_PROC_DPCMD_DPCM_16_12_1 0x12
162 #define CAL_PIX_PROC_DPCMD_DPCM_16_10_1 0x14
163 #define CAL_PIX_PROC_DPCMD_DPCM_16_8_1 0x16
164 #define CAL_PIX_PROC_DPCME_MASK GENMASK(15, 11)
165 #define CAL_PIX_PROC_DPCME_BYPASS 0x0
166 #define CAL_PIX_PROC_DPCME_DPCM_10_8_1 0x2
167 #define CAL_PIX_PROC_DPCME_DPCM_12_8_1 0x8
168 #define CAL_PIX_PROC_DPCME_DPCM_14_10 0xe
169 #define CAL_PIX_PROC_DPCME_DPCM_14_8_1 0x10
170 #define CAL_PIX_PROC_DPCME_DPCM_16_12_1 0x12
171 #define CAL_PIX_PROC_DPCME_DPCM_16_10_1 0x14
172 #define CAL_PIX_PROC_DPCME_DPCM_16_8_1 0x16
173 #define CAL_PIX_PROC_PACK_MASK GENMASK(18, 16)
174 #define CAL_PIX_PROC_PACK_B8 0x0
175 #define CAL_PIX_PROC_PACK_B10_MIPI 0x2
176 #define CAL_PIX_PROC_PACK_B12 0x3
177 #define CAL_PIX_PROC_PACK_B12_MIPI 0x4
178 #define CAL_PIX_PROC_PACK_B16 0x5
179 #define CAL_PIX_PROC_PACK_ARGB 0x6
180 #define CAL_PIX_PROC_CPORT_MASK GENMASK(23, 19)
181
182 #define CAL_CTRL_POSTED_WRITES_MASK BIT_MASK(0)
183 #define CAL_CTRL_POSTED_WRITES_NONPOSTED 0
184 #define CAL_CTRL_POSTED_WRITES 1
185 #define CAL_CTRL_TAGCNT_MASK GENMASK(4, 1)
186 #define CAL_CTRL_BURSTSIZE_MASK GENMASK(6, 5)
187 #define CAL_CTRL_BURSTSIZE_BURST16 0x0
188 #define CAL_CTRL_BURSTSIZE_BURST32 0x1
189 #define CAL_CTRL_BURSTSIZE_BURST64 0x2
190 #define CAL_CTRL_BURSTSIZE_BURST128 0x3
191 #define CAL_CTRL_LL_FORCE_STATE_MASK GENMASK(12, 7)
192 #define CAL_CTRL_MFLAGL_MASK GENMASK(20, 13)
193 #define CAL_CTRL_PWRSCPCLK_MASK BIT_MASK(21)
194 #define CAL_CTRL_PWRSCPCLK_AUTO 0
195 #define CAL_CTRL_PWRSCPCLK_FORCE 1
196 #define CAL_CTRL_RD_DMA_STALL_MASK BIT_MASK(22)
197 #define CAL_CTRL_MFLAGH_MASK GENMASK(31, 24)
198
199 #define CAL_CTRL1_PPI_GROUPING_MASK GENMASK(1, 0)
200 #define CAL_CTRL1_PPI_GROUPING_DISABLED 0
201 #define CAL_CTRL1_PPI_GROUPING_RESERVED 1
202 #define CAL_CTRL1_PPI_GROUPING_0 2
203 #define CAL_CTRL1_PPI_GROUPING_1 3
204 #define CAL_CTRL1_INTERLEAVE01_MASK GENMASK(3, 2)
205 #define CAL_CTRL1_INTERLEAVE01_DISABLED 0
206 #define CAL_CTRL1_INTERLEAVE01_PIX1 1
207 #define CAL_CTRL1_INTERLEAVE01_PIX4 2
208 #define CAL_CTRL1_INTERLEAVE01_RESERVED 3
209 #define CAL_CTRL1_INTERLEAVE23_MASK GENMASK(5, 4)
210 #define CAL_CTRL1_INTERLEAVE23_DISABLED 0
211 #define CAL_CTRL1_INTERLEAVE23_PIX1 1
212 #define CAL_CTRL1_INTERLEAVE23_PIX4 2
213 #define CAL_CTRL1_INTERLEAVE23_RESERVED 3
214
215 #define CAL_LINE_NUMBER_EVT_CPORT_MASK GENMASK(4, 0)
216 #define CAL_LINE_NUMBER_EVT_MASK GENMASK(29, 16)
217
218 #define CAL_VPORT_CTRL1_PCLK_MASK GENMASK(16, 0)
219 #define CAL_VPORT_CTRL1_XBLK_MASK GENMASK(24, 17)
220 #define CAL_VPORT_CTRL1_YBLK_MASK GENMASK(30, 25)
221 #define CAL_VPORT_CTRL1_WIDTH_MASK BIT_MASK(31)
222 #define CAL_VPORT_CTRL1_WIDTH_ONE 0
223 #define CAL_VPORT_CTRL1_WIDTH_TWO 1
224
225 #define CAL_VPORT_CTRL2_CPORT_MASK GENMASK(4, 0)
226 #define CAL_VPORT_CTRL2_FREERUNNING_MASK BIT_MASK(15)
227 #define CAL_VPORT_CTRL2_FREERUNNING_GATED 0
228 #define CAL_VPORT_CTRL2_FREERUNNING_FREE 1
229 #define CAL_VPORT_CTRL2_FS_RESETS_MASK BIT_MASK(16)
230 #define CAL_VPORT_CTRL2_FS_RESETS_NO 0
231 #define CAL_VPORT_CTRL2_FS_RESETS_YES 1
232 #define CAL_VPORT_CTRL2_FSM_RESET_MASK BIT_MASK(17)
233 #define CAL_VPORT_CTRL2_FSM_RESET_NOEFFECT 0
234 #define CAL_VPORT_CTRL2_FSM_RESET 1
235 #define CAL_VPORT_CTRL2_RDY_THR_MASK GENMASK(31, 18)
236
237 #define CAL_BYS_CTRL1_PCLK_MASK GENMASK(16, 0)
238 #define CAL_BYS_CTRL1_XBLK_MASK GENMASK(24, 17)
239 #define CAL_BYS_CTRL1_YBLK_MASK GENMASK(30, 25)
240 #define CAL_BYS_CTRL1_BYSINEN_MASK BIT_MASK(31)
241
242 #define CAL_BYS_CTRL2_CPORTIN_MASK GENMASK(4, 0)
243 #define CAL_BYS_CTRL2_CPORTOUT_MASK GENMASK(9, 5)
244 #define CAL_BYS_CTRL2_DUPLICATEDDATA_MASK BIT_MASK(10)
245 #define CAL_BYS_CTRL2_DUPLICATEDDATA_NO 0
246 #define CAL_BYS_CTRL2_DUPLICATEDDATA_YES 1
247 #define CAL_BYS_CTRL2_FREERUNNING_MASK BIT_MASK(11)
248 #define CAL_BYS_CTRL2_FREERUNNING_NO 0
249 #define CAL_BYS_CTRL2_FREERUNNING_YES 1
250
251 #define CAL_RD_DMA_CTRL_GO_MASK BIT_MASK(0)
252 #define CAL_RD_DMA_CTRL_GO_DIS 0
253 #define CAL_RD_DMA_CTRL_GO_EN 1
254 #define CAL_RD_DMA_CTRL_GO_IDLE 0
255 #define CAL_RD_DMA_CTRL_GO_BUSY 1
256 #define CAL_RD_DMA_CTRL_INIT_MASK BIT_MASK(1)
257 #define CAL_RD_DMA_CTRL_BW_LIMITER_MASK GENMASK(10, 2)
258 #define CAL_RD_DMA_CTRL_OCP_TAG_CNT_MASK GENMASK(14, 11)
259 #define CAL_RD_DMA_CTRL_PCLK_MASK GENMASK(31, 15)
260
261 #define CAL_RD_DMA_PIX_ADDR_MASK GENMASK(31, 3)
262
263 #define CAL_RD_DMA_PIX_OFST_MASK GENMASK(31, 4)
264
265 #define CAL_RD_DMA_XSIZE_MASK GENMASK(31, 19)
266
267 #define CAL_RD_DMA_YSIZE_MASK GENMASK(29, 16)
268
269 #define CAL_RD_DMA_INIT_ADDR_MASK GENMASK(31, 3)
270
271 #define CAL_RD_DMA_INIT_OFST_MASK GENMASK(31, 3)
272
273 #define CAL_RD_DMA_CTRL2_CIRC_MODE_MASK GENMASK(2, 0)
274 #define CAL_RD_DMA_CTRL2_CIRC_MODE_DIS 0
275 #define CAL_RD_DMA_CTRL2_CIRC_MODE_ONE 1
276 #define CAL_RD_DMA_CTRL2_CIRC_MODE_FOUR 2
277 #define CAL_RD_DMA_CTRL2_CIRC_MODE_SIXTEEN 3
278 #define CAL_RD_DMA_CTRL2_CIRC_MODE_SIXTYFOUR 4
279 #define CAL_RD_DMA_CTRL2_CIRC_MODE_RESERVED 5
280 #define CAL_RD_DMA_CTRL2_ICM_CSTART_MASK BIT_MASK(3)
281 #define CAL_RD_DMA_CTRL2_PATTERN_MASK GENMASK(5, 4)
282 #define CAL_RD_DMA_CTRL2_PATTERN_LINEAR 0
283 #define CAL_RD_DMA_CTRL2_PATTERN_YUV420 1
284 #define CAL_RD_DMA_CTRL2_PATTERN_RD2SKIP2 2
285 #define CAL_RD_DMA_CTRL2_PATTERN_RD2SKIP4 3
286 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_MASK BIT_MASK(6)
287 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_FREERUNNING 0
288 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_WAITFORBYSOUT 1
289 #define CAL_RD_DMA_CTRL2_CIRC_SIZE_MASK GENMASK(29, 16)
290
291 #define CAL_WR_DMA_CTRL_MODE_MASK GENMASK(2, 0)
292 #define CAL_WR_DMA_CTRL_MODE_DIS 0
293 #define CAL_WR_DMA_CTRL_MODE_SHD 1
294 #define CAL_WR_DMA_CTRL_MODE_CNT 2
295 #define CAL_WR_DMA_CTRL_MODE_CNT_INIT 3
296 #define CAL_WR_DMA_CTRL_MODE_CONST 4
297 #define CAL_WR_DMA_CTRL_MODE_RESERVED 5
298 #define CAL_WR_DMA_CTRL_PATTERN_MASK GENMASK(4, 3)
299 #define CAL_WR_DMA_CTRL_PATTERN_LINEAR 0
300 #define CAL_WR_DMA_CTRL_PATTERN_WR2SKIP2 2
301 #define CAL_WR_DMA_CTRL_PATTERN_WR2SKIP4 3
302 #define CAL_WR_DMA_CTRL_PATTERN_RESERVED 1
303 #define CAL_WR_DMA_CTRL_ICM_PSTART_MASK BIT_MASK(5)
304 #define CAL_WR_DMA_CTRL_DTAG_MASK GENMASK(8, 6)
305 #define CAL_WR_DMA_CTRL_DTAG_ATT_HDR 0
306 #define CAL_WR_DMA_CTRL_DTAG_ATT_DAT 1
307 #define CAL_WR_DMA_CTRL_DTAG 2
308 #define CAL_WR_DMA_CTRL_DTAG_PIX_HDR 3
309 #define CAL_WR_DMA_CTRL_DTAG_PIX_DAT 4
310 #define CAL_WR_DMA_CTRL_DTAG_D5 5
311 #define CAL_WR_DMA_CTRL_DTAG_D6 6
312 #define CAL_WR_DMA_CTRL_DTAG_D7 7
313 #define CAL_WR_DMA_CTRL_CPORT_MASK GENMASK(13, 9)
314 #define CAL_WR_DMA_CTRL_STALL_RD_MASK BIT_MASK(14)
315 #define CAL_WR_DMA_CTRL_YSIZE_MASK GENMASK(31, 18)
316
317 #define CAL_WR_DMA_ADDR_MASK GENMASK(31, 4)
318
319 #define CAL_WR_DMA_OFST_MASK GENMASK(18, 4)
320 #define CAL_WR_DMA_OFST_CIRC_MODE_MASK GENMASK(23, 22)
321 #define CAL_WR_DMA_OFST_CIRC_MODE_ONE 1
322 #define CAL_WR_DMA_OFST_CIRC_MODE_FOUR 2
323 #define CAL_WR_DMA_OFST_CIRC_MODE_SIXTYFOUR 3
324 #define CAL_WR_DMA_OFST_CIRC_MODE_DISABLED 0
325 #define CAL_WR_DMA_OFST_CIRC_SIZE_MASK GENMASK(31, 24)
326
327 #define CAL_WR_DMA_XSIZE_XSKIP_MASK GENMASK(15, 3)
328 #define CAL_WR_DMA_XSIZE_MASK GENMASK(31, 19)
329
330 #define CAL_CSI2_PPI_CTRL_IF_EN_MASK BIT_MASK(0)
331 #define CAL_CSI2_PPI_CTRL_ECC_EN_MASK BIT_MASK(2)
332 #define CAL_CSI2_PPI_CTRL_FRAME_MASK BIT_MASK(3)
333 #define CAL_CSI2_PPI_CTRL_FRAME_IMMEDIATE 0
334 #define CAL_CSI2_PPI_CTRL_FRAME 1
335
336 #define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK GENMASK(2, 0)
337 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_5 5
338 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_4 4
339 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_3 3
340 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_2 2
341 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_1 1
342 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_NOT_USED 0
343 #define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK BIT_MASK(3)
344 #define CAL_CSI2_COMPLEXIO_CFG_POL_PLUSMINUS 0
345 #define CAL_CSI2_COMPLEXIO_CFG_POL_MINUSPLUS 1
346 #define CAL_CSI2_COMPLEXIO_CFG_DATA1_POSITION_MASK GENMASK(6, 4)
347 #define CAL_CSI2_COMPLEXIO_CFG_DATA1_POL_MASK BIT_MASK(7)
348 #define CAL_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK GENMASK(10, 8)
349 #define CAL_CSI2_COMPLEXIO_CFG_DATA2_POL_MASK BIT_MASK(11)
350 #define CAL_CSI2_COMPLEXIO_CFG_DATA3_POSITION_MASK GENMASK(14, 12)
351 #define CAL_CSI2_COMPLEXIO_CFG_DATA3_POL_MASK BIT_MASK(15)
352 #define CAL_CSI2_COMPLEXIO_CFG_DATA4_POSITION_MASK GENMASK(18, 16)
353 #define CAL_CSI2_COMPLEXIO_CFG_DATA4_POL_MASK BIT_MASK(19)
354 #define CAL_CSI2_COMPLEXIO_CFG_PWR_AUTO_MASK BIT_MASK(24)
355 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK GENMASK(26, 25)
356 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_OFF 0
357 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ON 1
358 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ULP 2
359 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK GENMASK(28, 27)
360 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF 0
361 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON 1
362 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ULP 2
363 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK BIT_MASK(29)
364 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED 1
365 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETONGOING 0
366 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK BIT_MASK(30)
367 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL 0
368 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL 1
369
370 #define CAL_CSI2_SHORT_PACKET_MASK GENMASK(23, 0)
371
372 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS1_MASK BIT_MASK(0)
373 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS2_MASK BIT_MASK(1)
374 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS3_MASK BIT_MASK(2)
375 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS4_MASK BIT_MASK(3)
376 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS5_MASK BIT_MASK(4)
377 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1_MASK BIT_MASK(5)
378 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2_MASK BIT_MASK(6)
379 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3_MASK BIT_MASK(7)
380 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4_MASK BIT_MASK(8)
381 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5_MASK BIT_MASK(9)
382 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC1_MASK BIT_MASK(10)
383 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC2_MASK BIT_MASK(11)
384 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC3_MASK BIT_MASK(12)
385 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC4_MASK BIT_MASK(13)
386 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC5_MASK BIT_MASK(14)
387 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL1_MASK BIT_MASK(15)
388 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL2_MASK BIT_MASK(16)
389 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL3_MASK BIT_MASK(17)
390 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL4_MASK BIT_MASK(18)
391 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL5_MASK BIT_MASK(19)
392 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM1_MASK BIT_MASK(20)
393 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM2_MASK BIT_MASK(21)
394 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM3_MASK BIT_MASK(22)
395 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM4_MASK BIT_MASK(23)
396 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM5_MASK BIT_MASK(24)
397 #define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER_MASK BIT_MASK(25)
398 #define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT_MASK BIT_MASK(26)
399 #define CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK BIT_MASK(27)
400 #define CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK BIT_MASK(28)
401 #define CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK BIT_MASK(30)
402
403 #define CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK GENMASK(12, 0)
404 #define CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK BIT_MASK(13)
405 #define CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK BIT_MASK(14)
406 #define CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK BIT_MASK(15)
407
408 #define CAL_CSI2_VC_IRQ_FS_IRQ_0_MASK BIT_MASK(0)
409 #define CAL_CSI2_VC_IRQ_FE_IRQ_0_MASK BIT_MASK(1)
410 #define CAL_CSI2_VC_IRQ_LS_IRQ_0_MASK BIT_MASK(2)
411 #define CAL_CSI2_VC_IRQ_LE_IRQ_0_MASK BIT_MASK(3)
412 #define CAL_CSI2_VC_IRQ_CS_IRQ_0_MASK BIT_MASK(4)
413 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_0_MASK BIT_MASK(5)
414 #define CAL_CSI2_VC_IRQ_FS_IRQ_1_MASK BIT_MASK(8)
415 #define CAL_CSI2_VC_IRQ_FE_IRQ_1_MASK BIT_MASK(9)
416 #define CAL_CSI2_VC_IRQ_LS_IRQ_1_MASK BIT_MASK(10)
417 #define CAL_CSI2_VC_IRQ_LE_IRQ_1_MASK BIT_MASK(11)
418 #define CAL_CSI2_VC_IRQ_CS_IRQ_1_MASK BIT_MASK(12)
419 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_1_MASK BIT_MASK(13)
420 #define CAL_CSI2_VC_IRQ_FS_IRQ_2_MASK BIT_MASK(16)
421 #define CAL_CSI2_VC_IRQ_FE_IRQ_2_MASK BIT_MASK(17)
422 #define CAL_CSI2_VC_IRQ_LS_IRQ_2_MASK BIT_MASK(18)
423 #define CAL_CSI2_VC_IRQ_LE_IRQ_2_MASK BIT_MASK(19)
424 #define CAL_CSI2_VC_IRQ_CS_IRQ_2_MASK BIT_MASK(20)
425 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_2_MASK BIT_MASK(21)
426 #define CAL_CSI2_VC_IRQ_FS_IRQ_3_MASK BIT_MASK(24)
427 #define CAL_CSI2_VC_IRQ_FE_IRQ_3_MASK BIT_MASK(25)
428 #define CAL_CSI2_VC_IRQ_LS_IRQ_3_MASK BIT_MASK(26)
429 #define CAL_CSI2_VC_IRQ_LE_IRQ_3_MASK BIT_MASK(27)
430 #define CAL_CSI2_VC_IRQ_CS_IRQ_3_MASK BIT_MASK(28)
431 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_3_MASK BIT_MASK(29)
432
433 #define CAL_CSI2_CTX_DT_MASK GENMASK(5, 0)
434 #define CAL_CSI2_CTX_VC_MASK GENMASK(7, 6)
435 #define CAL_CSI2_CTX_CPORT_MASK GENMASK(12, 8)
436 #define CAL_CSI2_CTX_ATT_MASK BIT_MASK(13)
437 #define CAL_CSI2_CTX_ATT_PIX 0
438 #define CAL_CSI2_CTX_ATT 1
439 #define CAL_CSI2_CTX_PACK_MODE_MASK BIT_MASK(14)
440 #define CAL_CSI2_CTX_PACK_MODE_LINE 0
441 #define CAL_CSI2_CTX_PACK_MODE_FRAME 1
442 #define CAL_CSI2_CTX_LINES_MASK GENMASK(29, 16)
443
444 #define CAL_CSI2_STATUS_FRAME_MASK GENMASK(15, 0)
445
446 #define CAL_CSI2_PHY_REG0_THS_SETTLE_MASK GENMASK(7, 0)
447 #define CAL_CSI2_PHY_REG0_THS_TERM_MASK GENMASK(15, 8)
448 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK BIT_MASK(24)
449 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE 1
450 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_ENABLE 0
451
452 #define CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK GENMASK(7, 0)
453 #define CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK GENMASK(9, 8)
454 #define CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK GENMASK(17, 10)
455 #define CAL_CSI2_PHY_REG1_TCLK_TERM_MASK GENMASK(24, 18)
456 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_MASK BIT_MASK(25)
457 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_ERROR 1
458 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_SUCCESS 0
459 #define CAL_CSI2_PHY_REG1_RESET_DONE_STATUS_MASK GENMASK(29, 28)
460
461 #define CAL_CSI2_PHY_REG2_CCP2_SYNC_PATTERN_MASK GENMASK(23, 0)
462 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK GENMASK(25, 24)
463 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK GENMASK(27, 26)
464 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK GENMASK(29, 28)
465 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK GENMASK(31, 30)
466
467 #define CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK BIT_MASK(0)
468 #define CM_CAMERRX_CTRL_CSI1_CAMMODE_MASK GENMASK(2, 1)
469 #define CM_CAMERRX_CTRL_CSI1_LANEENABLE_MASK GENMASK(4, 3)
470 #define CM_CAMERRX_CTRL_CSI1_MODE_MASK BIT_MASK(5)
471 #define CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK BIT_MASK(10)
472 #define CM_CAMERRX_CTRL_CSI0_CAMMODE_MASK GENMASK(12, 11)
473 #define CM_CAMERRX_CTRL_CSI0_LANEENABLE_MASK GENMASK(16, 13)
474 #define CM_CAMERRX_CTRL_CSI0_MODE_MASK BIT_MASK(17)
475
476 #endif