1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Xilinx Video DMA
4 *
5 * Copyright (C) 2013-2015 Ideas on Board
6 * Copyright (C) 2013-2015 Xilinx, Inc.
7 *
8 * Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 */
11
12 #ifndef __XILINX_VIP_DMA_H__
13 #define __XILINX_VIP_DMA_H__
14
15 #include <linux/dmaengine.h>
16 #include <linux/mutex.h>
17 #include <linux/spinlock.h>
18 #include <linux/videodev2.h>
19
20 #include <media/media-entity.h>
21 #include <media/v4l2-dev.h>
22 #include <media/videobuf2-v4l2.h>
23
24 struct dma_chan;
25 struct xvip_composite_device;
26 struct xvip_video_format;
27
28 /**
29 * struct xvip_pipeline - Xilinx Video IP pipeline structure
30 * @pipe: media pipeline
31 * @lock: protects the pipeline @stream_count
32 * @use_count: number of DMA engines using the pipeline
33 * @stream_count: number of DMA engines currently streaming
34 * @num_dmas: number of DMA engines in the pipeline
35 * @output: DMA engine at the output of the pipeline
36 */
37 struct xvip_pipeline {
38 struct media_pipeline pipe;
39
40 struct mutex lock;
41 unsigned int use_count;
42 unsigned int stream_count;
43
44 unsigned int num_dmas;
45 struct xvip_dma *output;
46 };
47
48 static inline struct xvip_pipeline *to_xvip_pipeline(struct media_entity *e)
49 {
50 return container_of(e->pipe, struct xvip_pipeline, pipe);
51 }
52
53 /**
54 * struct xvip_dma - Video DMA channel
55 * @list: list entry in a composite device dmas list
56 * @video: V4L2 video device associated with the DMA channel
57 * @pad: media pad for the video device entity
58 * @xdev: composite device the DMA channel belongs to
59 * @pipe: pipeline belonging to the DMA channel
60 * @port: composite device DT node port number for the DMA channel
61 * @lock: protects the @format, @fmtinfo and @queue fields
62 * @format: active V4L2 pixel format
63 * @fmtinfo: format information corresponding to the active @format
64 * @queue: vb2 buffers queue
65 * @sequence: V4L2 buffers sequence number
66 * @queued_bufs: list of queued buffers
67 * @queued_lock: protects the buf_queued list
68 * @dma: DMA engine channel
69 * @align: transfer alignment required by the DMA channel (in bytes)
70 * @xt: dma interleaved template for dma configuration
71 * @sgl: data chunk structure for dma_interleaved_template
72 */
73 struct xvip_dma {
74 struct list_head list;
75 struct video_device video;
76 struct media_pad pad;
77
78 struct xvip_composite_device *xdev;
79 struct xvip_pipeline pipe;
80 unsigned int port;
81
82 struct mutex lock;
83 struct v4l2_pix_format format;
84 const struct xvip_video_format *fmtinfo;
85
86 struct vb2_queue queue;
87 unsigned int sequence;
88
89 struct list_head queued_bufs;
90 spinlock_t queued_lock;
91
92 struct dma_chan *dma;
93 unsigned int align;
94 struct dma_interleaved_template xt;
95 struct data_chunk sgl[1];
96 };
97
98 #define to_xvip_dma(vdev) container_of(vdev, struct xvip_dma, video)
99
100 int xvip_dma_init(struct xvip_composite_device *xdev, struct xvip_dma *dma,
101 enum v4l2_buf_type type, unsigned int port);
102 void xvip_dma_cleanup(struct xvip_dma *dma);
103
104 #endif /* __XILINX_VIP_DMA_H__ */