1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * omap3isp.h
4 *
5 * TI OMAP3 ISP - Bus Configuration
6 *
7 * Copyright (C) 2011 Nokia Corporation
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 */
12
13 #ifndef __OMAP3ISP_H__
14 #define __OMAP3ISP_H__
15
16 enum isp_interface_type {
17 ISP_INTERFACE_PARALLEL,
18 ISP_INTERFACE_CSI2A_PHY2,
19 ISP_INTERFACE_CCP2B_PHY1,
20 ISP_INTERFACE_CCP2B_PHY2,
21 ISP_INTERFACE_CSI2C_PHY1,
22 };
23
24 /**
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
31 * @clk_pol: Pixel clock polarity
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
33 * @hs_pol: Horizontal synchronization polarity
34 * 0 - Active high, 1 - Active low
35 * @vs_pol: Vertical synchronization polarity
36 * 0 - Active high, 1 - Active low
37 * @fld_pol: Field signal polarity
38 * 0 - Positive, 1 - Negative
39 * @data_pol: Data polarity
40 * 0 - Normal, 1 - One's complement
41 * @bt656: Data contain BT.656 embedded synchronization
42 */
43 struct isp_parallel_cfg {
44 unsigned int data_lane_shift:3;
45 unsigned int clk_pol:1;
46 unsigned int hs_pol:1;
47 unsigned int vs_pol:1;
48 unsigned int fld_pol:1;
49 unsigned int data_pol:1;
50 unsigned int bt656:1;
51 };
52
53 enum {
54 ISP_CCP2_PHY_DATA_CLOCK = 0,
55 ISP_CCP2_PHY_DATA_STROBE = 1,
56 };
57
58 enum {
59 ISP_CCP2_MODE_MIPI = 0,
60 ISP_CCP2_MODE_CCP2 = 1,
61 };
62
63 /**
64 * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity
65 * @pos: position of the lane
66 * @pol: polarity of the lane
67 */
68 struct isp_csiphy_lane {
69 u8 pos;
70 u8 pol;
71 };
72
73 #define ISP_CSIPHY1_NUM_DATA_LANES 1
74 #define ISP_CSIPHY2_NUM_DATA_LANES 2
75
76 /**
77 * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration
78 * @data: Configuration of one or two data lanes
79 * @clk: Clock lane configuration
80 */
81 struct isp_csiphy_lanes_cfg {
82 struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES];
83 struct isp_csiphy_lane clk;
84 };
85
86 /**
87 * struct isp_ccp2_cfg - CCP2 interface configuration
88 * @strobe_clk_pol: Strobe/clock polarity
89 * 0 - Non Inverted, 1 - Inverted
90 * @crc: Enable the cyclic redundancy check
91 * @ccp2_mode: Enable CCP2 compatibility mode
92 * ISP_CCP2_MODE_MIPI - MIPI-CSI1 mode
93 * ISP_CCP2_MODE_CCP2 - CCP2 mode
94 * @phy_layer: Physical layer selection
95 * ISP_CCP2_PHY_DATA_CLOCK - Data/clock physical layer
96 * ISP_CCP2_PHY_DATA_STROBE - Data/strobe physical layer
97 * @vpclk_div: Video port output clock control
98 */
99 struct isp_ccp2_cfg {
100 unsigned int strobe_clk_pol:1;
101 unsigned int crc:1;
102 unsigned int ccp2_mode:1;
103 unsigned int phy_layer:1;
104 unsigned int vpclk_div:2;
105 unsigned int vp_clk_pol:1;
106 struct isp_csiphy_lanes_cfg lanecfg;
107 };
108
109 /**
110 * struct isp_csi2_cfg - CSI2 interface configuration
111 * @crc: Enable the cyclic redundancy check
112 * @lanecfg: CSI-2 lane configuration
113 * @num_data_lanes: The number of data lanes in use
114 */
115 struct isp_csi2_cfg {
116 unsigned crc:1;
117 struct isp_csiphy_lanes_cfg lanecfg;
118 u8 num_data_lanes;
119 };
120
121 struct isp_bus_cfg {
122 enum isp_interface_type interface;
123 union {
124 struct isp_parallel_cfg parallel;
125 struct isp_ccp2_cfg ccp2;
126 struct isp_csi2_cfg csi2;
127 } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
128 };
129
130 #endif /* __OMAP3ISP_H__ */