1 /* 2 * Cobalt IRQ definitions. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1997 Cobalt Microserver 9 * Copyright (C) 1997, 2003 Ralf Baechle 10 * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv) 11 * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org> 12 */ 13 #ifndef _ASM_COBALT_IRQ_H 14 #define _ASM_COBALT_IRQ_H 15 16 /* 17 * i8259 interrupts used on Cobalt: 18 * 19 * 8 - RTC 20 * 9 - PCI slot 21 * 14 - IDE0 22 * 15 - IDE1(no connector on board) 23 */ 24 #define I8259A_IRQ_BASE 0 25 26 #define PCISLOT_IRQ (I8259A_IRQ_BASE + 9) 27 28 /* 29 * CPU interrupts used on Cobalt: 30 * 31 * 0 - Software interrupt 0 (unused) 32 * 1 - Software interrupt 0 (unused) 33 * 2 - cascade GT64111 34 * 3 - ethernet or SCSI host controller 35 * 4 - ethernet 36 * 5 - 16550 UART 37 * 6 - cascade i8259 38 * 7 - CP0 counter 39 */ 40 #define MIPS_CPU_IRQ_BASE 16 41 42 #define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) 43 #define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3) 44 #define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3) 45 #define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4) 46 #define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4) 47 #define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5) 48 #define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) 49 #define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) 50 51 #define GT641XX_IRQ_BASE 24 52 53 #include <asm/irq_gt641xx.h> 54 55 #define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1) 56 57 #endif /* _ASM_COBALT_IRQ_H */