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35 #ifndef I40IW_D_H
36 #define I40IW_D_H
37
38 #define I40IW_FIRST_USER_QP_ID 2
39
40 #define I40IW_DB_ADDR_OFFSET (4 * 1024 * 1024 - 64 * 1024)
41 #define I40IW_VF_DB_ADDR_OFFSET (64 * 1024)
42
43 #define I40IW_PUSH_OFFSET (4 * 1024 * 1024)
44 #define I40IW_PF_FIRST_PUSH_PAGE_INDEX 16
45 #define I40IW_VF_PUSH_OFFSET ((8 + 64) * 1024)
46 #define I40IW_VF_FIRST_PUSH_PAGE_INDEX 2
47
48 #define I40IW_PE_DB_SIZE_4M 1
49 #define I40IW_PE_DB_SIZE_8M 2
50
51 #define I40IW_DDP_VER 1
52 #define I40IW_RDMAP_VER 1
53
54 #define I40IW_RDMA_MODE_RDMAC 0
55 #define I40IW_RDMA_MODE_IETF 1
56
57 #define I40IW_QP_STATE_INVALID 0
58 #define I40IW_QP_STATE_IDLE 1
59 #define I40IW_QP_STATE_RTS 2
60 #define I40IW_QP_STATE_CLOSING 3
61 #define I40IW_QP_STATE_RESERVED 4
62 #define I40IW_QP_STATE_TERMINATE 5
63 #define I40IW_QP_STATE_ERROR 6
64
65 #define I40IW_STAG_STATE_INVALID 0
66 #define I40IW_STAG_STATE_VALID 1
67
68 #define I40IW_STAG_TYPE_SHARED 0
69 #define I40IW_STAG_TYPE_NONSHARED 1
70
71 #define I40IW_MAX_USER_PRIORITY 8
72 #define I40IW_MAX_STATS_COUNT 16
73 #define I40IW_FIRST_NON_PF_STAT 4
74
75
76 #define I40IW_MTU_TO_MSS_IPV4 40
77 #define I40IW_MTU_TO_MSS_IPV6 60
78 #define I40IW_DEFAULT_MTU 1500
79
80 #define LS_64_1(val, bits) ((u64)(uintptr_t)val << bits)
81 #define RS_64_1(val, bits) ((u64)(uintptr_t)val >> bits)
82 #define LS_32_1(val, bits) (u32)(val << bits)
83 #define RS_32_1(val, bits) (u32)(val >> bits)
84 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
85
86 #define QS_HANDLE_UNKNOWN 0xffff
87
88 #define LS_64(val, field) (((u64)val << field ## _SHIFT) & (field ## _MASK))
89
90 #define RS_64(val, field) ((u64)(val & field ## _MASK) >> field ## _SHIFT)
91 #define LS_32(val, field) ((val << field ## _SHIFT) & (field ## _MASK))
92 #define RS_32(val, field) ((val & field ## _MASK) >> field ## _SHIFT)
93
94 #define TERM_DDP_LEN_TAGGED 14
95 #define TERM_DDP_LEN_UNTAGGED 18
96 #define TERM_RDMA_LEN 28
97 #define RDMA_OPCODE_MASK 0x0f
98 #define RDMA_READ_REQ_OPCODE 1
99 #define Q2_BAD_FRAME_OFFSET 72
100 #define Q2_FPSN_OFFSET 64
101 #define CQE_MAJOR_DRV 0x8000
102
103 #define I40IW_TERM_SENT 0x01
104 #define I40IW_TERM_RCVD 0x02
105 #define I40IW_TERM_DONE 0x04
106 #define I40IW_MAC_HLEN 14
107
108 #define I40IW_INVALID_WQE_INDEX 0xffffffff
109
110 #define I40IW_CQP_WAIT_POLL_REGS 1
111 #define I40IW_CQP_WAIT_POLL_CQ 2
112 #define I40IW_CQP_WAIT_EVENT 3
113
114 #define I40IW_CQP_INIT_WQE(wqe) memset(wqe, 0, 64)
115
116 #define I40IW_GET_CURRENT_CQ_ELEMENT(_cq) \
117 ( \
118 &((_cq)->cq_base[I40IW_RING_GETCURRENT_HEAD((_cq)->cq_ring)]) \
119 )
120 #define I40IW_GET_CURRENT_EXTENDED_CQ_ELEMENT(_cq) \
121 ( \
122 &(((struct i40iw_extended_cqe *) \
123 ((_cq)->cq_base))[I40IW_RING_GETCURRENT_HEAD((_cq)->cq_ring)]) \
124 )
125
126 #define I40IW_GET_CURRENT_AEQ_ELEMENT(_aeq) \
127 ( \
128 &_aeq->aeqe_base[I40IW_RING_GETCURRENT_TAIL(_aeq->aeq_ring)] \
129 )
130
131 #define I40IW_GET_CURRENT_CEQ_ELEMENT(_ceq) \
132 ( \
133 &_ceq->ceqe_base[I40IW_RING_GETCURRENT_TAIL(_ceq->ceq_ring)] \
134 )
135
136 #define I40IW_AE_SOURCE_RSVD 0x0
137 #define I40IW_AE_SOURCE_RQ 0x1
138 #define I40IW_AE_SOURCE_RQ_0011 0x3
139
140 #define I40IW_AE_SOURCE_CQ 0x2
141 #define I40IW_AE_SOURCE_CQ_0110 0x6
142 #define I40IW_AE_SOURCE_CQ_1010 0xA
143 #define I40IW_AE_SOURCE_CQ_1110 0xE
144
145 #define I40IW_AE_SOURCE_SQ 0x5
146 #define I40IW_AE_SOURCE_SQ_0111 0x7
147
148 #define I40IW_AE_SOURCE_IN_RR_WR 0x9
149 #define I40IW_AE_SOURCE_IN_RR_WR_1011 0xB
150 #define I40IW_AE_SOURCE_OUT_RR 0xD
151 #define I40IW_AE_SOURCE_OUT_RR_1111 0xF
152
153 #define I40IW_TCP_STATE_NON_EXISTENT 0
154 #define I40IW_TCP_STATE_CLOSED 1
155 #define I40IW_TCP_STATE_LISTEN 2
156 #define I40IW_STATE_SYN_SEND 3
157 #define I40IW_TCP_STATE_SYN_RECEIVED 4
158 #define I40IW_TCP_STATE_ESTABLISHED 5
159 #define I40IW_TCP_STATE_CLOSE_WAIT 6
160 #define I40IW_TCP_STATE_FIN_WAIT_1 7
161 #define I40IW_TCP_STATE_CLOSING 8
162 #define I40IW_TCP_STATE_LAST_ACK 9
163 #define I40IW_TCP_STATE_FIN_WAIT_2 10
164 #define I40IW_TCP_STATE_TIME_WAIT 11
165 #define I40IW_TCP_STATE_RESERVED_1 12
166 #define I40IW_TCP_STATE_RESERVED_2 13
167 #define I40IW_TCP_STATE_RESERVED_3 14
168 #define I40IW_TCP_STATE_RESERVED_4 15
169
170
171 #define I40IW_CQPSQ_QHASH_VLANID_SHIFT 32
172 #define I40IW_CQPSQ_QHASH_VLANID_MASK \
173 ((u64)0xfff << I40IW_CQPSQ_QHASH_VLANID_SHIFT)
174
175 #define I40IW_CQPSQ_QHASH_QPN_SHIFT 32
176 #define I40IW_CQPSQ_QHASH_QPN_MASK \
177 ((u64)0x3ffff << I40IW_CQPSQ_QHASH_QPN_SHIFT)
178
179 #define I40IW_CQPSQ_QHASH_QS_HANDLE_SHIFT 0
180 #define I40IW_CQPSQ_QHASH_QS_HANDLE_MASK ((u64)0x3ff << I40IW_CQPSQ_QHASH_QS_HANDLE_SHIFT)
181
182 #define I40IW_CQPSQ_QHASH_SRC_PORT_SHIFT 16
183 #define I40IW_CQPSQ_QHASH_SRC_PORT_MASK \
184 ((u64)0xffff << I40IW_CQPSQ_QHASH_SRC_PORT_SHIFT)
185
186 #define I40IW_CQPSQ_QHASH_DEST_PORT_SHIFT 0
187 #define I40IW_CQPSQ_QHASH_DEST_PORT_MASK \
188 ((u64)0xffff << I40IW_CQPSQ_QHASH_DEST_PORT_SHIFT)
189
190 #define I40IW_CQPSQ_QHASH_ADDR0_SHIFT 32
191 #define I40IW_CQPSQ_QHASH_ADDR0_MASK \
192 ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR0_SHIFT)
193
194 #define I40IW_CQPSQ_QHASH_ADDR1_SHIFT 0
195 #define I40IW_CQPSQ_QHASH_ADDR1_MASK \
196 ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR1_SHIFT)
197
198 #define I40IW_CQPSQ_QHASH_ADDR2_SHIFT 32
199 #define I40IW_CQPSQ_QHASH_ADDR2_MASK \
200 ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR2_SHIFT)
201
202 #define I40IW_CQPSQ_QHASH_ADDR3_SHIFT 0
203 #define I40IW_CQPSQ_QHASH_ADDR3_MASK \
204 ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR3_SHIFT)
205
206 #define I40IW_CQPSQ_QHASH_WQEVALID_SHIFT 63
207 #define I40IW_CQPSQ_QHASH_WQEVALID_MASK \
208 ((u64)0x1 << I40IW_CQPSQ_QHASH_WQEVALID_SHIFT)
209 #define I40IW_CQPSQ_QHASH_OPCODE_SHIFT 32
210 #define I40IW_CQPSQ_QHASH_OPCODE_MASK \
211 ((u64)0x3f << I40IW_CQPSQ_QHASH_OPCODE_SHIFT)
212
213 #define I40IW_CQPSQ_QHASH_MANAGE_SHIFT 61
214 #define I40IW_CQPSQ_QHASH_MANAGE_MASK \
215 ((u64)0x3 << I40IW_CQPSQ_QHASH_MANAGE_SHIFT)
216
217 #define I40IW_CQPSQ_QHASH_IPV4VALID_SHIFT 60
218 #define I40IW_CQPSQ_QHASH_IPV4VALID_MASK \
219 ((u64)0x1 << I40IW_CQPSQ_QHASH_IPV4VALID_SHIFT)
220
221 #define I40IW_CQPSQ_QHASH_VLANVALID_SHIFT 59
222 #define I40IW_CQPSQ_QHASH_VLANVALID_MASK \
223 ((u64)0x1 << I40IW_CQPSQ_QHASH_VLANVALID_SHIFT)
224
225 #define I40IW_CQPSQ_QHASH_ENTRYTYPE_SHIFT 42
226 #define I40IW_CQPSQ_QHASH_ENTRYTYPE_MASK \
227 ((u64)0x7 << I40IW_CQPSQ_QHASH_ENTRYTYPE_SHIFT)
228
229 #define I40IW_CQPHC_EN_DC_TCP_SHIFT 0
230 #define I40IW_CQPHC_EN_DC_TCP_MASK (1UL << I40IW_CQPHC_EN_DC_TCP_SHIFT)
231
232 #define I40IW_CQPHC_SQSIZE_SHIFT 8
233 #define I40IW_CQPHC_SQSIZE_MASK (0xfUL << I40IW_CQPHC_SQSIZE_SHIFT)
234
235 #define I40IW_CQPHC_DISABLE_PFPDUS_SHIFT 1
236 #define I40IW_CQPHC_DISABLE_PFPDUS_MASK (0x1UL << I40IW_CQPHC_DISABLE_PFPDUS_SHIFT)
237
238 #define I40IW_CQPHC_ENABLED_VFS_SHIFT 32
239 #define I40IW_CQPHC_ENABLED_VFS_MASK (0x3fULL << I40IW_CQPHC_ENABLED_VFS_SHIFT)
240
241 #define I40IW_CQPHC_HMC_PROFILE_SHIFT 0
242 #define I40IW_CQPHC_HMC_PROFILE_MASK (0x7ULL << I40IW_CQPHC_HMC_PROFILE_SHIFT)
243
244 #define I40IW_CQPHC_SVER_SHIFT 24
245 #define I40IW_CQPHC_SVER_MASK (0xffUL << I40IW_CQPHC_SVER_SHIFT)
246
247 #define I40IW_CQPHC_SQBASE_SHIFT 9
248 #define I40IW_CQPHC_SQBASE_MASK \
249 (0xfffffffffffffeULL << I40IW_CQPHC_SQBASE_SHIFT)
250
251 #define I40IW_CQPHC_QPCTX_SHIFT 0
252 #define I40IW_CQPHC_QPCTX_MASK \
253 (0xffffffffffffffffULL << I40IW_CQPHC_QPCTX_SHIFT)
254 #define I40IW_CQPHC_SVER 1
255
256 #define I40IW_CQP_SW_SQSIZE_4 4
257 #define I40IW_CQP_SW_SQSIZE_2048 2048
258
259
260 #define I40IW_QP_DBSA_HW_SQ_TAIL_SHIFT 0
261 #define I40IW_QP_DBSA_HW_SQ_TAIL_MASK \
262 (0x3fffUL << I40IW_QP_DBSA_HW_SQ_TAIL_SHIFT)
263
264
265 #define I40IW_CQ_DBSA_CQEIDX_SHIFT 0
266 #define I40IW_CQ_DBSA_CQEIDX_MASK (0xfffffUL << I40IW_CQ_DBSA_CQEIDX_SHIFT)
267
268 #define I40IW_CQ_DBSA_SW_CQ_SELECT_SHIFT 0
269 #define I40IW_CQ_DBSA_SW_CQ_SELECT_MASK \
270 (0x3fffUL << I40IW_CQ_DBSA_SW_CQ_SELECT_SHIFT)
271
272 #define I40IW_CQ_DBSA_ARM_NEXT_SHIFT 14
273 #define I40IW_CQ_DBSA_ARM_NEXT_MASK (1UL << I40IW_CQ_DBSA_ARM_NEXT_SHIFT)
274
275 #define I40IW_CQ_DBSA_ARM_NEXT_SE_SHIFT 15
276 #define I40IW_CQ_DBSA_ARM_NEXT_SE_MASK (1UL << I40IW_CQ_DBSA_ARM_NEXT_SE_SHIFT)
277
278 #define I40IW_CQ_DBSA_ARM_SEQ_NUM_SHIFT 16
279 #define I40IW_CQ_DBSA_ARM_SEQ_NUM_MASK \
280 (0x3UL << I40IW_CQ_DBSA_ARM_SEQ_NUM_SHIFT)
281
282
283 #define I40IW_CQ_QPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT
284 #define I40IW_CQ_QPCTX_MASK I40IW_CQPHC_QPCTX_MASK
285
286 #define I40IW_CCQ_OPRETVAL_SHIFT 0
287 #define I40IW_CCQ_OPRETVAL_MASK (0xffffffffUL << I40IW_CCQ_OPRETVAL_SHIFT)
288
289 #define I40IW_CQ_MINERR_SHIFT 0
290 #define I40IW_CQ_MINERR_MASK (0xffffUL << I40IW_CQ_MINERR_SHIFT)
291
292 #define I40IW_CQ_MAJERR_SHIFT 16
293 #define I40IW_CQ_MAJERR_MASK (0xffffUL << I40IW_CQ_MAJERR_SHIFT)
294
295 #define I40IW_CQ_WQEIDX_SHIFT 32
296 #define I40IW_CQ_WQEIDX_MASK (0x3fffULL << I40IW_CQ_WQEIDX_SHIFT)
297
298 #define I40IW_CQ_ERROR_SHIFT 55
299 #define I40IW_CQ_ERROR_MASK (1ULL << I40IW_CQ_ERROR_SHIFT)
300
301 #define I40IW_CQ_SQ_SHIFT 62
302 #define I40IW_CQ_SQ_MASK (1ULL << I40IW_CQ_SQ_SHIFT)
303
304 #define I40IW_CQ_VALID_SHIFT 63
305 #define I40IW_CQ_VALID_MASK (1ULL << I40IW_CQ_VALID_SHIFT)
306
307 #define I40IWCQ_PAYLDLEN_SHIFT 0
308 #define I40IWCQ_PAYLDLEN_MASK (0xffffffffUL << I40IWCQ_PAYLDLEN_SHIFT)
309
310 #define I40IWCQ_TCPSEQNUM_SHIFT 32
311 #define I40IWCQ_TCPSEQNUM_MASK (0xffffffffULL << I40IWCQ_TCPSEQNUM_SHIFT)
312
313 #define I40IWCQ_INVSTAG_SHIFT 0
314 #define I40IWCQ_INVSTAG_MASK (0xffffffffUL << I40IWCQ_INVSTAG_SHIFT)
315
316 #define I40IWCQ_QPID_SHIFT 32
317 #define I40IWCQ_QPID_MASK (0x3ffffULL << I40IWCQ_QPID_SHIFT)
318
319 #define I40IWCQ_PSHDROP_SHIFT 51
320 #define I40IWCQ_PSHDROP_MASK (1ULL << I40IWCQ_PSHDROP_SHIFT)
321
322 #define I40IWCQ_SRQ_SHIFT 52
323 #define I40IWCQ_SRQ_MASK (1ULL << I40IWCQ_SRQ_SHIFT)
324
325 #define I40IWCQ_STAG_SHIFT 53
326 #define I40IWCQ_STAG_MASK (1ULL << I40IWCQ_STAG_SHIFT)
327
328 #define I40IWCQ_SOEVENT_SHIFT 54
329 #define I40IWCQ_SOEVENT_MASK (1ULL << I40IWCQ_SOEVENT_SHIFT)
330
331 #define I40IWCQ_OP_SHIFT 56
332 #define I40IWCQ_OP_MASK (0x3fULL << I40IWCQ_OP_SHIFT)
333
334
335 #define I40IW_CEQE_CQCTX_SHIFT 0
336 #define I40IW_CEQE_CQCTX_MASK \
337 (0x7fffffffffffffffULL << I40IW_CEQE_CQCTX_SHIFT)
338
339 #define I40IW_CEQE_VALID_SHIFT 63
340 #define I40IW_CEQE_VALID_MASK (1ULL << I40IW_CEQE_VALID_SHIFT)
341
342
343 #define I40IW_AEQE_COMPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT
344 #define I40IW_AEQE_COMPCTX_MASK I40IW_CQPHC_QPCTX_MASK
345
346 #define I40IW_AEQE_QPCQID_SHIFT 0
347 #define I40IW_AEQE_QPCQID_MASK (0x3ffffUL << I40IW_AEQE_QPCQID_SHIFT)
348
349 #define I40IW_AEQE_WQDESCIDX_SHIFT 18
350 #define I40IW_AEQE_WQDESCIDX_MASK (0x3fffULL << I40IW_AEQE_WQDESCIDX_SHIFT)
351
352 #define I40IW_AEQE_OVERFLOW_SHIFT 33
353 #define I40IW_AEQE_OVERFLOW_MASK (1ULL << I40IW_AEQE_OVERFLOW_SHIFT)
354
355 #define I40IW_AEQE_AECODE_SHIFT 34
356 #define I40IW_AEQE_AECODE_MASK (0xffffULL << I40IW_AEQE_AECODE_SHIFT)
357
358 #define I40IW_AEQE_AESRC_SHIFT 50
359 #define I40IW_AEQE_AESRC_MASK (0xfULL << I40IW_AEQE_AESRC_SHIFT)
360
361 #define I40IW_AEQE_IWSTATE_SHIFT 54
362 #define I40IW_AEQE_IWSTATE_MASK (0x7ULL << I40IW_AEQE_IWSTATE_SHIFT)
363
364 #define I40IW_AEQE_TCPSTATE_SHIFT 57
365 #define I40IW_AEQE_TCPSTATE_MASK (0xfULL << I40IW_AEQE_TCPSTATE_SHIFT)
366
367 #define I40IW_AEQE_Q2DATA_SHIFT 61
368 #define I40IW_AEQE_Q2DATA_MASK (0x3ULL << I40IW_AEQE_Q2DATA_SHIFT)
369
370 #define I40IW_AEQE_VALID_SHIFT 63
371 #define I40IW_AEQE_VALID_MASK (1ULL << I40IW_AEQE_VALID_SHIFT)
372
373
374 #define I40IW_QP_TYPE_IWARP 1
375 #define I40IW_QP_TYPE_UDA 2
376 #define I40IW_QP_TYPE_CQP 4
377
378 #define I40IW_CQ_TYPE_IWARP 1
379 #define I40IW_CQ_TYPE_ILQ 2
380 #define I40IW_CQ_TYPE_IEQ 3
381 #define I40IW_CQ_TYPE_CQP 4
382
383 #define I40IWQP_TERM_SEND_TERM_AND_FIN 0
384 #define I40IWQP_TERM_SEND_TERM_ONLY 1
385 #define I40IWQP_TERM_SEND_FIN_ONLY 2
386 #define I40IWQP_TERM_DONOT_SEND_TERM_OR_FIN 3
387
388 #define I40IW_CQP_OP_CREATE_QP 0
389 #define I40IW_CQP_OP_MODIFY_QP 0x1
390 #define I40IW_CQP_OP_DESTROY_QP 0x02
391 #define I40IW_CQP_OP_CREATE_CQ 0x03
392 #define I40IW_CQP_OP_MODIFY_CQ 0x04
393 #define I40IW_CQP_OP_DESTROY_CQ 0x05
394 #define I40IW_CQP_OP_CREATE_SRQ 0x06
395 #define I40IW_CQP_OP_MODIFY_SRQ 0x07
396 #define I40IW_CQP_OP_DESTROY_SRQ 0x08
397 #define I40IW_CQP_OP_ALLOC_STAG 0x09
398 #define I40IW_CQP_OP_REG_MR 0x0a
399 #define I40IW_CQP_OP_QUERY_STAG 0x0b
400 #define I40IW_CQP_OP_REG_SMR 0x0c
401 #define I40IW_CQP_OP_DEALLOC_STAG 0x0d
402 #define I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE 0x0e
403 #define I40IW_CQP_OP_MANAGE_ARP 0x0f
404 #define I40IW_CQP_OP_MANAGE_VF_PBLE_BP 0x10
405 #define I40IW_CQP_OP_MANAGE_PUSH_PAGES 0x11
406 #define I40IW_CQP_OP_MANAGE_PE_TEAM 0x12
407 #define I40IW_CQP_OP_UPLOAD_CONTEXT 0x13
408 #define I40IW_CQP_OP_ALLOCATE_LOC_MAC_IP_TABLE_ENTRY 0x14
409 #define I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE 0x15
410 #define I40IW_CQP_OP_CREATE_CEQ 0x16
411 #define I40IW_CQP_OP_DESTROY_CEQ 0x18
412 #define I40IW_CQP_OP_CREATE_AEQ 0x19
413 #define I40IW_CQP_OP_DESTROY_AEQ 0x1b
414 #define I40IW_CQP_OP_CREATE_ADDR_VECT 0x1c
415 #define I40IW_CQP_OP_MODIFY_ADDR_VECT 0x1d
416 #define I40IW_CQP_OP_DESTROY_ADDR_VECT 0x1e
417 #define I40IW_CQP_OP_UPDATE_PE_SDS 0x1f
418 #define I40IW_CQP_OP_QUERY_FPM_VALUES 0x20
419 #define I40IW_CQP_OP_COMMIT_FPM_VALUES 0x21
420 #define I40IW_CQP_OP_FLUSH_WQES 0x22
421
422 #define I40IW_CQP_OP_GEN_AE 0x22
423 #define I40IW_CQP_OP_MANAGE_APBVT 0x23
424 #define I40IW_CQP_OP_NOP 0x24
425 #define I40IW_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY 0x25
426 #define I40IW_CQP_OP_CREATE_UDA_MCAST_GROUP 0x26
427 #define I40IW_CQP_OP_MODIFY_UDA_MCAST_GROUP 0x27
428 #define I40IW_CQP_OP_DESTROY_UDA_MCAST_GROUP 0x28
429 #define I40IW_CQP_OP_SUSPEND_QP 0x29
430 #define I40IW_CQP_OP_RESUME_QP 0x2a
431 #define I40IW_CQP_OP_SHMC_PAGES_ALLOCATED 0x2b
432 #define I40IW_CQP_OP_SET_HMC_RESOURCE_PROFILE 0x2d
433
434 #define I40IW_UDA_QPSQ_NEXT_HEADER_SHIFT 16
435 #define I40IW_UDA_QPSQ_NEXT_HEADER_MASK ((u64)0xff << I40IW_UDA_QPSQ_NEXT_HEADER_SHIFT)
436
437 #define I40IW_UDA_QPSQ_OPCODE_SHIFT 32
438 #define I40IW_UDA_QPSQ_OPCODE_MASK ((u64)0x3f << I40IW_UDA_QPSQ_OPCODE_SHIFT)
439
440 #define I40IW_UDA_QPSQ_MACLEN_SHIFT 56
441 #define I40IW_UDA_QPSQ_MACLEN_MASK \
442 ((u64)0x7f << I40IW_UDA_QPSQ_MACLEN_SHIFT)
443
444 #define I40IW_UDA_QPSQ_IPLEN_SHIFT 48
445 #define I40IW_UDA_QPSQ_IPLEN_MASK \
446 ((u64)0x7f << I40IW_UDA_QPSQ_IPLEN_SHIFT)
447
448 #define I40IW_UDA_QPSQ_L4T_SHIFT 30
449 #define I40IW_UDA_QPSQ_L4T_MASK \
450 ((u64)0x3 << I40IW_UDA_QPSQ_L4T_SHIFT)
451
452 #define I40IW_UDA_QPSQ_IIPT_SHIFT 28
453 #define I40IW_UDA_QPSQ_IIPT_MASK \
454 ((u64)0x3 << I40IW_UDA_QPSQ_IIPT_SHIFT)
455
456 #define I40IW_UDA_QPSQ_L4LEN_SHIFT 24
457 #define I40IW_UDA_QPSQ_L4LEN_MASK ((u64)0xf << I40IW_UDA_QPSQ_L4LEN_SHIFT)
458
459 #define I40IW_UDA_QPSQ_AVIDX_SHIFT 0
460 #define I40IW_UDA_QPSQ_AVIDX_MASK ((u64)0xffff << I40IW_UDA_QPSQ_AVIDX_SHIFT)
461
462 #define I40IW_UDA_QPSQ_VALID_SHIFT 63
463 #define I40IW_UDA_QPSQ_VALID_MASK \
464 ((u64)0x1 << I40IW_UDA_QPSQ_VALID_SHIFT)
465
466 #define I40IW_UDA_QPSQ_SIGCOMPL_SHIFT 62
467 #define I40IW_UDA_QPSQ_SIGCOMPL_MASK ((u64)0x1 << I40IW_UDA_QPSQ_SIGCOMPL_SHIFT)
468
469 #define I40IW_UDA_PAYLOADLEN_SHIFT 0
470 #define I40IW_UDA_PAYLOADLEN_MASK ((u64)0x3fff << I40IW_UDA_PAYLOADLEN_SHIFT)
471
472 #define I40IW_UDA_HDRLEN_SHIFT 16
473 #define I40IW_UDA_HDRLEN_MASK ((u64)0x1ff << I40IW_UDA_HDRLEN_SHIFT)
474
475 #define I40IW_VLAN_TAG_VALID_SHIFT 50
476 #define I40IW_VLAN_TAG_VALID_MASK ((u64)0x1 << I40IW_VLAN_TAG_VALID_SHIFT)
477
478 #define I40IW_UDA_L3PROTO_SHIFT 0
479 #define I40IW_UDA_L3PROTO_MASK ((u64)0x3 << I40IW_UDA_L3PROTO_SHIFT)
480
481 #define I40IW_UDA_L4PROTO_SHIFT 16
482 #define I40IW_UDA_L4PROTO_MASK ((u64)0x3 << I40IW_UDA_L4PROTO_SHIFT)
483
484 #define I40IW_UDA_QPSQ_DOLOOPBACK_SHIFT 44
485 #define I40IW_UDA_QPSQ_DOLOOPBACK_MASK \
486 ((u64)0x1 << I40IW_UDA_QPSQ_DOLOOPBACK_SHIFT)
487
488
489 #define I40IW_CQPSQ_OPCODE_SHIFT 32
490 #define I40IW_CQPSQ_OPCODE_MASK (0x3fULL << I40IW_CQPSQ_OPCODE_SHIFT)
491
492 #define I40IW_CQPSQ_WQEVALID_SHIFT 63
493 #define I40IW_CQPSQ_WQEVALID_MASK (1ULL << I40IW_CQPSQ_WQEVALID_SHIFT)
494
495 #define I40IW_CQPSQ_TPHVAL_SHIFT 0
496 #define I40IW_CQPSQ_TPHVAL_MASK (0xffUL << I40IW_CQPSQ_TPHVAL_SHIFT)
497
498 #define I40IW_CQPSQ_TPHEN_SHIFT 60
499 #define I40IW_CQPSQ_TPHEN_MASK (1ULL << I40IW_CQPSQ_TPHEN_SHIFT)
500
501 #define I40IW_CQPSQ_PBUFADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT
502 #define I40IW_CQPSQ_PBUFADDR_MASK I40IW_CQPHC_QPCTX_MASK
503
504
505
506 #define I40IW_CQPSQ_QP_NEWMSS_SHIFT 32
507 #define I40IW_CQPSQ_QP_NEWMSS_MASK (0x3fffULL << I40IW_CQPSQ_QP_NEWMSS_SHIFT)
508
509 #define I40IW_CQPSQ_QP_TERMLEN_SHIFT 48
510 #define I40IW_CQPSQ_QP_TERMLEN_MASK (0xfULL << I40IW_CQPSQ_QP_TERMLEN_SHIFT)
511
512 #define I40IW_CQPSQ_QP_QPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT
513 #define I40IW_CQPSQ_QP_QPCTX_MASK I40IW_CQPHC_QPCTX_MASK
514
515 #define I40IW_CQPSQ_QP_QPID_SHIFT 0
516 #define I40IW_CQPSQ_QP_QPID_MASK (0x3FFFFUL)
517
518
519 #define I40IW_CQPSQ_QP_OP_SHIFT 32
520 #define I40IW_CQPSQ_QP_OP_MASK I40IWCQ_OP_MASK
521
522 #define I40IW_CQPSQ_QP_ORDVALID_SHIFT 42
523 #define I40IW_CQPSQ_QP_ORDVALID_MASK (1ULL << I40IW_CQPSQ_QP_ORDVALID_SHIFT)
524
525 #define I40IW_CQPSQ_QP_TOECTXVALID_SHIFT 43
526 #define I40IW_CQPSQ_QP_TOECTXVALID_MASK \
527 (1ULL << I40IW_CQPSQ_QP_TOECTXVALID_SHIFT)
528
529 #define I40IW_CQPSQ_QP_CACHEDVARVALID_SHIFT 44
530 #define I40IW_CQPSQ_QP_CACHEDVARVALID_MASK \
531 (1ULL << I40IW_CQPSQ_QP_CACHEDVARVALID_SHIFT)
532
533 #define I40IW_CQPSQ_QP_VQ_SHIFT 45
534 #define I40IW_CQPSQ_QP_VQ_MASK (1ULL << I40IW_CQPSQ_QP_VQ_SHIFT)
535
536 #define I40IW_CQPSQ_QP_FORCELOOPBACK_SHIFT 46
537 #define I40IW_CQPSQ_QP_FORCELOOPBACK_MASK \
538 (1ULL << I40IW_CQPSQ_QP_FORCELOOPBACK_SHIFT)
539
540 #define I40IW_CQPSQ_QP_CQNUMVALID_SHIFT 47
541 #define I40IW_CQPSQ_QP_CQNUMVALID_MASK \
542 (1ULL << I40IW_CQPSQ_QP_CQNUMVALID_SHIFT)
543
544 #define I40IW_CQPSQ_QP_QPTYPE_SHIFT 48
545 #define I40IW_CQPSQ_QP_QPTYPE_MASK (0x3ULL << I40IW_CQPSQ_QP_QPTYPE_SHIFT)
546
547 #define I40IW_CQPSQ_QP_MSSCHANGE_SHIFT 52
548 #define I40IW_CQPSQ_QP_MSSCHANGE_MASK (1ULL << I40IW_CQPSQ_QP_MSSCHANGE_SHIFT)
549
550 #define I40IW_CQPSQ_QP_IGNOREMWBOUND_SHIFT 54
551 #define I40IW_CQPSQ_QP_IGNOREMWBOUND_MASK \
552 (1ULL << I40IW_CQPSQ_QP_IGNOREMWBOUND_SHIFT)
553
554 #define I40IW_CQPSQ_QP_REMOVEHASHENTRY_SHIFT 55
555 #define I40IW_CQPSQ_QP_REMOVEHASHENTRY_MASK \
556 (1ULL << I40IW_CQPSQ_QP_REMOVEHASHENTRY_SHIFT)
557
558 #define I40IW_CQPSQ_QP_TERMACT_SHIFT 56
559 #define I40IW_CQPSQ_QP_TERMACT_MASK (0x3ULL << I40IW_CQPSQ_QP_TERMACT_SHIFT)
560
561 #define I40IW_CQPSQ_QP_RESETCON_SHIFT 58
562 #define I40IW_CQPSQ_QP_RESETCON_MASK (1ULL << I40IW_CQPSQ_QP_RESETCON_SHIFT)
563
564 #define I40IW_CQPSQ_QP_ARPTABIDXVALID_SHIFT 59
565 #define I40IW_CQPSQ_QP_ARPTABIDXVALID_MASK \
566 (1ULL << I40IW_CQPSQ_QP_ARPTABIDXVALID_SHIFT)
567
568 #define I40IW_CQPSQ_QP_NEXTIWSTATE_SHIFT 60
569 #define I40IW_CQPSQ_QP_NEXTIWSTATE_MASK \
570 (0x7ULL << I40IW_CQPSQ_QP_NEXTIWSTATE_SHIFT)
571
572 #define I40IW_CQPSQ_QP_DBSHADOWADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT
573 #define I40IW_CQPSQ_QP_DBSHADOWADDR_MASK I40IW_CQPHC_QPCTX_MASK
574
575
576 #define I40IW_CQPSQ_CQ_CQSIZE_SHIFT 0
577 #define I40IW_CQPSQ_CQ_CQSIZE_MASK (0x3ffffUL << I40IW_CQPSQ_CQ_CQSIZE_SHIFT)
578
579 #define I40IW_CQPSQ_CQ_CQCTX_SHIFT 0
580 #define I40IW_CQPSQ_CQ_CQCTX_MASK \
581 (0x7fffffffffffffffULL << I40IW_CQPSQ_CQ_CQCTX_SHIFT)
582
583 #define I40IW_CQPSQ_CQ_CQCTX_SHIFT 0
584 #define I40IW_CQPSQ_CQ_CQCTX_MASK \
585 (0x7fffffffffffffffULL << I40IW_CQPSQ_CQ_CQCTX_SHIFT)
586
587 #define I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD_SHIFT 0
588 #define I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD_MASK \
589 (0x3ffff << I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD_SHIFT)
590
591 #define I40IW_CQPSQ_CQ_CEQID_SHIFT 24
592 #define I40IW_CQPSQ_CQ_CEQID_MASK (0x7fUL << I40IW_CQPSQ_CQ_CEQID_SHIFT)
593
594 #define I40IW_CQPSQ_CQ_OP_SHIFT 32
595 #define I40IW_CQPSQ_CQ_OP_MASK (0x3fULL << I40IW_CQPSQ_CQ_OP_SHIFT)
596
597 #define I40IW_CQPSQ_CQ_CQRESIZE_SHIFT 43
598 #define I40IW_CQPSQ_CQ_CQRESIZE_MASK (1ULL << I40IW_CQPSQ_CQ_CQRESIZE_SHIFT)
599
600 #define I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT 44
601 #define I40IW_CQPSQ_CQ_LPBLSIZE_MASK (3ULL << I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT)
602
603 #define I40IW_CQPSQ_CQ_CHKOVERFLOW_SHIFT 46
604 #define I40IW_CQPSQ_CQ_CHKOVERFLOW_MASK \
605 (1ULL << I40IW_CQPSQ_CQ_CHKOVERFLOW_SHIFT)
606
607 #define I40IW_CQPSQ_CQ_VIRTMAP_SHIFT 47
608 #define I40IW_CQPSQ_CQ_VIRTMAP_MASK (1ULL << I40IW_CQPSQ_CQ_VIRTMAP_SHIFT)
609
610 #define I40IW_CQPSQ_CQ_ENCEQEMASK_SHIFT 48
611 #define I40IW_CQPSQ_CQ_ENCEQEMASK_MASK \
612 (1ULL << I40IW_CQPSQ_CQ_ENCEQEMASK_SHIFT)
613
614 #define I40IW_CQPSQ_CQ_CEQIDVALID_SHIFT 49
615 #define I40IW_CQPSQ_CQ_CEQIDVALID_MASK \
616 (1ULL << I40IW_CQPSQ_CQ_CEQIDVALID_SHIFT)
617
618 #define I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT_SHIFT 61
619 #define I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT_MASK \
620 (1ULL << I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT_SHIFT)
621
622
623
624 #define I40IW_CQPSQ_SRQ_RQSIZE_SHIFT 0
625 #define I40IW_CQPSQ_SRQ_RQSIZE_MASK (0xfUL << I40IW_CQPSQ_SRQ_RQSIZE_SHIFT)
626
627 #define I40IW_CQPSQ_SRQ_RQWQESIZE_SHIFT 4
628 #define I40IW_CQPSQ_SRQ_RQWQESIZE_MASK \
629 (0x7UL << I40IW_CQPSQ_SRQ_RQWQESIZE_SHIFT)
630
631 #define I40IW_CQPSQ_SRQ_SRQLIMIT_SHIFT 32
632 #define I40IW_CQPSQ_SRQ_SRQLIMIT_MASK \
633 (0xfffULL << I40IW_CQPSQ_SRQ_SRQLIMIT_SHIFT)
634
635 #define I40IW_CQPSQ_SRQ_SRQCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT
636 #define I40IW_CQPSQ_SRQ_SRQCTX_MASK I40IW_CQPHC_QPCTX_MASK
637
638 #define I40IW_CQPSQ_SRQ_PDID_SHIFT 16
639 #define I40IW_CQPSQ_SRQ_PDID_MASK \
640 (0x7fffULL << I40IW_CQPSQ_SRQ_PDID_SHIFT)
641
642 #define I40IW_CQPSQ_SRQ_SRQID_SHIFT 0
643 #define I40IW_CQPSQ_SRQ_SRQID_MASK (0x7fffUL << I40IW_CQPSQ_SRQ_SRQID_SHIFT)
644
645 #define I40IW_CQPSQ_SRQ_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT
646 #define I40IW_CQPSQ_SRQ_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK
647
648 #define I40IW_CQPSQ_SRQ_VIRTMAP_SHIFT I40IW_CQPSQ_CQ_VIRTMAP_SHIFT
649 #define I40IW_CQPSQ_SRQ_VIRTMAP_MASK I40IW_CQPSQ_CQ_VIRTMAP_MASK
650
651 #define I40IW_CQPSQ_SRQ_TPHEN_SHIFT I40IW_CQPSQ_TPHEN_SHIFT
652 #define I40IW_CQPSQ_SRQ_TPHEN_MASK I40IW_CQPSQ_TPHEN_MASK
653
654 #define I40IW_CQPSQ_SRQ_ARMLIMITEVENT_SHIFT 61
655 #define I40IW_CQPSQ_SRQ_ARMLIMITEVENT_MASK \
656 (1ULL << I40IW_CQPSQ_SRQ_ARMLIMITEVENT_SHIFT)
657
658 #define I40IW_CQPSQ_SRQ_DBSHADOWAREA_SHIFT 6
659 #define I40IW_CQPSQ_SRQ_DBSHADOWAREA_MASK \
660 (0x3ffffffffffffffULL << I40IW_CQPSQ_SRQ_DBSHADOWAREA_SHIFT)
661
662 #define I40IW_CQPSQ_SRQ_FIRSTPMPBLIDX_SHIFT 0
663 #define I40IW_CQPSQ_SRQ_FIRSTPMPBLIDX_MASK \
664 (0xfffffffUL << I40IW_CQPSQ_SRQ_FIRSTPMPBLIDX_SHIFT)
665
666
667 #define I40IW_CQPSQ_STAG_VA_FBO_SHIFT I40IW_CQPHC_QPCTX_SHIFT
668 #define I40IW_CQPSQ_STAG_VA_FBO_MASK I40IW_CQPHC_QPCTX_MASK
669
670 #define I40IW_CQPSQ_STAG_STAGLEN_SHIFT 0
671 #define I40IW_CQPSQ_STAG_STAGLEN_MASK \
672 (0x3fffffffffffULL << I40IW_CQPSQ_STAG_STAGLEN_SHIFT)
673
674 #define I40IW_CQPSQ_STAG_PDID_SHIFT 48
675 #define I40IW_CQPSQ_STAG_PDID_MASK (0x7fffULL << I40IW_CQPSQ_STAG_PDID_SHIFT)
676
677 #define I40IW_CQPSQ_STAG_KEY_SHIFT 0
678 #define I40IW_CQPSQ_STAG_KEY_MASK (0xffUL << I40IW_CQPSQ_STAG_KEY_SHIFT)
679
680 #define I40IW_CQPSQ_STAG_IDX_SHIFT 8
681 #define I40IW_CQPSQ_STAG_IDX_MASK (0xffffffUL << I40IW_CQPSQ_STAG_IDX_SHIFT)
682
683 #define I40IW_CQPSQ_STAG_PARENTSTAGIDX_SHIFT 32
684 #define I40IW_CQPSQ_STAG_PARENTSTAGIDX_MASK \
685 (0xffffffULL << I40IW_CQPSQ_STAG_PARENTSTAGIDX_SHIFT)
686
687 #define I40IW_CQPSQ_STAG_MR_SHIFT 43
688 #define I40IW_CQPSQ_STAG_MR_MASK (1ULL << I40IW_CQPSQ_STAG_MR_SHIFT)
689
690 #define I40IW_CQPSQ_STAG_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT
691 #define I40IW_CQPSQ_STAG_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK
692
693 #define I40IW_CQPSQ_STAG_HPAGESIZE_SHIFT 46
694 #define I40IW_CQPSQ_STAG_HPAGESIZE_MASK \
695 (1ULL << I40IW_CQPSQ_STAG_HPAGESIZE_SHIFT)
696
697 #define I40IW_CQPSQ_STAG_ARIGHTS_SHIFT 48
698 #define I40IW_CQPSQ_STAG_ARIGHTS_MASK \
699 (0x1fULL << I40IW_CQPSQ_STAG_ARIGHTS_SHIFT)
700
701 #define I40IW_CQPSQ_STAG_REMACCENABLED_SHIFT 53
702 #define I40IW_CQPSQ_STAG_REMACCENABLED_MASK \
703 (1ULL << I40IW_CQPSQ_STAG_REMACCENABLED_SHIFT)
704
705 #define I40IW_CQPSQ_STAG_VABASEDTO_SHIFT 59
706 #define I40IW_CQPSQ_STAG_VABASEDTO_MASK \
707 (1ULL << I40IW_CQPSQ_STAG_VABASEDTO_SHIFT)
708
709 #define I40IW_CQPSQ_STAG_USEHMCFNIDX_SHIFT 60
710 #define I40IW_CQPSQ_STAG_USEHMCFNIDX_MASK \
711 (1ULL << I40IW_CQPSQ_STAG_USEHMCFNIDX_SHIFT)
712
713 #define I40IW_CQPSQ_STAG_USEPFRID_SHIFT 61
714 #define I40IW_CQPSQ_STAG_USEPFRID_MASK \
715 (1ULL << I40IW_CQPSQ_STAG_USEPFRID_SHIFT)
716
717 #define I40IW_CQPSQ_STAG_PBA_SHIFT I40IW_CQPHC_QPCTX_SHIFT
718 #define I40IW_CQPSQ_STAG_PBA_MASK I40IW_CQPHC_QPCTX_MASK
719
720 #define I40IW_CQPSQ_STAG_HMCFNIDX_SHIFT 0
721 #define I40IW_CQPSQ_STAG_HMCFNIDX_MASK \
722 (0x3fUL << I40IW_CQPSQ_STAG_HMCFNIDX_SHIFT)
723
724 #define I40IW_CQPSQ_STAG_FIRSTPMPBLIDX_SHIFT 0
725 #define I40IW_CQPSQ_STAG_FIRSTPMPBLIDX_MASK \
726 (0xfffffffUL << I40IW_CQPSQ_STAG_FIRSTPMPBLIDX_SHIFT)
727
728
729 #define I40IW_CQPSQ_QUERYSTAG_IDX_SHIFT I40IW_CQPSQ_STAG_IDX_SHIFT
730 #define I40IW_CQPSQ_QUERYSTAG_IDX_MASK I40IW_CQPSQ_STAG_IDX_MASK
731
732
733
734
735 #define I40IW_CQPSQ_MLIPA_IPV6LO_SHIFT I40IW_CQPHC_QPCTX_SHIFT
736 #define I40IW_CQPSQ_MLIPA_IPV6LO_MASK I40IW_CQPHC_QPCTX_MASK
737
738 #define I40IW_CQPSQ_MLIPA_IPV6HI_SHIFT I40IW_CQPHC_QPCTX_SHIFT
739 #define I40IW_CQPSQ_MLIPA_IPV6HI_MASK I40IW_CQPHC_QPCTX_MASK
740
741 #define I40IW_CQPSQ_MLIPA_IPV4_SHIFT 0
742 #define I40IW_CQPSQ_MLIPA_IPV4_MASK \
743 (0xffffffffUL << I40IW_CQPSQ_MLIPA_IPV4_SHIFT)
744
745 #define I40IW_CQPSQ_MLIPA_IPTABLEIDX_SHIFT 0
746 #define I40IW_CQPSQ_MLIPA_IPTABLEIDX_MASK \
747 (0x3fUL << I40IW_CQPSQ_MLIPA_IPTABLEIDX_SHIFT)
748
749 #define I40IW_CQPSQ_MLIPA_IPV4VALID_SHIFT 42
750 #define I40IW_CQPSQ_MLIPA_IPV4VALID_MASK \
751 (1ULL << I40IW_CQPSQ_MLIPA_IPV4VALID_SHIFT)
752
753 #define I40IW_CQPSQ_MLIPA_IPV6VALID_SHIFT 43
754 #define I40IW_CQPSQ_MLIPA_IPV6VALID_MASK \
755 (1ULL << I40IW_CQPSQ_MLIPA_IPV6VALID_SHIFT)
756
757 #define I40IW_CQPSQ_MLIPA_FREEENTRY_SHIFT 62
758 #define I40IW_CQPSQ_MLIPA_FREEENTRY_MASK \
759 (1ULL << I40IW_CQPSQ_MLIPA_FREEENTRY_SHIFT)
760
761 #define I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT_SHIFT 61
762 #define I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT_MASK \
763 (1ULL << I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT_SHIFT)
764
765 #define I40IW_CQPSQ_MLIPA_MAC0_SHIFT 0
766 #define I40IW_CQPSQ_MLIPA_MAC0_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC0_SHIFT)
767
768 #define I40IW_CQPSQ_MLIPA_MAC1_SHIFT 8
769 #define I40IW_CQPSQ_MLIPA_MAC1_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC1_SHIFT)
770
771 #define I40IW_CQPSQ_MLIPA_MAC2_SHIFT 16
772 #define I40IW_CQPSQ_MLIPA_MAC2_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC2_SHIFT)
773
774 #define I40IW_CQPSQ_MLIPA_MAC3_SHIFT 24
775 #define I40IW_CQPSQ_MLIPA_MAC3_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC3_SHIFT)
776
777 #define I40IW_CQPSQ_MLIPA_MAC4_SHIFT 32
778 #define I40IW_CQPSQ_MLIPA_MAC4_MASK (0xffULL << I40IW_CQPSQ_MLIPA_MAC4_SHIFT)
779
780 #define I40IW_CQPSQ_MLIPA_MAC5_SHIFT 40
781 #define I40IW_CQPSQ_MLIPA_MAC5_MASK (0xffULL << I40IW_CQPSQ_MLIPA_MAC5_SHIFT)
782
783
784 #define I40IW_CQPSQ_MAT_REACHMAX_SHIFT 0
785 #define I40IW_CQPSQ_MAT_REACHMAX_MASK \
786 (0xffffffffUL << I40IW_CQPSQ_MAT_REACHMAX_SHIFT)
787
788 #define I40IW_CQPSQ_MAT_MACADDR_SHIFT 0
789 #define I40IW_CQPSQ_MAT_MACADDR_MASK \
790 (0xffffffffffffULL << I40IW_CQPSQ_MAT_MACADDR_SHIFT)
791
792 #define I40IW_CQPSQ_MAT_ARPENTRYIDX_SHIFT 0
793 #define I40IW_CQPSQ_MAT_ARPENTRYIDX_MASK \
794 (0xfffUL << I40IW_CQPSQ_MAT_ARPENTRYIDX_SHIFT)
795
796 #define I40IW_CQPSQ_MAT_ENTRYVALID_SHIFT 42
797 #define I40IW_CQPSQ_MAT_ENTRYVALID_MASK \
798 (1ULL << I40IW_CQPSQ_MAT_ENTRYVALID_SHIFT)
799
800 #define I40IW_CQPSQ_MAT_PERMANENT_SHIFT 43
801 #define I40IW_CQPSQ_MAT_PERMANENT_MASK \
802 (1ULL << I40IW_CQPSQ_MAT_PERMANENT_SHIFT)
803
804 #define I40IW_CQPSQ_MAT_QUERY_SHIFT 44
805 #define I40IW_CQPSQ_MAT_QUERY_MASK (1ULL << I40IW_CQPSQ_MAT_QUERY_SHIFT)
806
807
808 #define I40IW_CQPSQ_MVPBP_PD_ENTRY_CNT_SHIFT 0
809 #define I40IW_CQPSQ_MVPBP_PD_ENTRY_CNT_MASK \
810 (0x3ffULL << I40IW_CQPSQ_MVPBP_PD_ENTRY_CNT_SHIFT)
811
812 #define I40IW_CQPSQ_MVPBP_FIRST_PD_INX_SHIFT 16
813 #define I40IW_CQPSQ_MVPBP_FIRST_PD_INX_MASK \
814 (0x1ffULL << I40IW_CQPSQ_MVPBP_FIRST_PD_INX_SHIFT)
815
816 #define I40IW_CQPSQ_MVPBP_SD_INX_SHIFT 32
817 #define I40IW_CQPSQ_MVPBP_SD_INX_MASK \
818 (0xfffULL << I40IW_CQPSQ_MVPBP_SD_INX_SHIFT)
819
820 #define I40IW_CQPSQ_MVPBP_INV_PD_ENT_SHIFT 62
821 #define I40IW_CQPSQ_MVPBP_INV_PD_ENT_MASK \
822 (0x1ULL << I40IW_CQPSQ_MVPBP_INV_PD_ENT_SHIFT)
823
824 #define I40IW_CQPSQ_MVPBP_PD_PLPBA_SHIFT 3
825 #define I40IW_CQPSQ_MVPBP_PD_PLPBA_MASK \
826 (0x1fffffffffffffffULL << I40IW_CQPSQ_MVPBP_PD_PLPBA_SHIFT)
827
828
829 #define I40IW_INVALID_PUSH_PAGE_INDEX 0xffff
830
831 #define I40IW_CQPSQ_MPP_QS_HANDLE_SHIFT 0
832 #define I40IW_CQPSQ_MPP_QS_HANDLE_MASK (0xffffUL << \
833 I40IW_CQPSQ_MPP_QS_HANDLE_SHIFT)
834
835 #define I40IW_CQPSQ_MPP_PPIDX_SHIFT 0
836 #define I40IW_CQPSQ_MPP_PPIDX_MASK (0x3ffUL << I40IW_CQPSQ_MPP_PPIDX_SHIFT)
837
838 #define I40IW_CQPSQ_MPP_FREE_PAGE_SHIFT 62
839 #define I40IW_CQPSQ_MPP_FREE_PAGE_MASK (1ULL << I40IW_CQPSQ_MPP_FREE_PAGE_SHIFT)
840
841
842 #define I40IW_CQPSQ_UCTX_QPCTXADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT
843 #define I40IW_CQPSQ_UCTX_QPCTXADDR_MASK I40IW_CQPHC_QPCTX_MASK
844
845 #define I40IW_CQPSQ_UCTX_QPID_SHIFT 0
846 #define I40IW_CQPSQ_UCTX_QPID_MASK (0x3ffffUL << I40IW_CQPSQ_UCTX_QPID_SHIFT)
847
848 #define I40IW_CQPSQ_UCTX_QPTYPE_SHIFT 48
849 #define I40IW_CQPSQ_UCTX_QPTYPE_MASK (0xfULL << I40IW_CQPSQ_UCTX_QPTYPE_SHIFT)
850
851 #define I40IW_CQPSQ_UCTX_RAWFORMAT_SHIFT 61
852 #define I40IW_CQPSQ_UCTX_RAWFORMAT_MASK \
853 (1ULL << I40IW_CQPSQ_UCTX_RAWFORMAT_SHIFT)
854
855 #define I40IW_CQPSQ_UCTX_FREEZEQP_SHIFT 62
856 #define I40IW_CQPSQ_UCTX_FREEZEQP_MASK \
857 (1ULL << I40IW_CQPSQ_UCTX_FREEZEQP_SHIFT)
858
859
860 #define I40IW_CQPSQ_MHMC_VFIDX_SHIFT 0
861 #define I40IW_CQPSQ_MHMC_VFIDX_MASK (0x7fUL << I40IW_CQPSQ_MHMC_VFIDX_SHIFT)
862
863 #define I40IW_CQPSQ_MHMC_FREEPMFN_SHIFT 62
864 #define I40IW_CQPSQ_MHMC_FREEPMFN_MASK \
865 (1ULL << I40IW_CQPSQ_MHMC_FREEPMFN_SHIFT)
866
867
868 #define I40IW_CQPSQ_SHMCRP_HMC_PROFILE_SHIFT 0
869 #define I40IW_CQPSQ_SHMCRP_HMC_PROFILE_MASK \
870 (0x7ULL << I40IW_CQPSQ_SHMCRP_HMC_PROFILE_SHIFT)
871 #define I40IW_CQPSQ_SHMCRP_VFNUM_SHIFT 32
872 #define I40IW_CQPSQ_SHMCRP_VFNUM_MASK (0x3fULL << I40IW_CQPSQ_SHMCRP_VFNUM_SHIFT)
873
874
875 #define I40IW_CQPSQ_CEQ_CEQSIZE_SHIFT 0
876 #define I40IW_CQPSQ_CEQ_CEQSIZE_MASK \
877 (0x1ffffUL << I40IW_CQPSQ_CEQ_CEQSIZE_SHIFT)
878
879 #define I40IW_CQPSQ_CEQ_CEQID_SHIFT 0
880 #define I40IW_CQPSQ_CEQ_CEQID_MASK (0x7fUL << I40IW_CQPSQ_CEQ_CEQID_SHIFT)
881
882 #define I40IW_CQPSQ_CEQ_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT
883 #define I40IW_CQPSQ_CEQ_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK
884
885 #define I40IW_CQPSQ_CEQ_VMAP_SHIFT 47
886 #define I40IW_CQPSQ_CEQ_VMAP_MASK (1ULL << I40IW_CQPSQ_CEQ_VMAP_SHIFT)
887
888 #define I40IW_CQPSQ_CEQ_FIRSTPMPBLIDX_SHIFT 0
889 #define I40IW_CQPSQ_CEQ_FIRSTPMPBLIDX_MASK \
890 (0xfffffffUL << I40IW_CQPSQ_CEQ_FIRSTPMPBLIDX_SHIFT)
891
892
893 #define I40IW_CQPSQ_AEQ_AEQECNT_SHIFT 0
894 #define I40IW_CQPSQ_AEQ_AEQECNT_MASK \
895 (0x7ffffUL << I40IW_CQPSQ_AEQ_AEQECNT_SHIFT)
896
897 #define I40IW_CQPSQ_AEQ_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT
898 #define I40IW_CQPSQ_AEQ_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK
899
900 #define I40IW_CQPSQ_AEQ_VMAP_SHIFT 47
901 #define I40IW_CQPSQ_AEQ_VMAP_MASK (1ULL << I40IW_CQPSQ_AEQ_VMAP_SHIFT)
902
903 #define I40IW_CQPSQ_AEQ_FIRSTPMPBLIDX_SHIFT 0
904 #define I40IW_CQPSQ_AEQ_FIRSTPMPBLIDX_MASK \
905 (0xfffffffUL << I40IW_CQPSQ_AEQ_FIRSTPMPBLIDX_SHIFT)
906
907
908 #define I40IW_CQPSQ_CFPM_HMCFNID_SHIFT 0
909 #define I40IW_CQPSQ_CFPM_HMCFNID_MASK (0x3fUL << I40IW_CQPSQ_CFPM_HMCFNID_SHIFT)
910
911
912 #define I40IW_CQPSQ_FWQE_AECODE_SHIFT 0
913 #define I40IW_CQPSQ_FWQE_AECODE_MASK (0xffffUL << I40IW_CQPSQ_FWQE_AECODE_SHIFT)
914
915 #define I40IW_CQPSQ_FWQE_AESOURCE_SHIFT 16
916 #define I40IW_CQPSQ_FWQE_AESOURCE_MASK \
917 (0xfUL << I40IW_CQPSQ_FWQE_AESOURCE_SHIFT)
918
919 #define I40IW_CQPSQ_FWQE_RQMNERR_SHIFT 0
920 #define I40IW_CQPSQ_FWQE_RQMNERR_MASK \
921 (0xffffUL << I40IW_CQPSQ_FWQE_RQMNERR_SHIFT)
922
923 #define I40IW_CQPSQ_FWQE_RQMJERR_SHIFT 16
924 #define I40IW_CQPSQ_FWQE_RQMJERR_MASK \
925 (0xffffUL << I40IW_CQPSQ_FWQE_RQMJERR_SHIFT)
926
927 #define I40IW_CQPSQ_FWQE_SQMNERR_SHIFT 32
928 #define I40IW_CQPSQ_FWQE_SQMNERR_MASK \
929 (0xffffULL << I40IW_CQPSQ_FWQE_SQMNERR_SHIFT)
930
931 #define I40IW_CQPSQ_FWQE_SQMJERR_SHIFT 48
932 #define I40IW_CQPSQ_FWQE_SQMJERR_MASK \
933 (0xffffULL << I40IW_CQPSQ_FWQE_SQMJERR_SHIFT)
934
935 #define I40IW_CQPSQ_FWQE_QPID_SHIFT 0
936 #define I40IW_CQPSQ_FWQE_QPID_MASK (0x3ffffULL << I40IW_CQPSQ_FWQE_QPID_SHIFT)
937
938 #define I40IW_CQPSQ_FWQE_GENERATE_AE_SHIFT 59
939 #define I40IW_CQPSQ_FWQE_GENERATE_AE_MASK (1ULL << \
940 I40IW_CQPSQ_FWQE_GENERATE_AE_SHIFT)
941
942 #define I40IW_CQPSQ_FWQE_USERFLCODE_SHIFT 60
943 #define I40IW_CQPSQ_FWQE_USERFLCODE_MASK \
944 (1ULL << I40IW_CQPSQ_FWQE_USERFLCODE_SHIFT)
945
946 #define I40IW_CQPSQ_FWQE_FLUSHSQ_SHIFT 61
947 #define I40IW_CQPSQ_FWQE_FLUSHSQ_MASK (1ULL << I40IW_CQPSQ_FWQE_FLUSHSQ_SHIFT)
948
949 #define I40IW_CQPSQ_FWQE_FLUSHRQ_SHIFT 62
950 #define I40IW_CQPSQ_FWQE_FLUSHRQ_MASK (1ULL << I40IW_CQPSQ_FWQE_FLUSHRQ_SHIFT)
951
952
953 #define I40IW_CQPSQ_MAPT_PORT_SHIFT 0
954 #define I40IW_CQPSQ_MAPT_PORT_MASK (0xffffUL << I40IW_CQPSQ_MAPT_PORT_SHIFT)
955
956 #define I40IW_CQPSQ_MAPT_ADDPORT_SHIFT 62
957 #define I40IW_CQPSQ_MAPT_ADDPORT_MASK (1ULL << I40IW_CQPSQ_MAPT_ADDPORT_SHIFT)
958
959
960 #define I40IW_CQPSQ_UPESD_SDCMD_SHIFT 0
961 #define I40IW_CQPSQ_UPESD_SDCMD_MASK (0xffffffffUL << I40IW_CQPSQ_UPESD_SDCMD_SHIFT)
962
963 #define I40IW_CQPSQ_UPESD_SDDATALOW_SHIFT 0
964 #define I40IW_CQPSQ_UPESD_SDDATALOW_MASK \
965 (0xffffffffUL << I40IW_CQPSQ_UPESD_SDDATALOW_SHIFT)
966
967 #define I40IW_CQPSQ_UPESD_SDDATAHI_SHIFT 32
968 #define I40IW_CQPSQ_UPESD_SDDATAHI_MASK \
969 (0xffffffffULL << I40IW_CQPSQ_UPESD_SDDATAHI_SHIFT)
970 #define I40IW_CQPSQ_UPESD_HMCFNID_SHIFT 0
971 #define I40IW_CQPSQ_UPESD_HMCFNID_MASK \
972 (0x3fUL << I40IW_CQPSQ_UPESD_HMCFNID_SHIFT)
973
974 #define I40IW_CQPSQ_UPESD_ENTRY_VALID_SHIFT 63
975 #define I40IW_CQPSQ_UPESD_ENTRY_VALID_MASK \
976 ((u64)1 << I40IW_CQPSQ_UPESD_ENTRY_VALID_SHIFT)
977
978 #define I40IW_CQPSQ_UPESD_ENTRY_COUNT_SHIFT 0
979 #define I40IW_CQPSQ_UPESD_ENTRY_COUNT_MASK \
980 (0xfUL << I40IW_CQPSQ_UPESD_ENTRY_COUNT_SHIFT)
981
982 #define I40IW_CQPSQ_UPESD_SKIP_ENTRY_SHIFT 7
983 #define I40IW_CQPSQ_UPESD_SKIP_ENTRY_MASK \
984 (0x1UL << I40IW_CQPSQ_UPESD_SKIP_ENTRY_SHIFT)
985
986
987 #define I40IW_CQPSQ_SUSPENDQP_QPID_SHIFT 0
988 #define I40IW_CQPSQ_SUSPENDQP_QPID_MASK (0x3FFFFUL)
989
990
991
992 #define I40IW_CQPSQ_RESUMEQP_QSHANDLE_SHIFT 0
993 #define I40IW_CQPSQ_RESUMEQP_QSHANDLE_MASK \
994 (0xffffffffUL << I40IW_CQPSQ_RESUMEQP_QSHANDLE_SHIFT)
995
996 #define I40IW_CQPSQ_RESUMEQP_QPID_SHIFT 0
997 #define I40IW_CQPSQ_RESUMEQP_QPID_MASK (0x3FFFFUL)
998
999
1000
1001 #define I40IWQPC_DDP_VER_SHIFT 0
1002 #define I40IWQPC_DDP_VER_MASK (3UL << I40IWQPC_DDP_VER_SHIFT)
1003
1004 #define I40IWQPC_SNAP_SHIFT 2
1005 #define I40IWQPC_SNAP_MASK (1UL << I40IWQPC_SNAP_SHIFT)
1006
1007 #define I40IWQPC_IPV4_SHIFT 3
1008 #define I40IWQPC_IPV4_MASK (1UL << I40IWQPC_IPV4_SHIFT)
1009
1010 #define I40IWQPC_NONAGLE_SHIFT 4
1011 #define I40IWQPC_NONAGLE_MASK (1UL << I40IWQPC_NONAGLE_SHIFT)
1012
1013 #define I40IWQPC_INSERTVLANTAG_SHIFT 5
1014 #define I40IWQPC_INSERTVLANTAG_MASK (1 << I40IWQPC_INSERTVLANTAG_SHIFT)
1015
1016 #define I40IWQPC_USESRQ_SHIFT 6
1017 #define I40IWQPC_USESRQ_MASK (1UL << I40IWQPC_USESRQ_SHIFT)
1018
1019 #define I40IWQPC_TIMESTAMP_SHIFT 7
1020 #define I40IWQPC_TIMESTAMP_MASK (1UL << I40IWQPC_TIMESTAMP_SHIFT)
1021
1022 #define I40IWQPC_RQWQESIZE_SHIFT 8
1023 #define I40IWQPC_RQWQESIZE_MASK (3UL << I40IWQPC_RQWQESIZE_SHIFT)
1024
1025 #define I40IWQPC_INSERTL2TAG2_SHIFT 11
1026 #define I40IWQPC_INSERTL2TAG2_MASK (1UL << I40IWQPC_INSERTL2TAG2_SHIFT)
1027
1028 #define I40IWQPC_LIMIT_SHIFT 12
1029 #define I40IWQPC_LIMIT_MASK (3UL << I40IWQPC_LIMIT_SHIFT)
1030
1031 #define I40IWQPC_DROPOOOSEG_SHIFT 15
1032 #define I40IWQPC_DROPOOOSEG_MASK (1UL << I40IWQPC_DROPOOOSEG_SHIFT)
1033
1034 #define I40IWQPC_DUPACK_THRESH_SHIFT 16
1035 #define I40IWQPC_DUPACK_THRESH_MASK (7UL << I40IWQPC_DUPACK_THRESH_SHIFT)
1036
1037 #define I40IWQPC_ERR_RQ_IDX_VALID_SHIFT 19
1038 #define I40IWQPC_ERR_RQ_IDX_VALID_MASK (1UL << I40IWQPC_ERR_RQ_IDX_VALID_SHIFT)
1039
1040 #define I40IWQPC_DIS_VLAN_CHECKS_SHIFT 19
1041 #define I40IWQPC_DIS_VLAN_CHECKS_MASK (7UL << I40IWQPC_DIS_VLAN_CHECKS_SHIFT)
1042
1043 #define I40IWQPC_RCVTPHEN_SHIFT 28
1044 #define I40IWQPC_RCVTPHEN_MASK (1UL << I40IWQPC_RCVTPHEN_SHIFT)
1045
1046 #define I40IWQPC_XMITTPHEN_SHIFT 29
1047 #define I40IWQPC_XMITTPHEN_MASK (1ULL << I40IWQPC_XMITTPHEN_SHIFT)
1048
1049 #define I40IWQPC_RQTPHEN_SHIFT 30
1050 #define I40IWQPC_RQTPHEN_MASK (1UL << I40IWQPC_RQTPHEN_SHIFT)
1051
1052 #define I40IWQPC_SQTPHEN_SHIFT 31
1053 #define I40IWQPC_SQTPHEN_MASK (1ULL << I40IWQPC_SQTPHEN_SHIFT)
1054
1055 #define I40IWQPC_PPIDX_SHIFT 32
1056 #define I40IWQPC_PPIDX_MASK (0x3ffULL << I40IWQPC_PPIDX_SHIFT)
1057
1058 #define I40IWQPC_PMENA_SHIFT 47
1059 #define I40IWQPC_PMENA_MASK (1ULL << I40IWQPC_PMENA_SHIFT)
1060
1061 #define I40IWQPC_RDMAP_VER_SHIFT 62
1062 #define I40IWQPC_RDMAP_VER_MASK (3ULL << I40IWQPC_RDMAP_VER_SHIFT)
1063
1064 #define I40IWQPC_SQADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1065 #define I40IWQPC_SQADDR_MASK I40IW_CQPHC_QPCTX_MASK
1066
1067 #define I40IWQPC_RQADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1068 #define I40IWQPC_RQADDR_MASK I40IW_CQPHC_QPCTX_MASK
1069
1070 #define I40IWQPC_TTL_SHIFT 0
1071 #define I40IWQPC_TTL_MASK (0xffUL << I40IWQPC_TTL_SHIFT)
1072
1073 #define I40IWQPC_RQSIZE_SHIFT 8
1074 #define I40IWQPC_RQSIZE_MASK (0xfUL << I40IWQPC_RQSIZE_SHIFT)
1075
1076 #define I40IWQPC_SQSIZE_SHIFT 12
1077 #define I40IWQPC_SQSIZE_MASK (0xfUL << I40IWQPC_SQSIZE_SHIFT)
1078
1079 #define I40IWQPC_SRCMACADDRIDX_SHIFT 16
1080 #define I40IWQPC_SRCMACADDRIDX_MASK (0x3fUL << I40IWQPC_SRCMACADDRIDX_SHIFT)
1081
1082 #define I40IWQPC_AVOIDSTRETCHACK_SHIFT 23
1083 #define I40IWQPC_AVOIDSTRETCHACK_MASK (1UL << I40IWQPC_AVOIDSTRETCHACK_SHIFT)
1084
1085 #define I40IWQPC_TOS_SHIFT 24
1086 #define I40IWQPC_TOS_MASK (0xffUL << I40IWQPC_TOS_SHIFT)
1087
1088 #define I40IWQPC_SRCPORTNUM_SHIFT 32
1089 #define I40IWQPC_SRCPORTNUM_MASK (0xffffULL << I40IWQPC_SRCPORTNUM_SHIFT)
1090
1091 #define I40IWQPC_DESTPORTNUM_SHIFT 48
1092 #define I40IWQPC_DESTPORTNUM_MASK (0xffffULL << I40IWQPC_DESTPORTNUM_SHIFT)
1093
1094 #define I40IWQPC_DESTIPADDR0_SHIFT 32
1095 #define I40IWQPC_DESTIPADDR0_MASK \
1096 (0xffffffffULL << I40IWQPC_DESTIPADDR0_SHIFT)
1097
1098 #define I40IWQPC_DESTIPADDR1_SHIFT 0
1099 #define I40IWQPC_DESTIPADDR1_MASK \
1100 (0xffffffffULL << I40IWQPC_DESTIPADDR1_SHIFT)
1101
1102 #define I40IWQPC_DESTIPADDR2_SHIFT 32
1103 #define I40IWQPC_DESTIPADDR2_MASK \
1104 (0xffffffffULL << I40IWQPC_DESTIPADDR2_SHIFT)
1105
1106 #define I40IWQPC_DESTIPADDR3_SHIFT 0
1107 #define I40IWQPC_DESTIPADDR3_MASK \
1108 (0xffffffffULL << I40IWQPC_DESTIPADDR3_SHIFT)
1109
1110 #define I40IWQPC_SNDMSS_SHIFT 16
1111 #define I40IWQPC_SNDMSS_MASK (0x3fffUL << I40IWQPC_SNDMSS_SHIFT)
1112
1113 #define I40IW_UDA_QPC_MAXFRAMESIZE_SHIFT 16
1114 #define I40IW_UDA_QPC_MAXFRAMESIZE_MASK (0x3fffUL << I40IW_UDA_QPC_MAXFRAMESIZE_SHIFT)
1115
1116 #define I40IWQPC_VLANTAG_SHIFT 32
1117 #define I40IWQPC_VLANTAG_MASK (0xffffULL << I40IWQPC_VLANTAG_SHIFT)
1118
1119 #define I40IWQPC_ARPIDX_SHIFT 48
1120 #define I40IWQPC_ARPIDX_MASK (0xffffULL << I40IWQPC_ARPIDX_SHIFT)
1121
1122 #define I40IWQPC_FLOWLABEL_SHIFT 0
1123 #define I40IWQPC_FLOWLABEL_MASK (0xfffffUL << I40IWQPC_FLOWLABEL_SHIFT)
1124
1125 #define I40IWQPC_WSCALE_SHIFT 20
1126 #define I40IWQPC_WSCALE_MASK (1UL << I40IWQPC_WSCALE_SHIFT)
1127
1128 #define I40IWQPC_KEEPALIVE_SHIFT 21
1129 #define I40IWQPC_KEEPALIVE_MASK (1UL << I40IWQPC_KEEPALIVE_SHIFT)
1130
1131 #define I40IWQPC_IGNORE_TCP_OPT_SHIFT 22
1132 #define I40IWQPC_IGNORE_TCP_OPT_MASK (1UL << I40IWQPC_IGNORE_TCP_OPT_SHIFT)
1133
1134 #define I40IWQPC_IGNORE_TCP_UNS_OPT_SHIFT 23
1135 #define I40IWQPC_IGNORE_TCP_UNS_OPT_MASK \
1136 (1UL << I40IWQPC_IGNORE_TCP_UNS_OPT_SHIFT)
1137
1138 #define I40IWQPC_TCPSTATE_SHIFT 28
1139 #define I40IWQPC_TCPSTATE_MASK (0xfUL << I40IWQPC_TCPSTATE_SHIFT)
1140
1141 #define I40IWQPC_RCVSCALE_SHIFT 32
1142 #define I40IWQPC_RCVSCALE_MASK (0xfULL << I40IWQPC_RCVSCALE_SHIFT)
1143
1144 #define I40IWQPC_SNDSCALE_SHIFT 40
1145 #define I40IWQPC_SNDSCALE_MASK (0xfULL << I40IWQPC_SNDSCALE_SHIFT)
1146
1147 #define I40IWQPC_PDIDX_SHIFT 48
1148 #define I40IWQPC_PDIDX_MASK (0x7fffULL << I40IWQPC_PDIDX_SHIFT)
1149
1150 #define I40IWQPC_KALIVE_TIMER_MAX_PROBES_SHIFT 16
1151 #define I40IWQPC_KALIVE_TIMER_MAX_PROBES_MASK \
1152 (0xffUL << I40IWQPC_KALIVE_TIMER_MAX_PROBES_SHIFT)
1153
1154 #define I40IWQPC_KEEPALIVE_INTERVAL_SHIFT 24
1155 #define I40IWQPC_KEEPALIVE_INTERVAL_MASK \
1156 (0xffUL << I40IWQPC_KEEPALIVE_INTERVAL_SHIFT)
1157
1158 #define I40IWQPC_TIMESTAMP_RECENT_SHIFT 0
1159 #define I40IWQPC_TIMESTAMP_RECENT_MASK \
1160 (0xffffffffUL << I40IWQPC_TIMESTAMP_RECENT_SHIFT)
1161
1162 #define I40IWQPC_TIMESTAMP_AGE_SHIFT 32
1163 #define I40IWQPC_TIMESTAMP_AGE_MASK \
1164 (0xffffffffULL << I40IWQPC_TIMESTAMP_AGE_SHIFT)
1165
1166 #define I40IWQPC_SNDNXT_SHIFT 0
1167 #define I40IWQPC_SNDNXT_MASK (0xffffffffUL << I40IWQPC_SNDNXT_SHIFT)
1168
1169 #define I40IWQPC_SNDWND_SHIFT 32
1170 #define I40IWQPC_SNDWND_MASK (0xffffffffULL << I40IWQPC_SNDWND_SHIFT)
1171
1172 #define I40IWQPC_RCVNXT_SHIFT 0
1173 #define I40IWQPC_RCVNXT_MASK (0xffffffffUL << I40IWQPC_RCVNXT_SHIFT)
1174
1175 #define I40IWQPC_RCVWND_SHIFT 32
1176 #define I40IWQPC_RCVWND_MASK (0xffffffffULL << I40IWQPC_RCVWND_SHIFT)
1177
1178 #define I40IWQPC_SNDMAX_SHIFT 0
1179 #define I40IWQPC_SNDMAX_MASK (0xffffffffUL << I40IWQPC_SNDMAX_SHIFT)
1180
1181 #define I40IWQPC_SNDUNA_SHIFT 32
1182 #define I40IWQPC_SNDUNA_MASK (0xffffffffULL << I40IWQPC_SNDUNA_SHIFT)
1183
1184 #define I40IWQPC_SRTT_SHIFT 0
1185 #define I40IWQPC_SRTT_MASK (0xffffffffUL << I40IWQPC_SRTT_SHIFT)
1186
1187 #define I40IWQPC_RTTVAR_SHIFT 32
1188 #define I40IWQPC_RTTVAR_MASK (0xffffffffULL << I40IWQPC_RTTVAR_SHIFT)
1189
1190 #define I40IWQPC_SSTHRESH_SHIFT 0
1191 #define I40IWQPC_SSTHRESH_MASK (0xffffffffUL << I40IWQPC_SSTHRESH_SHIFT)
1192
1193 #define I40IWQPC_CWND_SHIFT 32
1194 #define I40IWQPC_CWND_MASK (0xffffffffULL << I40IWQPC_CWND_SHIFT)
1195
1196 #define I40IWQPC_SNDWL1_SHIFT 0
1197 #define I40IWQPC_SNDWL1_MASK (0xffffffffUL << I40IWQPC_SNDWL1_SHIFT)
1198
1199 #define I40IWQPC_SNDWL2_SHIFT 32
1200 #define I40IWQPC_SNDWL2_MASK (0xffffffffULL << I40IWQPC_SNDWL2_SHIFT)
1201
1202 #define I40IWQPC_ERR_RQ_IDX_SHIFT 32
1203 #define I40IWQPC_ERR_RQ_IDX_MASK (0x3fffULL << I40IWQPC_ERR_RQ_IDX_SHIFT)
1204
1205 #define I40IWQPC_MAXSNDWND_SHIFT 0
1206 #define I40IWQPC_MAXSNDWND_MASK (0xffffffffUL << I40IWQPC_MAXSNDWND_SHIFT)
1207
1208 #define I40IWQPC_REXMIT_THRESH_SHIFT 48
1209 #define I40IWQPC_REXMIT_THRESH_MASK (0x3fULL << I40IWQPC_REXMIT_THRESH_SHIFT)
1210
1211 #define I40IWQPC_TXCQNUM_SHIFT 0
1212 #define I40IWQPC_TXCQNUM_MASK (0x1ffffUL << I40IWQPC_TXCQNUM_SHIFT)
1213
1214 #define I40IWQPC_RXCQNUM_SHIFT 32
1215 #define I40IWQPC_RXCQNUM_MASK (0x1ffffULL << I40IWQPC_RXCQNUM_SHIFT)
1216
1217 #define I40IWQPC_STAT_INDEX_SHIFT 0
1218 #define I40IWQPC_STAT_INDEX_MASK (0x1fULL << I40IWQPC_STAT_INDEX_SHIFT)
1219
1220 #define I40IWQPC_Q2ADDR_SHIFT 0
1221 #define I40IWQPC_Q2ADDR_MASK (0xffffffffffffff00ULL << I40IWQPC_Q2ADDR_SHIFT)
1222
1223 #define I40IWQPC_LASTBYTESENT_SHIFT 0
1224 #define I40IWQPC_LASTBYTESENT_MASK (0xffUL << I40IWQPC_LASTBYTESENT_SHIFT)
1225
1226 #define I40IWQPC_SRQID_SHIFT 32
1227 #define I40IWQPC_SRQID_MASK (0xffULL << I40IWQPC_SRQID_SHIFT)
1228
1229 #define I40IWQPC_ORDSIZE_SHIFT 0
1230 #define I40IWQPC_ORDSIZE_MASK (0x7fUL << I40IWQPC_ORDSIZE_SHIFT)
1231
1232 #define I40IWQPC_IRDSIZE_SHIFT 16
1233 #define I40IWQPC_IRDSIZE_MASK (0x3UL << I40IWQPC_IRDSIZE_SHIFT)
1234
1235 #define I40IWQPC_WRRDRSPOK_SHIFT 20
1236 #define I40IWQPC_WRRDRSPOK_MASK (1UL << I40IWQPC_WRRDRSPOK_SHIFT)
1237
1238 #define I40IWQPC_RDOK_SHIFT 21
1239 #define I40IWQPC_RDOK_MASK (1UL << I40IWQPC_RDOK_SHIFT)
1240
1241 #define I40IWQPC_SNDMARKERS_SHIFT 22
1242 #define I40IWQPC_SNDMARKERS_MASK (1UL << I40IWQPC_SNDMARKERS_SHIFT)
1243
1244 #define I40IWQPC_BINDEN_SHIFT 23
1245 #define I40IWQPC_BINDEN_MASK (1UL << I40IWQPC_BINDEN_SHIFT)
1246
1247 #define I40IWQPC_FASTREGEN_SHIFT 24
1248 #define I40IWQPC_FASTREGEN_MASK (1UL << I40IWQPC_FASTREGEN_SHIFT)
1249
1250 #define I40IWQPC_PRIVEN_SHIFT 25
1251 #define I40IWQPC_PRIVEN_MASK (1UL << I40IWQPC_PRIVEN_SHIFT)
1252
1253 #define I40IWQPC_USESTATSINSTANCE_SHIFT 26
1254 #define I40IWQPC_USESTATSINSTANCE_MASK (1UL << I40IWQPC_USESTATSINSTANCE_SHIFT)
1255
1256 #define I40IWQPC_IWARPMODE_SHIFT 28
1257 #define I40IWQPC_IWARPMODE_MASK (1UL << I40IWQPC_IWARPMODE_SHIFT)
1258
1259 #define I40IWQPC_RCVMARKERS_SHIFT 29
1260 #define I40IWQPC_RCVMARKERS_MASK (1UL << I40IWQPC_RCVMARKERS_SHIFT)
1261
1262 #define I40IWQPC_ALIGNHDRS_SHIFT 30
1263 #define I40IWQPC_ALIGNHDRS_MASK (1UL << I40IWQPC_ALIGNHDRS_SHIFT)
1264
1265 #define I40IWQPC_RCVNOMPACRC_SHIFT 31
1266 #define I40IWQPC_RCVNOMPACRC_MASK (1UL << I40IWQPC_RCVNOMPACRC_SHIFT)
1267
1268 #define I40IWQPC_RCVMARKOFFSET_SHIFT 33
1269 #define I40IWQPC_RCVMARKOFFSET_MASK (0x1ffULL << I40IWQPC_RCVMARKOFFSET_SHIFT)
1270
1271 #define I40IWQPC_SNDMARKOFFSET_SHIFT 48
1272 #define I40IWQPC_SNDMARKOFFSET_MASK (0x1ffULL << I40IWQPC_SNDMARKOFFSET_SHIFT)
1273
1274 #define I40IWQPC_QPCOMPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1275 #define I40IWQPC_QPCOMPCTX_MASK I40IW_CQPHC_QPCTX_MASK
1276
1277 #define I40IWQPC_SQTPHVAL_SHIFT 0
1278 #define I40IWQPC_SQTPHVAL_MASK (0xffUL << I40IWQPC_SQTPHVAL_SHIFT)
1279
1280 #define I40IWQPC_RQTPHVAL_SHIFT 8
1281 #define I40IWQPC_RQTPHVAL_MASK (0xffUL << I40IWQPC_RQTPHVAL_SHIFT)
1282
1283 #define I40IWQPC_QSHANDLE_SHIFT 16
1284 #define I40IWQPC_QSHANDLE_MASK (0x3ffUL << I40IWQPC_QSHANDLE_SHIFT)
1285
1286 #define I40IWQPC_EXCEPTION_LAN_QUEUE_SHIFT 32
1287 #define I40IWQPC_EXCEPTION_LAN_QUEUE_MASK (0xfffULL << \
1288 I40IWQPC_EXCEPTION_LAN_QUEUE_SHIFT)
1289
1290 #define I40IWQPC_LOCAL_IPADDR3_SHIFT 0
1291 #define I40IWQPC_LOCAL_IPADDR3_MASK \
1292 (0xffffffffUL << I40IWQPC_LOCAL_IPADDR3_SHIFT)
1293
1294 #define I40IWQPC_LOCAL_IPADDR2_SHIFT 32
1295 #define I40IWQPC_LOCAL_IPADDR2_MASK \
1296 (0xffffffffULL << I40IWQPC_LOCAL_IPADDR2_SHIFT)
1297
1298 #define I40IWQPC_LOCAL_IPADDR1_SHIFT 0
1299 #define I40IWQPC_LOCAL_IPADDR1_MASK \
1300 (0xffffffffUL << I40IWQPC_LOCAL_IPADDR1_SHIFT)
1301
1302 #define I40IWQPC_LOCAL_IPADDR0_SHIFT 32
1303 #define I40IWQPC_LOCAL_IPADDR0_MASK \
1304 (0xffffffffULL << I40IWQPC_LOCAL_IPADDR0_SHIFT)
1305
1306
1307 #define I40IW_QP_SW_MIN_WQSIZE 4
1308 #define I40IW_SQ_RSVD 2
1309 #define I40IW_RQ_RSVD 1
1310 #define I40IW_MAX_QUANTAS_PER_WR 2
1311 #define I40IW_QP_SW_MAX_SQ_QUANTAS 2048
1312 #define I40IW_QP_SW_MAX_RQ_QUANTAS 16384
1313 #define I40IW_MAX_QP_WRS ((I40IW_QP_SW_MAX_SQ_QUANTAS / I40IW_MAX_QUANTAS_PER_WR) - 1)
1314
1315 #define I40IWQP_OP_RDMA_WRITE 0
1316 #define I40IWQP_OP_RDMA_READ 1
1317 #define I40IWQP_OP_RDMA_SEND 3
1318 #define I40IWQP_OP_RDMA_SEND_INV 4
1319 #define I40IWQP_OP_RDMA_SEND_SOL_EVENT 5
1320 #define I40IWQP_OP_RDMA_SEND_SOL_EVENT_INV 6
1321 #define I40IWQP_OP_BIND_MW 8
1322 #define I40IWQP_OP_FAST_REGISTER 9
1323 #define I40IWQP_OP_LOCAL_INVALIDATE 10
1324 #define I40IWQP_OP_RDMA_READ_LOC_INV 11
1325 #define I40IWQP_OP_NOP 12
1326
1327 #define I40IW_RSVD_SHIFT 41
1328 #define I40IW_RSVD_MASK (0x7fffULL << I40IW_RSVD_SHIFT)
1329
1330
1331 #define I40IWQPSQ_OPCODE_SHIFT 32
1332 #define I40IWQPSQ_OPCODE_MASK (0x3fULL << I40IWQPSQ_OPCODE_SHIFT)
1333
1334 #define I40IWQPSQ_ADDFRAGCNT_SHIFT 38
1335 #define I40IWQPSQ_ADDFRAGCNT_MASK (0x7ULL << I40IWQPSQ_ADDFRAGCNT_SHIFT)
1336
1337 #define I40IWQPSQ_PUSHWQE_SHIFT 56
1338 #define I40IWQPSQ_PUSHWQE_MASK (1ULL << I40IWQPSQ_PUSHWQE_SHIFT)
1339
1340 #define I40IWQPSQ_STREAMMODE_SHIFT 58
1341 #define I40IWQPSQ_STREAMMODE_MASK (1ULL << I40IWQPSQ_STREAMMODE_SHIFT)
1342
1343 #define I40IWQPSQ_WAITFORRCVPDU_SHIFT 59
1344 #define I40IWQPSQ_WAITFORRCVPDU_MASK (1ULL << I40IWQPSQ_WAITFORRCVPDU_SHIFT)
1345
1346 #define I40IWQPSQ_READFENCE_SHIFT 60
1347 #define I40IWQPSQ_READFENCE_MASK (1ULL << I40IWQPSQ_READFENCE_SHIFT)
1348
1349 #define I40IWQPSQ_LOCALFENCE_SHIFT 61
1350 #define I40IWQPSQ_LOCALFENCE_MASK (1ULL << I40IWQPSQ_LOCALFENCE_SHIFT)
1351
1352 #define I40IWQPSQ_SIGCOMPL_SHIFT 62
1353 #define I40IWQPSQ_SIGCOMPL_MASK (1ULL << I40IWQPSQ_SIGCOMPL_SHIFT)
1354
1355 #define I40IWQPSQ_VALID_SHIFT 63
1356 #define I40IWQPSQ_VALID_MASK (1ULL << I40IWQPSQ_VALID_SHIFT)
1357
1358 #define I40IWQPSQ_FRAG_TO_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1359 #define I40IWQPSQ_FRAG_TO_MASK I40IW_CQPHC_QPCTX_MASK
1360
1361 #define I40IWQPSQ_FRAG_LEN_SHIFT 0
1362 #define I40IWQPSQ_FRAG_LEN_MASK (0xffffffffUL << I40IWQPSQ_FRAG_LEN_SHIFT)
1363
1364 #define I40IWQPSQ_FRAG_STAG_SHIFT 32
1365 #define I40IWQPSQ_FRAG_STAG_MASK (0xffffffffULL << I40IWQPSQ_FRAG_STAG_SHIFT)
1366
1367 #define I40IWQPSQ_REMSTAGINV_SHIFT 0
1368 #define I40IWQPSQ_REMSTAGINV_MASK (0xffffffffUL << I40IWQPSQ_REMSTAGINV_SHIFT)
1369
1370 #define I40IWQPSQ_INLINEDATAFLAG_SHIFT 57
1371 #define I40IWQPSQ_INLINEDATAFLAG_MASK (1ULL << I40IWQPSQ_INLINEDATAFLAG_SHIFT)
1372
1373 #define I40IWQPSQ_INLINEDATALEN_SHIFT 48
1374 #define I40IWQPSQ_INLINEDATALEN_MASK \
1375 (0x7fULL << I40IWQPSQ_INLINEDATALEN_SHIFT)
1376
1377
1378 #define I40IWQPSQ_WQDESCIDX_SHIFT 0
1379 #define I40IWQPSQ_WQDESCIDX_MASK (0x3fffUL << I40IWQPSQ_WQDESCIDX_SHIFT)
1380
1381
1382 #define I40IWQPSQ_REMSTAG_SHIFT 0
1383 #define I40IWQPSQ_REMSTAG_MASK (0xffffffffUL << I40IWQPSQ_REMSTAG_SHIFT)
1384
1385 #define I40IWQPSQ_REMTO_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1386 #define I40IWQPSQ_REMTO_MASK I40IW_CQPHC_QPCTX_MASK
1387
1388
1389 #define I40IWQPSQ_STAGRIGHTS_SHIFT 48
1390 #define I40IWQPSQ_STAGRIGHTS_MASK (0x1fULL << I40IWQPSQ_STAGRIGHTS_SHIFT)
1391
1392 #define I40IWQPSQ_VABASEDTO_SHIFT 53
1393 #define I40IWQPSQ_VABASEDTO_MASK (1ULL << I40IWQPSQ_VABASEDTO_SHIFT)
1394
1395 #define I40IWQPSQ_MWLEN_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1396 #define I40IWQPSQ_MWLEN_MASK I40IW_CQPHC_QPCTX_MASK
1397
1398 #define I40IWQPSQ_PARENTMRSTAG_SHIFT 0
1399 #define I40IWQPSQ_PARENTMRSTAG_MASK \
1400 (0xffffffffUL << I40IWQPSQ_PARENTMRSTAG_SHIFT)
1401
1402 #define I40IWQPSQ_MWSTAG_SHIFT 32
1403 #define I40IWQPSQ_MWSTAG_MASK (0xffffffffULL << I40IWQPSQ_MWSTAG_SHIFT)
1404
1405 #define I40IWQPSQ_BASEVA_TO_FBO_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1406 #define I40IWQPSQ_BASEVA_TO_FBO_MASK I40IW_CQPHC_QPCTX_MASK
1407
1408
1409 #define I40IWQPSQ_LOCSTAG_SHIFT 32
1410 #define I40IWQPSQ_LOCSTAG_MASK (0xffffffffULL << I40IWQPSQ_LOCSTAG_SHIFT)
1411
1412
1413 #define I40IWQPSQ_STAGKEY_SHIFT 0
1414 #define I40IWQPSQ_STAGKEY_MASK (0xffUL << I40IWQPSQ_STAGKEY_SHIFT)
1415
1416 #define I40IWQPSQ_STAGINDEX_SHIFT 8
1417 #define I40IWQPSQ_STAGINDEX_MASK (0xffffffUL << I40IWQPSQ_STAGINDEX_SHIFT)
1418
1419 #define I40IWQPSQ_COPYHOSTPBLS_SHIFT 43
1420 #define I40IWQPSQ_COPYHOSTPBLS_MASK (1ULL << I40IWQPSQ_COPYHOSTPBLS_SHIFT)
1421
1422 #define I40IWQPSQ_LPBLSIZE_SHIFT 44
1423 #define I40IWQPSQ_LPBLSIZE_MASK (3ULL << I40IWQPSQ_LPBLSIZE_SHIFT)
1424
1425 #define I40IWQPSQ_HPAGESIZE_SHIFT 46
1426 #define I40IWQPSQ_HPAGESIZE_MASK (3ULL << I40IWQPSQ_HPAGESIZE_SHIFT)
1427
1428 #define I40IWQPSQ_STAGLEN_SHIFT 0
1429 #define I40IWQPSQ_STAGLEN_MASK (0x1ffffffffffULL << I40IWQPSQ_STAGLEN_SHIFT)
1430
1431 #define I40IWQPSQ_FIRSTPMPBLIDXLO_SHIFT 48
1432 #define I40IWQPSQ_FIRSTPMPBLIDXLO_MASK \
1433 (0xffffULL << I40IWQPSQ_FIRSTPMPBLIDXLO_SHIFT)
1434
1435 #define I40IWQPSQ_FIRSTPMPBLIDXHI_SHIFT 0
1436 #define I40IWQPSQ_FIRSTPMPBLIDXHI_MASK \
1437 (0xfffUL << I40IWQPSQ_FIRSTPMPBLIDXHI_SHIFT)
1438
1439 #define I40IWQPSQ_PBLADDR_SHIFT 12
1440 #define I40IWQPSQ_PBLADDR_MASK (0xfffffffffffffULL << I40IWQPSQ_PBLADDR_SHIFT)
1441
1442
1443 #define I40IWQPRQ_ADDFRAGCNT_SHIFT I40IWQPSQ_ADDFRAGCNT_SHIFT
1444 #define I40IWQPRQ_ADDFRAGCNT_MASK I40IWQPSQ_ADDFRAGCNT_MASK
1445
1446 #define I40IWQPRQ_VALID_SHIFT I40IWQPSQ_VALID_SHIFT
1447 #define I40IWQPRQ_VALID_MASK I40IWQPSQ_VALID_MASK
1448
1449 #define I40IWQPRQ_COMPLCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1450 #define I40IWQPRQ_COMPLCTX_MASK I40IW_CQPHC_QPCTX_MASK
1451
1452 #define I40IWQPRQ_FRAG_LEN_SHIFT I40IWQPSQ_FRAG_LEN_SHIFT
1453 #define I40IWQPRQ_FRAG_LEN_MASK I40IWQPSQ_FRAG_LEN_MASK
1454
1455 #define I40IWQPRQ_STAG_SHIFT I40IWQPSQ_FRAG_STAG_SHIFT
1456 #define I40IWQPRQ_STAG_MASK I40IWQPSQ_FRAG_STAG_MASK
1457
1458 #define I40IWQPRQ_TO_SHIFT I40IWQPSQ_FRAG_TO_SHIFT
1459 #define I40IWQPRQ_TO_MASK I40IWQPSQ_FRAG_TO_MASK
1460
1461
1462 #define I40IW_QUERY_FPM_MAX_QPS_SHIFT 0
1463 #define I40IW_QUERY_FPM_MAX_QPS_MASK \
1464 (0x7ffffUL << I40IW_QUERY_FPM_MAX_QPS_SHIFT)
1465
1466 #define I40IW_QUERY_FPM_MAX_CQS_SHIFT 0
1467 #define I40IW_QUERY_FPM_MAX_CQS_MASK \
1468 (0x3ffffUL << I40IW_QUERY_FPM_MAX_CQS_SHIFT)
1469
1470 #define I40IW_QUERY_FPM_FIRST_PE_SD_INDEX_SHIFT 0
1471 #define I40IW_QUERY_FPM_FIRST_PE_SD_INDEX_MASK \
1472 (0x3fffUL << I40IW_QUERY_FPM_FIRST_PE_SD_INDEX_SHIFT)
1473
1474 #define I40IW_QUERY_FPM_MAX_PE_SDS_SHIFT 32
1475 #define I40IW_QUERY_FPM_MAX_PE_SDS_MASK \
1476 (0x3fffULL << I40IW_QUERY_FPM_MAX_PE_SDS_SHIFT)
1477
1478 #define I40IW_QUERY_FPM_MAX_QPS_SHIFT 0
1479 #define I40IW_QUERY_FPM_MAX_QPS_MASK \
1480 (0x7ffffUL << I40IW_QUERY_FPM_MAX_QPS_SHIFT)
1481
1482 #define I40IW_QUERY_FPM_MAX_CQS_SHIFT 0
1483 #define I40IW_QUERY_FPM_MAX_CQS_MASK \
1484 (0x3ffffUL << I40IW_QUERY_FPM_MAX_CQS_SHIFT)
1485
1486 #define I40IW_QUERY_FPM_MAX_CEQS_SHIFT 0
1487 #define I40IW_QUERY_FPM_MAX_CEQS_MASK \
1488 (0xffUL << I40IW_QUERY_FPM_MAX_CEQS_SHIFT)
1489
1490 #define I40IW_QUERY_FPM_XFBLOCKSIZE_SHIFT 32
1491 #define I40IW_QUERY_FPM_XFBLOCKSIZE_MASK \
1492 (0xffffffffULL << I40IW_QUERY_FPM_XFBLOCKSIZE_SHIFT)
1493
1494 #define I40IW_QUERY_FPM_Q1BLOCKSIZE_SHIFT 32
1495 #define I40IW_QUERY_FPM_Q1BLOCKSIZE_MASK \
1496 (0xffffffffULL << I40IW_QUERY_FPM_Q1BLOCKSIZE_SHIFT)
1497
1498 #define I40IW_QUERY_FPM_HTMULTIPLIER_SHIFT 16
1499 #define I40IW_QUERY_FPM_HTMULTIPLIER_MASK \
1500 (0xfUL << I40IW_QUERY_FPM_HTMULTIPLIER_SHIFT)
1501
1502 #define I40IW_QUERY_FPM_TIMERBUCKET_SHIFT 32
1503 #define I40IW_QUERY_FPM_TIMERBUCKET_MASK \
1504 (0xffFFULL << I40IW_QUERY_FPM_TIMERBUCKET_SHIFT)
1505
1506
1507 #define I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID_SHIFT 0
1508 #define I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID_MASK \
1509 (0x3fUL << I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID_SHIFT)
1510
1511 #define I40IW_HW_PAGE_SIZE 4096
1512 #define I40IW_DONE_COUNT 1000
1513 #define I40IW_SLEEP_COUNT 10
1514
1515 enum {
1516 I40IW_QUEUES_ALIGNMENT_MASK = (128 - 1),
1517 I40IW_AEQ_ALIGNMENT_MASK = (256 - 1),
1518 I40IW_Q2_ALIGNMENT_MASK = (256 - 1),
1519 I40IW_CEQ_ALIGNMENT_MASK = (256 - 1),
1520 I40IW_CQ0_ALIGNMENT_MASK = (256 - 1),
1521 I40IW_HOST_CTX_ALIGNMENT_MASK = (4 - 1),
1522 I40IW_SHADOWAREA_MASK = (128 - 1),
1523 I40IW_FPM_QUERY_BUF_ALIGNMENT_MASK = (4 - 1),
1524 I40IW_FPM_COMMIT_BUF_ALIGNMENT_MASK = (4 - 1)
1525 };
1526
1527 enum i40iw_alignment {
1528 I40IW_CQP_ALIGNMENT = 0x200,
1529 I40IW_AEQ_ALIGNMENT = 0x100,
1530 I40IW_CEQ_ALIGNMENT = 0x100,
1531 I40IW_CQ0_ALIGNMENT = 0x100,
1532 I40IW_SD_BUF_ALIGNMENT = 0x80
1533 };
1534
1535 #define I40IW_WQE_SIZE_64 64
1536
1537 #define I40IW_QP_WQE_MIN_SIZE 32
1538 #define I40IW_QP_WQE_MAX_SIZE 128
1539
1540 #define I40IW_UPDATE_SD_BUF_SIZE 128
1541
1542 #define I40IW_CQE_QTYPE_RQ 0
1543 #define I40IW_CQE_QTYPE_SQ 1
1544
1545 #define I40IW_RING_INIT(_ring, _size) \
1546 { \
1547 (_ring).head = 0; \
1548 (_ring).tail = 0; \
1549 (_ring).size = (_size); \
1550 }
1551 #define I40IW_RING_GETSIZE(_ring) ((_ring).size)
1552 #define I40IW_RING_GETCURRENT_HEAD(_ring) ((_ring).head)
1553 #define I40IW_RING_GETCURRENT_TAIL(_ring) ((_ring).tail)
1554
1555 #define I40IW_RING_MOVE_HEAD(_ring, _retcode) \
1556 { \
1557 register u32 size; \
1558 size = (_ring).size; \
1559 if (!I40IW_RING_FULL_ERR(_ring)) { \
1560 (_ring).head = ((_ring).head + 1) % size; \
1561 (_retcode) = 0; \
1562 } else { \
1563 (_retcode) = I40IW_ERR_RING_FULL; \
1564 } \
1565 }
1566
1567 #define I40IW_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \
1568 { \
1569 register u32 size; \
1570 size = (_ring).size; \
1571 if ((I40IW_RING_WORK_AVAILABLE(_ring) + (_count)) < size) { \
1572 (_ring).head = ((_ring).head + (_count)) % size; \
1573 (_retcode) = 0; \
1574 } else { \
1575 (_retcode) = I40IW_ERR_RING_FULL; \
1576 } \
1577 }
1578
1579 #define I40IW_RING_MOVE_TAIL(_ring) \
1580 (_ring).tail = ((_ring).tail + 1) % (_ring).size
1581
1582 #define I40IW_RING_MOVE_HEAD_NOCHECK(_ring) \
1583 (_ring).head = ((_ring).head + 1) % (_ring).size
1584
1585 #define I40IW_RING_MOVE_TAIL_BY_COUNT(_ring, _count) \
1586 (_ring).tail = ((_ring).tail + (_count)) % (_ring).size
1587
1588 #define I40IW_RING_SET_TAIL(_ring, _pos) \
1589 (_ring).tail = (_pos) % (_ring).size
1590
1591 #define I40IW_RING_FULL_ERR(_ring) \
1592 ( \
1593 (I40IW_RING_WORK_AVAILABLE(_ring) == ((_ring).size - 1)) \
1594 )
1595
1596 #define I40IW_ERR_RING_FULL2(_ring) \
1597 ( \
1598 (I40IW_RING_WORK_AVAILABLE(_ring) == ((_ring).size - 2)) \
1599 )
1600
1601 #define I40IW_ERR_RING_FULL3(_ring) \
1602 ( \
1603 (I40IW_RING_WORK_AVAILABLE(_ring) == ((_ring).size - 3)) \
1604 )
1605
1606 #define I40IW_RING_MORE_WORK(_ring) \
1607 ( \
1608 (I40IW_RING_WORK_AVAILABLE(_ring) != 0) \
1609 )
1610
1611 #define I40IW_RING_WORK_AVAILABLE(_ring) \
1612 ( \
1613 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1614 )
1615
1616 #define I40IW_RING_GET_WQES_AVAILABLE(_ring) \
1617 ( \
1618 ((_ring).size - I40IW_RING_WORK_AVAILABLE(_ring) - 1) \
1619 )
1620
1621 #define I40IW_ATOMIC_RING_MOVE_HEAD(_ring, index, _retcode) \
1622 { \
1623 index = I40IW_RING_GETCURRENT_HEAD(_ring); \
1624 I40IW_RING_MOVE_HEAD(_ring, _retcode); \
1625 }
1626
1627
1628 #define I40IW_AE_AMP_UNALLOCATED_STAG 0x0102
1629 #define I40IW_AE_AMP_INVALID_STAG 0x0103
1630 #define I40IW_AE_AMP_BAD_QP 0x0104
1631 #define I40IW_AE_AMP_BAD_PD 0x0105
1632 #define I40IW_AE_AMP_BAD_STAG_KEY 0x0106
1633 #define I40IW_AE_AMP_BAD_STAG_INDEX 0x0107
1634 #define I40IW_AE_AMP_BOUNDS_VIOLATION 0x0108
1635 #define I40IW_AE_AMP_RIGHTS_VIOLATION 0x0109
1636 #define I40IW_AE_AMP_TO_WRAP 0x010a
1637 #define I40IW_AE_AMP_FASTREG_SHARED 0x010b
1638 #define I40IW_AE_AMP_FASTREG_VALID_STAG 0x010c
1639 #define I40IW_AE_AMP_FASTREG_MW_STAG 0x010d
1640 #define I40IW_AE_AMP_FASTREG_INVALID_RIGHTS 0x010e
1641 #define I40IW_AE_AMP_FASTREG_PBL_TABLE_OVERFLOW 0x010f
1642 #define I40IW_AE_AMP_FASTREG_INVALID_LENGTH 0x0110
1643 #define I40IW_AE_AMP_INVALIDATE_SHARED 0x0111
1644 #define I40IW_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS 0x0112
1645 #define I40IW_AE_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS 0x0113
1646 #define I40IW_AE_AMP_MWBIND_VALID_STAG 0x0114
1647 #define I40IW_AE_AMP_MWBIND_OF_MR_STAG 0x0115
1648 #define I40IW_AE_AMP_MWBIND_TO_ZERO_BASED_STAG 0x0116
1649 #define I40IW_AE_AMP_MWBIND_TO_MW_STAG 0x0117
1650 #define I40IW_AE_AMP_MWBIND_INVALID_RIGHTS 0x0118
1651 #define I40IW_AE_AMP_MWBIND_INVALID_BOUNDS 0x0119
1652 #define I40IW_AE_AMP_MWBIND_TO_INVALID_PARENT 0x011a
1653 #define I40IW_AE_AMP_MWBIND_BIND_DISABLED 0x011b
1654 #define I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG 0x0132
1655 #define I40IW_AE_UDA_XMIT_DGRAM_TOO_SHORT 0x0134
1656 #define I40IW_AE_BAD_CLOSE 0x0201
1657 #define I40IW_AE_RDMAP_ROE_BAD_LLP_CLOSE 0x0202
1658 #define I40IW_AE_CQ_OPERATION_ERROR 0x0203
1659 #define I40IW_AE_PRIV_OPERATION_DENIED 0x011c
1660 #define I40IW_AE_RDMA_READ_WHILE_ORD_ZERO 0x0205
1661 #define I40IW_AE_STAG_ZERO_INVALID 0x0206
1662 #define I40IW_AE_IB_RREQ_AND_Q1_FULL 0x0207
1663 #define I40IW_AE_WQE_UNEXPECTED_OPCODE 0x020a
1664 #define I40IW_AE_WQE_INVALID_PARAMETER 0x020b
1665 #define I40IW_AE_WQE_LSMM_TOO_LONG 0x0220
1666 #define I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301
1667 #define I40IW_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303
1668 #define I40IW_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304
1669 #define I40IW_AE_DDP_UBE_INVALID_MO 0x0305
1670 #define I40IW_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE 0x0306
1671 #define I40IW_AE_DDP_UBE_INVALID_QN 0x0307
1672 #define I40IW_AE_DDP_NO_L_BIT 0x0308
1673 #define I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION 0x0311
1674 #define I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE 0x0312
1675 #define I40IW_AE_ROE_INVALID_RDMA_READ_REQUEST 0x0313
1676 #define I40IW_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP 0x0314
1677 #define I40IW_AE_INVALID_ARP_ENTRY 0x0401
1678 #define I40IW_AE_INVALID_TCP_OPTION_RCVD 0x0402
1679 #define I40IW_AE_STALE_ARP_ENTRY 0x0403
1680 #define I40IW_AE_INVALID_MAC_ENTRY 0x0405
1681 #define I40IW_AE_LLP_CLOSE_COMPLETE 0x0501
1682 #define I40IW_AE_LLP_CONNECTION_RESET 0x0502
1683 #define I40IW_AE_LLP_FIN_RECEIVED 0x0503
1684 #define I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR 0x0505
1685 #define I40IW_AE_LLP_SEGMENT_TOO_LARGE 0x0506
1686 #define I40IW_AE_LLP_SEGMENT_TOO_SMALL 0x0507
1687 #define I40IW_AE_LLP_SYN_RECEIVED 0x0508
1688 #define I40IW_AE_LLP_TERMINATE_RECEIVED 0x0509
1689 #define I40IW_AE_LLP_TOO_MANY_RETRIES 0x050a
1690 #define I40IW_AE_LLP_TOO_MANY_KEEPALIVE_RETRIES 0x050b
1691 #define I40IW_AE_LLP_DOUBT_REACHABILITY 0x050c
1692 #define I40IW_AE_LLP_RX_VLAN_MISMATCH 0x050d
1693 #define I40IW_AE_RESOURCE_EXHAUSTION 0x0520
1694 #define I40IW_AE_RESET_SENT 0x0601
1695 #define I40IW_AE_TERMINATE_SENT 0x0602
1696 #define I40IW_AE_RESET_NOT_SENT 0x0603
1697 #define I40IW_AE_LCE_QP_CATASTROPHIC 0x0700
1698 #define I40IW_AE_LCE_FUNCTION_CATASTROPHIC 0x0701
1699 #define I40IW_AE_LCE_CQ_CATASTROPHIC 0x0702
1700 #define I40IW_AE_QP_SUSPEND_COMPLETE 0x0900
1701
1702 #define OP_DELETE_LOCAL_MAC_IPADDR_ENTRY 1
1703 #define OP_CEQ_DESTROY 2
1704 #define OP_AEQ_DESTROY 3
1705 #define OP_DELETE_ARP_CACHE_ENTRY 4
1706 #define OP_MANAGE_APBVT_ENTRY 5
1707 #define OP_CEQ_CREATE 6
1708 #define OP_AEQ_CREATE 7
1709 #define OP_ALLOC_LOCAL_MAC_IPADDR_ENTRY 8
1710 #define OP_ADD_LOCAL_MAC_IPADDR_ENTRY 9
1711 #define OP_MANAGE_QHASH_TABLE_ENTRY 10
1712 #define OP_QP_MODIFY 11
1713 #define OP_QP_UPLOAD_CONTEXT 12
1714 #define OP_CQ_CREATE 13
1715 #define OP_CQ_DESTROY 14
1716 #define OP_QP_CREATE 15
1717 #define OP_QP_DESTROY 16
1718 #define OP_ALLOC_STAG 17
1719 #define OP_MR_REG_NON_SHARED 18
1720 #define OP_DEALLOC_STAG 19
1721 #define OP_MW_ALLOC 20
1722 #define OP_QP_FLUSH_WQES 21
1723 #define OP_ADD_ARP_CACHE_ENTRY 22
1724 #define OP_MANAGE_PUSH_PAGE 23
1725 #define OP_UPDATE_PE_SDS 24
1726 #define OP_MANAGE_HMC_PM_FUNC_TABLE 25
1727 #define OP_SUSPEND 26
1728 #define OP_RESUME 27
1729 #define OP_MANAGE_VF_PBLE_BP 28
1730 #define OP_QUERY_FPM_VALUES 29
1731 #define OP_COMMIT_FPM_VALUES 30
1732 #define OP_REQUESTED_COMMANDS 31
1733 #define OP_COMPLETED_COMMANDS 32
1734 #define OP_GEN_AE 33
1735 #define OP_SIZE_CQP_STAT_ARRAY 34
1736
1737 #endif