This source file includes following definitions.
- is_qp0
- is_sqp
- mlx5_ib_read_user_wqe_common
- mlx5_ib_read_user_wqe_sq
- mlx5_ib_read_user_wqe_rq
- mlx5_ib_read_user_wqe_srq
- mlx5_ib_qp_event
- set_rq_size
- sq_overhead
- calc_send_wqe
- get_send_sge
- calc_sq_size
- set_user_buf_size
- qp_has_rq
- max_bfregs
- num_med_bfreg
- first_med_bfreg
- first_hi_bfreg
- alloc_high_class_bfreg
- alloc_med_class_bfreg
- alloc_bfreg
- mlx5_ib_free_bfreg
- to_mlx5_state
- to_mlx5_st
- bfregn_to_uar_index
- mlx5_ib_umem_get
- destroy_user_rq
- create_user_rq
- adjust_bfregn
- create_user_qp
- destroy_qp_user
- get_sq_edge
- create_kernel_qp
- destroy_qp_kernel
- get_rx_type
- is_connected
- create_raw_packet_qp_tis
- destroy_raw_packet_qp_tis
- destroy_flow_rule_vport_sq
- create_raw_packet_qp_sq
- destroy_raw_packet_qp_sq
- get_rq_pas_size
- create_raw_packet_qp_rq
- destroy_raw_packet_qp_rq
- tunnel_offload_supported
- destroy_raw_packet_qp_tir
- create_raw_packet_qp_tir
- create_raw_packet_qp
- destroy_raw_packet_qp
- raw_packet_qp_copy_info
- destroy_rss_raw_qp_tir
- create_rss_raw_qp_tir
- configure_responder_scat_cqe
- configure_requester_scat_cqe
- atomic_size_to_mode
- get_atomic_mode
- check_flags_mask
- create_qp_common
- mlx5_ib_lock_cqs
- mlx5_ib_unlock_cqs
- get_pd
- get_cqs
- destroy_qp_common
- ib_qp_type_str
- mlx5_ib_create_dct
- set_mlx_qp_type
- mlx5_ib_create_qp
- mlx5_ib_destroy_dct
- mlx5_ib_destroy_qp
- to_mlx5_access_flags
- ib_rate_to_mlx5
- modify_raw_packet_eth_prio
- modify_raw_packet_tx_affinity
- mlx5_set_path
- ib_nr_to_mlx5_nr
- ib_mask_to_mlx5_opt
- modify_raw_packet_qp_rq
- modify_raw_packet_qp_sq
- modify_raw_packet_qp
- get_tx_affinity
- __mlx5_ib_qp_set_counter
- __mlx5_ib_modify_qp
- is_valid_mask
- modify_dci_qp_is_ok
- mlx5_ib_modify_dct
- mlx5_ib_modify_qp
- _handle_post_send_edge
- handle_post_send_edge
- memcpy_send_wqe
- mlx5_wq_overflow
- set_raddr_seg
- set_eth_seg
- set_datagram_seg
- set_data_ptr_seg
- get_xlt_octo
- frwr_mkey_mask
- sig_mkey_mask
- set_reg_umr_seg
- set_linv_umr_seg
- get_umr_enable_mr_mask
- get_umr_disable_mr_mask
- get_umr_update_translation_mask
- get_umr_update_access_mask
- get_umr_update_pd_mask
- umr_check_mkey_mask
- set_reg_umr_segment
- get_umr_flags
- set_reg_mkey_seg
- set_linv_mkey_seg
- set_reg_mkey_segment
- set_reg_data_seg
- send_ieth
- calc_sig
- wq_sig
- set_data_inl_seg
- prot_field_size
- bs_selector
- mlx5_fill_inl_bsf
- mlx5_set_bsf
- set_sig_data_segment
- set_sig_mkey_segment
- set_sig_umr_segment
- set_pi_umr_wr
- set_psv_wr
- set_reg_wr
- set_linv_wr
- dump_wqe
- __begin_wqe
- begin_wqe
- finish_wqe
- _mlx5_ib_post_send
- mlx5_ib_post_send
- set_sig_seg
- _mlx5_ib_post_recv
- mlx5_ib_post_recv
- to_ib_qp_state
- to_ib_mig_state
- to_ib_qp_access_flags
- to_rdma_ah_attr
- query_raw_packet_qp_sq_state
- query_raw_packet_qp_rq_state
- sqrq_state_to_qp_state
- query_raw_packet_qp_state
- query_qp_attr
- mlx5_ib_dct_query_qp
- mlx5_ib_query_qp
- mlx5_ib_alloc_xrcd
- mlx5_ib_dealloc_xrcd
- mlx5_ib_wq_event
- set_delay_drop
- create_rq
- set_user_rq_size
- prepare_user_rq
- mlx5_ib_create_wq
- mlx5_ib_destroy_wq
- mlx5_ib_create_rwq_ind_table
- mlx5_ib_destroy_rwq_ind_table
- mlx5_ib_modify_wq
- mlx5_ib_drain_qp_done
- handle_drain_completion
- mlx5_ib_drain_sq
- mlx5_ib_drain_rq
- mlx5_ib_qp_set_counter
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33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <rdma/rdma_counter.h>
38 #include <linux/mlx5/fs.h>
39 #include "mlx5_ib.h"
40 #include "ib_rep.h"
41 #include "cmd.h"
42
43
44 static int wq_signature;
45
46 enum {
47 MLX5_IB_ACK_REQ_FREQ = 8,
48 };
49
50 enum {
51 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
52 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
53 MLX5_IB_LINK_TYPE_IB = 0,
54 MLX5_IB_LINK_TYPE_ETH = 1
55 };
56
57 enum {
58 MLX5_IB_SQ_STRIDE = 6,
59 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
60 };
61
62 static const u32 mlx5_ib_opcode[] = {
63 [IB_WR_SEND] = MLX5_OPCODE_SEND,
64 [IB_WR_LSO] = MLX5_OPCODE_LSO,
65 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
66 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
67 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
68 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
69 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
70 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
71 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
72 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
73 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
74 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
75 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
76 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
77 };
78
79 struct mlx5_wqe_eth_pad {
80 u8 rsvd0[16];
81 };
82
83 enum raw_qp_set_mask_map {
84 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
85 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
86 };
87
88 struct mlx5_modify_raw_qp_param {
89 u16 operation;
90
91 u32 set_mask;
92
93 struct mlx5_rate_limit rl;
94
95 u8 rq_q_ctr_id;
96 u16 port;
97 };
98
99 static void get_cqs(enum ib_qp_type qp_type,
100 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
101 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
102
103 static int is_qp0(enum ib_qp_type qp_type)
104 {
105 return qp_type == IB_QPT_SMI;
106 }
107
108 static int is_sqp(enum ib_qp_type qp_type)
109 {
110 return is_qp0(qp_type) || is_qp1(qp_type);
111 }
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132 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem,
133 void *buffer,
134 u32 buflen,
135 int wqe_index,
136 int wq_offset,
137 int wq_wqe_cnt,
138 int wq_wqe_shift,
139 int bcnt,
140 size_t *bytes_copied)
141 {
142 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
143 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
144 size_t copy_length;
145 int ret;
146
147
148
149
150 copy_length = min_t(u32, buflen, wq_end - offset);
151 copy_length = min_t(u32, copy_length, bcnt);
152
153 ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
154 if (ret)
155 return ret;
156
157 if (!ret && bytes_copied)
158 *bytes_copied = copy_length;
159
160 return 0;
161 }
162
163 int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp,
164 int wqe_index,
165 void *buffer,
166 int buflen,
167 size_t *bc)
168 {
169 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
170 struct ib_umem *umem = base->ubuffer.umem;
171 struct mlx5_ib_wq *wq = &qp->sq;
172 struct mlx5_wqe_ctrl_seg *ctrl;
173 size_t bytes_copied;
174 size_t bytes_copied2;
175 size_t wqe_length;
176 int ret;
177 int ds;
178
179 if (buflen < sizeof(*ctrl))
180 return -EINVAL;
181
182
183 ret = mlx5_ib_read_user_wqe_common(umem,
184 buffer,
185 buflen,
186 wqe_index,
187 wq->offset,
188 wq->wqe_cnt,
189 wq->wqe_shift,
190 buflen,
191 &bytes_copied);
192 if (ret)
193 return ret;
194
195
196 if (bytes_copied < sizeof(*ctrl))
197 return -EINVAL;
198
199 ctrl = buffer;
200 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
201 wqe_length = ds * MLX5_WQE_DS_UNITS;
202
203
204 if (bytes_copied >= wqe_length) {
205 *bc = bytes_copied;
206 return 0;
207 }
208
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211
212
213 ret = mlx5_ib_read_user_wqe_common(umem,
214 buffer + bytes_copied,
215 buflen - bytes_copied,
216 0,
217 wq->offset,
218 wq->wqe_cnt,
219 wq->wqe_shift,
220 wqe_length - bytes_copied,
221 &bytes_copied2);
222
223 if (ret)
224 return ret;
225 *bc = bytes_copied + bytes_copied2;
226 return 0;
227 }
228
229 int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp,
230 int wqe_index,
231 void *buffer,
232 int buflen,
233 size_t *bc)
234 {
235 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
236 struct ib_umem *umem = base->ubuffer.umem;
237 struct mlx5_ib_wq *wq = &qp->rq;
238 size_t bytes_copied;
239 int ret;
240
241 ret = mlx5_ib_read_user_wqe_common(umem,
242 buffer,
243 buflen,
244 wqe_index,
245 wq->offset,
246 wq->wqe_cnt,
247 wq->wqe_shift,
248 buflen,
249 &bytes_copied);
250
251 if (ret)
252 return ret;
253 *bc = bytes_copied;
254 return 0;
255 }
256
257 int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq,
258 int wqe_index,
259 void *buffer,
260 int buflen,
261 size_t *bc)
262 {
263 struct ib_umem *umem = srq->umem;
264 size_t bytes_copied;
265 int ret;
266
267 ret = mlx5_ib_read_user_wqe_common(umem,
268 buffer,
269 buflen,
270 wqe_index,
271 0,
272 srq->msrq.max,
273 srq->msrq.wqe_shift,
274 buflen,
275 &bytes_copied);
276
277 if (ret)
278 return ret;
279 *bc = bytes_copied;
280 return 0;
281 }
282
283 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
284 {
285 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
286 struct ib_event event;
287
288 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
289
290 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
291 }
292
293 if (ibqp->event_handler) {
294 event.device = ibqp->device;
295 event.element.qp = ibqp;
296 switch (type) {
297 case MLX5_EVENT_TYPE_PATH_MIG:
298 event.event = IB_EVENT_PATH_MIG;
299 break;
300 case MLX5_EVENT_TYPE_COMM_EST:
301 event.event = IB_EVENT_COMM_EST;
302 break;
303 case MLX5_EVENT_TYPE_SQ_DRAINED:
304 event.event = IB_EVENT_SQ_DRAINED;
305 break;
306 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
307 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
308 break;
309 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
310 event.event = IB_EVENT_QP_FATAL;
311 break;
312 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
313 event.event = IB_EVENT_PATH_MIG_ERR;
314 break;
315 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
316 event.event = IB_EVENT_QP_REQ_ERR;
317 break;
318 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
319 event.event = IB_EVENT_QP_ACCESS_ERR;
320 break;
321 default:
322 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
323 return;
324 }
325
326 ibqp->event_handler(&event, ibqp->qp_context);
327 }
328 }
329
330 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
331 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
332 {
333 int wqe_size;
334 int wq_size;
335
336
337 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
338 return -EINVAL;
339
340 if (!has_rq) {
341 qp->rq.max_gs = 0;
342 qp->rq.wqe_cnt = 0;
343 qp->rq.wqe_shift = 0;
344 cap->max_recv_wr = 0;
345 cap->max_recv_sge = 0;
346 } else {
347 if (ucmd) {
348 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
349 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
350 return -EINVAL;
351 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
352 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
353 return -EINVAL;
354 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
355 qp->rq.max_post = qp->rq.wqe_cnt;
356 } else {
357 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
358 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
359 wqe_size = roundup_pow_of_two(wqe_size);
360 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
361 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
362 qp->rq.wqe_cnt = wq_size / wqe_size;
363 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
364 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
365 wqe_size,
366 MLX5_CAP_GEN(dev->mdev,
367 max_wqe_sz_rq));
368 return -EINVAL;
369 }
370 qp->rq.wqe_shift = ilog2(wqe_size);
371 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
372 qp->rq.max_post = qp->rq.wqe_cnt;
373 }
374 }
375
376 return 0;
377 }
378
379 static int sq_overhead(struct ib_qp_init_attr *attr)
380 {
381 int size = 0;
382
383 switch (attr->qp_type) {
384 case IB_QPT_XRC_INI:
385 size += sizeof(struct mlx5_wqe_xrc_seg);
386
387 case IB_QPT_RC:
388 size += sizeof(struct mlx5_wqe_ctrl_seg) +
389 max(sizeof(struct mlx5_wqe_atomic_seg) +
390 sizeof(struct mlx5_wqe_raddr_seg),
391 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
392 sizeof(struct mlx5_mkey_seg) +
393 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
394 MLX5_IB_UMR_OCTOWORD);
395 break;
396
397 case IB_QPT_XRC_TGT:
398 return 0;
399
400 case IB_QPT_UC:
401 size += sizeof(struct mlx5_wqe_ctrl_seg) +
402 max(sizeof(struct mlx5_wqe_raddr_seg),
403 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
404 sizeof(struct mlx5_mkey_seg));
405 break;
406
407 case IB_QPT_UD:
408 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
409 size += sizeof(struct mlx5_wqe_eth_pad) +
410 sizeof(struct mlx5_wqe_eth_seg);
411
412 case IB_QPT_SMI:
413 case MLX5_IB_QPT_HW_GSI:
414 size += sizeof(struct mlx5_wqe_ctrl_seg) +
415 sizeof(struct mlx5_wqe_datagram_seg);
416 break;
417
418 case MLX5_IB_QPT_REG_UMR:
419 size += sizeof(struct mlx5_wqe_ctrl_seg) +
420 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
421 sizeof(struct mlx5_mkey_seg);
422 break;
423
424 default:
425 return -EINVAL;
426 }
427
428 return size;
429 }
430
431 static int calc_send_wqe(struct ib_qp_init_attr *attr)
432 {
433 int inl_size = 0;
434 int size;
435
436 size = sq_overhead(attr);
437 if (size < 0)
438 return size;
439
440 if (attr->cap.max_inline_data) {
441 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
442 attr->cap.max_inline_data;
443 }
444
445 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
446 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN &&
447 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
448 return MLX5_SIG_WQE_SIZE;
449 else
450 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
451 }
452
453 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
454 {
455 int max_sge;
456
457 if (attr->qp_type == IB_QPT_RC)
458 max_sge = (min_t(int, wqe_size, 512) -
459 sizeof(struct mlx5_wqe_ctrl_seg) -
460 sizeof(struct mlx5_wqe_raddr_seg)) /
461 sizeof(struct mlx5_wqe_data_seg);
462 else if (attr->qp_type == IB_QPT_XRC_INI)
463 max_sge = (min_t(int, wqe_size, 512) -
464 sizeof(struct mlx5_wqe_ctrl_seg) -
465 sizeof(struct mlx5_wqe_xrc_seg) -
466 sizeof(struct mlx5_wqe_raddr_seg)) /
467 sizeof(struct mlx5_wqe_data_seg);
468 else
469 max_sge = (wqe_size - sq_overhead(attr)) /
470 sizeof(struct mlx5_wqe_data_seg);
471
472 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
473 sizeof(struct mlx5_wqe_data_seg));
474 }
475
476 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
477 struct mlx5_ib_qp *qp)
478 {
479 int wqe_size;
480 int wq_size;
481
482 if (!attr->cap.max_send_wr)
483 return 0;
484
485 wqe_size = calc_send_wqe(attr);
486 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
487 if (wqe_size < 0)
488 return wqe_size;
489
490 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
491 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
492 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
493 return -EINVAL;
494 }
495
496 qp->max_inline_data = wqe_size - sq_overhead(attr) -
497 sizeof(struct mlx5_wqe_inline_seg);
498 attr->cap.max_inline_data = qp->max_inline_data;
499
500 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
501 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
502 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
503 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
504 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
505 qp->sq.wqe_cnt,
506 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
507 return -ENOMEM;
508 }
509 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
510 qp->sq.max_gs = get_send_sge(attr, wqe_size);
511 if (qp->sq.max_gs < attr->cap.max_send_sge)
512 return -ENOMEM;
513
514 attr->cap.max_send_sge = qp->sq.max_gs;
515 qp->sq.max_post = wq_size / wqe_size;
516 attr->cap.max_send_wr = qp->sq.max_post;
517
518 return wq_size;
519 }
520
521 static int set_user_buf_size(struct mlx5_ib_dev *dev,
522 struct mlx5_ib_qp *qp,
523 struct mlx5_ib_create_qp *ucmd,
524 struct mlx5_ib_qp_base *base,
525 struct ib_qp_init_attr *attr)
526 {
527 int desc_sz = 1 << qp->sq.wqe_shift;
528
529 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
530 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
531 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
532 return -EINVAL;
533 }
534
535 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
536 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
537 ucmd->sq_wqe_count);
538 return -EINVAL;
539 }
540
541 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
542
543 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
544 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
545 qp->sq.wqe_cnt,
546 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
547 return -EINVAL;
548 }
549
550 if (attr->qp_type == IB_QPT_RAW_PACKET ||
551 qp->flags & MLX5_IB_QP_UNDERLAY) {
552 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
553 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
554 } else {
555 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
556 (qp->sq.wqe_cnt << 6);
557 }
558
559 return 0;
560 }
561
562 static int qp_has_rq(struct ib_qp_init_attr *attr)
563 {
564 if (attr->qp_type == IB_QPT_XRC_INI ||
565 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
566 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
567 !attr->cap.max_recv_wr)
568 return 0;
569
570 return 1;
571 }
572
573 enum {
574
575
576
577
578
579 NUM_NON_BLUE_FLAME_BFREGS = 1,
580 };
581
582 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
583 {
584 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
585 }
586
587 static int num_med_bfreg(struct mlx5_ib_dev *dev,
588 struct mlx5_bfreg_info *bfregi)
589 {
590 int n;
591
592 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
593 NUM_NON_BLUE_FLAME_BFREGS;
594
595 return n >= 0 ? n : 0;
596 }
597
598 static int first_med_bfreg(struct mlx5_ib_dev *dev,
599 struct mlx5_bfreg_info *bfregi)
600 {
601 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
602 }
603
604 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
605 struct mlx5_bfreg_info *bfregi)
606 {
607 int med;
608
609 med = num_med_bfreg(dev, bfregi);
610 return ++med;
611 }
612
613 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
614 struct mlx5_bfreg_info *bfregi)
615 {
616 int i;
617
618 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
619 if (!bfregi->count[i]) {
620 bfregi->count[i]++;
621 return i;
622 }
623 }
624
625 return -ENOMEM;
626 }
627
628 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
629 struct mlx5_bfreg_info *bfregi)
630 {
631 int minidx = first_med_bfreg(dev, bfregi);
632 int i;
633
634 if (minidx < 0)
635 return minidx;
636
637 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
638 if (bfregi->count[i] < bfregi->count[minidx])
639 minidx = i;
640 if (!bfregi->count[minidx])
641 break;
642 }
643
644 bfregi->count[minidx]++;
645 return minidx;
646 }
647
648 static int alloc_bfreg(struct mlx5_ib_dev *dev,
649 struct mlx5_bfreg_info *bfregi)
650 {
651 int bfregn = -ENOMEM;
652
653 mutex_lock(&bfregi->lock);
654 if (bfregi->ver >= 2) {
655 bfregn = alloc_high_class_bfreg(dev, bfregi);
656 if (bfregn < 0)
657 bfregn = alloc_med_class_bfreg(dev, bfregi);
658 }
659
660 if (bfregn < 0) {
661 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
662 bfregn = 0;
663 bfregi->count[bfregn]++;
664 }
665 mutex_unlock(&bfregi->lock);
666
667 return bfregn;
668 }
669
670 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
671 {
672 mutex_lock(&bfregi->lock);
673 bfregi->count[bfregn]--;
674 mutex_unlock(&bfregi->lock);
675 }
676
677 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
678 {
679 switch (state) {
680 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
681 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
682 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
683 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
684 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
685 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
686 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
687 default: return -1;
688 }
689 }
690
691 static int to_mlx5_st(enum ib_qp_type type)
692 {
693 switch (type) {
694 case IB_QPT_RC: return MLX5_QP_ST_RC;
695 case IB_QPT_UC: return MLX5_QP_ST_UC;
696 case IB_QPT_UD: return MLX5_QP_ST_UD;
697 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
698 case IB_QPT_XRC_INI:
699 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
700 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
701 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
702 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
703 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
704 case IB_QPT_RAW_PACKET:
705 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
706 case IB_QPT_MAX:
707 default: return -EINVAL;
708 }
709 }
710
711 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
712 struct mlx5_ib_cq *recv_cq);
713 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
714 struct mlx5_ib_cq *recv_cq);
715
716 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
717 struct mlx5_bfreg_info *bfregi, u32 bfregn,
718 bool dyn_bfreg)
719 {
720 unsigned int bfregs_per_sys_page;
721 u32 index_of_sys_page;
722 u32 offset;
723
724 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
725 MLX5_NON_FP_BFREGS_PER_UAR;
726 index_of_sys_page = bfregn / bfregs_per_sys_page;
727
728 if (dyn_bfreg) {
729 index_of_sys_page += bfregi->num_static_sys_pages;
730
731 if (index_of_sys_page >= bfregi->num_sys_pages)
732 return -EINVAL;
733
734 if (bfregn > bfregi->num_dyn_bfregs ||
735 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
736 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
737 return -EINVAL;
738 }
739 }
740
741 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
742 return bfregi->sys_pages[index_of_sys_page] + offset;
743 }
744
745 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
746 unsigned long addr, size_t size,
747 struct ib_umem **umem, int *npages, int *page_shift,
748 int *ncont, u32 *offset)
749 {
750 int err;
751
752 *umem = ib_umem_get(udata, addr, size, 0, 0);
753 if (IS_ERR(*umem)) {
754 mlx5_ib_dbg(dev, "umem_get failed\n");
755 return PTR_ERR(*umem);
756 }
757
758 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
759
760 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
761 if (err) {
762 mlx5_ib_warn(dev, "bad offset\n");
763 goto err_umem;
764 }
765
766 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
767 addr, size, *npages, *page_shift, *ncont, *offset);
768
769 return 0;
770
771 err_umem:
772 ib_umem_release(*umem);
773 *umem = NULL;
774
775 return err;
776 }
777
778 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
779 struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
780 {
781 struct mlx5_ib_ucontext *context =
782 rdma_udata_to_drv_context(
783 udata,
784 struct mlx5_ib_ucontext,
785 ibucontext);
786
787 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
788 atomic_dec(&dev->delay_drop.rqs_cnt);
789
790 mlx5_ib_db_unmap_user(context, &rwq->db);
791 ib_umem_release(rwq->umem);
792 }
793
794 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
795 struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
796 struct mlx5_ib_create_wq *ucmd)
797 {
798 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
799 udata, struct mlx5_ib_ucontext, ibucontext);
800 int page_shift = 0;
801 int npages;
802 u32 offset = 0;
803 int ncont = 0;
804 int err;
805
806 if (!ucmd->buf_addr)
807 return -EINVAL;
808
809 rwq->umem = ib_umem_get(udata, ucmd->buf_addr, rwq->buf_size, 0, 0);
810 if (IS_ERR(rwq->umem)) {
811 mlx5_ib_dbg(dev, "umem_get failed\n");
812 err = PTR_ERR(rwq->umem);
813 return err;
814 }
815
816 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
817 &ncont, NULL);
818 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
819 &rwq->rq_page_offset);
820 if (err) {
821 mlx5_ib_warn(dev, "bad offset\n");
822 goto err_umem;
823 }
824
825 rwq->rq_num_pas = ncont;
826 rwq->page_shift = page_shift;
827 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
828 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
829
830 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
831 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
832 npages, page_shift, ncont, offset);
833
834 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
835 if (err) {
836 mlx5_ib_dbg(dev, "map failed\n");
837 goto err_umem;
838 }
839
840 rwq->create_type = MLX5_WQ_USER;
841 return 0;
842
843 err_umem:
844 ib_umem_release(rwq->umem);
845 return err;
846 }
847
848 static int adjust_bfregn(struct mlx5_ib_dev *dev,
849 struct mlx5_bfreg_info *bfregi, int bfregn)
850 {
851 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
852 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
853 }
854
855 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
856 struct mlx5_ib_qp *qp, struct ib_udata *udata,
857 struct ib_qp_init_attr *attr,
858 u32 **in,
859 struct mlx5_ib_create_qp_resp *resp, int *inlen,
860 struct mlx5_ib_qp_base *base)
861 {
862 struct mlx5_ib_ucontext *context;
863 struct mlx5_ib_create_qp ucmd;
864 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
865 int page_shift = 0;
866 int uar_index = 0;
867 int npages;
868 u32 offset = 0;
869 int bfregn;
870 int ncont = 0;
871 __be64 *pas;
872 void *qpc;
873 int err;
874 u16 uid;
875
876 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
877 if (err) {
878 mlx5_ib_dbg(dev, "copy failed\n");
879 return err;
880 }
881
882 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
883 ibucontext);
884 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
885 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
886 ucmd.bfreg_index, true);
887 if (uar_index < 0)
888 return uar_index;
889
890 bfregn = MLX5_IB_INVALID_BFREG;
891 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
892
893
894
895
896 bfregn = MLX5_CROSS_CHANNEL_BFREG;
897 }
898 else {
899 bfregn = alloc_bfreg(dev, &context->bfregi);
900 if (bfregn < 0)
901 return bfregn;
902 }
903
904 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
905 if (bfregn != MLX5_IB_INVALID_BFREG)
906 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
907 false);
908
909 qp->rq.offset = 0;
910 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
911 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
912
913 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
914 if (err)
915 goto err_bfreg;
916
917 if (ucmd.buf_addr && ubuffer->buf_size) {
918 ubuffer->buf_addr = ucmd.buf_addr;
919 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
920 ubuffer->buf_size, &ubuffer->umem,
921 &npages, &page_shift, &ncont, &offset);
922 if (err)
923 goto err_bfreg;
924 } else {
925 ubuffer->umem = NULL;
926 }
927
928 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
929 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
930 *in = kvzalloc(*inlen, GFP_KERNEL);
931 if (!*in) {
932 err = -ENOMEM;
933 goto err_umem;
934 }
935
936 uid = (attr->qp_type != IB_QPT_XRC_TGT &&
937 attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
938 MLX5_SET(create_qp_in, *in, uid, uid);
939 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
940 if (ubuffer->umem)
941 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
942
943 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
944
945 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
946 MLX5_SET(qpc, qpc, page_offset, offset);
947
948 MLX5_SET(qpc, qpc, uar_page, uar_index);
949 if (bfregn != MLX5_IB_INVALID_BFREG)
950 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
951 else
952 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
953 qp->bfregn = bfregn;
954
955 err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &qp->db);
956 if (err) {
957 mlx5_ib_dbg(dev, "map failed\n");
958 goto err_free;
959 }
960
961 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
962 if (err) {
963 mlx5_ib_dbg(dev, "copy failed\n");
964 goto err_unmap;
965 }
966 qp->create_type = MLX5_QP_USER;
967
968 return 0;
969
970 err_unmap:
971 mlx5_ib_db_unmap_user(context, &qp->db);
972
973 err_free:
974 kvfree(*in);
975
976 err_umem:
977 ib_umem_release(ubuffer->umem);
978
979 err_bfreg:
980 if (bfregn != MLX5_IB_INVALID_BFREG)
981 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
982 return err;
983 }
984
985 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
986 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base,
987 struct ib_udata *udata)
988 {
989 struct mlx5_ib_ucontext *context =
990 rdma_udata_to_drv_context(
991 udata,
992 struct mlx5_ib_ucontext,
993 ibucontext);
994
995 mlx5_ib_db_unmap_user(context, &qp->db);
996 ib_umem_release(base->ubuffer.umem);
997
998
999
1000
1001
1002 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1003 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
1004 }
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
1020 {
1021 void *fragment_end;
1022
1023 fragment_end = mlx5_frag_buf_get_wqe
1024 (&sq->fbc,
1025 mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx));
1026
1027 return fragment_end + MLX5_SEND_WQE_BB;
1028 }
1029
1030 static int create_kernel_qp(struct mlx5_ib_dev *dev,
1031 struct ib_qp_init_attr *init_attr,
1032 struct mlx5_ib_qp *qp,
1033 u32 **in, int *inlen,
1034 struct mlx5_ib_qp_base *base)
1035 {
1036 int uar_index;
1037 void *qpc;
1038 int err;
1039
1040 if (init_attr->create_flags & ~(IB_QP_CREATE_INTEGRITY_EN |
1041 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
1042 IB_QP_CREATE_IPOIB_UD_LSO |
1043 IB_QP_CREATE_NETIF_QP |
1044 mlx5_ib_create_qp_sqpn_qp1()))
1045 return -EINVAL;
1046
1047 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
1048 qp->bf.bfreg = &dev->fp_bfreg;
1049 else
1050 qp->bf.bfreg = &dev->bfreg;
1051
1052
1053
1054
1055 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
1056 uar_index = qp->bf.bfreg->index;
1057
1058 err = calc_sq_size(dev, init_attr, qp);
1059 if (err < 0) {
1060 mlx5_ib_dbg(dev, "err %d\n", err);
1061 return err;
1062 }
1063
1064 qp->rq.offset = 0;
1065 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
1066 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
1067
1068 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1069 &qp->buf, dev->mdev->priv.numa_node);
1070 if (err) {
1071 mlx5_ib_dbg(dev, "err %d\n", err);
1072 return err;
1073 }
1074
1075 if (qp->rq.wqe_cnt)
1076 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1077 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1078
1079 if (qp->sq.wqe_cnt) {
1080 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) /
1081 MLX5_SEND_WQE_BB;
1082 mlx5_init_fbc_offset(qp->buf.frags +
1083 (qp->sq.offset / PAGE_SIZE),
1084 ilog2(MLX5_SEND_WQE_BB),
1085 ilog2(qp->sq.wqe_cnt),
1086 sq_strides_offset, &qp->sq.fbc);
1087
1088 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1089 }
1090
1091 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1092 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1093 *in = kvzalloc(*inlen, GFP_KERNEL);
1094 if (!*in) {
1095 err = -ENOMEM;
1096 goto err_buf;
1097 }
1098
1099 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1100 MLX5_SET(qpc, qpc, uar_page, uar_index);
1101 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1102
1103
1104 MLX5_SET(qpc, qpc, fre, 1);
1105 MLX5_SET(qpc, qpc, rlky, 1);
1106
1107 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
1108 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1109 qp->flags |= MLX5_IB_QP_SQPN_QP1;
1110 }
1111
1112 mlx5_fill_page_frag_array(&qp->buf,
1113 (__be64 *)MLX5_ADDR_OF(create_qp_in,
1114 *in, pas));
1115
1116 err = mlx5_db_alloc(dev->mdev, &qp->db);
1117 if (err) {
1118 mlx5_ib_dbg(dev, "err %d\n", err);
1119 goto err_free;
1120 }
1121
1122 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1123 sizeof(*qp->sq.wrid), GFP_KERNEL);
1124 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1125 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1126 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1127 sizeof(*qp->rq.wrid), GFP_KERNEL);
1128 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1129 sizeof(*qp->sq.w_list), GFP_KERNEL);
1130 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1131 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1132
1133 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1134 !qp->sq.w_list || !qp->sq.wqe_head) {
1135 err = -ENOMEM;
1136 goto err_wrid;
1137 }
1138 qp->create_type = MLX5_QP_KERNEL;
1139
1140 return 0;
1141
1142 err_wrid:
1143 kvfree(qp->sq.wqe_head);
1144 kvfree(qp->sq.w_list);
1145 kvfree(qp->sq.wrid);
1146 kvfree(qp->sq.wr_data);
1147 kvfree(qp->rq.wrid);
1148 mlx5_db_free(dev->mdev, &qp->db);
1149
1150 err_free:
1151 kvfree(*in);
1152
1153 err_buf:
1154 mlx5_frag_buf_free(dev->mdev, &qp->buf);
1155 return err;
1156 }
1157
1158 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1159 {
1160 kvfree(qp->sq.wqe_head);
1161 kvfree(qp->sq.w_list);
1162 kvfree(qp->sq.wrid);
1163 kvfree(qp->sq.wr_data);
1164 kvfree(qp->rq.wrid);
1165 mlx5_db_free(dev->mdev, &qp->db);
1166 mlx5_frag_buf_free(dev->mdev, &qp->buf);
1167 }
1168
1169 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1170 {
1171 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1172 (attr->qp_type == MLX5_IB_QPT_DCI) ||
1173 (attr->qp_type == IB_QPT_XRC_INI))
1174 return MLX5_SRQ_RQ;
1175 else if (!qp->has_rq)
1176 return MLX5_ZERO_LEN_RQ;
1177 else
1178 return MLX5_NON_ZERO_RQ;
1179 }
1180
1181 static int is_connected(enum ib_qp_type qp_type)
1182 {
1183 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC ||
1184 qp_type == MLX5_IB_QPT_DCI)
1185 return 1;
1186
1187 return 0;
1188 }
1189
1190 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1191 struct mlx5_ib_qp *qp,
1192 struct mlx5_ib_sq *sq, u32 tdn,
1193 struct ib_pd *pd)
1194 {
1195 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1196 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1197
1198 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1199 MLX5_SET(tisc, tisc, transport_domain, tdn);
1200 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1201 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1202
1203 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1204 }
1205
1206 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1207 struct mlx5_ib_sq *sq, struct ib_pd *pd)
1208 {
1209 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1210 }
1211
1212 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq)
1213 {
1214 if (sq->flow_rule)
1215 mlx5_del_flow_rules(sq->flow_rule);
1216 sq->flow_rule = NULL;
1217 }
1218
1219 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1220 struct ib_udata *udata,
1221 struct mlx5_ib_sq *sq, void *qpin,
1222 struct ib_pd *pd)
1223 {
1224 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1225 __be64 *pas;
1226 void *in;
1227 void *sqc;
1228 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1229 void *wq;
1230 int inlen;
1231 int err;
1232 int page_shift = 0;
1233 int npages;
1234 int ncont = 0;
1235 u32 offset = 0;
1236
1237 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1238 &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1239 &offset);
1240 if (err)
1241 return err;
1242
1243 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1244 in = kvzalloc(inlen, GFP_KERNEL);
1245 if (!in) {
1246 err = -ENOMEM;
1247 goto err_umem;
1248 }
1249
1250 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1251 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1252 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1253 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1254 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1255 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1256 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1257 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1258 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1259 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1260 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1261 MLX5_CAP_ETH(dev->mdev, swp))
1262 MLX5_SET(sqc, sqc, allow_swp, 1);
1263
1264 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1265 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1266 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1267 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1268 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1269 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1270 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1271 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1272 MLX5_SET(wq, wq, page_offset, offset);
1273
1274 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1275 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1276
1277 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1278
1279 kvfree(in);
1280
1281 if (err)
1282 goto err_umem;
1283
1284 return 0;
1285
1286 err_umem:
1287 ib_umem_release(sq->ubuffer.umem);
1288 sq->ubuffer.umem = NULL;
1289
1290 return err;
1291 }
1292
1293 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1294 struct mlx5_ib_sq *sq)
1295 {
1296 destroy_flow_rule_vport_sq(sq);
1297 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1298 ib_umem_release(sq->ubuffer.umem);
1299 }
1300
1301 static size_t get_rq_pas_size(void *qpc)
1302 {
1303 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1304 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1305 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1306 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1307 u32 po_quanta = 1 << (log_page_size - 6);
1308 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1309 u32 page_size = 1 << log_page_size;
1310 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1311 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1312
1313 return rq_num_pas * sizeof(u64);
1314 }
1315
1316 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1317 struct mlx5_ib_rq *rq, void *qpin,
1318 size_t qpinlen, struct ib_pd *pd)
1319 {
1320 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1321 __be64 *pas;
1322 __be64 *qp_pas;
1323 void *in;
1324 void *rqc;
1325 void *wq;
1326 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1327 size_t rq_pas_size = get_rq_pas_size(qpc);
1328 size_t inlen;
1329 int err;
1330
1331 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1332 return -EINVAL;
1333
1334 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1335 in = kvzalloc(inlen, GFP_KERNEL);
1336 if (!in)
1337 return -ENOMEM;
1338
1339 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1340 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1341 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1342 MLX5_SET(rqc, rqc, vsd, 1);
1343 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1344 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1345 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1346 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1347 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1348
1349 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1350 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1351
1352 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1353 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1354 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1355 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1356 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1357 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1358 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1359 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1360 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1361 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1362
1363 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1364 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1365 memcpy(pas, qp_pas, rq_pas_size);
1366
1367 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1368
1369 kvfree(in);
1370
1371 return err;
1372 }
1373
1374 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1375 struct mlx5_ib_rq *rq)
1376 {
1377 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1378 }
1379
1380 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1381 {
1382 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1383 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1384 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1385 }
1386
1387 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1388 struct mlx5_ib_rq *rq,
1389 u32 qp_flags_en,
1390 struct ib_pd *pd)
1391 {
1392 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1393 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1394 mlx5_ib_disable_lb(dev, false, true);
1395 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1396 }
1397
1398 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1399 struct mlx5_ib_rq *rq, u32 tdn,
1400 u32 *qp_flags_en,
1401 struct ib_pd *pd,
1402 u32 *out, int outlen)
1403 {
1404 u8 lb_flag = 0;
1405 u32 *in;
1406 void *tirc;
1407 int inlen;
1408 int err;
1409
1410 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1411 in = kvzalloc(inlen, GFP_KERNEL);
1412 if (!in)
1413 return -ENOMEM;
1414
1415 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1416 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1417 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1418 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1419 MLX5_SET(tirc, tirc, transport_domain, tdn);
1420 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1421 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1422
1423 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1424 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1425
1426 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1427 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1428
1429 if (dev->is_rep) {
1430 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1431 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1432 }
1433
1434 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1435
1436 err = mlx5_core_create_tir_out(dev->mdev, in, inlen, out, outlen);
1437
1438 rq->tirn = MLX5_GET(create_tir_out, out, tirn);
1439 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1440 err = mlx5_ib_enable_lb(dev, false, true);
1441
1442 if (err)
1443 destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1444 }
1445 kvfree(in);
1446
1447 return err;
1448 }
1449
1450 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1451 u32 *in, size_t inlen,
1452 struct ib_pd *pd,
1453 struct ib_udata *udata,
1454 struct mlx5_ib_create_qp_resp *resp)
1455 {
1456 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1457 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1458 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1459 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1460 udata, struct mlx5_ib_ucontext, ibucontext);
1461 int err;
1462 u32 tdn = mucontext->tdn;
1463 u16 uid = to_mpd(pd)->uid;
1464 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {};
1465
1466 if (qp->sq.wqe_cnt) {
1467 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1468 if (err)
1469 return err;
1470
1471 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
1472 if (err)
1473 goto err_destroy_tis;
1474
1475 if (uid) {
1476 resp->tisn = sq->tisn;
1477 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1478 resp->sqn = sq->base.mqp.qpn;
1479 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1480 }
1481
1482 sq->base.container_mibqp = qp;
1483 sq->base.mqp.event = mlx5_ib_qp_event;
1484 }
1485
1486 if (qp->rq.wqe_cnt) {
1487 rq->base.container_mibqp = qp;
1488
1489 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1490 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1491 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1492 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1493 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1494 if (err)
1495 goto err_destroy_sq;
1496
1497 err = create_raw_packet_qp_tir(
1498 dev, rq, tdn, &qp->flags_en, pd, out,
1499 MLX5_ST_SZ_BYTES(create_tir_out));
1500 if (err)
1501 goto err_destroy_rq;
1502
1503 if (uid) {
1504 resp->rqn = rq->base.mqp.qpn;
1505 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1506 resp->tirn = rq->tirn;
1507 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1508 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1509 resp->tir_icm_addr = MLX5_GET(
1510 create_tir_out, out, icm_address_31_0);
1511 resp->tir_icm_addr |=
1512 (u64)MLX5_GET(create_tir_out, out,
1513 icm_address_39_32)
1514 << 32;
1515 resp->tir_icm_addr |=
1516 (u64)MLX5_GET(create_tir_out, out,
1517 icm_address_63_40)
1518 << 40;
1519 resp->comp_mask |=
1520 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1521 }
1522 }
1523 }
1524
1525 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1526 rq->base.mqp.qpn;
1527 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1528 if (err)
1529 goto err_destroy_tir;
1530
1531 return 0;
1532
1533 err_destroy_tir:
1534 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
1535 err_destroy_rq:
1536 destroy_raw_packet_qp_rq(dev, rq);
1537 err_destroy_sq:
1538 if (!qp->sq.wqe_cnt)
1539 return err;
1540 destroy_raw_packet_qp_sq(dev, sq);
1541 err_destroy_tis:
1542 destroy_raw_packet_qp_tis(dev, sq, pd);
1543
1544 return err;
1545 }
1546
1547 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1548 struct mlx5_ib_qp *qp)
1549 {
1550 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1551 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1552 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1553
1554 if (qp->rq.wqe_cnt) {
1555 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1556 destroy_raw_packet_qp_rq(dev, rq);
1557 }
1558
1559 if (qp->sq.wqe_cnt) {
1560 destroy_raw_packet_qp_sq(dev, sq);
1561 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1562 }
1563 }
1564
1565 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1566 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1567 {
1568 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1569 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1570
1571 sq->sq = &qp->sq;
1572 rq->rq = &qp->rq;
1573 sq->doorbell = &qp->db;
1574 rq->doorbell = &qp->db;
1575 }
1576
1577 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1578 {
1579 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1580 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1581 mlx5_ib_disable_lb(dev, false, true);
1582 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1583 to_mpd(qp->ibqp.pd)->uid);
1584 }
1585
1586 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1587 struct ib_pd *pd,
1588 struct ib_qp_init_attr *init_attr,
1589 struct ib_udata *udata)
1590 {
1591 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1592 udata, struct mlx5_ib_ucontext, ibucontext);
1593 struct mlx5_ib_create_qp_resp resp = {};
1594 int inlen;
1595 int outlen;
1596 int err;
1597 u32 *in;
1598 u32 *out;
1599 void *tirc;
1600 void *hfso;
1601 u32 selected_fields = 0;
1602 u32 outer_l4;
1603 size_t min_resp_len;
1604 u32 tdn = mucontext->tdn;
1605 struct mlx5_ib_create_qp_rss ucmd = {};
1606 size_t required_cmd_sz;
1607 u8 lb_flag = 0;
1608
1609 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1610 return -EOPNOTSUPP;
1611
1612 if (init_attr->create_flags || init_attr->send_cq)
1613 return -EINVAL;
1614
1615 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1616 if (udata->outlen < min_resp_len)
1617 return -EINVAL;
1618
1619 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1620 if (udata->inlen < required_cmd_sz) {
1621 mlx5_ib_dbg(dev, "invalid inlen\n");
1622 return -EINVAL;
1623 }
1624
1625 if (udata->inlen > sizeof(ucmd) &&
1626 !ib_is_udata_cleared(udata, sizeof(ucmd),
1627 udata->inlen - sizeof(ucmd))) {
1628 mlx5_ib_dbg(dev, "inlen is not supported\n");
1629 return -EOPNOTSUPP;
1630 }
1631
1632 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1633 mlx5_ib_dbg(dev, "copy failed\n");
1634 return -EFAULT;
1635 }
1636
1637 if (ucmd.comp_mask) {
1638 mlx5_ib_dbg(dev, "invalid comp mask\n");
1639 return -EOPNOTSUPP;
1640 }
1641
1642 if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1643 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1644 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
1645 mlx5_ib_dbg(dev, "invalid flags\n");
1646 return -EOPNOTSUPP;
1647 }
1648
1649 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1650 !tunnel_offload_supported(dev->mdev)) {
1651 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1652 return -EOPNOTSUPP;
1653 }
1654
1655 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1656 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1657 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1658 return -EOPNOTSUPP;
1659 }
1660
1661 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->is_rep) {
1662 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1663 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1664 }
1665
1666 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1667 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1668 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1669 }
1670
1671 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1672 if (err) {
1673 mlx5_ib_dbg(dev, "copy failed\n");
1674 return -EINVAL;
1675 }
1676
1677 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1678 outlen = MLX5_ST_SZ_BYTES(create_tir_out);
1679 in = kvzalloc(inlen + outlen, GFP_KERNEL);
1680 if (!in)
1681 return -ENOMEM;
1682
1683 out = in + MLX5_ST_SZ_DW(create_tir_in);
1684 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1685 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1686 MLX5_SET(tirc, tirc, disp_type,
1687 MLX5_TIRC_DISP_TYPE_INDIRECT);
1688 MLX5_SET(tirc, tirc, indirect_table,
1689 init_attr->rwq_ind_tbl->ind_tbl_num);
1690 MLX5_SET(tirc, tirc, transport_domain, tdn);
1691
1692 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1693
1694 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1695 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1696
1697 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1698
1699 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1700 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1701 else
1702 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1703
1704 switch (ucmd.rx_hash_function) {
1705 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1706 {
1707 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1708 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1709
1710 if (len != ucmd.rx_key_len) {
1711 err = -EINVAL;
1712 goto err;
1713 }
1714
1715 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1716 memcpy(rss_key, ucmd.rx_hash_key, len);
1717 break;
1718 }
1719 default:
1720 err = -EOPNOTSUPP;
1721 goto err;
1722 }
1723
1724 if (!ucmd.rx_hash_fields_mask) {
1725
1726 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1727 goto create_tir;
1728 err = -EINVAL;
1729 goto err;
1730 }
1731
1732 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1733 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1734 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1735 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1736 err = -EINVAL;
1737 goto err;
1738 }
1739
1740
1741 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1742 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1743 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1744 MLX5_L3_PROT_TYPE_IPV4);
1745 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1746 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1747 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1748 MLX5_L3_PROT_TYPE_IPV6);
1749
1750 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1751 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1752 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1753 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1754 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1755
1756
1757 if (outer_l4 & (outer_l4 - 1)) {
1758 err = -EINVAL;
1759 goto err;
1760 }
1761
1762
1763 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1764 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1765 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1766 MLX5_L4_PROT_TYPE_TCP);
1767 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1768 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1769 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1770 MLX5_L4_PROT_TYPE_UDP);
1771
1772 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1773 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1774 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1775
1776 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1777 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1778 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1779
1780 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1781 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1782 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1783
1784 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1785 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1786 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1787
1788 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1789 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1790
1791 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1792
1793 create_tir:
1794 err = mlx5_core_create_tir_out(dev->mdev, in, inlen, out, outlen);
1795
1796 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn);
1797 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1798 err = mlx5_ib_enable_lb(dev, false, true);
1799
1800 if (err)
1801 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1802 to_mpd(pd)->uid);
1803 }
1804
1805 if (err)
1806 goto err;
1807
1808 if (mucontext->devx_uid) {
1809 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1810 resp.tirn = qp->rss_qp.tirn;
1811 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1812 resp.tir_icm_addr =
1813 MLX5_GET(create_tir_out, out, icm_address_31_0);
1814 resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out,
1815 icm_address_39_32)
1816 << 32;
1817 resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out,
1818 icm_address_63_40)
1819 << 40;
1820 resp.comp_mask |=
1821 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1822 }
1823 }
1824
1825 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1826 if (err)
1827 goto err_copy;
1828
1829 kvfree(in);
1830
1831 qp->trans_qp.base.mqp.qpn = 0;
1832 qp->flags |= MLX5_IB_QP_RSS;
1833 return 0;
1834
1835 err_copy:
1836 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
1837 err:
1838 kvfree(in);
1839 return err;
1840 }
1841
1842 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr,
1843 void *qpc)
1844 {
1845 int rcqe_sz;
1846
1847 if (init_attr->qp_type == MLX5_IB_QPT_DCI)
1848 return;
1849
1850 rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
1851
1852 if (init_attr->qp_type == MLX5_IB_QPT_DCT) {
1853 if (rcqe_sz == 128)
1854 MLX5_SET(dctc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1855
1856 return;
1857 }
1858
1859 MLX5_SET(qpc, qpc, cs_res,
1860 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE :
1861 MLX5_RES_SCAT_DATA32_CQE);
1862 }
1863
1864 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1865 struct ib_qp_init_attr *init_attr,
1866 struct mlx5_ib_create_qp *ucmd,
1867 void *qpc)
1868 {
1869 enum ib_qp_type qpt = init_attr->qp_type;
1870 int scqe_sz;
1871 bool allow_scat_cqe = 0;
1872
1873 if (qpt == IB_QPT_UC || qpt == IB_QPT_UD)
1874 return;
1875
1876 if (ucmd)
1877 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1878
1879 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1880 return;
1881
1882 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1883 if (scqe_sz == 128) {
1884 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1885 return;
1886 }
1887
1888 if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1889 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1890 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1891 }
1892
1893 static int atomic_size_to_mode(int size_mask)
1894 {
1895
1896
1897
1898 int supported_size_mask = size_mask & 0x1ff;
1899 int log_max_size;
1900
1901 if (!supported_size_mask)
1902 return -EOPNOTSUPP;
1903
1904 log_max_size = __fls(supported_size_mask);
1905
1906 if (log_max_size > 3)
1907 return log_max_size;
1908
1909 return MLX5_ATOMIC_MODE_8B;
1910 }
1911
1912 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1913 enum ib_qp_type qp_type)
1914 {
1915 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1916 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1917 int atomic_mode = -EOPNOTSUPP;
1918 int atomic_size_mask;
1919
1920 if (!atomic)
1921 return -EOPNOTSUPP;
1922
1923 if (qp_type == MLX5_IB_QPT_DCT)
1924 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1925 else
1926 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1927
1928 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1929 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1930 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1931
1932 if (atomic_mode <= 0 &&
1933 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1934 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1935 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1936
1937 return atomic_mode;
1938 }
1939
1940 static inline bool check_flags_mask(uint64_t input, uint64_t supported)
1941 {
1942 return (input & ~supported) == 0;
1943 }
1944
1945 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1946 struct ib_qp_init_attr *init_attr,
1947 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1948 {
1949 struct mlx5_ib_resources *devr = &dev->devr;
1950 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1951 struct mlx5_core_dev *mdev = dev->mdev;
1952 struct mlx5_ib_create_qp_resp resp = {};
1953 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
1954 udata, struct mlx5_ib_ucontext, ibucontext);
1955 struct mlx5_ib_cq *send_cq;
1956 struct mlx5_ib_cq *recv_cq;
1957 unsigned long flags;
1958 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1959 struct mlx5_ib_create_qp ucmd;
1960 struct mlx5_ib_qp_base *base;
1961 int mlx5_st;
1962 void *qpc;
1963 u32 *in;
1964 int err;
1965
1966 mutex_init(&qp->mutex);
1967 spin_lock_init(&qp->sq.lock);
1968 spin_lock_init(&qp->rq.lock);
1969
1970 mlx5_st = to_mlx5_st(init_attr->qp_type);
1971 if (mlx5_st < 0)
1972 return -EINVAL;
1973
1974 if (init_attr->rwq_ind_tbl) {
1975 if (!udata)
1976 return -ENOSYS;
1977
1978 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1979 return err;
1980 }
1981
1982 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1983 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1984 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1985 return -EINVAL;
1986 } else {
1987 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1988 }
1989 }
1990
1991 if (init_attr->create_flags &
1992 (IB_QP_CREATE_CROSS_CHANNEL |
1993 IB_QP_CREATE_MANAGED_SEND |
1994 IB_QP_CREATE_MANAGED_RECV)) {
1995 if (!MLX5_CAP_GEN(mdev, cd)) {
1996 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1997 return -EINVAL;
1998 }
1999 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
2000 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
2001 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
2002 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
2003 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
2004 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
2005 }
2006
2007 if (init_attr->qp_type == IB_QPT_UD &&
2008 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
2009 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
2010 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
2011 return -EOPNOTSUPP;
2012 }
2013
2014 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
2015 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2016 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
2017 return -EOPNOTSUPP;
2018 }
2019 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
2020 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
2021 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
2022 return -EOPNOTSUPP;
2023 }
2024 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
2025 }
2026
2027 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
2028 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
2029
2030 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
2031 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
2032 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
2033 (init_attr->qp_type != IB_QPT_RAW_PACKET))
2034 return -EOPNOTSUPP;
2035 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
2036 }
2037
2038 if (udata) {
2039 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
2040 mlx5_ib_dbg(dev, "copy failed\n");
2041 return -EFAULT;
2042 }
2043
2044 if (!check_flags_mask(ucmd.flags,
2045 MLX5_QP_FLAG_ALLOW_SCATTER_CQE |
2046 MLX5_QP_FLAG_BFREG_INDEX |
2047 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE |
2048 MLX5_QP_FLAG_SCATTER_CQE |
2049 MLX5_QP_FLAG_SIGNATURE |
2050 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC |
2051 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
2052 MLX5_QP_FLAG_TUNNEL_OFFLOADS |
2053 MLX5_QP_FLAG_TYPE_DCI |
2054 MLX5_QP_FLAG_TYPE_DCT))
2055 return -EINVAL;
2056
2057 err = get_qp_user_index(ucontext, &ucmd, udata->inlen, &uidx);
2058 if (err)
2059 return err;
2060
2061 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
2062 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe))
2063 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
2064 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
2065 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
2066 !tunnel_offload_supported(mdev)) {
2067 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
2068 return -EOPNOTSUPP;
2069 }
2070 qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
2071 }
2072
2073 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
2074 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2075 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
2076 return -EOPNOTSUPP;
2077 }
2078 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
2079 }
2080
2081 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
2082 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2083 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
2084 return -EOPNOTSUPP;
2085 }
2086 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
2087 }
2088
2089 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) {
2090 if (init_attr->qp_type != IB_QPT_RC ||
2091 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) {
2092 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n");
2093 return -EOPNOTSUPP;
2094 }
2095 qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT;
2096 }
2097
2098 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
2099 if (init_attr->qp_type != IB_QPT_UD ||
2100 (MLX5_CAP_GEN(dev->mdev, port_type) !=
2101 MLX5_CAP_PORT_TYPE_IB) ||
2102 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
2103 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
2104 return -EOPNOTSUPP;
2105 }
2106
2107 qp->flags |= MLX5_IB_QP_UNDERLAY;
2108 qp->underlay_qpn = init_attr->source_qpn;
2109 }
2110 } else {
2111 qp->wq_sig = !!wq_signature;
2112 }
2113
2114 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2115 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2116 &qp->raw_packet_qp.rq.base :
2117 &qp->trans_qp.base;
2118
2119 qp->has_rq = qp_has_rq(init_attr);
2120 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
2121 qp, udata ? &ucmd : NULL);
2122 if (err) {
2123 mlx5_ib_dbg(dev, "err %d\n", err);
2124 return err;
2125 }
2126
2127 if (pd) {
2128 if (udata) {
2129 __u32 max_wqes =
2130 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
2131 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
2132 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
2133 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
2134 mlx5_ib_dbg(dev, "invalid rq params\n");
2135 return -EINVAL;
2136 }
2137 if (ucmd.sq_wqe_count > max_wqes) {
2138 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
2139 ucmd.sq_wqe_count, max_wqes);
2140 return -EINVAL;
2141 }
2142 if (init_attr->create_flags &
2143 mlx5_ib_create_qp_sqpn_qp1()) {
2144 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
2145 return -EINVAL;
2146 }
2147 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
2148 &resp, &inlen, base);
2149 if (err)
2150 mlx5_ib_dbg(dev, "err %d\n", err);
2151 } else {
2152 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
2153 base);
2154 if (err)
2155 mlx5_ib_dbg(dev, "err %d\n", err);
2156 }
2157
2158 if (err)
2159 return err;
2160 } else {
2161 in = kvzalloc(inlen, GFP_KERNEL);
2162 if (!in)
2163 return -ENOMEM;
2164
2165 qp->create_type = MLX5_QP_EMPTY;
2166 }
2167
2168 if (is_sqp(init_attr->qp_type))
2169 qp->port = init_attr->port_num;
2170
2171 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2172
2173 MLX5_SET(qpc, qpc, st, mlx5_st);
2174 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2175
2176 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
2177 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2178 else
2179 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2180
2181
2182 if (qp->wq_sig)
2183 MLX5_SET(qpc, qpc, wq_signature, 1);
2184
2185 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2186 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2187
2188 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
2189 MLX5_SET(qpc, qpc, cd_master, 1);
2190 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
2191 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2192 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
2193 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2194 if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT)
2195 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
2196 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
2197 configure_responder_scat_cqe(init_attr, qpc);
2198 configure_requester_scat_cqe(dev, init_attr,
2199 udata ? &ucmd : NULL,
2200 qpc);
2201 }
2202
2203 if (qp->rq.wqe_cnt) {
2204 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2205 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2206 }
2207
2208 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2209
2210 if (qp->sq.wqe_cnt) {
2211 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2212 } else {
2213 MLX5_SET(qpc, qpc, no_sq, 1);
2214 if (init_attr->srq &&
2215 init_attr->srq->srq_type == IB_SRQT_TM)
2216 MLX5_SET(qpc, qpc, offload_type,
2217 MLX5_QPC_OFFLOAD_TYPE_RNDV);
2218 }
2219
2220
2221 switch (init_attr->qp_type) {
2222 case IB_QPT_XRC_TGT:
2223 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2224 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
2225 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2226 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
2227 break;
2228 case IB_QPT_XRC_INI:
2229 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2230 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2231 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2232 break;
2233 default:
2234 if (init_attr->srq) {
2235 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2236 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2237 } else {
2238 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2239 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2240 }
2241 }
2242
2243 if (init_attr->send_cq)
2244 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2245
2246 if (init_attr->recv_cq)
2247 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2248
2249 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2250
2251
2252 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2253 MLX5_SET(qpc, qpc, user_index, uidx);
2254
2255
2256 if (init_attr->qp_type == IB_QPT_UD &&
2257 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
2258 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2259 qp->flags |= MLX5_IB_QP_LSO;
2260 }
2261
2262 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
2263 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
2264 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
2265 err = -EOPNOTSUPP;
2266 goto err;
2267 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2268 MLX5_SET(qpc, qpc, end_padding_mode,
2269 MLX5_WQ_END_PAD_MODE_ALIGN);
2270 } else {
2271 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
2272 }
2273 }
2274
2275 if (inlen < 0) {
2276 err = -EINVAL;
2277 goto err;
2278 }
2279
2280 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2281 qp->flags & MLX5_IB_QP_UNDERLAY) {
2282 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
2283 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2284 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2285 &resp);
2286 } else {
2287 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
2288 }
2289
2290 if (err) {
2291 mlx5_ib_dbg(dev, "create qp failed\n");
2292 goto err_create;
2293 }
2294
2295 kvfree(in);
2296
2297 base->container_mibqp = qp;
2298 base->mqp.event = mlx5_ib_qp_event;
2299
2300 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2301 &send_cq, &recv_cq);
2302 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2303 mlx5_ib_lock_cqs(send_cq, recv_cq);
2304
2305
2306
2307 list_add_tail(&qp->qps_list, &dev->qp_list);
2308
2309
2310 if (send_cq)
2311 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2312 if (recv_cq)
2313 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2314 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2315 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2316
2317 return 0;
2318
2319 err_create:
2320 if (qp->create_type == MLX5_QP_USER)
2321 destroy_qp_user(dev, pd, qp, base, udata);
2322 else if (qp->create_type == MLX5_QP_KERNEL)
2323 destroy_qp_kernel(dev, qp);
2324
2325 err:
2326 kvfree(in);
2327 return err;
2328 }
2329
2330 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2331 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2332 {
2333 if (send_cq) {
2334 if (recv_cq) {
2335 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2336 spin_lock(&send_cq->lock);
2337 spin_lock_nested(&recv_cq->lock,
2338 SINGLE_DEPTH_NESTING);
2339 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2340 spin_lock(&send_cq->lock);
2341 __acquire(&recv_cq->lock);
2342 } else {
2343 spin_lock(&recv_cq->lock);
2344 spin_lock_nested(&send_cq->lock,
2345 SINGLE_DEPTH_NESTING);
2346 }
2347 } else {
2348 spin_lock(&send_cq->lock);
2349 __acquire(&recv_cq->lock);
2350 }
2351 } else if (recv_cq) {
2352 spin_lock(&recv_cq->lock);
2353 __acquire(&send_cq->lock);
2354 } else {
2355 __acquire(&send_cq->lock);
2356 __acquire(&recv_cq->lock);
2357 }
2358 }
2359
2360 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2361 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2362 {
2363 if (send_cq) {
2364 if (recv_cq) {
2365 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2366 spin_unlock(&recv_cq->lock);
2367 spin_unlock(&send_cq->lock);
2368 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2369 __release(&recv_cq->lock);
2370 spin_unlock(&send_cq->lock);
2371 } else {
2372 spin_unlock(&send_cq->lock);
2373 spin_unlock(&recv_cq->lock);
2374 }
2375 } else {
2376 __release(&recv_cq->lock);
2377 spin_unlock(&send_cq->lock);
2378 }
2379 } else if (recv_cq) {
2380 __release(&send_cq->lock);
2381 spin_unlock(&recv_cq->lock);
2382 } else {
2383 __release(&recv_cq->lock);
2384 __release(&send_cq->lock);
2385 }
2386 }
2387
2388 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2389 {
2390 return to_mpd(qp->ibqp.pd);
2391 }
2392
2393 static void get_cqs(enum ib_qp_type qp_type,
2394 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2395 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2396 {
2397 switch (qp_type) {
2398 case IB_QPT_XRC_TGT:
2399 *send_cq = NULL;
2400 *recv_cq = NULL;
2401 break;
2402 case MLX5_IB_QPT_REG_UMR:
2403 case IB_QPT_XRC_INI:
2404 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2405 *recv_cq = NULL;
2406 break;
2407
2408 case IB_QPT_SMI:
2409 case MLX5_IB_QPT_HW_GSI:
2410 case IB_QPT_RC:
2411 case IB_QPT_UC:
2412 case IB_QPT_UD:
2413 case IB_QPT_RAW_IPV6:
2414 case IB_QPT_RAW_ETHERTYPE:
2415 case IB_QPT_RAW_PACKET:
2416 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2417 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2418 break;
2419
2420 case IB_QPT_MAX:
2421 default:
2422 *send_cq = NULL;
2423 *recv_cq = NULL;
2424 break;
2425 }
2426 }
2427
2428 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2429 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2430 u8 lag_tx_affinity);
2431
2432 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2433 struct ib_udata *udata)
2434 {
2435 struct mlx5_ib_cq *send_cq, *recv_cq;
2436 struct mlx5_ib_qp_base *base;
2437 unsigned long flags;
2438 int err;
2439
2440 if (qp->ibqp.rwq_ind_tbl) {
2441 destroy_rss_raw_qp_tir(dev, qp);
2442 return;
2443 }
2444
2445 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2446 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2447 &qp->raw_packet_qp.rq.base :
2448 &qp->trans_qp.base;
2449
2450 if (qp->state != IB_QPS_RESET) {
2451 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2452 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2453 err = mlx5_core_qp_modify(dev->mdev,
2454 MLX5_CMD_OP_2RST_QP, 0,
2455 NULL, &base->mqp);
2456 } else {
2457 struct mlx5_modify_raw_qp_param raw_qp_param = {
2458 .operation = MLX5_CMD_OP_2RST_QP
2459 };
2460
2461 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2462 }
2463 if (err)
2464 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2465 base->mqp.qpn);
2466 }
2467
2468 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2469 &send_cq, &recv_cq);
2470
2471 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2472 mlx5_ib_lock_cqs(send_cq, recv_cq);
2473
2474 list_del(&qp->qps_list);
2475 if (send_cq)
2476 list_del(&qp->cq_send_list);
2477
2478 if (recv_cq)
2479 list_del(&qp->cq_recv_list);
2480
2481 if (qp->create_type == MLX5_QP_KERNEL) {
2482 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2483 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2484 if (send_cq != recv_cq)
2485 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2486 NULL);
2487 }
2488 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2489 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2490
2491 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2492 qp->flags & MLX5_IB_QP_UNDERLAY) {
2493 destroy_raw_packet_qp(dev, qp);
2494 } else {
2495 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2496 if (err)
2497 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2498 base->mqp.qpn);
2499 }
2500
2501 if (qp->create_type == MLX5_QP_KERNEL)
2502 destroy_qp_kernel(dev, qp);
2503 else if (qp->create_type == MLX5_QP_USER)
2504 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata);
2505 }
2506
2507 static const char *ib_qp_type_str(enum ib_qp_type type)
2508 {
2509 switch (type) {
2510 case IB_QPT_SMI:
2511 return "IB_QPT_SMI";
2512 case IB_QPT_GSI:
2513 return "IB_QPT_GSI";
2514 case IB_QPT_RC:
2515 return "IB_QPT_RC";
2516 case IB_QPT_UC:
2517 return "IB_QPT_UC";
2518 case IB_QPT_UD:
2519 return "IB_QPT_UD";
2520 case IB_QPT_RAW_IPV6:
2521 return "IB_QPT_RAW_IPV6";
2522 case IB_QPT_RAW_ETHERTYPE:
2523 return "IB_QPT_RAW_ETHERTYPE";
2524 case IB_QPT_XRC_INI:
2525 return "IB_QPT_XRC_INI";
2526 case IB_QPT_XRC_TGT:
2527 return "IB_QPT_XRC_TGT";
2528 case IB_QPT_RAW_PACKET:
2529 return "IB_QPT_RAW_PACKET";
2530 case MLX5_IB_QPT_REG_UMR:
2531 return "MLX5_IB_QPT_REG_UMR";
2532 case IB_QPT_DRIVER:
2533 return "IB_QPT_DRIVER";
2534 case IB_QPT_MAX:
2535 default:
2536 return "Invalid QP type";
2537 }
2538 }
2539
2540 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2541 struct ib_qp_init_attr *attr,
2542 struct mlx5_ib_create_qp *ucmd,
2543 struct ib_udata *udata)
2544 {
2545 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2546 udata, struct mlx5_ib_ucontext, ibucontext);
2547 struct mlx5_ib_qp *qp;
2548 int err = 0;
2549 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2550 void *dctc;
2551
2552 if (!attr->srq || !attr->recv_cq)
2553 return ERR_PTR(-EINVAL);
2554
2555 err = get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &uidx);
2556 if (err)
2557 return ERR_PTR(err);
2558
2559 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2560 if (!qp)
2561 return ERR_PTR(-ENOMEM);
2562
2563 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2564 if (!qp->dct.in) {
2565 err = -ENOMEM;
2566 goto err_free;
2567 }
2568
2569 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2570 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2571 qp->qp_sub_type = MLX5_IB_QPT_DCT;
2572 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2573 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2574 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2575 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2576 MLX5_SET(dctc, dctc, user_index, uidx);
2577
2578 if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE)
2579 configure_responder_scat_cqe(attr, dctc);
2580
2581 qp->state = IB_QPS_RESET;
2582
2583 return &qp->ibqp;
2584 err_free:
2585 kfree(qp);
2586 return ERR_PTR(err);
2587 }
2588
2589 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2590 struct ib_qp_init_attr *init_attr,
2591 struct mlx5_ib_create_qp *ucmd,
2592 struct ib_udata *udata)
2593 {
2594 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2595 int err;
2596
2597 if (!udata)
2598 return -EINVAL;
2599
2600 if (udata->inlen < sizeof(*ucmd)) {
2601 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2602 return -EINVAL;
2603 }
2604 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2605 if (err)
2606 return err;
2607
2608 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2609 init_attr->qp_type = MLX5_IB_QPT_DCI;
2610 } else {
2611 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2612 init_attr->qp_type = MLX5_IB_QPT_DCT;
2613 } else {
2614 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2615 return -EINVAL;
2616 }
2617 }
2618
2619 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2620 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2621 return -EOPNOTSUPP;
2622 }
2623
2624 return 0;
2625 }
2626
2627 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2628 struct ib_qp_init_attr *verbs_init_attr,
2629 struct ib_udata *udata)
2630 {
2631 struct mlx5_ib_dev *dev;
2632 struct mlx5_ib_qp *qp;
2633 u16 xrcdn = 0;
2634 int err;
2635 struct ib_qp_init_attr mlx_init_attr;
2636 struct ib_qp_init_attr *init_attr = verbs_init_attr;
2637 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2638 udata, struct mlx5_ib_ucontext, ibucontext);
2639
2640 if (pd) {
2641 dev = to_mdev(pd->device);
2642
2643 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2644 if (!ucontext) {
2645 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2646 return ERR_PTR(-EINVAL);
2647 } else if (!ucontext->cqe_version) {
2648 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2649 return ERR_PTR(-EINVAL);
2650 }
2651 }
2652 } else {
2653
2654 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2655 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2656 pr_warn("%s: no PD for transport %s\n", __func__,
2657 ib_qp_type_str(init_attr->qp_type));
2658 return ERR_PTR(-EINVAL);
2659 }
2660 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2661 }
2662
2663 if (init_attr->qp_type == IB_QPT_DRIVER) {
2664 struct mlx5_ib_create_qp ucmd;
2665
2666 init_attr = &mlx_init_attr;
2667 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2668 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2669 if (err)
2670 return ERR_PTR(err);
2671
2672 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2673 if (init_attr->cap.max_recv_wr ||
2674 init_attr->cap.max_recv_sge) {
2675 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2676 return ERR_PTR(-EINVAL);
2677 }
2678 } else {
2679 return mlx5_ib_create_dct(pd, init_attr, &ucmd, udata);
2680 }
2681 }
2682
2683 switch (init_attr->qp_type) {
2684 case IB_QPT_XRC_TGT:
2685 case IB_QPT_XRC_INI:
2686 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2687 mlx5_ib_dbg(dev, "XRC not supported\n");
2688 return ERR_PTR(-ENOSYS);
2689 }
2690 init_attr->recv_cq = NULL;
2691 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2692 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2693 init_attr->send_cq = NULL;
2694 }
2695
2696
2697 case IB_QPT_RAW_PACKET:
2698 case IB_QPT_RC:
2699 case IB_QPT_UC:
2700 case IB_QPT_UD:
2701 case IB_QPT_SMI:
2702 case MLX5_IB_QPT_HW_GSI:
2703 case MLX5_IB_QPT_REG_UMR:
2704 case MLX5_IB_QPT_DCI:
2705 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2706 if (!qp)
2707 return ERR_PTR(-ENOMEM);
2708
2709 err = create_qp_common(dev, pd, init_attr, udata, qp);
2710 if (err) {
2711 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2712 kfree(qp);
2713 return ERR_PTR(err);
2714 }
2715
2716 if (is_qp0(init_attr->qp_type))
2717 qp->ibqp.qp_num = 0;
2718 else if (is_qp1(init_attr->qp_type))
2719 qp->ibqp.qp_num = 1;
2720 else
2721 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2722
2723 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2724 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2725 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2726 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2727
2728 qp->trans_qp.xrcdn = xrcdn;
2729
2730 break;
2731
2732 case IB_QPT_GSI:
2733 return mlx5_ib_gsi_create_qp(pd, init_attr);
2734
2735 case IB_QPT_RAW_IPV6:
2736 case IB_QPT_RAW_ETHERTYPE:
2737 case IB_QPT_MAX:
2738 default:
2739 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2740 init_attr->qp_type);
2741
2742 return ERR_PTR(-EINVAL);
2743 }
2744
2745 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2746 qp->qp_sub_type = init_attr->qp_type;
2747
2748 return &qp->ibqp;
2749 }
2750
2751 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2752 {
2753 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2754
2755 if (mqp->state == IB_QPS_RTR) {
2756 int err;
2757
2758 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2759 if (err) {
2760 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2761 return err;
2762 }
2763 }
2764
2765 kfree(mqp->dct.in);
2766 kfree(mqp);
2767 return 0;
2768 }
2769
2770 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
2771 {
2772 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2773 struct mlx5_ib_qp *mqp = to_mqp(qp);
2774
2775 if (unlikely(qp->qp_type == IB_QPT_GSI))
2776 return mlx5_ib_gsi_destroy_qp(qp);
2777
2778 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2779 return mlx5_ib_destroy_dct(mqp);
2780
2781 destroy_qp_common(dev, mqp, udata);
2782
2783 kfree(mqp);
2784
2785 return 0;
2786 }
2787
2788 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2789 const struct ib_qp_attr *attr,
2790 int attr_mask, __be32 *hw_access_flags_be)
2791 {
2792 u8 dest_rd_atomic;
2793 u32 access_flags, hw_access_flags = 0;
2794
2795 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2796
2797 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2798 dest_rd_atomic = attr->max_dest_rd_atomic;
2799 else
2800 dest_rd_atomic = qp->trans_qp.resp_depth;
2801
2802 if (attr_mask & IB_QP_ACCESS_FLAGS)
2803 access_flags = attr->qp_access_flags;
2804 else
2805 access_flags = qp->trans_qp.atomic_rd_en;
2806
2807 if (!dest_rd_atomic)
2808 access_flags &= IB_ACCESS_REMOTE_WRITE;
2809
2810 if (access_flags & IB_ACCESS_REMOTE_READ)
2811 hw_access_flags |= MLX5_QP_BIT_RRE;
2812 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
2813 int atomic_mode;
2814
2815 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2816 if (atomic_mode < 0)
2817 return -EOPNOTSUPP;
2818
2819 hw_access_flags |= MLX5_QP_BIT_RAE;
2820 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
2821 }
2822
2823 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2824 hw_access_flags |= MLX5_QP_BIT_RWE;
2825
2826 *hw_access_flags_be = cpu_to_be32(hw_access_flags);
2827
2828 return 0;
2829 }
2830
2831 enum {
2832 MLX5_PATH_FLAG_FL = 1 << 0,
2833 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2834 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2835 };
2836
2837 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2838 {
2839 if (rate == IB_RATE_PORT_CURRENT)
2840 return 0;
2841
2842 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
2843 return -EINVAL;
2844
2845 while (rate != IB_RATE_PORT_CURRENT &&
2846 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2847 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2848 --rate;
2849
2850 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2851 }
2852
2853 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2854 struct mlx5_ib_sq *sq, u8 sl,
2855 struct ib_pd *pd)
2856 {
2857 void *in;
2858 void *tisc;
2859 int inlen;
2860 int err;
2861
2862 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2863 in = kvzalloc(inlen, GFP_KERNEL);
2864 if (!in)
2865 return -ENOMEM;
2866
2867 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2868 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2869
2870 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2871 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2872
2873 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2874
2875 kvfree(in);
2876
2877 return err;
2878 }
2879
2880 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2881 struct mlx5_ib_sq *sq, u8 tx_affinity,
2882 struct ib_pd *pd)
2883 {
2884 void *in;
2885 void *tisc;
2886 int inlen;
2887 int err;
2888
2889 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2890 in = kvzalloc(inlen, GFP_KERNEL);
2891 if (!in)
2892 return -ENOMEM;
2893
2894 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2895 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2896
2897 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2898 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2899
2900 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2901
2902 kvfree(in);
2903
2904 return err;
2905 }
2906
2907 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2908 const struct rdma_ah_attr *ah,
2909 struct mlx5_qp_path *path, u8 port, int attr_mask,
2910 u32 path_flags, const struct ib_qp_attr *attr,
2911 bool alt)
2912 {
2913 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2914 int err;
2915 enum ib_gid_type gid_type;
2916 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2917 u8 sl = rdma_ah_get_sl(ah);
2918
2919 if (attr_mask & IB_QP_PKEY_INDEX)
2920 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2921 attr->pkey_index);
2922
2923 if (ah_flags & IB_AH_GRH) {
2924 if (grh->sgid_index >=
2925 dev->mdev->port_caps[port - 1].gid_table_len) {
2926 pr_err("sgid_index (%u) too large. max is %d\n",
2927 grh->sgid_index,
2928 dev->mdev->port_caps[port - 1].gid_table_len);
2929 return -EINVAL;
2930 }
2931 }
2932
2933 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2934 if (!(ah_flags & IB_AH_GRH))
2935 return -EINVAL;
2936
2937 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2938 if (qp->ibqp.qp_type == IB_QPT_RC ||
2939 qp->ibqp.qp_type == IB_QPT_UC ||
2940 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2941 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2942 path->udp_sport =
2943 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2944 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2945 gid_type = ah->grh.sgid_attr->gid_type;
2946 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2947 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2948 } else {
2949 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2950 path->fl_free_ar |=
2951 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2952 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2953 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2954 if (ah_flags & IB_AH_GRH)
2955 path->grh_mlid |= 1 << 7;
2956 path->dci_cfi_prio_sl = sl & 0xf;
2957 }
2958
2959 if (ah_flags & IB_AH_GRH) {
2960 path->mgid_index = grh->sgid_index;
2961 path->hop_limit = grh->hop_limit;
2962 path->tclass_flowlabel =
2963 cpu_to_be32((grh->traffic_class << 20) |
2964 (grh->flow_label));
2965 memcpy(path->rgid, grh->dgid.raw, 16);
2966 }
2967
2968 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2969 if (err < 0)
2970 return err;
2971 path->static_rate = err;
2972 path->port = port;
2973
2974 if (attr_mask & IB_QP_TIMEOUT)
2975 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2976
2977 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2978 return modify_raw_packet_eth_prio(dev->mdev,
2979 &qp->raw_packet_qp.sq,
2980 sl & 0xf, qp->ibqp.pd);
2981
2982 return 0;
2983 }
2984
2985 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2986 [MLX5_QP_STATE_INIT] = {
2987 [MLX5_QP_STATE_INIT] = {
2988 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2989 MLX5_QP_OPTPAR_RAE |
2990 MLX5_QP_OPTPAR_RWE |
2991 MLX5_QP_OPTPAR_PKEY_INDEX |
2992 MLX5_QP_OPTPAR_PRI_PORT,
2993 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2994 MLX5_QP_OPTPAR_PKEY_INDEX |
2995 MLX5_QP_OPTPAR_PRI_PORT,
2996 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2997 MLX5_QP_OPTPAR_Q_KEY |
2998 MLX5_QP_OPTPAR_PRI_PORT,
2999 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE |
3000 MLX5_QP_OPTPAR_RAE |
3001 MLX5_QP_OPTPAR_RWE |
3002 MLX5_QP_OPTPAR_PKEY_INDEX |
3003 MLX5_QP_OPTPAR_PRI_PORT,
3004 },
3005 [MLX5_QP_STATE_RTR] = {
3006 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3007 MLX5_QP_OPTPAR_RRE |
3008 MLX5_QP_OPTPAR_RAE |
3009 MLX5_QP_OPTPAR_RWE |
3010 MLX5_QP_OPTPAR_PKEY_INDEX,
3011 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3012 MLX5_QP_OPTPAR_RWE |
3013 MLX5_QP_OPTPAR_PKEY_INDEX,
3014 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
3015 MLX5_QP_OPTPAR_Q_KEY,
3016 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
3017 MLX5_QP_OPTPAR_Q_KEY,
3018 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3019 MLX5_QP_OPTPAR_RRE |
3020 MLX5_QP_OPTPAR_RAE |
3021 MLX5_QP_OPTPAR_RWE |
3022 MLX5_QP_OPTPAR_PKEY_INDEX,
3023 },
3024 },
3025 [MLX5_QP_STATE_RTR] = {
3026 [MLX5_QP_STATE_RTS] = {
3027 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3028 MLX5_QP_OPTPAR_RRE |
3029 MLX5_QP_OPTPAR_RAE |
3030 MLX5_QP_OPTPAR_RWE |
3031 MLX5_QP_OPTPAR_PM_STATE |
3032 MLX5_QP_OPTPAR_RNR_TIMEOUT,
3033 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3034 MLX5_QP_OPTPAR_RWE |
3035 MLX5_QP_OPTPAR_PM_STATE,
3036 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3037 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3038 MLX5_QP_OPTPAR_RRE |
3039 MLX5_QP_OPTPAR_RAE |
3040 MLX5_QP_OPTPAR_RWE |
3041 MLX5_QP_OPTPAR_PM_STATE |
3042 MLX5_QP_OPTPAR_RNR_TIMEOUT,
3043 },
3044 },
3045 [MLX5_QP_STATE_RTS] = {
3046 [MLX5_QP_STATE_RTS] = {
3047 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
3048 MLX5_QP_OPTPAR_RAE |
3049 MLX5_QP_OPTPAR_RWE |
3050 MLX5_QP_OPTPAR_RNR_TIMEOUT |
3051 MLX5_QP_OPTPAR_PM_STATE |
3052 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3053 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
3054 MLX5_QP_OPTPAR_PM_STATE |
3055 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3056 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
3057 MLX5_QP_OPTPAR_SRQN |
3058 MLX5_QP_OPTPAR_CQN_RCV,
3059 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE |
3060 MLX5_QP_OPTPAR_RAE |
3061 MLX5_QP_OPTPAR_RWE |
3062 MLX5_QP_OPTPAR_RNR_TIMEOUT |
3063 MLX5_QP_OPTPAR_PM_STATE |
3064 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3065 },
3066 },
3067 [MLX5_QP_STATE_SQER] = {
3068 [MLX5_QP_STATE_RTS] = {
3069 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3070 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
3071 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
3072 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
3073 MLX5_QP_OPTPAR_RWE |
3074 MLX5_QP_OPTPAR_RAE |
3075 MLX5_QP_OPTPAR_RRE,
3076 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
3077 MLX5_QP_OPTPAR_RWE |
3078 MLX5_QP_OPTPAR_RAE |
3079 MLX5_QP_OPTPAR_RRE,
3080 },
3081 },
3082 };
3083
3084 static int ib_nr_to_mlx5_nr(int ib_mask)
3085 {
3086 switch (ib_mask) {
3087 case IB_QP_STATE:
3088 return 0;
3089 case IB_QP_CUR_STATE:
3090 return 0;
3091 case IB_QP_EN_SQD_ASYNC_NOTIFY:
3092 return 0;
3093 case IB_QP_ACCESS_FLAGS:
3094 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3095 MLX5_QP_OPTPAR_RAE;
3096 case IB_QP_PKEY_INDEX:
3097 return MLX5_QP_OPTPAR_PKEY_INDEX;
3098 case IB_QP_PORT:
3099 return MLX5_QP_OPTPAR_PRI_PORT;
3100 case IB_QP_QKEY:
3101 return MLX5_QP_OPTPAR_Q_KEY;
3102 case IB_QP_AV:
3103 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3104 MLX5_QP_OPTPAR_PRI_PORT;
3105 case IB_QP_PATH_MTU:
3106 return 0;
3107 case IB_QP_TIMEOUT:
3108 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3109 case IB_QP_RETRY_CNT:
3110 return MLX5_QP_OPTPAR_RETRY_COUNT;
3111 case IB_QP_RNR_RETRY:
3112 return MLX5_QP_OPTPAR_RNR_RETRY;
3113 case IB_QP_RQ_PSN:
3114 return 0;
3115 case IB_QP_MAX_QP_RD_ATOMIC:
3116 return MLX5_QP_OPTPAR_SRA_MAX;
3117 case IB_QP_ALT_PATH:
3118 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3119 case IB_QP_MIN_RNR_TIMER:
3120 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3121 case IB_QP_SQ_PSN:
3122 return 0;
3123 case IB_QP_MAX_DEST_RD_ATOMIC:
3124 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3125 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3126 case IB_QP_PATH_MIG_STATE:
3127 return MLX5_QP_OPTPAR_PM_STATE;
3128 case IB_QP_CAP:
3129 return 0;
3130 case IB_QP_DEST_QPN:
3131 return 0;
3132 }
3133 return 0;
3134 }
3135
3136 static int ib_mask_to_mlx5_opt(int ib_mask)
3137 {
3138 int result = 0;
3139 int i;
3140
3141 for (i = 0; i < 8 * sizeof(int); i++) {
3142 if ((1 << i) & ib_mask)
3143 result |= ib_nr_to_mlx5_nr(1 << i);
3144 }
3145
3146 return result;
3147 }
3148
3149 static int modify_raw_packet_qp_rq(
3150 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3151 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3152 {
3153 void *in;
3154 void *rqc;
3155 int inlen;
3156 int err;
3157
3158 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
3159 in = kvzalloc(inlen, GFP_KERNEL);
3160 if (!in)
3161 return -ENOMEM;
3162
3163 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3164 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
3165
3166 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3167 MLX5_SET(rqc, rqc, state, new_state);
3168
3169 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3170 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3171 MLX5_SET64(modify_rq_in, in, modify_bitmask,
3172 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3173 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3174 } else
3175 dev_info_once(
3176 &dev->ib_dev.dev,
3177 "RAW PACKET QP counters are not supported on current FW\n");
3178 }
3179
3180 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
3181 if (err)
3182 goto out;
3183
3184 rq->state = new_state;
3185
3186 out:
3187 kvfree(in);
3188 return err;
3189 }
3190
3191 static int modify_raw_packet_qp_sq(
3192 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3193 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3194 {
3195 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3196 struct mlx5_rate_limit old_rl = ibqp->rl;
3197 struct mlx5_rate_limit new_rl = old_rl;
3198 bool new_rate_added = false;
3199 u16 rl_index = 0;
3200 void *in;
3201 void *sqc;
3202 int inlen;
3203 int err;
3204
3205 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3206 in = kvzalloc(inlen, GFP_KERNEL);
3207 if (!in)
3208 return -ENOMEM;
3209
3210 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3211 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3212
3213 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3214 MLX5_SET(sqc, sqc, state, new_state);
3215
3216 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3217 if (new_state != MLX5_SQC_STATE_RDY)
3218 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3219 __func__);
3220 else
3221 new_rl = raw_qp_param->rl;
3222 }
3223
3224 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3225 if (new_rl.rate) {
3226 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3227 if (err) {
3228 pr_err("Failed configuring rate limit(err %d): \
3229 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3230 err, new_rl.rate, new_rl.max_burst_sz,
3231 new_rl.typical_pkt_sz);
3232
3233 goto out;
3234 }
3235 new_rate_added = true;
3236 }
3237
3238 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3239
3240 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3241 }
3242
3243 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
3244 if (err) {
3245
3246 if (new_rate_added)
3247 mlx5_rl_remove_rate(dev, &new_rl);
3248 goto out;
3249 }
3250
3251
3252 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3253 (new_state != MLX5_SQC_STATE_RDY)) {
3254 mlx5_rl_remove_rate(dev, &old_rl);
3255 if (new_state != MLX5_SQC_STATE_RDY)
3256 memset(&new_rl, 0, sizeof(new_rl));
3257 }
3258
3259 ibqp->rl = new_rl;
3260 sq->state = new_state;
3261
3262 out:
3263 kvfree(in);
3264 return err;
3265 }
3266
3267 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3268 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3269 u8 tx_affinity)
3270 {
3271 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3272 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3273 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3274 int modify_rq = !!qp->rq.wqe_cnt;
3275 int modify_sq = !!qp->sq.wqe_cnt;
3276 int rq_state;
3277 int sq_state;
3278 int err;
3279
3280 switch (raw_qp_param->operation) {
3281 case MLX5_CMD_OP_RST2INIT_QP:
3282 rq_state = MLX5_RQC_STATE_RDY;
3283 sq_state = MLX5_SQC_STATE_RDY;
3284 break;
3285 case MLX5_CMD_OP_2ERR_QP:
3286 rq_state = MLX5_RQC_STATE_ERR;
3287 sq_state = MLX5_SQC_STATE_ERR;
3288 break;
3289 case MLX5_CMD_OP_2RST_QP:
3290 rq_state = MLX5_RQC_STATE_RST;
3291 sq_state = MLX5_SQC_STATE_RST;
3292 break;
3293 case MLX5_CMD_OP_RTR2RTS_QP:
3294 case MLX5_CMD_OP_RTS2RTS_QP:
3295 if (raw_qp_param->set_mask ==
3296 MLX5_RAW_QP_RATE_LIMIT) {
3297 modify_rq = 0;
3298 sq_state = sq->state;
3299 } else {
3300 return raw_qp_param->set_mask ? -EINVAL : 0;
3301 }
3302 break;
3303 case MLX5_CMD_OP_INIT2INIT_QP:
3304 case MLX5_CMD_OP_INIT2RTR_QP:
3305 if (raw_qp_param->set_mask)
3306 return -EINVAL;
3307 else
3308 return 0;
3309 default:
3310 WARN_ON(1);
3311 return -EINVAL;
3312 }
3313
3314 if (modify_rq) {
3315 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3316 qp->ibqp.pd);
3317 if (err)
3318 return err;
3319 }
3320
3321 if (modify_sq) {
3322 struct mlx5_flow_handle *flow_rule;
3323
3324 if (tx_affinity) {
3325 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3326 tx_affinity,
3327 qp->ibqp.pd);
3328 if (err)
3329 return err;
3330 }
3331
3332 flow_rule = create_flow_rule_vport_sq(dev, sq,
3333 raw_qp_param->port);
3334 if (IS_ERR(flow_rule))
3335 return PTR_ERR(flow_rule);
3336
3337 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3338 raw_qp_param, qp->ibqp.pd);
3339 if (err) {
3340 if (flow_rule)
3341 mlx5_del_flow_rules(flow_rule);
3342 return err;
3343 }
3344
3345 if (flow_rule) {
3346 destroy_flow_rule_vport_sq(sq);
3347 sq->flow_rule = flow_rule;
3348 }
3349
3350 return err;
3351 }
3352
3353 return 0;
3354 }
3355
3356 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3357 struct mlx5_ib_pd *pd,
3358 struct mlx5_ib_qp_base *qp_base,
3359 u8 port_num, struct ib_udata *udata)
3360 {
3361 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3362 udata, struct mlx5_ib_ucontext, ibucontext);
3363 unsigned int tx_port_affinity;
3364
3365 if (ucontext) {
3366 tx_port_affinity = (unsigned int)atomic_add_return(
3367 1, &ucontext->tx_port_affinity) %
3368 MLX5_MAX_PORTS +
3369 1;
3370 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3371 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3372 } else {
3373 tx_port_affinity =
3374 (unsigned int)atomic_add_return(
3375 1, &dev->port[port_num].roce.tx_port_affinity) %
3376 MLX5_MAX_PORTS +
3377 1;
3378 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3379 tx_port_affinity, qp_base->mqp.qpn);
3380 }
3381
3382 return tx_port_affinity;
3383 }
3384
3385 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
3386 struct rdma_counter *counter)
3387 {
3388 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3389 struct mlx5_ib_qp *mqp = to_mqp(qp);
3390 struct mlx5_qp_context context = {};
3391 struct mlx5_ib_qp_base *base;
3392 u32 set_id;
3393
3394 if (counter)
3395 set_id = counter->id;
3396 else
3397 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1);
3398
3399 base = &mqp->trans_qp.base;
3400 context.qp_counter_set_usr_page &= cpu_to_be32(0xffffff);
3401 context.qp_counter_set_usr_page |= cpu_to_be32(set_id << 24);
3402 return mlx5_core_qp_modify(dev->mdev,
3403 MLX5_CMD_OP_RTS2RTS_QP,
3404 MLX5_QP_OPTPAR_COUNTER_SET_ID,
3405 &context, &base->mqp);
3406 }
3407
3408 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3409 const struct ib_qp_attr *attr, int attr_mask,
3410 enum ib_qp_state cur_state,
3411 enum ib_qp_state new_state,
3412 const struct mlx5_ib_modify_qp *ucmd,
3413 struct ib_udata *udata)
3414 {
3415 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3416 [MLX5_QP_STATE_RST] = {
3417 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3418 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3419 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
3420 },
3421 [MLX5_QP_STATE_INIT] = {
3422 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3423 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3424 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
3425 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
3426 },
3427 [MLX5_QP_STATE_RTR] = {
3428 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3429 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3430 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
3431 },
3432 [MLX5_QP_STATE_RTS] = {
3433 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3434 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3435 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
3436 },
3437 [MLX5_QP_STATE_SQD] = {
3438 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3439 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3440 },
3441 [MLX5_QP_STATE_SQER] = {
3442 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3443 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3444 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
3445 },
3446 [MLX5_QP_STATE_ERR] = {
3447 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3448 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3449 }
3450 };
3451
3452 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3453 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3454 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3455 struct mlx5_ib_cq *send_cq, *recv_cq;
3456 struct mlx5_qp_context *context;
3457 struct mlx5_ib_pd *pd;
3458 enum mlx5_qp_state mlx5_cur, mlx5_new;
3459 enum mlx5_qp_optpar optpar;
3460 u32 set_id = 0;
3461 int mlx5_st;
3462 int err;
3463 u16 op;
3464 u8 tx_affinity = 0;
3465
3466 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3467 qp->qp_sub_type : ibqp->qp_type);
3468 if (mlx5_st < 0)
3469 return -EINVAL;
3470
3471 context = kzalloc(sizeof(*context), GFP_KERNEL);
3472 if (!context)
3473 return -ENOMEM;
3474
3475 pd = get_pd(qp);
3476 context->flags = cpu_to_be32(mlx5_st << 16);
3477
3478 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3479 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3480 } else {
3481 switch (attr->path_mig_state) {
3482 case IB_MIG_MIGRATED:
3483 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3484 break;
3485 case IB_MIG_REARM:
3486 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3487 break;
3488 case IB_MIG_ARMED:
3489 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3490 break;
3491 }
3492 }
3493
3494 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3495 if ((ibqp->qp_type == IB_QPT_RC) ||
3496 (ibqp->qp_type == IB_QPT_UD &&
3497 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3498 (ibqp->qp_type == IB_QPT_UC) ||
3499 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3500 (ibqp->qp_type == IB_QPT_XRC_INI) ||
3501 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3502 if (dev->lag_active) {
3503 u8 p = mlx5_core_native_port_num(dev->mdev) - 1;
3504 tx_affinity = get_tx_affinity(dev, pd, base, p,
3505 udata);
3506 context->flags |= cpu_to_be32(tx_affinity << 24);
3507 }
3508 }
3509 }
3510
3511 if (is_sqp(ibqp->qp_type)) {
3512 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3513 } else if ((ibqp->qp_type == IB_QPT_UD &&
3514 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3515 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3516 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3517 } else if (attr_mask & IB_QP_PATH_MTU) {
3518 if (attr->path_mtu < IB_MTU_256 ||
3519 attr->path_mtu > IB_MTU_4096) {
3520 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3521 err = -EINVAL;
3522 goto out;
3523 }
3524 context->mtu_msgmax = (attr->path_mtu << 5) |
3525 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3526 }
3527
3528 if (attr_mask & IB_QP_DEST_QPN)
3529 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3530
3531 if (attr_mask & IB_QP_PKEY_INDEX)
3532 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3533
3534
3535
3536 if (is_sqp(ibqp->qp_type))
3537 context->pri_path.port = qp->port;
3538
3539 if (attr_mask & IB_QP_PORT)
3540 context->pri_path.port = attr->port_num;
3541
3542 if (attr_mask & IB_QP_AV) {
3543 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3544 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3545 attr_mask, 0, attr, false);
3546 if (err)
3547 goto out;
3548 }
3549
3550 if (attr_mask & IB_QP_TIMEOUT)
3551 context->pri_path.ackto_lt |= attr->timeout << 3;
3552
3553 if (attr_mask & IB_QP_ALT_PATH) {
3554 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3555 &context->alt_path,
3556 attr->alt_port_num,
3557 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3558 0, attr, true);
3559 if (err)
3560 goto out;
3561 }
3562
3563 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3564 &send_cq, &recv_cq);
3565
3566 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3567 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3568 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3569 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3570
3571 if (attr_mask & IB_QP_RNR_RETRY)
3572 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3573
3574 if (attr_mask & IB_QP_RETRY_CNT)
3575 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3576
3577 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3578 if (attr->max_rd_atomic)
3579 context->params1 |=
3580 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3581 }
3582
3583 if (attr_mask & IB_QP_SQ_PSN)
3584 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3585
3586 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3587 if (attr->max_dest_rd_atomic)
3588 context->params2 |=
3589 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3590 }
3591
3592 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3593 __be32 access_flags;
3594
3595 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
3596 if (err)
3597 goto out;
3598
3599 context->params2 |= access_flags;
3600 }
3601
3602 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3603 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3604
3605 if (attr_mask & IB_QP_RQ_PSN)
3606 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3607
3608 if (attr_mask & IB_QP_QKEY)
3609 context->qkey = cpu_to_be32(attr->qkey);
3610
3611 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3612 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3613
3614 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3615 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3616 qp->port) - 1;
3617
3618
3619 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3620 port_num = 0;
3621
3622 if (ibqp->counter)
3623 set_id = ibqp->counter->id;
3624 else
3625 set_id = mlx5_ib_get_counters_id(dev, port_num);
3626 context->qp_counter_set_usr_page |=
3627 cpu_to_be32(set_id << 24);
3628 }
3629
3630 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3631 context->sq_crq_size |= cpu_to_be16(1 << 4);
3632
3633 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3634 context->deth_sqpn = cpu_to_be32(1);
3635
3636 mlx5_cur = to_mlx5_state(cur_state);
3637 mlx5_new = to_mlx5_state(new_state);
3638
3639 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3640 !optab[mlx5_cur][mlx5_new]) {
3641 err = -EINVAL;
3642 goto out;
3643 }
3644
3645 op = optab[mlx5_cur][mlx5_new];
3646 optpar = ib_mask_to_mlx5_opt(attr_mask);
3647 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3648
3649 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3650 qp->flags & MLX5_IB_QP_UNDERLAY) {
3651 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3652
3653 raw_qp_param.operation = op;
3654 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3655 raw_qp_param.rq_q_ctr_id = set_id;
3656 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3657 }
3658
3659 if (attr_mask & IB_QP_PORT)
3660 raw_qp_param.port = attr->port_num;
3661
3662 if (attr_mask & IB_QP_RATE_LIMIT) {
3663 raw_qp_param.rl.rate = attr->rate_limit;
3664
3665 if (ucmd->burst_info.max_burst_sz) {
3666 if (attr->rate_limit &&
3667 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3668 raw_qp_param.rl.max_burst_sz =
3669 ucmd->burst_info.max_burst_sz;
3670 } else {
3671 err = -EINVAL;
3672 goto out;
3673 }
3674 }
3675
3676 if (ucmd->burst_info.typical_pkt_sz) {
3677 if (attr->rate_limit &&
3678 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3679 raw_qp_param.rl.typical_pkt_sz =
3680 ucmd->burst_info.typical_pkt_sz;
3681 } else {
3682 err = -EINVAL;
3683 goto out;
3684 }
3685 }
3686
3687 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3688 }
3689
3690 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3691 } else {
3692 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3693 &base->mqp);
3694 }
3695
3696 if (err)
3697 goto out;
3698
3699 qp->state = new_state;
3700
3701 if (attr_mask & IB_QP_ACCESS_FLAGS)
3702 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3703 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3704 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3705 if (attr_mask & IB_QP_PORT)
3706 qp->port = attr->port_num;
3707 if (attr_mask & IB_QP_ALT_PATH)
3708 qp->trans_qp.alt_port = attr->alt_port_num;
3709
3710
3711
3712
3713
3714 if (new_state == IB_QPS_RESET &&
3715 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3716 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3717 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3718 if (send_cq != recv_cq)
3719 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3720
3721 qp->rq.head = 0;
3722 qp->rq.tail = 0;
3723 qp->sq.head = 0;
3724 qp->sq.tail = 0;
3725 qp->sq.cur_post = 0;
3726 if (qp->sq.wqe_cnt)
3727 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
3728 qp->sq.last_poll = 0;
3729 qp->db.db[MLX5_RCV_DBR] = 0;
3730 qp->db.db[MLX5_SND_DBR] = 0;
3731 }
3732
3733 if ((new_state == IB_QPS_RTS) && qp->counter_pending) {
3734 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter);
3735 if (!err)
3736 qp->counter_pending = 0;
3737 }
3738
3739 out:
3740 kfree(context);
3741 return err;
3742 }
3743
3744 static inline bool is_valid_mask(int mask, int req, int opt)
3745 {
3746 if ((mask & req) != req)
3747 return false;
3748
3749 if (mask & ~(req | opt))
3750 return false;
3751
3752 return true;
3753 }
3754
3755
3756
3757
3758 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3759 enum ib_qp_attr_mask attr_mask)
3760 {
3761 int req = IB_QP_STATE;
3762 int opt = 0;
3763
3764 if (new_state == IB_QPS_RESET) {
3765 return is_valid_mask(attr_mask, req, opt);
3766 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3767 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3768 return is_valid_mask(attr_mask, req, opt);
3769 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3770 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3771 return is_valid_mask(attr_mask, req, opt);
3772 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3773 req |= IB_QP_PATH_MTU;
3774 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
3775 return is_valid_mask(attr_mask, req, opt);
3776 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3777 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3778 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3779 opt = IB_QP_MIN_RNR_TIMER;
3780 return is_valid_mask(attr_mask, req, opt);
3781 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3782 opt = IB_QP_MIN_RNR_TIMER;
3783 return is_valid_mask(attr_mask, req, opt);
3784 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3785 return is_valid_mask(attr_mask, req, opt);
3786 }
3787 return false;
3788 }
3789
3790
3791
3792
3793
3794
3795
3796
3797 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3798 int attr_mask, struct ib_udata *udata)
3799 {
3800 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3801 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3802 enum ib_qp_state cur_state, new_state;
3803 int err = 0;
3804 int required = IB_QP_STATE;
3805 void *dctc;
3806
3807 if (!(attr_mask & IB_QP_STATE))
3808 return -EINVAL;
3809
3810 cur_state = qp->state;
3811 new_state = attr->qp_state;
3812
3813 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3814 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3815 u16 set_id;
3816
3817 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3818 if (!is_valid_mask(attr_mask, required, 0))
3819 return -EINVAL;
3820
3821 if (attr->port_num == 0 ||
3822 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3823 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3824 attr->port_num, dev->num_ports);
3825 return -EINVAL;
3826 }
3827 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3828 MLX5_SET(dctc, dctc, rre, 1);
3829 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3830 MLX5_SET(dctc, dctc, rwe, 1);
3831 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3832 int atomic_mode;
3833
3834 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
3835 if (atomic_mode < 0)
3836 return -EOPNOTSUPP;
3837
3838 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
3839 MLX5_SET(dctc, dctc, rae, 1);
3840 }
3841 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3842 MLX5_SET(dctc, dctc, port, attr->port_num);
3843
3844 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1);
3845 MLX5_SET(dctc, dctc, counter_set_id, set_id);
3846
3847 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3848 struct mlx5_ib_modify_qp_resp resp = {};
3849 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0};
3850 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3851 sizeof(resp.dctn);
3852
3853 if (udata->outlen < min_resp_len)
3854 return -EINVAL;
3855 resp.response_length = min_resp_len;
3856
3857 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3858 if (!is_valid_mask(attr_mask, required, 0))
3859 return -EINVAL;
3860 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3861 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3862 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3863 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3864 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3865 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3866
3867 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3868 MLX5_ST_SZ_BYTES(create_dct_in), out,
3869 sizeof(out));
3870 if (err)
3871 return err;
3872 resp.dctn = qp->dct.mdct.mqp.qpn;
3873 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3874 if (err) {
3875 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3876 return err;
3877 }
3878 } else {
3879 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3880 return -EINVAL;
3881 }
3882 if (err)
3883 qp->state = IB_QPS_ERR;
3884 else
3885 qp->state = new_state;
3886 return err;
3887 }
3888
3889 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3890 int attr_mask, struct ib_udata *udata)
3891 {
3892 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3893 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3894 struct mlx5_ib_modify_qp ucmd = {};
3895 enum ib_qp_type qp_type;
3896 enum ib_qp_state cur_state, new_state;
3897 size_t required_cmd_sz;
3898 int err = -EINVAL;
3899 int port;
3900
3901 if (ibqp->rwq_ind_tbl)
3902 return -ENOSYS;
3903
3904 if (udata && udata->inlen) {
3905 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3906 sizeof(ucmd.reserved);
3907 if (udata->inlen < required_cmd_sz)
3908 return -EINVAL;
3909
3910 if (udata->inlen > sizeof(ucmd) &&
3911 !ib_is_udata_cleared(udata, sizeof(ucmd),
3912 udata->inlen - sizeof(ucmd)))
3913 return -EOPNOTSUPP;
3914
3915 if (ib_copy_from_udata(&ucmd, udata,
3916 min(udata->inlen, sizeof(ucmd))))
3917 return -EFAULT;
3918
3919 if (ucmd.comp_mask ||
3920 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3921 memchr_inv(&ucmd.burst_info.reserved, 0,
3922 sizeof(ucmd.burst_info.reserved)))
3923 return -EOPNOTSUPP;
3924 }
3925
3926 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3927 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3928
3929 if (ibqp->qp_type == IB_QPT_DRIVER)
3930 qp_type = qp->qp_sub_type;
3931 else
3932 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3933 IB_QPT_GSI : ibqp->qp_type;
3934
3935 if (qp_type == MLX5_IB_QPT_DCT)
3936 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3937
3938 mutex_lock(&qp->mutex);
3939
3940 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3941 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3942
3943 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3944 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3945 }
3946
3947 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3948 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3949 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3950 attr_mask);
3951 goto out;
3952 }
3953 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3954 qp_type != MLX5_IB_QPT_DCI &&
3955 !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
3956 attr_mask)) {
3957 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3958 cur_state, new_state, ibqp->qp_type, attr_mask);
3959 goto out;
3960 } else if (qp_type == MLX5_IB_QPT_DCI &&
3961 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3962 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3963 cur_state, new_state, qp_type, attr_mask);
3964 goto out;
3965 }
3966
3967 if ((attr_mask & IB_QP_PORT) &&
3968 (attr->port_num == 0 ||
3969 attr->port_num > dev->num_ports)) {
3970 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3971 attr->port_num, dev->num_ports);
3972 goto out;
3973 }
3974
3975 if (attr_mask & IB_QP_PKEY_INDEX) {
3976 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3977 if (attr->pkey_index >=
3978 dev->mdev->port_caps[port - 1].pkey_table_len) {
3979 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3980 attr->pkey_index);
3981 goto out;
3982 }
3983 }
3984
3985 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3986 attr->max_rd_atomic >
3987 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3988 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3989 attr->max_rd_atomic);
3990 goto out;
3991 }
3992
3993 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3994 attr->max_dest_rd_atomic >
3995 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3996 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3997 attr->max_dest_rd_atomic);
3998 goto out;
3999 }
4000
4001 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
4002 err = 0;
4003 goto out;
4004 }
4005
4006 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
4007 new_state, &ucmd, udata);
4008
4009 out:
4010 mutex_unlock(&qp->mutex);
4011 return err;
4012 }
4013
4014 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
4015 u32 wqe_sz, void **cur_edge)
4016 {
4017 u32 idx;
4018
4019 idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
4020 *cur_edge = get_sq_edge(sq, idx);
4021
4022 *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
4023 }
4024
4025
4026
4027
4028
4029
4030
4031
4032 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
4033 u32 wqe_sz, void **cur_edge)
4034 {
4035 if (likely(*seg != *cur_edge))
4036 return;
4037
4038 _handle_post_send_edge(sq, seg, wqe_sz, cur_edge);
4039 }
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
4051 void **seg, u32 *wqe_sz, const void *src,
4052 size_t n)
4053 {
4054 while (likely(n)) {
4055 size_t leftlen = *cur_edge - *seg;
4056 size_t copysz = min_t(size_t, leftlen, n);
4057 size_t stride;
4058
4059 memcpy(*seg, src, copysz);
4060
4061 n -= copysz;
4062 src += copysz;
4063 stride = !n ? ALIGN(copysz, 16) : copysz;
4064 *seg += stride;
4065 *wqe_sz += stride >> 4;
4066 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
4067 }
4068 }
4069
4070 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
4071 {
4072 struct mlx5_ib_cq *cq;
4073 unsigned cur;
4074
4075 cur = wq->head - wq->tail;
4076 if (likely(cur + nreq < wq->max_post))
4077 return 0;
4078
4079 cq = to_mcq(ib_cq);
4080 spin_lock(&cq->lock);
4081 cur = wq->head - wq->tail;
4082 spin_unlock(&cq->lock);
4083
4084 return cur + nreq >= wq->max_post;
4085 }
4086
4087 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
4088 u64 remote_addr, u32 rkey)
4089 {
4090 rseg->raddr = cpu_to_be64(remote_addr);
4091 rseg->rkey = cpu_to_be32(rkey);
4092 rseg->reserved = 0;
4093 }
4094
4095 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
4096 void **seg, int *size, void **cur_edge)
4097 {
4098 struct mlx5_wqe_eth_seg *eseg = *seg;
4099
4100 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
4101
4102 if (wr->send_flags & IB_SEND_IP_CSUM)
4103 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
4104 MLX5_ETH_WQE_L4_CSUM;
4105
4106 if (wr->opcode == IB_WR_LSO) {
4107 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
4108 size_t left, copysz;
4109 void *pdata = ud_wr->header;
4110 size_t stride;
4111
4112 left = ud_wr->hlen;
4113 eseg->mss = cpu_to_be16(ud_wr->mss);
4114 eseg->inline_hdr.sz = cpu_to_be16(left);
4115
4116
4117
4118
4119
4120 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start,
4121 left);
4122 memcpy(eseg->inline_hdr.start, pdata, copysz);
4123 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) -
4124 sizeof(eseg->inline_hdr.start) + copysz, 16);
4125 *size += stride / 16;
4126 *seg += stride;
4127
4128 if (copysz < left) {
4129 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4130 left -= copysz;
4131 pdata += copysz;
4132 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata,
4133 left);
4134 }
4135
4136 return;
4137 }
4138
4139 *seg += sizeof(struct mlx5_wqe_eth_seg);
4140 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
4141 }
4142
4143 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
4144 const struct ib_send_wr *wr)
4145 {
4146 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
4147 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
4148 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
4149 }
4150
4151 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
4152 {
4153 dseg->byte_count = cpu_to_be32(sg->length);
4154 dseg->lkey = cpu_to_be32(sg->lkey);
4155 dseg->addr = cpu_to_be64(sg->addr);
4156 }
4157
4158 static u64 get_xlt_octo(u64 bytes)
4159 {
4160 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
4161 MLX5_IB_UMR_OCTOWORD;
4162 }
4163
4164 static __be64 frwr_mkey_mask(bool atomic)
4165 {
4166 u64 result;
4167
4168 result = MLX5_MKEY_MASK_LEN |
4169 MLX5_MKEY_MASK_PAGE_SIZE |
4170 MLX5_MKEY_MASK_START_ADDR |
4171 MLX5_MKEY_MASK_EN_RINVAL |
4172 MLX5_MKEY_MASK_KEY |
4173 MLX5_MKEY_MASK_LR |
4174 MLX5_MKEY_MASK_LW |
4175 MLX5_MKEY_MASK_RR |
4176 MLX5_MKEY_MASK_RW |
4177 MLX5_MKEY_MASK_SMALL_FENCE |
4178 MLX5_MKEY_MASK_FREE;
4179
4180 if (atomic)
4181 result |= MLX5_MKEY_MASK_A;
4182
4183 return cpu_to_be64(result);
4184 }
4185
4186 static __be64 sig_mkey_mask(void)
4187 {
4188 u64 result;
4189
4190 result = MLX5_MKEY_MASK_LEN |
4191 MLX5_MKEY_MASK_PAGE_SIZE |
4192 MLX5_MKEY_MASK_START_ADDR |
4193 MLX5_MKEY_MASK_EN_SIGERR |
4194 MLX5_MKEY_MASK_EN_RINVAL |
4195 MLX5_MKEY_MASK_KEY |
4196 MLX5_MKEY_MASK_LR |
4197 MLX5_MKEY_MASK_LW |
4198 MLX5_MKEY_MASK_RR |
4199 MLX5_MKEY_MASK_RW |
4200 MLX5_MKEY_MASK_SMALL_FENCE |
4201 MLX5_MKEY_MASK_FREE |
4202 MLX5_MKEY_MASK_BSF_EN;
4203
4204 return cpu_to_be64(result);
4205 }
4206
4207 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
4208 struct mlx5_ib_mr *mr, u8 flags, bool atomic)
4209 {
4210 int size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size;
4211
4212 memset(umr, 0, sizeof(*umr));
4213
4214 umr->flags = flags;
4215 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4216 umr->mkey_mask = frwr_mkey_mask(atomic);
4217 }
4218
4219 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
4220 {
4221 memset(umr, 0, sizeof(*umr));
4222 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
4223 umr->flags = MLX5_UMR_INLINE;
4224 }
4225
4226 static __be64 get_umr_enable_mr_mask(void)
4227 {
4228 u64 result;
4229
4230 result = MLX5_MKEY_MASK_KEY |
4231 MLX5_MKEY_MASK_FREE;
4232
4233 return cpu_to_be64(result);
4234 }
4235
4236 static __be64 get_umr_disable_mr_mask(void)
4237 {
4238 u64 result;
4239
4240 result = MLX5_MKEY_MASK_FREE;
4241
4242 return cpu_to_be64(result);
4243 }
4244
4245 static __be64 get_umr_update_translation_mask(void)
4246 {
4247 u64 result;
4248
4249 result = MLX5_MKEY_MASK_LEN |
4250 MLX5_MKEY_MASK_PAGE_SIZE |
4251 MLX5_MKEY_MASK_START_ADDR;
4252
4253 return cpu_to_be64(result);
4254 }
4255
4256 static __be64 get_umr_update_access_mask(int atomic)
4257 {
4258 u64 result;
4259
4260 result = MLX5_MKEY_MASK_LR |
4261 MLX5_MKEY_MASK_LW |
4262 MLX5_MKEY_MASK_RR |
4263 MLX5_MKEY_MASK_RW;
4264
4265 if (atomic)
4266 result |= MLX5_MKEY_MASK_A;
4267
4268 return cpu_to_be64(result);
4269 }
4270
4271 static __be64 get_umr_update_pd_mask(void)
4272 {
4273 u64 result;
4274
4275 result = MLX5_MKEY_MASK_PD;
4276
4277 return cpu_to_be64(result);
4278 }
4279
4280 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
4281 {
4282 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
4283 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
4284 (mask & MLX5_MKEY_MASK_A &&
4285 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
4286 return -EPERM;
4287 return 0;
4288 }
4289
4290 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
4291 struct mlx5_wqe_umr_ctrl_seg *umr,
4292 const struct ib_send_wr *wr, int atomic)
4293 {
4294 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4295
4296 memset(umr, 0, sizeof(*umr));
4297
4298 if (!umrwr->ignore_free_state) {
4299 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
4300
4301 umr->flags = MLX5_UMR_CHECK_FREE;
4302 else
4303
4304 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
4305 }
4306
4307 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
4308 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
4309 u64 offset = get_xlt_octo(umrwr->offset);
4310
4311 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
4312 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
4313 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
4314 }
4315 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
4316 umr->mkey_mask |= get_umr_update_translation_mask();
4317 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
4318 umr->mkey_mask |= get_umr_update_access_mask(atomic);
4319 umr->mkey_mask |= get_umr_update_pd_mask();
4320 }
4321 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
4322 umr->mkey_mask |= get_umr_enable_mr_mask();
4323 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4324 umr->mkey_mask |= get_umr_disable_mr_mask();
4325
4326 if (!wr->num_sge)
4327 umr->flags |= MLX5_UMR_INLINE;
4328
4329 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
4330 }
4331
4332 static u8 get_umr_flags(int acc)
4333 {
4334 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
4335 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
4336 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
4337 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
4338 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
4339 }
4340
4341 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
4342 struct mlx5_ib_mr *mr,
4343 u32 key, int access)
4344 {
4345 int ndescs = ALIGN(mr->ndescs + mr->meta_ndescs, 8) >> 1;
4346
4347 memset(seg, 0, sizeof(*seg));
4348
4349 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
4350 seg->log2_page_size = ilog2(mr->ibmr.page_size);
4351 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
4352
4353 ndescs *= 2;
4354
4355 seg->flags = get_umr_flags(access) | mr->access_mode;
4356 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
4357 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
4358 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
4359 seg->len = cpu_to_be64(mr->ibmr.length);
4360 seg->xlt_oct_size = cpu_to_be32(ndescs);
4361 }
4362
4363 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
4364 {
4365 memset(seg, 0, sizeof(*seg));
4366 seg->status = MLX5_MKEY_STATUS_FREE;
4367 }
4368
4369 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
4370 const struct ib_send_wr *wr)
4371 {
4372 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4373
4374 memset(seg, 0, sizeof(*seg));
4375 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4376 seg->status = MLX5_MKEY_STATUS_FREE;
4377
4378 seg->flags = convert_access(umrwr->access_flags);
4379 if (umrwr->pd)
4380 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
4381 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
4382 !umrwr->length)
4383 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
4384
4385 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
4386 seg->len = cpu_to_be64(umrwr->length);
4387 seg->log2_page_size = umrwr->page_shift;
4388 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
4389 mlx5_mkey_variant(umrwr->mkey));
4390 }
4391
4392 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4393 struct mlx5_ib_mr *mr,
4394 struct mlx5_ib_pd *pd)
4395 {
4396 int bcount = mr->desc_size * (mr->ndescs + mr->meta_ndescs);
4397
4398 dseg->addr = cpu_to_be64(mr->desc_map);
4399 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4400 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4401 }
4402
4403 static __be32 send_ieth(const struct ib_send_wr *wr)
4404 {
4405 switch (wr->opcode) {
4406 case IB_WR_SEND_WITH_IMM:
4407 case IB_WR_RDMA_WRITE_WITH_IMM:
4408 return wr->ex.imm_data;
4409
4410 case IB_WR_SEND_WITH_INV:
4411 return cpu_to_be32(wr->ex.invalidate_rkey);
4412
4413 default:
4414 return 0;
4415 }
4416 }
4417
4418 static u8 calc_sig(void *wqe, int size)
4419 {
4420 u8 *p = wqe;
4421 u8 res = 0;
4422 int i;
4423
4424 for (i = 0; i < size; i++)
4425 res ^= p[i];
4426
4427 return ~res;
4428 }
4429
4430 static u8 wq_sig(void *wqe)
4431 {
4432 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4433 }
4434
4435 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
4436 void **wqe, int *wqe_sz, void **cur_edge)
4437 {
4438 struct mlx5_wqe_inline_seg *seg;
4439 size_t offset;
4440 int inl = 0;
4441 int i;
4442
4443 seg = *wqe;
4444 *wqe += sizeof(*seg);
4445 offset = sizeof(*seg);
4446
4447 for (i = 0; i < wr->num_sge; i++) {
4448 size_t len = wr->sg_list[i].length;
4449 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4450
4451 inl += len;
4452
4453 if (unlikely(inl > qp->max_inline_data))
4454 return -ENOMEM;
4455
4456 while (likely(len)) {
4457 size_t leftlen;
4458 size_t copysz;
4459
4460 handle_post_send_edge(&qp->sq, wqe,
4461 *wqe_sz + (offset >> 4),
4462 cur_edge);
4463
4464 leftlen = *cur_edge - *wqe;
4465 copysz = min_t(size_t, leftlen, len);
4466
4467 memcpy(*wqe, addr, copysz);
4468 len -= copysz;
4469 addr += copysz;
4470 *wqe += copysz;
4471 offset += copysz;
4472 }
4473 }
4474
4475 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4476
4477 *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
4478
4479 return 0;
4480 }
4481
4482 static u16 prot_field_size(enum ib_signature_type type)
4483 {
4484 switch (type) {
4485 case IB_SIG_TYPE_T10_DIF:
4486 return MLX5_DIF_SIZE;
4487 default:
4488 return 0;
4489 }
4490 }
4491
4492 static u8 bs_selector(int block_size)
4493 {
4494 switch (block_size) {
4495 case 512: return 0x1;
4496 case 520: return 0x2;
4497 case 4096: return 0x3;
4498 case 4160: return 0x4;
4499 case 1073741824: return 0x5;
4500 default: return 0;
4501 }
4502 }
4503
4504 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4505 struct mlx5_bsf_inl *inl)
4506 {
4507
4508 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4509 MLX5_BSF_REFRESH_DIF);
4510 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4511 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
4512
4513 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4514 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4515 MLX5_DIF_CRC : MLX5_DIF_IPCS;
4516
4517 if (domain->sig.dif.ref_remap)
4518 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4519
4520 if (domain->sig.dif.app_escape) {
4521 if (domain->sig.dif.ref_escape)
4522 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4523 else
4524 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4525 }
4526
4527 inl->dif_app_bitmask_check =
4528 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4529 }
4530
4531 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4532 struct ib_sig_attrs *sig_attrs,
4533 struct mlx5_bsf *bsf, u32 data_size)
4534 {
4535 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4536 struct mlx5_bsf_basic *basic = &bsf->basic;
4537 struct ib_sig_domain *mem = &sig_attrs->mem;
4538 struct ib_sig_domain *wire = &sig_attrs->wire;
4539
4540 memset(bsf, 0, sizeof(*bsf));
4541
4542
4543 basic->bsf_size_sbs = 1 << 7;
4544
4545 basic->check_byte_mask = sig_attrs->check_mask;
4546 basic->raw_data_size = cpu_to_be32(data_size);
4547
4548
4549 switch (sig_attrs->mem.sig_type) {
4550 case IB_SIG_TYPE_NONE:
4551 break;
4552 case IB_SIG_TYPE_T10_DIF:
4553 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4554 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4555 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4556 break;
4557 default:
4558 return -EINVAL;
4559 }
4560
4561
4562 switch (sig_attrs->wire.sig_type) {
4563 case IB_SIG_TYPE_NONE:
4564 break;
4565 case IB_SIG_TYPE_T10_DIF:
4566 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4567 mem->sig_type == wire->sig_type) {
4568
4569 basic->bsf_size_sbs |= 1 << 4;
4570 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4571 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4572 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4573 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4574 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4575 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4576 } else
4577 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4578
4579 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4580 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4581 break;
4582 default:
4583 return -EINVAL;
4584 }
4585
4586 return 0;
4587 }
4588
4589 static int set_sig_data_segment(const struct ib_send_wr *send_wr,
4590 struct ib_mr *sig_mr,
4591 struct ib_sig_attrs *sig_attrs,
4592 struct mlx5_ib_qp *qp, void **seg, int *size,
4593 void **cur_edge)
4594 {
4595 struct mlx5_bsf *bsf;
4596 u32 data_len;
4597 u32 data_key;
4598 u64 data_va;
4599 u32 prot_len = 0;
4600 u32 prot_key = 0;
4601 u64 prot_va = 0;
4602 bool prot = false;
4603 int ret;
4604 int wqe_size;
4605 struct mlx5_ib_mr *mr = to_mmr(sig_mr);
4606 struct mlx5_ib_mr *pi_mr = mr->pi_mr;
4607
4608 data_len = pi_mr->data_length;
4609 data_key = pi_mr->ibmr.lkey;
4610 data_va = pi_mr->data_iova;
4611 if (pi_mr->meta_ndescs) {
4612 prot_len = pi_mr->meta_length;
4613 prot_key = pi_mr->ibmr.lkey;
4614 prot_va = pi_mr->pi_iova;
4615 prot = true;
4616 }
4617
4618 if (!prot || (data_key == prot_key && data_va == prot_va &&
4619 data_len == prot_len)) {
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630 struct mlx5_klm *data_klm = *seg;
4631
4632 data_klm->bcount = cpu_to_be32(data_len);
4633 data_klm->key = cpu_to_be32(data_key);
4634 data_klm->va = cpu_to_be64(data_va);
4635 wqe_size = ALIGN(sizeof(*data_klm), 64);
4636 } else {
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4651 struct mlx5_stride_block_entry *data_sentry;
4652 struct mlx5_stride_block_entry *prot_sentry;
4653 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4654 int prot_size;
4655
4656 sblock_ctrl = *seg;
4657 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4658 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4659
4660 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4661 if (!prot_size) {
4662 pr_err("Bad block size given: %u\n", block_size);
4663 return -EINVAL;
4664 }
4665 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4666 prot_size);
4667 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4668 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4669 sblock_ctrl->num_entries = cpu_to_be16(2);
4670
4671 data_sentry->bcount = cpu_to_be16(block_size);
4672 data_sentry->key = cpu_to_be32(data_key);
4673 data_sentry->va = cpu_to_be64(data_va);
4674 data_sentry->stride = cpu_to_be16(block_size);
4675
4676 prot_sentry->bcount = cpu_to_be16(prot_size);
4677 prot_sentry->key = cpu_to_be32(prot_key);
4678 prot_sentry->va = cpu_to_be64(prot_va);
4679 prot_sentry->stride = cpu_to_be16(prot_size);
4680
4681 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4682 sizeof(*prot_sentry), 64);
4683 }
4684
4685 *seg += wqe_size;
4686 *size += wqe_size / 16;
4687 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4688
4689 bsf = *seg;
4690 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4691 if (ret)
4692 return -EINVAL;
4693
4694 *seg += sizeof(*bsf);
4695 *size += sizeof(*bsf) / 16;
4696 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4697
4698 return 0;
4699 }
4700
4701 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4702 struct ib_mr *sig_mr, int access_flags,
4703 u32 size, u32 length, u32 pdn)
4704 {
4705 u32 sig_key = sig_mr->rkey;
4706 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4707
4708 memset(seg, 0, sizeof(*seg));
4709
4710 seg->flags = get_umr_flags(access_flags) | MLX5_MKC_ACCESS_MODE_KLMS;
4711 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4712 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4713 MLX5_MKEY_BSF_EN | pdn);
4714 seg->len = cpu_to_be64(length);
4715 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4716 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4717 }
4718
4719 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4720 u32 size)
4721 {
4722 memset(umr, 0, sizeof(*umr));
4723
4724 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4725 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4726 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4727 umr->mkey_mask = sig_mkey_mask();
4728 }
4729
4730 static int set_pi_umr_wr(const struct ib_send_wr *send_wr,
4731 struct mlx5_ib_qp *qp, void **seg, int *size,
4732 void **cur_edge)
4733 {
4734 const struct ib_reg_wr *wr = reg_wr(send_wr);
4735 struct mlx5_ib_mr *sig_mr = to_mmr(wr->mr);
4736 struct mlx5_ib_mr *pi_mr = sig_mr->pi_mr;
4737 struct ib_sig_attrs *sig_attrs = sig_mr->ibmr.sig_attrs;
4738 u32 pdn = get_pd(qp)->pdn;
4739 u32 xlt_size;
4740 int region_len, ret;
4741
4742 if (unlikely(send_wr->num_sge != 0) ||
4743 unlikely(wr->access & IB_ACCESS_REMOTE_ATOMIC) ||
4744 unlikely(!sig_mr->sig) || unlikely(!qp->ibqp.integrity_en) ||
4745 unlikely(!sig_mr->sig->sig_status_checked))
4746 return -EINVAL;
4747
4748
4749 region_len = pi_mr->ibmr.length;
4750
4751
4752
4753
4754
4755
4756 if (sig_attrs->mem.sig_type != IB_SIG_TYPE_NONE)
4757 xlt_size = 0x30;
4758 else
4759 xlt_size = sizeof(struct mlx5_klm);
4760
4761 set_sig_umr_segment(*seg, xlt_size);
4762 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4763 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4764 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4765
4766 set_sig_mkey_segment(*seg, wr->mr, wr->access, xlt_size, region_len,
4767 pdn);
4768 *seg += sizeof(struct mlx5_mkey_seg);
4769 *size += sizeof(struct mlx5_mkey_seg) / 16;
4770 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4771
4772 ret = set_sig_data_segment(send_wr, wr->mr, sig_attrs, qp, seg, size,
4773 cur_edge);
4774 if (ret)
4775 return ret;
4776
4777 sig_mr->sig->sig_status_checked = false;
4778 return 0;
4779 }
4780
4781 static int set_psv_wr(struct ib_sig_domain *domain,
4782 u32 psv_idx, void **seg, int *size)
4783 {
4784 struct mlx5_seg_set_psv *psv_seg = *seg;
4785
4786 memset(psv_seg, 0, sizeof(*psv_seg));
4787 psv_seg->psv_num = cpu_to_be32(psv_idx);
4788 switch (domain->sig_type) {
4789 case IB_SIG_TYPE_NONE:
4790 break;
4791 case IB_SIG_TYPE_T10_DIF:
4792 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4793 domain->sig.dif.app_tag);
4794 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4795 break;
4796 default:
4797 pr_err("Bad signature type (%d) is given.\n",
4798 domain->sig_type);
4799 return -EINVAL;
4800 }
4801
4802 *seg += sizeof(*psv_seg);
4803 *size += sizeof(*psv_seg) / 16;
4804
4805 return 0;
4806 }
4807
4808 static int set_reg_wr(struct mlx5_ib_qp *qp,
4809 const struct ib_reg_wr *wr,
4810 void **seg, int *size, void **cur_edge,
4811 bool check_not_free)
4812 {
4813 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4814 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4815 struct mlx5_ib_dev *dev = to_mdev(pd->ibpd.device);
4816 int mr_list_size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size;
4817 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4818 bool atomic = wr->access & IB_ACCESS_REMOTE_ATOMIC;
4819 u8 flags = 0;
4820
4821 if (!mlx5_ib_can_use_umr(dev, atomic)) {
4822 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4823 "Fast update of %s for MR is disabled\n",
4824 (MLX5_CAP_GEN(dev->mdev,
4825 umr_modify_entity_size_disabled)) ?
4826 "entity size" :
4827 "atomic access");
4828 return -EINVAL;
4829 }
4830
4831 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4832 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4833 "Invalid IB_SEND_INLINE send flag\n");
4834 return -EINVAL;
4835 }
4836
4837 if (check_not_free)
4838 flags |= MLX5_UMR_CHECK_NOT_FREE;
4839 if (umr_inline)
4840 flags |= MLX5_UMR_INLINE;
4841
4842 set_reg_umr_seg(*seg, mr, flags, atomic);
4843 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4844 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4845 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4846
4847 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4848 *seg += sizeof(struct mlx5_mkey_seg);
4849 *size += sizeof(struct mlx5_mkey_seg) / 16;
4850 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4851
4852 if (umr_inline) {
4853 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
4854 mr_list_size);
4855 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4);
4856 } else {
4857 set_reg_data_seg(*seg, mr, pd);
4858 *seg += sizeof(struct mlx5_wqe_data_seg);
4859 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4860 }
4861 return 0;
4862 }
4863
4864 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size,
4865 void **cur_edge)
4866 {
4867 set_linv_umr_seg(*seg);
4868 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4869 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4870 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4871 set_linv_mkey_seg(*seg);
4872 *seg += sizeof(struct mlx5_mkey_seg);
4873 *size += sizeof(struct mlx5_mkey_seg) / 16;
4874 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4875 }
4876
4877 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16)
4878 {
4879 __be32 *p = NULL;
4880 int i, j;
4881
4882 pr_debug("dump WQE index %u:\n", idx);
4883 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4884 if ((i & 0xf) == 0) {
4885 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, idx);
4886 pr_debug("WQBB at %p:\n", (void *)p);
4887 j = 0;
4888 idx = (idx + 1) & (qp->sq.wqe_cnt - 1);
4889 }
4890 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4891 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4892 be32_to_cpu(p[j + 3]));
4893 }
4894 }
4895
4896 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4897 struct mlx5_wqe_ctrl_seg **ctrl,
4898 const struct ib_send_wr *wr, unsigned int *idx,
4899 int *size, void **cur_edge, int nreq,
4900 bool send_signaled, bool solicited)
4901 {
4902 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4903 return -ENOMEM;
4904
4905 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4906 *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx);
4907 *ctrl = *seg;
4908 *(uint32_t *)(*seg + 8) = 0;
4909 (*ctrl)->imm = send_ieth(wr);
4910 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4911 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4912 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
4913
4914 *seg += sizeof(**ctrl);
4915 *size = sizeof(**ctrl) / 16;
4916 *cur_edge = qp->sq.cur_edge;
4917
4918 return 0;
4919 }
4920
4921 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4922 struct mlx5_wqe_ctrl_seg **ctrl,
4923 const struct ib_send_wr *wr, unsigned *idx,
4924 int *size, void **cur_edge, int nreq)
4925 {
4926 return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
4927 wr->send_flags & IB_SEND_SIGNALED,
4928 wr->send_flags & IB_SEND_SOLICITED);
4929 }
4930
4931 static void finish_wqe(struct mlx5_ib_qp *qp,
4932 struct mlx5_wqe_ctrl_seg *ctrl,
4933 void *seg, u8 size, void *cur_edge,
4934 unsigned int idx, u64 wr_id, int nreq, u8 fence,
4935 u32 mlx5_opcode)
4936 {
4937 u8 opmod = 0;
4938
4939 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4940 mlx5_opcode | ((u32)opmod << 24));
4941 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4942 ctrl->fm_ce_se |= fence;
4943 if (unlikely(qp->wq_sig))
4944 ctrl->signature = wq_sig(ctrl);
4945
4946 qp->sq.wrid[idx] = wr_id;
4947 qp->sq.w_list[idx].opcode = mlx5_opcode;
4948 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4949 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4950 qp->sq.w_list[idx].next = qp->sq.cur_post;
4951
4952
4953
4954
4955 seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB);
4956 qp->sq.cur_edge = (unlikely(seg == cur_edge)) ?
4957 get_sq_edge(&qp->sq, qp->sq.cur_post &
4958 (qp->sq.wqe_cnt - 1)) :
4959 cur_edge;
4960 }
4961
4962 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4963 const struct ib_send_wr **bad_wr, bool drain)
4964 {
4965 struct mlx5_wqe_ctrl_seg *ctrl = NULL;
4966 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4967 struct mlx5_core_dev *mdev = dev->mdev;
4968 struct ib_reg_wr reg_pi_wr;
4969 struct mlx5_ib_qp *qp;
4970 struct mlx5_ib_mr *mr;
4971 struct mlx5_ib_mr *pi_mr;
4972 struct mlx5_ib_mr pa_pi_mr;
4973 struct ib_sig_attrs *sig_attrs;
4974 struct mlx5_wqe_xrc_seg *xrc;
4975 struct mlx5_bf *bf;
4976 void *cur_edge;
4977 int uninitialized_var(size);
4978 unsigned long flags;
4979 unsigned idx;
4980 int err = 0;
4981 int num_sge;
4982 void *seg;
4983 int nreq;
4984 int i;
4985 u8 next_fence = 0;
4986 u8 fence;
4987
4988 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4989 !drain)) {
4990 *bad_wr = wr;
4991 return -EIO;
4992 }
4993
4994 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4995 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4996
4997 qp = to_mqp(ibqp);
4998 bf = &qp->bf;
4999
5000 spin_lock_irqsave(&qp->sq.lock, flags);
5001
5002 for (nreq = 0; wr; nreq++, wr = wr->next) {
5003 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
5004 mlx5_ib_warn(dev, "\n");
5005 err = -EINVAL;
5006 *bad_wr = wr;
5007 goto out;
5008 }
5009
5010 num_sge = wr->num_sge;
5011 if (unlikely(num_sge > qp->sq.max_gs)) {
5012 mlx5_ib_warn(dev, "\n");
5013 err = -EINVAL;
5014 *bad_wr = wr;
5015 goto out;
5016 }
5017
5018 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge,
5019 nreq);
5020 if (err) {
5021 mlx5_ib_warn(dev, "\n");
5022 err = -ENOMEM;
5023 *bad_wr = wr;
5024 goto out;
5025 }
5026
5027 if (wr->opcode == IB_WR_REG_MR ||
5028 wr->opcode == IB_WR_REG_MR_INTEGRITY) {
5029 fence = dev->umr_fence;
5030 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
5031 } else {
5032 if (wr->send_flags & IB_SEND_FENCE) {
5033 if (qp->next_fence)
5034 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
5035 else
5036 fence = MLX5_FENCE_MODE_FENCE;
5037 } else {
5038 fence = qp->next_fence;
5039 }
5040 }
5041
5042 switch (ibqp->qp_type) {
5043 case IB_QPT_XRC_INI:
5044 xrc = seg;
5045 seg += sizeof(*xrc);
5046 size += sizeof(*xrc) / 16;
5047
5048 case IB_QPT_RC:
5049 switch (wr->opcode) {
5050 case IB_WR_RDMA_READ:
5051 case IB_WR_RDMA_WRITE:
5052 case IB_WR_RDMA_WRITE_WITH_IMM:
5053 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5054 rdma_wr(wr)->rkey);
5055 seg += sizeof(struct mlx5_wqe_raddr_seg);
5056 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5057 break;
5058
5059 case IB_WR_ATOMIC_CMP_AND_SWP:
5060 case IB_WR_ATOMIC_FETCH_AND_ADD:
5061 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
5062 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
5063 err = -ENOSYS;
5064 *bad_wr = wr;
5065 goto out;
5066
5067 case IB_WR_LOCAL_INV:
5068 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
5069 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
5070 set_linv_wr(qp, &seg, &size, &cur_edge);
5071 num_sge = 0;
5072 break;
5073
5074 case IB_WR_REG_MR:
5075 qp->sq.wr_data[idx] = IB_WR_REG_MR;
5076 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
5077 err = set_reg_wr(qp, reg_wr(wr), &seg, &size,
5078 &cur_edge, true);
5079 if (err) {
5080 *bad_wr = wr;
5081 goto out;
5082 }
5083 num_sge = 0;
5084 break;
5085
5086 case IB_WR_REG_MR_INTEGRITY:
5087 qp->sq.wr_data[idx] = IB_WR_REG_MR_INTEGRITY;
5088
5089 mr = to_mmr(reg_wr(wr)->mr);
5090 pi_mr = mr->pi_mr;
5091
5092 if (pi_mr) {
5093 memset(®_pi_wr, 0,
5094 sizeof(struct ib_reg_wr));
5095
5096 reg_pi_wr.mr = &pi_mr->ibmr;
5097 reg_pi_wr.access = reg_wr(wr)->access;
5098 reg_pi_wr.key = pi_mr->ibmr.rkey;
5099
5100 ctrl->imm = cpu_to_be32(reg_pi_wr.key);
5101
5102 err = set_reg_wr(qp, ®_pi_wr, &seg,
5103 &size, &cur_edge,
5104 false);
5105 if (err) {
5106 *bad_wr = wr;
5107 goto out;
5108 }
5109 finish_wqe(qp, ctrl, seg, size,
5110 cur_edge, idx, wr->wr_id,
5111 nreq, fence,
5112 MLX5_OPCODE_UMR);
5113
5114 err = begin_wqe(qp, &seg, &ctrl, wr,
5115 &idx, &size, &cur_edge,
5116 nreq);
5117 if (err) {
5118 mlx5_ib_warn(dev, "\n");
5119 err = -ENOMEM;
5120 *bad_wr = wr;
5121 goto out;
5122 }
5123 } else {
5124 memset(&pa_pi_mr, 0,
5125 sizeof(struct mlx5_ib_mr));
5126
5127 pa_pi_mr.ibmr.lkey =
5128 mr->ibmr.pd->local_dma_lkey;
5129
5130 pa_pi_mr.ndescs = mr->ndescs;
5131 pa_pi_mr.data_length = mr->data_length;
5132 pa_pi_mr.data_iova = mr->data_iova;
5133 if (mr->meta_ndescs) {
5134 pa_pi_mr.meta_ndescs =
5135 mr->meta_ndescs;
5136 pa_pi_mr.meta_length =
5137 mr->meta_length;
5138 pa_pi_mr.pi_iova = mr->pi_iova;
5139 }
5140
5141 pa_pi_mr.ibmr.length = mr->ibmr.length;
5142 mr->pi_mr = &pa_pi_mr;
5143 }
5144 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
5145
5146 err = set_pi_umr_wr(wr, qp, &seg, &size,
5147 &cur_edge);
5148 if (err) {
5149 mlx5_ib_warn(dev, "\n");
5150 *bad_wr = wr;
5151 goto out;
5152 }
5153 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5154 wr->wr_id, nreq, fence,
5155 MLX5_OPCODE_UMR);
5156
5157
5158
5159
5160
5161 sig_attrs = mr->ibmr.sig_attrs;
5162 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
5163 &size, &cur_edge, nreq, false,
5164 true);
5165 if (err) {
5166 mlx5_ib_warn(dev, "\n");
5167 err = -ENOMEM;
5168 *bad_wr = wr;
5169 goto out;
5170 }
5171 err = set_psv_wr(&sig_attrs->mem,
5172 mr->sig->psv_memory.psv_idx,
5173 &seg, &size);
5174 if (err) {
5175 mlx5_ib_warn(dev, "\n");
5176 *bad_wr = wr;
5177 goto out;
5178 }
5179 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5180 wr->wr_id, nreq, next_fence,
5181 MLX5_OPCODE_SET_PSV);
5182
5183 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
5184 &size, &cur_edge, nreq, false,
5185 true);
5186 if (err) {
5187 mlx5_ib_warn(dev, "\n");
5188 err = -ENOMEM;
5189 *bad_wr = wr;
5190 goto out;
5191 }
5192 err = set_psv_wr(&sig_attrs->wire,
5193 mr->sig->psv_wire.psv_idx,
5194 &seg, &size);
5195 if (err) {
5196 mlx5_ib_warn(dev, "\n");
5197 *bad_wr = wr;
5198 goto out;
5199 }
5200 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5201 wr->wr_id, nreq, next_fence,
5202 MLX5_OPCODE_SET_PSV);
5203
5204 qp->next_fence =
5205 MLX5_FENCE_MODE_INITIATOR_SMALL;
5206 num_sge = 0;
5207 goto skip_psv;
5208
5209 default:
5210 break;
5211 }
5212 break;
5213
5214 case IB_QPT_UC:
5215 switch (wr->opcode) {
5216 case IB_WR_RDMA_WRITE:
5217 case IB_WR_RDMA_WRITE_WITH_IMM:
5218 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5219 rdma_wr(wr)->rkey);
5220 seg += sizeof(struct mlx5_wqe_raddr_seg);
5221 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5222 break;
5223
5224 default:
5225 break;
5226 }
5227 break;
5228
5229 case IB_QPT_SMI:
5230 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
5231 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
5232 err = -EPERM;
5233 *bad_wr = wr;
5234 goto out;
5235 }
5236
5237 case MLX5_IB_QPT_HW_GSI:
5238 set_datagram_seg(seg, wr);
5239 seg += sizeof(struct mlx5_wqe_datagram_seg);
5240 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5241 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5242
5243 break;
5244 case IB_QPT_UD:
5245 set_datagram_seg(seg, wr);
5246 seg += sizeof(struct mlx5_wqe_datagram_seg);
5247 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5248 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5249
5250
5251 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
5252 struct mlx5_wqe_eth_pad *pad;
5253
5254 pad = seg;
5255 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
5256 seg += sizeof(struct mlx5_wqe_eth_pad);
5257 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
5258 set_eth_seg(wr, qp, &seg, &size, &cur_edge);
5259 handle_post_send_edge(&qp->sq, &seg, size,
5260 &cur_edge);
5261 }
5262 break;
5263 case MLX5_IB_QPT_REG_UMR:
5264 if (wr->opcode != MLX5_IB_WR_UMR) {
5265 err = -EINVAL;
5266 mlx5_ib_warn(dev, "bad opcode\n");
5267 goto out;
5268 }
5269 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
5270 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
5271 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
5272 if (unlikely(err))
5273 goto out;
5274 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
5275 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
5276 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5277 set_reg_mkey_segment(seg, wr);
5278 seg += sizeof(struct mlx5_mkey_seg);
5279 size += sizeof(struct mlx5_mkey_seg) / 16;
5280 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5281 break;
5282
5283 default:
5284 break;
5285 }
5286
5287 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
5288 err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge);
5289 if (unlikely(err)) {
5290 mlx5_ib_warn(dev, "\n");
5291 *bad_wr = wr;
5292 goto out;
5293 }
5294 } else {
5295 for (i = 0; i < num_sge; i++) {
5296 handle_post_send_edge(&qp->sq, &seg, size,
5297 &cur_edge);
5298 if (likely(wr->sg_list[i].length)) {
5299 set_data_ptr_seg
5300 ((struct mlx5_wqe_data_seg *)seg,
5301 wr->sg_list + i);
5302 size += sizeof(struct mlx5_wqe_data_seg) / 16;
5303 seg += sizeof(struct mlx5_wqe_data_seg);
5304 }
5305 }
5306 }
5307
5308 qp->next_fence = next_fence;
5309 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq,
5310 fence, mlx5_ib_opcode[wr->opcode]);
5311 skip_psv:
5312 if (0)
5313 dump_wqe(qp, idx, size);
5314 }
5315
5316 out:
5317 if (likely(nreq)) {
5318 qp->sq.head += nreq;
5319
5320
5321
5322
5323 wmb();
5324
5325 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
5326
5327
5328
5329 wmb();
5330
5331
5332 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset);
5333
5334
5335
5336 bf->offset ^= bf->buf_size;
5337 }
5338
5339 spin_unlock_irqrestore(&qp->sq.lock, flags);
5340
5341 return err;
5342 }
5343
5344 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5345 const struct ib_send_wr **bad_wr)
5346 {
5347 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
5348 }
5349
5350 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
5351 {
5352 sig->signature = calc_sig(sig, size);
5353 }
5354
5355 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5356 const struct ib_recv_wr **bad_wr, bool drain)
5357 {
5358 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5359 struct mlx5_wqe_data_seg *scat;
5360 struct mlx5_rwqe_sig *sig;
5361 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5362 struct mlx5_core_dev *mdev = dev->mdev;
5363 unsigned long flags;
5364 int err = 0;
5365 int nreq;
5366 int ind;
5367 int i;
5368
5369 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5370 !drain)) {
5371 *bad_wr = wr;
5372 return -EIO;
5373 }
5374
5375 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5376 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
5377
5378 spin_lock_irqsave(&qp->rq.lock, flags);
5379
5380 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
5381
5382 for (nreq = 0; wr; nreq++, wr = wr->next) {
5383 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
5384 err = -ENOMEM;
5385 *bad_wr = wr;
5386 goto out;
5387 }
5388
5389 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
5390 err = -EINVAL;
5391 *bad_wr = wr;
5392 goto out;
5393 }
5394
5395 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind);
5396 if (qp->wq_sig)
5397 scat++;
5398
5399 for (i = 0; i < wr->num_sge; i++)
5400 set_data_ptr_seg(scat + i, wr->sg_list + i);
5401
5402 if (i < qp->rq.max_gs) {
5403 scat[i].byte_count = 0;
5404 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
5405 scat[i].addr = 0;
5406 }
5407
5408 if (qp->wq_sig) {
5409 sig = (struct mlx5_rwqe_sig *)scat;
5410 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
5411 }
5412
5413 qp->rq.wrid[ind] = wr->wr_id;
5414
5415 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
5416 }
5417
5418 out:
5419 if (likely(nreq)) {
5420 qp->rq.head += nreq;
5421
5422
5423
5424
5425 wmb();
5426
5427 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
5428 }
5429
5430 spin_unlock_irqrestore(&qp->rq.lock, flags);
5431
5432 return err;
5433 }
5434
5435 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5436 const struct ib_recv_wr **bad_wr)
5437 {
5438 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
5439 }
5440
5441 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
5442 {
5443 switch (mlx5_state) {
5444 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
5445 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
5446 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
5447 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
5448 case MLX5_QP_STATE_SQ_DRAINING:
5449 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
5450 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
5451 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
5452 default: return -1;
5453 }
5454 }
5455
5456 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
5457 {
5458 switch (mlx5_mig_state) {
5459 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
5460 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
5461 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
5462 default: return -1;
5463 }
5464 }
5465
5466 static int to_ib_qp_access_flags(int mlx5_flags)
5467 {
5468 int ib_flags = 0;
5469
5470 if (mlx5_flags & MLX5_QP_BIT_RRE)
5471 ib_flags |= IB_ACCESS_REMOTE_READ;
5472 if (mlx5_flags & MLX5_QP_BIT_RWE)
5473 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5474 if (mlx5_flags & MLX5_QP_BIT_RAE)
5475 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5476
5477 return ib_flags;
5478 }
5479
5480 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
5481 struct rdma_ah_attr *ah_attr,
5482 struct mlx5_qp_path *path)
5483 {
5484
5485 memset(ah_attr, 0, sizeof(*ah_attr));
5486
5487 if (!path->port || path->port > ibdev->num_ports)
5488 return;
5489
5490 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5491
5492 rdma_ah_set_port_num(ah_attr, path->port);
5493 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
5494
5495 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5496 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5497 rdma_ah_set_static_rate(ah_attr,
5498 path->static_rate ? path->static_rate - 5 : 0);
5499
5500 if (path->grh_mlid & (1 << 7) ||
5501 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) {
5502 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5503
5504 rdma_ah_set_grh(ah_attr, NULL,
5505 tc_fl & 0xfffff,
5506 path->mgid_index,
5507 path->hop_limit,
5508 (tc_fl >> 20) & 0xff);
5509 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
5510 }
5511 }
5512
5513 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5514 struct mlx5_ib_sq *sq,
5515 u8 *sq_state)
5516 {
5517 int err;
5518
5519 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
5520 if (err)
5521 goto out;
5522 sq->state = *sq_state;
5523
5524 out:
5525 return err;
5526 }
5527
5528 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5529 struct mlx5_ib_rq *rq,
5530 u8 *rq_state)
5531 {
5532 void *out;
5533 void *rqc;
5534 int inlen;
5535 int err;
5536
5537 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
5538 out = kvzalloc(inlen, GFP_KERNEL);
5539 if (!out)
5540 return -ENOMEM;
5541
5542 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5543 if (err)
5544 goto out;
5545
5546 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5547 *rq_state = MLX5_GET(rqc, rqc, state);
5548 rq->state = *rq_state;
5549
5550 out:
5551 kvfree(out);
5552 return err;
5553 }
5554
5555 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5556 struct mlx5_ib_qp *qp, u8 *qp_state)
5557 {
5558 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5559 [MLX5_RQC_STATE_RST] = {
5560 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
5561 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
5562 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
5563 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
5564 },
5565 [MLX5_RQC_STATE_RDY] = {
5566 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
5567 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
5568 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
5569 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
5570 },
5571 [MLX5_RQC_STATE_ERR] = {
5572 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
5573 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
5574 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
5575 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
5576 },
5577 [MLX5_RQ_STATE_NA] = {
5578 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
5579 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
5580 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
5581 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
5582 },
5583 };
5584
5585 *qp_state = sqrq_trans[rq_state][sq_state];
5586
5587 if (*qp_state == MLX5_QP_STATE_BAD) {
5588 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5589 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5590 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5591 return -EINVAL;
5592 }
5593
5594 if (*qp_state == MLX5_QP_STATE)
5595 *qp_state = qp->state;
5596
5597 return 0;
5598 }
5599
5600 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5601 struct mlx5_ib_qp *qp,
5602 u8 *raw_packet_qp_state)
5603 {
5604 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5605 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5606 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5607 int err;
5608 u8 sq_state = MLX5_SQ_STATE_NA;
5609 u8 rq_state = MLX5_RQ_STATE_NA;
5610
5611 if (qp->sq.wqe_cnt) {
5612 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5613 if (err)
5614 return err;
5615 }
5616
5617 if (qp->rq.wqe_cnt) {
5618 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5619 if (err)
5620 return err;
5621 }
5622
5623 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5624 raw_packet_qp_state);
5625 }
5626
5627 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5628 struct ib_qp_attr *qp_attr)
5629 {
5630 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5631 struct mlx5_qp_context *context;
5632 int mlx5_state;
5633 u32 *outb;
5634 int err = 0;
5635
5636 outb = kzalloc(outlen, GFP_KERNEL);
5637 if (!outb)
5638 return -ENOMEM;
5639
5640 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
5641 outlen);
5642 if (err)
5643 goto out;
5644
5645
5646 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5647
5648 mlx5_state = be32_to_cpu(context->flags) >> 28;
5649
5650 qp->state = to_ib_qp_state(mlx5_state);
5651 qp_attr->path_mtu = context->mtu_msgmax >> 5;
5652 qp_attr->path_mig_state =
5653 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5654 qp_attr->qkey = be32_to_cpu(context->qkey);
5655 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5656 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
5657 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5658 qp_attr->qp_access_flags =
5659 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5660
5661 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5662 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5663 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5664 qp_attr->alt_pkey_index =
5665 be16_to_cpu(context->alt_path.pkey_index);
5666 qp_attr->alt_port_num =
5667 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5668 }
5669
5670 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5671 qp_attr->port_num = context->pri_path.port;
5672
5673
5674 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5675
5676 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5677
5678 qp_attr->max_dest_rd_atomic =
5679 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5680 qp_attr->min_rnr_timer =
5681 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5682 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
5683 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
5684 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
5685 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
5686
5687 out:
5688 kfree(outb);
5689 return err;
5690 }
5691
5692 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5693 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5694 struct ib_qp_init_attr *qp_init_attr)
5695 {
5696 struct mlx5_core_dct *dct = &mqp->dct.mdct;
5697 u32 *out;
5698 u32 access_flags = 0;
5699 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5700 void *dctc;
5701 int err;
5702 int supported_mask = IB_QP_STATE |
5703 IB_QP_ACCESS_FLAGS |
5704 IB_QP_PORT |
5705 IB_QP_MIN_RNR_TIMER |
5706 IB_QP_AV |
5707 IB_QP_PATH_MTU |
5708 IB_QP_PKEY_INDEX;
5709
5710 if (qp_attr_mask & ~supported_mask)
5711 return -EINVAL;
5712 if (mqp->state != IB_QPS_RTR)
5713 return -EINVAL;
5714
5715 out = kzalloc(outlen, GFP_KERNEL);
5716 if (!out)
5717 return -ENOMEM;
5718
5719 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5720 if (err)
5721 goto out;
5722
5723 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5724
5725 if (qp_attr_mask & IB_QP_STATE)
5726 qp_attr->qp_state = IB_QPS_RTR;
5727
5728 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5729 if (MLX5_GET(dctc, dctc, rre))
5730 access_flags |= IB_ACCESS_REMOTE_READ;
5731 if (MLX5_GET(dctc, dctc, rwe))
5732 access_flags |= IB_ACCESS_REMOTE_WRITE;
5733 if (MLX5_GET(dctc, dctc, rae))
5734 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5735 qp_attr->qp_access_flags = access_flags;
5736 }
5737
5738 if (qp_attr_mask & IB_QP_PORT)
5739 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5740 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5741 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5742 if (qp_attr_mask & IB_QP_AV) {
5743 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5744 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5745 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5746 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5747 }
5748 if (qp_attr_mask & IB_QP_PATH_MTU)
5749 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5750 if (qp_attr_mask & IB_QP_PKEY_INDEX)
5751 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5752 out:
5753 kfree(out);
5754 return err;
5755 }
5756
5757 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5758 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5759 {
5760 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5761 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5762 int err = 0;
5763 u8 raw_packet_qp_state;
5764
5765 if (ibqp->rwq_ind_tbl)
5766 return -ENOSYS;
5767
5768 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5769 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5770 qp_init_attr);
5771
5772
5773 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5774 memset(qp_attr, 0, sizeof(*qp_attr));
5775
5776 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5777 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5778 qp_attr_mask, qp_init_attr);
5779
5780 mutex_lock(&qp->mutex);
5781
5782 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5783 qp->flags & MLX5_IB_QP_UNDERLAY) {
5784 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5785 if (err)
5786 goto out;
5787 qp->state = raw_packet_qp_state;
5788 qp_attr->port_num = 1;
5789 } else {
5790 err = query_qp_attr(dev, qp, qp_attr);
5791 if (err)
5792 goto out;
5793 }
5794
5795 qp_attr->qp_state = qp->state;
5796 qp_attr->cur_qp_state = qp_attr->qp_state;
5797 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5798 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5799
5800 if (!ibqp->uobject) {
5801 qp_attr->cap.max_send_wr = qp->sq.max_post;
5802 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5803 qp_init_attr->qp_context = ibqp->qp_context;
5804 } else {
5805 qp_attr->cap.max_send_wr = 0;
5806 qp_attr->cap.max_send_sge = 0;
5807 }
5808
5809 qp_init_attr->qp_type = ibqp->qp_type;
5810 qp_init_attr->recv_cq = ibqp->recv_cq;
5811 qp_init_attr->send_cq = ibqp->send_cq;
5812 qp_init_attr->srq = ibqp->srq;
5813 qp_attr->cap.max_inline_data = qp->max_inline_data;
5814
5815 qp_init_attr->cap = qp_attr->cap;
5816
5817 qp_init_attr->create_flags = 0;
5818 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5819 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5820
5821 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5822 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5823 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5824 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5825 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5826 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5827 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5828 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5829
5830 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5831 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5832
5833 out:
5834 mutex_unlock(&qp->mutex);
5835 return err;
5836 }
5837
5838 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5839 struct ib_udata *udata)
5840 {
5841 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5842 struct mlx5_ib_xrcd *xrcd;
5843 int err;
5844
5845 if (!MLX5_CAP_GEN(dev->mdev, xrc))
5846 return ERR_PTR(-ENOSYS);
5847
5848 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5849 if (!xrcd)
5850 return ERR_PTR(-ENOMEM);
5851
5852 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
5853 if (err) {
5854 kfree(xrcd);
5855 return ERR_PTR(-ENOMEM);
5856 }
5857
5858 return &xrcd->ibxrcd;
5859 }
5860
5861 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
5862 {
5863 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5864 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5865 int err;
5866
5867 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
5868 if (err)
5869 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5870
5871 kfree(xrcd);
5872 return 0;
5873 }
5874
5875 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5876 {
5877 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5878 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5879 struct ib_event event;
5880
5881 if (rwq->ibwq.event_handler) {
5882 event.device = rwq->ibwq.device;
5883 event.element.wq = &rwq->ibwq;
5884 switch (type) {
5885 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5886 event.event = IB_EVENT_WQ_FATAL;
5887 break;
5888 default:
5889 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5890 return;
5891 }
5892
5893 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5894 }
5895 }
5896
5897 static int set_delay_drop(struct mlx5_ib_dev *dev)
5898 {
5899 int err = 0;
5900
5901 mutex_lock(&dev->delay_drop.lock);
5902 if (dev->delay_drop.activate)
5903 goto out;
5904
5905 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5906 if (err)
5907 goto out;
5908
5909 dev->delay_drop.activate = true;
5910 out:
5911 mutex_unlock(&dev->delay_drop.lock);
5912
5913 if (!err)
5914 atomic_inc(&dev->delay_drop.rqs_cnt);
5915 return err;
5916 }
5917
5918 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5919 struct ib_wq_init_attr *init_attr)
5920 {
5921 struct mlx5_ib_dev *dev;
5922 int has_net_offloads;
5923 __be64 *rq_pas0;
5924 void *in;
5925 void *rqc;
5926 void *wq;
5927 int inlen;
5928 int err;
5929
5930 dev = to_mdev(pd->device);
5931
5932 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5933 in = kvzalloc(inlen, GFP_KERNEL);
5934 if (!in)
5935 return -ENOMEM;
5936
5937 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
5938 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5939 MLX5_SET(rqc, rqc, mem_rq_type,
5940 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5941 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5942 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5943 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5944 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5945 wq = MLX5_ADDR_OF(rqc, rqc, wq);
5946 MLX5_SET(wq, wq, wq_type,
5947 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5948 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5949 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5950 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5951 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5952 err = -EOPNOTSUPP;
5953 goto out;
5954 } else {
5955 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5956 }
5957 }
5958 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5959 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5960 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5961 MLX5_SET(wq, wq, log_wqe_stride_size,
5962 rwq->single_stride_log_num_of_bytes -
5963 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5964 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5965 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5966 }
5967 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5968 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5969 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5970 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5971 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5972 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5973 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5974 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5975 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5976 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5977 err = -EOPNOTSUPP;
5978 goto out;
5979 }
5980 } else {
5981 MLX5_SET(rqc, rqc, vsd, 1);
5982 }
5983 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5984 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5985 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5986 err = -EOPNOTSUPP;
5987 goto out;
5988 }
5989 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5990 }
5991 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5992 if (!(dev->ib_dev.attrs.raw_packet_caps &
5993 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5994 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5995 err = -EOPNOTSUPP;
5996 goto out;
5997 }
5998 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5999 }
6000 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
6001 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
6002 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
6003 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
6004 err = set_delay_drop(dev);
6005 if (err) {
6006 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
6007 err);
6008 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
6009 } else {
6010 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
6011 }
6012 }
6013 out:
6014 kvfree(in);
6015 return err;
6016 }
6017
6018 static int set_user_rq_size(struct mlx5_ib_dev *dev,
6019 struct ib_wq_init_attr *wq_init_attr,
6020 struct mlx5_ib_create_wq *ucmd,
6021 struct mlx5_ib_rwq *rwq)
6022 {
6023
6024 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
6025 return -EINVAL;
6026
6027 if (!ucmd->rq_wqe_count)
6028 return -EINVAL;
6029
6030 rwq->wqe_count = ucmd->rq_wqe_count;
6031 rwq->wqe_shift = ucmd->rq_wqe_shift;
6032 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
6033 return -EINVAL;
6034
6035 rwq->log_rq_stride = rwq->wqe_shift;
6036 rwq->log_rq_size = ilog2(rwq->wqe_count);
6037 return 0;
6038 }
6039
6040 static int prepare_user_rq(struct ib_pd *pd,
6041 struct ib_wq_init_attr *init_attr,
6042 struct ib_udata *udata,
6043 struct mlx5_ib_rwq *rwq)
6044 {
6045 struct mlx5_ib_dev *dev = to_mdev(pd->device);
6046 struct mlx5_ib_create_wq ucmd = {};
6047 int err;
6048 size_t required_cmd_sz;
6049
6050 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
6051 + sizeof(ucmd.single_stride_log_num_of_bytes);
6052 if (udata->inlen < required_cmd_sz) {
6053 mlx5_ib_dbg(dev, "invalid inlen\n");
6054 return -EINVAL;
6055 }
6056
6057 if (udata->inlen > sizeof(ucmd) &&
6058 !ib_is_udata_cleared(udata, sizeof(ucmd),
6059 udata->inlen - sizeof(ucmd))) {
6060 mlx5_ib_dbg(dev, "inlen is not supported\n");
6061 return -EOPNOTSUPP;
6062 }
6063
6064 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
6065 mlx5_ib_dbg(dev, "copy failed\n");
6066 return -EFAULT;
6067 }
6068
6069 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
6070 mlx5_ib_dbg(dev, "invalid comp mask\n");
6071 return -EOPNOTSUPP;
6072 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
6073 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
6074 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
6075 return -EOPNOTSUPP;
6076 }
6077 if ((ucmd.single_stride_log_num_of_bytes <
6078 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
6079 (ucmd.single_stride_log_num_of_bytes >
6080 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
6081 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
6082 ucmd.single_stride_log_num_of_bytes,
6083 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
6084 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
6085 return -EINVAL;
6086 }
6087 if ((ucmd.single_wqe_log_num_of_strides >
6088 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
6089 (ucmd.single_wqe_log_num_of_strides <
6090 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
6091 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
6092 ucmd.single_wqe_log_num_of_strides,
6093 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
6094 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
6095 return -EINVAL;
6096 }
6097 rwq->single_stride_log_num_of_bytes =
6098 ucmd.single_stride_log_num_of_bytes;
6099 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
6100 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
6101 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
6102 }
6103
6104 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
6105 if (err) {
6106 mlx5_ib_dbg(dev, "err %d\n", err);
6107 return err;
6108 }
6109
6110 err = create_user_rq(dev, pd, udata, rwq, &ucmd);
6111 if (err) {
6112 mlx5_ib_dbg(dev, "err %d\n", err);
6113 return err;
6114 }
6115
6116 rwq->user_index = ucmd.user_index;
6117 return 0;
6118 }
6119
6120 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
6121 struct ib_wq_init_attr *init_attr,
6122 struct ib_udata *udata)
6123 {
6124 struct mlx5_ib_dev *dev;
6125 struct mlx5_ib_rwq *rwq;
6126 struct mlx5_ib_create_wq_resp resp = {};
6127 size_t min_resp_len;
6128 int err;
6129
6130 if (!udata)
6131 return ERR_PTR(-ENOSYS);
6132
6133 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6134 if (udata->outlen && udata->outlen < min_resp_len)
6135 return ERR_PTR(-EINVAL);
6136
6137 if (!capable(CAP_SYS_RAWIO) &&
6138 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
6139 return ERR_PTR(-EPERM);
6140
6141 dev = to_mdev(pd->device);
6142 switch (init_attr->wq_type) {
6143 case IB_WQT_RQ:
6144 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
6145 if (!rwq)
6146 return ERR_PTR(-ENOMEM);
6147 err = prepare_user_rq(pd, init_attr, udata, rwq);
6148 if (err)
6149 goto err;
6150 err = create_rq(rwq, pd, init_attr);
6151 if (err)
6152 goto err_user_rq;
6153 break;
6154 default:
6155 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
6156 init_attr->wq_type);
6157 return ERR_PTR(-EINVAL);
6158 }
6159
6160 rwq->ibwq.wq_num = rwq->core_qp.qpn;
6161 rwq->ibwq.state = IB_WQS_RESET;
6162 if (udata->outlen) {
6163 resp.response_length = offsetof(typeof(resp), response_length) +
6164 sizeof(resp.response_length);
6165 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6166 if (err)
6167 goto err_copy;
6168 }
6169
6170 rwq->core_qp.event = mlx5_ib_wq_event;
6171 rwq->ibwq.event_handler = init_attr->event_handler;
6172 return &rwq->ibwq;
6173
6174 err_copy:
6175 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
6176 err_user_rq:
6177 destroy_user_rq(dev, pd, rwq, udata);
6178 err:
6179 kfree(rwq);
6180 return ERR_PTR(err);
6181 }
6182
6183 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
6184 {
6185 struct mlx5_ib_dev *dev = to_mdev(wq->device);
6186 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6187
6188 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
6189 destroy_user_rq(dev, wq->pd, rwq, udata);
6190 kfree(rwq);
6191 }
6192
6193 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
6194 struct ib_rwq_ind_table_init_attr *init_attr,
6195 struct ib_udata *udata)
6196 {
6197 struct mlx5_ib_dev *dev = to_mdev(device);
6198 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
6199 int sz = 1 << init_attr->log_ind_tbl_size;
6200 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
6201 size_t min_resp_len;
6202 int inlen;
6203 int err;
6204 int i;
6205 u32 *in;
6206 void *rqtc;
6207
6208 if (udata->inlen > 0 &&
6209 !ib_is_udata_cleared(udata, 0,
6210 udata->inlen))
6211 return ERR_PTR(-EOPNOTSUPP);
6212
6213 if (init_attr->log_ind_tbl_size >
6214 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
6215 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
6216 init_attr->log_ind_tbl_size,
6217 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
6218 return ERR_PTR(-EINVAL);
6219 }
6220
6221 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6222 if (udata->outlen && udata->outlen < min_resp_len)
6223 return ERR_PTR(-EINVAL);
6224
6225 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
6226 if (!rwq_ind_tbl)
6227 return ERR_PTR(-ENOMEM);
6228
6229 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
6230 in = kvzalloc(inlen, GFP_KERNEL);
6231 if (!in) {
6232 err = -ENOMEM;
6233 goto err;
6234 }
6235
6236 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
6237
6238 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
6239 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
6240
6241 for (i = 0; i < sz; i++)
6242 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
6243
6244 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
6245 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
6246
6247 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
6248 kvfree(in);
6249
6250 if (err)
6251 goto err;
6252
6253 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
6254 if (udata->outlen) {
6255 resp.response_length = offsetof(typeof(resp), response_length) +
6256 sizeof(resp.response_length);
6257 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6258 if (err)
6259 goto err_copy;
6260 }
6261
6262 return &rwq_ind_tbl->ib_rwq_ind_tbl;
6263
6264 err_copy:
6265 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6266 err:
6267 kfree(rwq_ind_tbl);
6268 return ERR_PTR(err);
6269 }
6270
6271 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
6272 {
6273 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
6274 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
6275
6276 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6277
6278 kfree(rwq_ind_tbl);
6279 return 0;
6280 }
6281
6282 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
6283 u32 wq_attr_mask, struct ib_udata *udata)
6284 {
6285 struct mlx5_ib_dev *dev = to_mdev(wq->device);
6286 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6287 struct mlx5_ib_modify_wq ucmd = {};
6288 size_t required_cmd_sz;
6289 int curr_wq_state;
6290 int wq_state;
6291 int inlen;
6292 int err;
6293 void *rqc;
6294 void *in;
6295
6296 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
6297 if (udata->inlen < required_cmd_sz)
6298 return -EINVAL;
6299
6300 if (udata->inlen > sizeof(ucmd) &&
6301 !ib_is_udata_cleared(udata, sizeof(ucmd),
6302 udata->inlen - sizeof(ucmd)))
6303 return -EOPNOTSUPP;
6304
6305 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
6306 return -EFAULT;
6307
6308 if (ucmd.comp_mask || ucmd.reserved)
6309 return -EOPNOTSUPP;
6310
6311 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
6312 in = kvzalloc(inlen, GFP_KERNEL);
6313 if (!in)
6314 return -ENOMEM;
6315
6316 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
6317
6318 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
6319 wq_attr->curr_wq_state : wq->state;
6320 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
6321 wq_attr->wq_state : curr_wq_state;
6322 if (curr_wq_state == IB_WQS_ERR)
6323 curr_wq_state = MLX5_RQC_STATE_ERR;
6324 if (wq_state == IB_WQS_ERR)
6325 wq_state = MLX5_RQC_STATE_ERR;
6326 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
6327 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
6328 MLX5_SET(rqc, rqc, state, wq_state);
6329
6330 if (wq_attr_mask & IB_WQ_FLAGS) {
6331 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6332 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
6333 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6334 mlx5_ib_dbg(dev, "VLAN offloads are not "
6335 "supported\n");
6336 err = -EOPNOTSUPP;
6337 goto out;
6338 }
6339 MLX5_SET64(modify_rq_in, in, modify_bitmask,
6340 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
6341 MLX5_SET(rqc, rqc, vsd,
6342 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
6343 }
6344
6345 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6346 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
6347 err = -EOPNOTSUPP;
6348 goto out;
6349 }
6350 }
6351
6352 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
6353 u16 set_id;
6354
6355 set_id = mlx5_ib_get_counters_id(dev, 0);
6356 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
6357 MLX5_SET64(modify_rq_in, in, modify_bitmask,
6358 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
6359 MLX5_SET(rqc, rqc, counter_set_id, set_id);
6360 } else
6361 dev_info_once(
6362 &dev->ib_dev.dev,
6363 "Receive WQ counters are not supported on current FW\n");
6364 }
6365
6366 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
6367 if (!err)
6368 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
6369
6370 out:
6371 kvfree(in);
6372 return err;
6373 }
6374
6375 struct mlx5_ib_drain_cqe {
6376 struct ib_cqe cqe;
6377 struct completion done;
6378 };
6379
6380 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
6381 {
6382 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
6383 struct mlx5_ib_drain_cqe,
6384 cqe);
6385
6386 complete(&cqe->done);
6387 }
6388
6389
6390 static void handle_drain_completion(struct ib_cq *cq,
6391 struct mlx5_ib_drain_cqe *sdrain,
6392 struct mlx5_ib_dev *dev)
6393 {
6394 struct mlx5_core_dev *mdev = dev->mdev;
6395
6396 if (cq->poll_ctx == IB_POLL_DIRECT) {
6397 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
6398 ib_process_cq_direct(cq, -1);
6399 return;
6400 }
6401
6402 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6403 struct mlx5_ib_cq *mcq = to_mcq(cq);
6404 bool triggered = false;
6405 unsigned long flags;
6406
6407 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
6408
6409 if (!mcq->mcq.reset_notify_added)
6410 mcq->mcq.reset_notify_added = 1;
6411 else
6412 triggered = true;
6413 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
6414
6415 if (triggered) {
6416
6417 switch (cq->poll_ctx) {
6418 case IB_POLL_SOFTIRQ:
6419 irq_poll_disable(&cq->iop);
6420 irq_poll_enable(&cq->iop);
6421 break;
6422 case IB_POLL_WORKQUEUE:
6423 cancel_work_sync(&cq->work);
6424 break;
6425 default:
6426 WARN_ON_ONCE(1);
6427 }
6428 }
6429
6430
6431
6432
6433 mcq->mcq.comp(&mcq->mcq, NULL);
6434 }
6435
6436 wait_for_completion(&sdrain->done);
6437 }
6438
6439 void mlx5_ib_drain_sq(struct ib_qp *qp)
6440 {
6441 struct ib_cq *cq = qp->send_cq;
6442 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6443 struct mlx5_ib_drain_cqe sdrain;
6444 const struct ib_send_wr *bad_swr;
6445 struct ib_rdma_wr swr = {
6446 .wr = {
6447 .next = NULL,
6448 { .wr_cqe = &sdrain.cqe, },
6449 .opcode = IB_WR_RDMA_WRITE,
6450 },
6451 };
6452 int ret;
6453 struct mlx5_ib_dev *dev = to_mdev(qp->device);
6454 struct mlx5_core_dev *mdev = dev->mdev;
6455
6456 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6457 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6458 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6459 return;
6460 }
6461
6462 sdrain.cqe.done = mlx5_ib_drain_qp_done;
6463 init_completion(&sdrain.done);
6464
6465 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
6466 if (ret) {
6467 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6468 return;
6469 }
6470
6471 handle_drain_completion(cq, &sdrain, dev);
6472 }
6473
6474 void mlx5_ib_drain_rq(struct ib_qp *qp)
6475 {
6476 struct ib_cq *cq = qp->recv_cq;
6477 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6478 struct mlx5_ib_drain_cqe rdrain;
6479 struct ib_recv_wr rwr = {};
6480 const struct ib_recv_wr *bad_rwr;
6481 int ret;
6482 struct mlx5_ib_dev *dev = to_mdev(qp->device);
6483 struct mlx5_core_dev *mdev = dev->mdev;
6484
6485 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6486 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6487 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6488 return;
6489 }
6490
6491 rwr.wr_cqe = &rdrain.cqe;
6492 rdrain.cqe.done = mlx5_ib_drain_qp_done;
6493 init_completion(&rdrain.done);
6494
6495 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6496 if (ret) {
6497 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6498 return;
6499 }
6500
6501 handle_drain_completion(cq, &rdrain, dev);
6502 }
6503
6504
6505
6506
6507
6508 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter)
6509 {
6510 struct mlx5_ib_dev *dev = to_mdev(qp->device);
6511 struct mlx5_ib_qp *mqp = to_mqp(qp);
6512 int err = 0;
6513
6514 mutex_lock(&mqp->mutex);
6515 if (mqp->state == IB_QPS_RESET) {
6516 qp->counter = counter;
6517 goto out;
6518 }
6519
6520 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) {
6521 err = -EOPNOTSUPP;
6522 goto out;
6523 }
6524
6525 if (mqp->state == IB_QPS_RTS) {
6526 err = __mlx5_ib_qp_set_counter(qp, counter);
6527 if (!err)
6528 qp->counter = counter;
6529
6530 goto out;
6531 }
6532
6533 mqp->counter_pending = 1;
6534 qp->counter = counter;
6535
6536 out:
6537 mutex_unlock(&mqp->mutex);
6538 return err;
6539 }