This source file includes following definitions.
- mlx5_ib_get_ibdev_from_mpi
- mlx5_port_type_cap_to_rdma_ll
- mlx5_ib_port_link_layer
- get_port_state
- mlx5_get_rep_roce
- mlx5_netdev_event
- mlx5_ib_get_netdev
- mlx5_ib_get_native_port_mdev
- mlx5_ib_put_native_port_mdev
- translate_eth_legacy_proto_oper
- translate_eth_ext_proto_oper
- translate_eth_proto_oper
- mlx5_query_port_roce
- set_roce_addr
- mlx5_ib_add_gid
- mlx5_ib_del_gid
- mlx5_get_roce_udp_sport
- mlx5_use_mad_ifc
- mlx5_get_vport_access_method
- get_atomic_caps
- get_atomic_caps_qp
- get_atomic_caps_dc
- mlx5_ib_dc_atomic_is_supported
- mlx5_query_system_image_guid
- mlx5_query_max_pkeys
- mlx5_query_vendor_id
- mlx5_query_node_guid
- mlx5_query_node_desc
- mlx5_ib_query_device
- translate_active_width
- mlx5_mtu_to_ib_mtu
- translate_max_vl_num
- mlx5_query_hca_port
- mlx5_ib_query_port
- mlx5_ib_rep_query_port
- mlx5_ib_query_gid
- mlx5_query_hca_nic_pkey
- mlx5_ib_query_pkey
- mlx5_ib_modify_device
- set_port_caps_atomic
- mlx5_ib_modify_port
- print_lib_caps
- calc_dynamic_bfregs
- calc_total_bfregs
- allocate_uars
- deallocate_uars
- mlx5_ib_enable_lb
- mlx5_ib_disable_lb
- mlx5_ib_alloc_transport_domain
- mlx5_ib_dealloc_transport_domain
- mlx5_ib_alloc_ucontext
- mlx5_ib_dealloc_ucontext
- uar_index2pfn
- get_command
- get_arg
- get_index
- get_extended_index
- mlx5_ib_disassociate_ucontext
- mmap_cmd2str
- mlx5_ib_mmap_clock_info_page
- uar_mmap
- dm_mmap
- mlx5_ib_mmap
- check_dm_type_support
- handle_alloc_dm_memic
- handle_alloc_dm_sw_icm
- mlx5_ib_alloc_dm
- mlx5_ib_dealloc_dm
- mlx5_ib_alloc_pd
- mlx5_ib_dealloc_pd
- get_match_criteria_enable
- set_proto
- set_flow_label
- set_tos
- check_mpls_supp_fields
- parse_flow_flow_action
- parse_flow_attr
- flow_is_multicast_only
- is_valid_esp_aes_gcm
- is_valid_spec
- is_valid_ethertype
- is_valid_attr
- put_flow_table
- counters_clear_description
- mlx5_ib_destroy_flow
- ib_prio_to_core_prio
- _get_prio
- get_flow_table
- set_underlay_qp
- read_flow_counters
- counters_set_description
- flow_counters_set_data
- mlx5_ib_set_rule_source_port
- _create_flow_rule
- create_flow_rule
- create_dont_trap_rule
- create_leftovers_rule
- create_sniffer_rule
- mlx5_ib_create_flow
- _get_flow_table
- _create_raw_flow_rule
- raw_fs_is_multicast
- mlx5_ib_raw_fs_rule_add
- mlx5_ib_flow_action_flags_to_accel_xfrm_flags
- mlx5_ib_create_flow_action_esp
- mlx5_ib_modify_flow_action_esp
- mlx5_ib_destroy_flow_action
- mlx5_ib_mcg_attach
- mlx5_ib_mcg_detach
- init_node_data
- fw_pages_show
- reg_pages_show
- hca_type_show
- hw_rev_show
- board_id_show
- pkey_change_handler
- mlx5_ib_handle_internal_error
- delay_drop_handler
- handle_general_event
- handle_port_change
- mlx5_ib_handle_event
- mlx5_ib_event
- mlx5_ib_event_slave_port
- set_has_smi_cap
- get_ext_port_caps
- __get_port_caps
- get_port_caps
- destroy_umrc_res
- create_umr_res
- mlx5_get_umr_fence
- create_dev_resources
- destroy_dev_resources
- get_core_cap_flags
- mlx5_port_immutable
- mlx5_port_rep_immutable
- get_dev_fw_str
- mlx5_eth_lag_init
- mlx5_eth_lag_cleanup
- mlx5_add_netdev_notifier
- mlx5_remove_netdev_notifier
- mlx5_enable_eth
- mlx5_disable_eth
- is_mdev_switchdev_mode
- mlx5_ib_dealloc_counters
- __mlx5_ib_alloc_counters
- mlx5_ib_fill_counters
- mlx5_ib_alloc_counters
- get_counters
- mlx5_ib_get_counters_id
- mlx5_ib_alloc_hw_stats
- mlx5_ib_query_q_counters
- mlx5_ib_query_ext_ppcnt_counters
- mlx5_ib_get_hw_stats
- mlx5_ib_counter_alloc_stats
- mlx5_ib_counter_update_stats
- mlx5_ib_counter_bind_qp
- mlx5_ib_counter_unbind_qp
- mlx5_ib_counter_dealloc
- mlx5_ib_rn_get_params
- delay_drop_debugfs_cleanup
- cancel_delay_drop
- delay_drop_timeout_read
- delay_drop_timeout_write
- delay_drop_debugfs_init
- init_delay_drop
- mlx5_ib_unbind_slave_port
- mlx5_ib_bind_slave_port
- mlx5_ib_init_multiport_master
- mlx5_ib_cleanup_multiport_master
- mlx5_ib_read_counters
- mlx5_ib_destroy_counters
- mlx5_ib_create_counters
- mlx5_ib_stage_init_cleanup
- mlx5_ib_stage_init_init
- mlx5_ib_stage_flow_db_init
- mlx5_ib_stage_flow_db_cleanup
- mlx5_ib_stage_caps_init
- mlx5_ib_stage_non_default_cb
- mlx5_ib_stage_rep_non_default_cb
- mlx5_ib_stage_common_roce_init
- mlx5_ib_stage_common_roce_cleanup
- mlx5_ib_stage_rep_roce_init
- mlx5_ib_stage_rep_roce_cleanup
- mlx5_ib_stage_roce_init
- mlx5_ib_stage_roce_cleanup
- mlx5_ib_stage_dev_res_init
- mlx5_ib_stage_dev_res_cleanup
- mlx5_ib_stage_odp_init
- mlx5_ib_stage_odp_cleanup
- mlx5_ib_stage_counters_init
- mlx5_ib_stage_counters_cleanup
- mlx5_ib_stage_cong_debugfs_init
- mlx5_ib_stage_cong_debugfs_cleanup
- mlx5_ib_stage_uar_init
- mlx5_ib_stage_uar_cleanup
- mlx5_ib_stage_bfrag_init
- mlx5_ib_stage_bfrag_cleanup
- mlx5_ib_stage_ib_reg_init
- mlx5_ib_stage_pre_ib_reg_umr_cleanup
- mlx5_ib_stage_ib_reg_cleanup
- mlx5_ib_stage_post_ib_reg_umr_init
- mlx5_ib_stage_delay_drop_init
- mlx5_ib_stage_delay_drop_cleanup
- mlx5_ib_stage_dev_notifier_init
- mlx5_ib_stage_dev_notifier_cleanup
- mlx5_ib_stage_devx_init
- mlx5_ib_stage_devx_cleanup
- __mlx5_ib_remove
- __mlx5_ib_add
- mlx5_ib_add_slave_port
- mlx5_ib_add
- mlx5_ib_remove
- mlx5_ib_get_xlt_emergency_page
- mlx5_ib_put_xlt_emergency_page
- mlx5_ib_init
- mlx5_ib_cleanup
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33 #include <linux/debugfs.h>
34 #include <linux/highmem.h>
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/errno.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/bitmap.h>
42 #if defined(CONFIG_X86)
43 #include <asm/pat.h>
44 #endif
45 #include <linux/sched.h>
46 #include <linux/sched/mm.h>
47 #include <linux/sched/task.h>
48 #include <linux/delay.h>
49 #include <rdma/ib_user_verbs.h>
50 #include <rdma/ib_addr.h>
51 #include <rdma/ib_cache.h>
52 #include <linux/mlx5/port.h>
53 #include <linux/mlx5/vport.h>
54 #include <linux/mlx5/fs.h>
55 #include <linux/mlx5/eswitch.h>
56 #include <linux/list.h>
57 #include <rdma/ib_smi.h>
58 #include <rdma/ib_umem.h>
59 #include <linux/in.h>
60 #include <linux/etherdevice.h>
61 #include "mlx5_ib.h"
62 #include "ib_rep.h"
63 #include "cmd.h"
64 #include "srq.h"
65 #include <linux/mlx5/fs_helpers.h>
66 #include <linux/mlx5/accel.h>
67 #include <rdma/uverbs_std_types.h>
68 #include <rdma/mlx5_user_ioctl_verbs.h>
69 #include <rdma/mlx5_user_ioctl_cmds.h>
70
71 #define UVERBS_MODULE_NAME mlx5_ib
72 #include <rdma/uverbs_named_ioctl.h>
73
74 #define DRIVER_NAME "mlx5_ib"
75 #define DRIVER_VERSION "5.0-0"
76
77 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
78 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
79 MODULE_LICENSE("Dual BSD/GPL");
80
81 static char mlx5_version[] =
82 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
83 DRIVER_VERSION "\n";
84
85 struct mlx5_ib_event_work {
86 struct work_struct work;
87 union {
88 struct mlx5_ib_dev *dev;
89 struct mlx5_ib_multiport_info *mpi;
90 };
91 bool is_slave;
92 unsigned int event;
93 void *param;
94 };
95
96 enum {
97 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
98 };
99
100 static struct workqueue_struct *mlx5_ib_event_wq;
101 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
102 static LIST_HEAD(mlx5_ib_dev_list);
103
104
105
106 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
107
108
109
110
111 static unsigned long xlt_emergency_page;
112 static struct mutex xlt_emergency_page_mutex;
113
114 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
115 {
116 struct mlx5_ib_dev *dev;
117
118 mutex_lock(&mlx5_ib_multiport_mutex);
119 dev = mpi->ibdev;
120 mutex_unlock(&mlx5_ib_multiport_mutex);
121 return dev;
122 }
123
124 static enum rdma_link_layer
125 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
126 {
127 switch (port_type_cap) {
128 case MLX5_CAP_PORT_TYPE_IB:
129 return IB_LINK_LAYER_INFINIBAND;
130 case MLX5_CAP_PORT_TYPE_ETH:
131 return IB_LINK_LAYER_ETHERNET;
132 default:
133 return IB_LINK_LAYER_UNSPECIFIED;
134 }
135 }
136
137 static enum rdma_link_layer
138 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
139 {
140 struct mlx5_ib_dev *dev = to_mdev(device);
141 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
142
143 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
144 }
145
146 static int get_port_state(struct ib_device *ibdev,
147 u8 port_num,
148 enum ib_port_state *state)
149 {
150 struct ib_port_attr attr;
151 int ret;
152
153 memset(&attr, 0, sizeof(attr));
154 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
155 if (!ret)
156 *state = attr.state;
157 return ret;
158 }
159
160 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
161 struct net_device *ndev,
162 u8 *port_num)
163 {
164 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
165 struct net_device *rep_ndev;
166 struct mlx5_ib_port *port;
167 int i;
168
169 for (i = 0; i < dev->num_ports; i++) {
170 port = &dev->port[i];
171 if (!port->rep)
172 continue;
173
174 read_lock(&port->roce.netdev_lock);
175 rep_ndev = mlx5_ib_get_rep_netdev(esw,
176 port->rep->vport);
177 if (rep_ndev == ndev) {
178 read_unlock(&port->roce.netdev_lock);
179 *port_num = i + 1;
180 return &port->roce;
181 }
182 read_unlock(&port->roce.netdev_lock);
183 }
184
185 return NULL;
186 }
187
188 static int mlx5_netdev_event(struct notifier_block *this,
189 unsigned long event, void *ptr)
190 {
191 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
192 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
193 u8 port_num = roce->native_port_num;
194 struct mlx5_core_dev *mdev;
195 struct mlx5_ib_dev *ibdev;
196
197 ibdev = roce->dev;
198 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
199 if (!mdev)
200 return NOTIFY_DONE;
201
202 switch (event) {
203 case NETDEV_REGISTER:
204
205 if (ibdev->is_rep)
206 break;
207 write_lock(&roce->netdev_lock);
208 if (ndev->dev.parent == mdev->device)
209 roce->netdev = ndev;
210 write_unlock(&roce->netdev_lock);
211 break;
212
213 case NETDEV_UNREGISTER:
214
215 write_lock(&roce->netdev_lock);
216 if (roce->netdev == ndev)
217 roce->netdev = NULL;
218 write_unlock(&roce->netdev_lock);
219 break;
220
221 case NETDEV_CHANGE:
222 case NETDEV_UP:
223 case NETDEV_DOWN: {
224 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
225 struct net_device *upper = NULL;
226
227 if (lag_ndev) {
228 upper = netdev_master_upper_dev_get(lag_ndev);
229 dev_put(lag_ndev);
230 }
231
232 if (ibdev->is_rep)
233 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
234 if (!roce)
235 return NOTIFY_DONE;
236 if ((upper == ndev || (!upper && ndev == roce->netdev))
237 && ibdev->ib_active) {
238 struct ib_event ibev = { };
239 enum ib_port_state port_state;
240
241 if (get_port_state(&ibdev->ib_dev, port_num,
242 &port_state))
243 goto done;
244
245 if (roce->last_port_state == port_state)
246 goto done;
247
248 roce->last_port_state = port_state;
249 ibev.device = &ibdev->ib_dev;
250 if (port_state == IB_PORT_DOWN)
251 ibev.event = IB_EVENT_PORT_ERR;
252 else if (port_state == IB_PORT_ACTIVE)
253 ibev.event = IB_EVENT_PORT_ACTIVE;
254 else
255 goto done;
256
257 ibev.element.port_num = port_num;
258 ib_dispatch_event(&ibev);
259 }
260 break;
261 }
262
263 default:
264 break;
265 }
266 done:
267 mlx5_ib_put_native_port_mdev(ibdev, port_num);
268 return NOTIFY_DONE;
269 }
270
271 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
272 u8 port_num)
273 {
274 struct mlx5_ib_dev *ibdev = to_mdev(device);
275 struct net_device *ndev;
276 struct mlx5_core_dev *mdev;
277
278 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
279 if (!mdev)
280 return NULL;
281
282 ndev = mlx5_lag_get_roce_netdev(mdev);
283 if (ndev)
284 goto out;
285
286
287
288 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
289 ndev = ibdev->port[port_num - 1].roce.netdev;
290 if (ndev)
291 dev_hold(ndev);
292 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
293
294 out:
295 mlx5_ib_put_native_port_mdev(ibdev, port_num);
296 return ndev;
297 }
298
299 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
300 u8 ib_port_num,
301 u8 *native_port_num)
302 {
303 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
304 ib_port_num);
305 struct mlx5_core_dev *mdev = NULL;
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
309 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
310 ll != IB_LINK_LAYER_ETHERNET) {
311 if (native_port_num)
312 *native_port_num = ib_port_num;
313 return ibdev->mdev;
314 }
315
316 if (native_port_num)
317 *native_port_num = 1;
318
319 port = &ibdev->port[ib_port_num - 1];
320 if (!port)
321 return NULL;
322
323 spin_lock(&port->mp.mpi_lock);
324 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
325 if (mpi && !mpi->unaffiliate) {
326 mdev = mpi->mdev;
327
328
329
330 if (!mpi->is_master)
331 mpi->mdev_refcnt++;
332 }
333 spin_unlock(&port->mp.mpi_lock);
334
335 return mdev;
336 }
337
338 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
339 {
340 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
341 port_num);
342 struct mlx5_ib_multiport_info *mpi;
343 struct mlx5_ib_port *port;
344
345 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
346 return;
347
348 port = &ibdev->port[port_num - 1];
349
350 spin_lock(&port->mp.mpi_lock);
351 mpi = ibdev->port[port_num - 1].mp.mpi;
352 if (mpi->is_master)
353 goto out;
354
355 mpi->mdev_refcnt--;
356 if (mpi->unaffiliate)
357 complete(&mpi->unref_comp);
358 out:
359 spin_unlock(&port->mp.mpi_lock);
360 }
361
362 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
363 u8 *active_width)
364 {
365 switch (eth_proto_oper) {
366 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
367 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
368 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
369 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
370 *active_width = IB_WIDTH_1X;
371 *active_speed = IB_SPEED_SDR;
372 break;
373 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
374 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
375 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
376 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
377 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
378 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
379 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
380 *active_width = IB_WIDTH_1X;
381 *active_speed = IB_SPEED_QDR;
382 break;
383 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
384 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
385 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
386 *active_width = IB_WIDTH_1X;
387 *active_speed = IB_SPEED_EDR;
388 break;
389 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
390 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
391 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
392 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
393 *active_width = IB_WIDTH_4X;
394 *active_speed = IB_SPEED_QDR;
395 break;
396 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
397 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
398 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
399 *active_width = IB_WIDTH_1X;
400 *active_speed = IB_SPEED_HDR;
401 break;
402 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
403 *active_width = IB_WIDTH_4X;
404 *active_speed = IB_SPEED_FDR;
405 break;
406 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
407 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
408 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
409 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
410 *active_width = IB_WIDTH_4X;
411 *active_speed = IB_SPEED_EDR;
412 break;
413 default:
414 return -EINVAL;
415 }
416
417 return 0;
418 }
419
420 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
421 u8 *active_width)
422 {
423 switch (eth_proto_oper) {
424 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
425 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
426 *active_width = IB_WIDTH_1X;
427 *active_speed = IB_SPEED_SDR;
428 break;
429 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
430 *active_width = IB_WIDTH_1X;
431 *active_speed = IB_SPEED_DDR;
432 break;
433 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
434 *active_width = IB_WIDTH_1X;
435 *active_speed = IB_SPEED_QDR;
436 break;
437 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
438 *active_width = IB_WIDTH_4X;
439 *active_speed = IB_SPEED_QDR;
440 break;
441 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
442 *active_width = IB_WIDTH_1X;
443 *active_speed = IB_SPEED_EDR;
444 break;
445 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
446 *active_width = IB_WIDTH_2X;
447 *active_speed = IB_SPEED_EDR;
448 break;
449 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
450 *active_width = IB_WIDTH_1X;
451 *active_speed = IB_SPEED_HDR;
452 break;
453 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
454 *active_width = IB_WIDTH_4X;
455 *active_speed = IB_SPEED_EDR;
456 break;
457 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
458 *active_width = IB_WIDTH_2X;
459 *active_speed = IB_SPEED_HDR;
460 break;
461 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
462 *active_width = IB_WIDTH_4X;
463 *active_speed = IB_SPEED_HDR;
464 break;
465 default:
466 return -EINVAL;
467 }
468
469 return 0;
470 }
471
472 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
473 u8 *active_width, bool ext)
474 {
475 return ext ?
476 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
477 active_width) :
478 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
479 active_width);
480 }
481
482 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
483 struct ib_port_attr *props)
484 {
485 struct mlx5_ib_dev *dev = to_mdev(device);
486 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
487 struct mlx5_core_dev *mdev;
488 struct net_device *ndev, *upper;
489 enum ib_mtu ndev_ib_mtu;
490 bool put_mdev = true;
491 u16 qkey_viol_cntr;
492 u32 eth_prot_oper;
493 u8 mdev_port_num;
494 bool ext;
495 int err;
496
497 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
498 if (!mdev) {
499
500
501
502 put_mdev = false;
503 mdev = dev->mdev;
504 mdev_port_num = 1;
505 port_num = 1;
506 }
507
508
509
510
511
512 if (dev->is_rep)
513 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
514 1);
515 else
516 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
517 mdev_port_num);
518 if (err)
519 goto out;
520 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
521 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
522
523 props->active_width = IB_WIDTH_4X;
524 props->active_speed = IB_SPEED_QDR;
525
526 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
527 &props->active_width, ext);
528
529 props->port_cap_flags |= IB_PORT_CM_SUP;
530 props->ip_gids = true;
531
532 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
533 roce_address_table_size);
534 props->max_mtu = IB_MTU_4096;
535 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
536 props->pkey_tbl_len = 1;
537 props->state = IB_PORT_DOWN;
538 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
539
540 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
541 props->qkey_viol_cntr = qkey_viol_cntr;
542
543
544 if (!put_mdev)
545 goto out;
546
547 ndev = mlx5_ib_get_netdev(device, port_num);
548 if (!ndev)
549 goto out;
550
551 if (dev->lag_active) {
552 rcu_read_lock();
553 upper = netdev_master_upper_dev_get_rcu(ndev);
554 if (upper) {
555 dev_put(ndev);
556 ndev = upper;
557 dev_hold(ndev);
558 }
559 rcu_read_unlock();
560 }
561
562 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
563 props->state = IB_PORT_ACTIVE;
564 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
565 }
566
567 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
568
569 dev_put(ndev);
570
571 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
572 out:
573 if (put_mdev)
574 mlx5_ib_put_native_port_mdev(dev, port_num);
575 return err;
576 }
577
578 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
579 unsigned int index, const union ib_gid *gid,
580 const struct ib_gid_attr *attr)
581 {
582 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
583 u16 vlan_id = 0xffff;
584 u8 roce_version = 0;
585 u8 roce_l3_type = 0;
586 u8 mac[ETH_ALEN];
587 int ret;
588
589 if (gid) {
590 gid_type = attr->gid_type;
591 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
592 if (ret)
593 return ret;
594 }
595
596 switch (gid_type) {
597 case IB_GID_TYPE_IB:
598 roce_version = MLX5_ROCE_VERSION_1;
599 break;
600 case IB_GID_TYPE_ROCE_UDP_ENCAP:
601 roce_version = MLX5_ROCE_VERSION_2;
602 if (ipv6_addr_v4mapped((void *)gid))
603 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
604 else
605 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
606 break;
607
608 default:
609 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
610 }
611
612 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
613 roce_l3_type, gid->raw, mac,
614 vlan_id < VLAN_CFI_MASK, vlan_id,
615 port_num);
616 }
617
618 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
619 __always_unused void **context)
620 {
621 return set_roce_addr(to_mdev(attr->device), attr->port_num,
622 attr->index, &attr->gid, attr);
623 }
624
625 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
626 __always_unused void **context)
627 {
628 return set_roce_addr(to_mdev(attr->device), attr->port_num,
629 attr->index, NULL, NULL);
630 }
631
632 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
633 const struct ib_gid_attr *attr)
634 {
635 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
636 return 0;
637
638 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
639 }
640
641 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
642 {
643 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
644 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
645 return 0;
646 }
647
648 enum {
649 MLX5_VPORT_ACCESS_METHOD_MAD,
650 MLX5_VPORT_ACCESS_METHOD_HCA,
651 MLX5_VPORT_ACCESS_METHOD_NIC,
652 };
653
654 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
655 {
656 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
657 return MLX5_VPORT_ACCESS_METHOD_MAD;
658
659 if (mlx5_ib_port_link_layer(ibdev, 1) ==
660 IB_LINK_LAYER_ETHERNET)
661 return MLX5_VPORT_ACCESS_METHOD_NIC;
662
663 return MLX5_VPORT_ACCESS_METHOD_HCA;
664 }
665
666 static void get_atomic_caps(struct mlx5_ib_dev *dev,
667 u8 atomic_size_qp,
668 struct ib_device_attr *props)
669 {
670 u8 tmp;
671 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
672 u8 atomic_req_8B_endianness_mode =
673 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
674
675
676
677
678 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
679 if (((atomic_operations & tmp) == tmp) &&
680 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
681 (atomic_req_8B_endianness_mode)) {
682 props->atomic_cap = IB_ATOMIC_HCA;
683 } else {
684 props->atomic_cap = IB_ATOMIC_NONE;
685 }
686 }
687
688 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
689 struct ib_device_attr *props)
690 {
691 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
692
693 get_atomic_caps(dev, atomic_size_qp, props);
694 }
695
696 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
697 struct ib_device_attr *props)
698 {
699 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
700
701 get_atomic_caps(dev, atomic_size_qp, props);
702 }
703
704 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
705 {
706 struct ib_device_attr props = {};
707
708 get_atomic_caps_dc(dev, &props);
709 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
710 }
711 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
712 __be64 *sys_image_guid)
713 {
714 struct mlx5_ib_dev *dev = to_mdev(ibdev);
715 struct mlx5_core_dev *mdev = dev->mdev;
716 u64 tmp;
717 int err;
718
719 switch (mlx5_get_vport_access_method(ibdev)) {
720 case MLX5_VPORT_ACCESS_METHOD_MAD:
721 return mlx5_query_mad_ifc_system_image_guid(ibdev,
722 sys_image_guid);
723
724 case MLX5_VPORT_ACCESS_METHOD_HCA:
725 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
726 break;
727
728 case MLX5_VPORT_ACCESS_METHOD_NIC:
729 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
730 break;
731
732 default:
733 return -EINVAL;
734 }
735
736 if (!err)
737 *sys_image_guid = cpu_to_be64(tmp);
738
739 return err;
740
741 }
742
743 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
744 u16 *max_pkeys)
745 {
746 struct mlx5_ib_dev *dev = to_mdev(ibdev);
747 struct mlx5_core_dev *mdev = dev->mdev;
748
749 switch (mlx5_get_vport_access_method(ibdev)) {
750 case MLX5_VPORT_ACCESS_METHOD_MAD:
751 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
752
753 case MLX5_VPORT_ACCESS_METHOD_HCA:
754 case MLX5_VPORT_ACCESS_METHOD_NIC:
755 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
756 pkey_table_size));
757 return 0;
758
759 default:
760 return -EINVAL;
761 }
762 }
763
764 static int mlx5_query_vendor_id(struct ib_device *ibdev,
765 u32 *vendor_id)
766 {
767 struct mlx5_ib_dev *dev = to_mdev(ibdev);
768
769 switch (mlx5_get_vport_access_method(ibdev)) {
770 case MLX5_VPORT_ACCESS_METHOD_MAD:
771 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
772
773 case MLX5_VPORT_ACCESS_METHOD_HCA:
774 case MLX5_VPORT_ACCESS_METHOD_NIC:
775 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
776
777 default:
778 return -EINVAL;
779 }
780 }
781
782 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
783 __be64 *node_guid)
784 {
785 u64 tmp;
786 int err;
787
788 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
789 case MLX5_VPORT_ACCESS_METHOD_MAD:
790 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
791
792 case MLX5_VPORT_ACCESS_METHOD_HCA:
793 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
794 break;
795
796 case MLX5_VPORT_ACCESS_METHOD_NIC:
797 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
798 break;
799
800 default:
801 return -EINVAL;
802 }
803
804 if (!err)
805 *node_guid = cpu_to_be64(tmp);
806
807 return err;
808 }
809
810 struct mlx5_reg_node_desc {
811 u8 desc[IB_DEVICE_NODE_DESC_MAX];
812 };
813
814 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
815 {
816 struct mlx5_reg_node_desc in;
817
818 if (mlx5_use_mad_ifc(dev))
819 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
820
821 memset(&in, 0, sizeof(in));
822
823 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
824 sizeof(struct mlx5_reg_node_desc),
825 MLX5_REG_NODE_DESC, 0, 0);
826 }
827
828 static int mlx5_ib_query_device(struct ib_device *ibdev,
829 struct ib_device_attr *props,
830 struct ib_udata *uhw)
831 {
832 size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
833 struct mlx5_ib_dev *dev = to_mdev(ibdev);
834 struct mlx5_core_dev *mdev = dev->mdev;
835 int err = -ENOMEM;
836 int max_sq_desc;
837 int max_rq_sg;
838 int max_sq_sg;
839 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
840 bool raw_support = !mlx5_core_mp_enabled(mdev);
841 struct mlx5_ib_query_device_resp resp = {};
842 size_t resp_len;
843 u64 max_tso;
844
845 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
846 if (uhw_outlen && uhw_outlen < resp_len)
847 return -EINVAL;
848 else
849 resp.response_length = resp_len;
850
851 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
852 return -EINVAL;
853
854 memset(props, 0, sizeof(*props));
855 err = mlx5_query_system_image_guid(ibdev,
856 &props->sys_image_guid);
857 if (err)
858 return err;
859
860 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
861 if (err)
862 return err;
863
864 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
865 if (err)
866 return err;
867
868 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
869 (fw_rev_min(dev->mdev) << 16) |
870 fw_rev_sub(dev->mdev);
871 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
872 IB_DEVICE_PORT_ACTIVE_EVENT |
873 IB_DEVICE_SYS_IMAGE_GUID |
874 IB_DEVICE_RC_RNR_NAK_GEN;
875
876 if (MLX5_CAP_GEN(mdev, pkv))
877 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
878 if (MLX5_CAP_GEN(mdev, qkv))
879 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
880 if (MLX5_CAP_GEN(mdev, apm))
881 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
882 if (MLX5_CAP_GEN(mdev, xrc))
883 props->device_cap_flags |= IB_DEVICE_XRC;
884 if (MLX5_CAP_GEN(mdev, imaicl)) {
885 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
886 IB_DEVICE_MEM_WINDOW_TYPE_2B;
887 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
888
889 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
890 }
891 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
892 if (MLX5_CAP_GEN(mdev, sho)) {
893 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
894
895 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
896 IB_PROT_T10DIF_TYPE_2 |
897 IB_PROT_T10DIF_TYPE_3;
898 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
899 IB_GUARD_T10DIF_CSUM;
900 }
901 if (MLX5_CAP_GEN(mdev, block_lb_mc))
902 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
903
904 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
905 if (MLX5_CAP_ETH(mdev, csum_cap)) {
906
907 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
908 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
909 }
910
911 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
912 props->raw_packet_caps |=
913 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
914
915 if (field_avail(typeof(resp), tso_caps, uhw_outlen)) {
916 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
917 if (max_tso) {
918 resp.tso_caps.max_tso = 1 << max_tso;
919 resp.tso_caps.supported_qpts |=
920 1 << IB_QPT_RAW_PACKET;
921 resp.response_length += sizeof(resp.tso_caps);
922 }
923 }
924
925 if (field_avail(typeof(resp), rss_caps, uhw_outlen)) {
926 resp.rss_caps.rx_hash_function =
927 MLX5_RX_HASH_FUNC_TOEPLITZ;
928 resp.rss_caps.rx_hash_fields_mask =
929 MLX5_RX_HASH_SRC_IPV4 |
930 MLX5_RX_HASH_DST_IPV4 |
931 MLX5_RX_HASH_SRC_IPV6 |
932 MLX5_RX_HASH_DST_IPV6 |
933 MLX5_RX_HASH_SRC_PORT_TCP |
934 MLX5_RX_HASH_DST_PORT_TCP |
935 MLX5_RX_HASH_SRC_PORT_UDP |
936 MLX5_RX_HASH_DST_PORT_UDP |
937 MLX5_RX_HASH_INNER;
938 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
939 MLX5_ACCEL_IPSEC_CAP_DEVICE)
940 resp.rss_caps.rx_hash_fields_mask |=
941 MLX5_RX_HASH_IPSEC_SPI;
942 resp.response_length += sizeof(resp.rss_caps);
943 }
944 } else {
945 if (field_avail(typeof(resp), tso_caps, uhw_outlen))
946 resp.response_length += sizeof(resp.tso_caps);
947 if (field_avail(typeof(resp), rss_caps, uhw_outlen))
948 resp.response_length += sizeof(resp.rss_caps);
949 }
950
951 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
952 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
953 props->device_cap_flags |= IB_DEVICE_UD_TSO;
954 }
955
956 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
957 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
958 raw_support)
959 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
960
961 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
962 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
963 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
964
965 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
966 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
967 raw_support) {
968
969 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
970 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
971 }
972
973 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
974 props->max_dm_size =
975 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
976 }
977
978 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
979 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
980
981 if (MLX5_CAP_GEN(mdev, end_pad))
982 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
983
984 props->vendor_part_id = mdev->pdev->device;
985 props->hw_ver = mdev->pdev->revision;
986
987 props->max_mr_size = ~0ull;
988 props->page_size_cap = ~(min_page_size - 1);
989 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
990 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
991 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
992 sizeof(struct mlx5_wqe_data_seg);
993 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
994 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
995 sizeof(struct mlx5_wqe_raddr_seg)) /
996 sizeof(struct mlx5_wqe_data_seg);
997 props->max_send_sge = max_sq_sg;
998 props->max_recv_sge = max_rq_sg;
999 props->max_sge_rd = MLX5_MAX_SGE_RD;
1000 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
1001 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
1002 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1003 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
1004 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
1005 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
1006 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
1007 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
1008 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
1009 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
1010 props->max_srq_sge = max_rq_sg - 1;
1011 props->max_fast_reg_page_list_len =
1012 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
1013 props->max_pi_fast_reg_page_list_len =
1014 props->max_fast_reg_page_list_len / 2;
1015 get_atomic_caps_qp(dev, props);
1016 props->masked_atomic_cap = IB_ATOMIC_NONE;
1017 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1018 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
1019 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1020 props->max_mcast_grp;
1021 props->max_map_per_fmr = INT_MAX;
1022 props->max_ah = INT_MAX;
1023 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1024 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
1025
1026 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1027 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
1028 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1029 props->odp_caps = dev->odp_caps;
1030 }
1031
1032 if (MLX5_CAP_GEN(mdev, cd))
1033 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1034
1035 if (!mlx5_core_is_pf(mdev))
1036 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1037
1038 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1039 IB_LINK_LAYER_ETHERNET && raw_support) {
1040 props->rss_caps.max_rwq_indirection_tables =
1041 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1042 props->rss_caps.max_rwq_indirection_table_size =
1043 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1044 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1045 props->max_wq_type_rq =
1046 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1047 }
1048
1049 if (MLX5_CAP_GEN(mdev, tag_matching)) {
1050 props->tm_caps.max_num_tags =
1051 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1052 props->tm_caps.max_ops =
1053 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1054 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1055 }
1056
1057 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1058 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1059 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1060 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1061 }
1062
1063 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1064 props->cq_caps.max_cq_moderation_count =
1065 MLX5_MAX_CQ_COUNT;
1066 props->cq_caps.max_cq_moderation_period =
1067 MLX5_MAX_CQ_PERIOD;
1068 }
1069
1070 if (field_avail(typeof(resp), cqe_comp_caps, uhw_outlen)) {
1071 resp.response_length += sizeof(resp.cqe_comp_caps);
1072
1073 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1074 resp.cqe_comp_caps.max_num =
1075 MLX5_CAP_GEN(dev->mdev,
1076 cqe_compression_max_num);
1077
1078 resp.cqe_comp_caps.supported_format =
1079 MLX5_IB_CQE_RES_FORMAT_HASH |
1080 MLX5_IB_CQE_RES_FORMAT_CSUM;
1081
1082 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1083 resp.cqe_comp_caps.supported_format |=
1084 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1085 }
1086 }
1087
1088 if (field_avail(typeof(resp), packet_pacing_caps, uhw_outlen) &&
1089 raw_support) {
1090 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1091 MLX5_CAP_GEN(mdev, qos)) {
1092 resp.packet_pacing_caps.qp_rate_limit_max =
1093 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1094 resp.packet_pacing_caps.qp_rate_limit_min =
1095 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1096 resp.packet_pacing_caps.supported_qpts |=
1097 1 << IB_QPT_RAW_PACKET;
1098 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1099 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1100 resp.packet_pacing_caps.cap_flags |=
1101 MLX5_IB_PP_SUPPORT_BURST;
1102 }
1103 resp.response_length += sizeof(resp.packet_pacing_caps);
1104 }
1105
1106 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1107 uhw_outlen)) {
1108 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1109 resp.mlx5_ib_support_multi_pkt_send_wqes =
1110 MLX5_IB_ALLOW_MPW;
1111
1112 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1113 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1114 MLX5_IB_SUPPORT_EMPW;
1115
1116 resp.response_length +=
1117 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1118 }
1119
1120 if (field_avail(typeof(resp), flags, uhw_outlen)) {
1121 resp.response_length += sizeof(resp.flags);
1122
1123 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1124 resp.flags |=
1125 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1126
1127 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1128 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1129 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1130 resp.flags |=
1131 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1132
1133 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1134 }
1135
1136 if (field_avail(typeof(resp), sw_parsing_caps, uhw_outlen)) {
1137 resp.response_length += sizeof(resp.sw_parsing_caps);
1138 if (MLX5_CAP_ETH(mdev, swp)) {
1139 resp.sw_parsing_caps.sw_parsing_offloads |=
1140 MLX5_IB_SW_PARSING;
1141
1142 if (MLX5_CAP_ETH(mdev, swp_csum))
1143 resp.sw_parsing_caps.sw_parsing_offloads |=
1144 MLX5_IB_SW_PARSING_CSUM;
1145
1146 if (MLX5_CAP_ETH(mdev, swp_lso))
1147 resp.sw_parsing_caps.sw_parsing_offloads |=
1148 MLX5_IB_SW_PARSING_LSO;
1149
1150 if (resp.sw_parsing_caps.sw_parsing_offloads)
1151 resp.sw_parsing_caps.supported_qpts =
1152 BIT(IB_QPT_RAW_PACKET);
1153 }
1154 }
1155
1156 if (field_avail(typeof(resp), striding_rq_caps, uhw_outlen) &&
1157 raw_support) {
1158 resp.response_length += sizeof(resp.striding_rq_caps);
1159 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1160 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1161 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1162 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1163 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1164 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1165 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1166 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1167 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1168 resp.striding_rq_caps.supported_qpts =
1169 BIT(IB_QPT_RAW_PACKET);
1170 }
1171 }
1172
1173 if (field_avail(typeof(resp), tunnel_offloads_caps, uhw_outlen)) {
1174 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1175 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1176 resp.tunnel_offloads_caps |=
1177 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1178 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1179 resp.tunnel_offloads_caps |=
1180 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1181 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1182 resp.tunnel_offloads_caps |=
1183 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1184 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1185 resp.tunnel_offloads_caps |=
1186 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1187 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1188 resp.tunnel_offloads_caps |=
1189 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1190 }
1191
1192 if (uhw_outlen) {
1193 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1194
1195 if (err)
1196 return err;
1197 }
1198
1199 return 0;
1200 }
1201
1202 enum mlx5_ib_width {
1203 MLX5_IB_WIDTH_1X = 1 << 0,
1204 MLX5_IB_WIDTH_2X = 1 << 1,
1205 MLX5_IB_WIDTH_4X = 1 << 2,
1206 MLX5_IB_WIDTH_8X = 1 << 3,
1207 MLX5_IB_WIDTH_12X = 1 << 4
1208 };
1209
1210 static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1211 u8 *ib_width)
1212 {
1213 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1214
1215 if (active_width & MLX5_IB_WIDTH_1X)
1216 *ib_width = IB_WIDTH_1X;
1217 else if (active_width & MLX5_IB_WIDTH_2X)
1218 *ib_width = IB_WIDTH_2X;
1219 else if (active_width & MLX5_IB_WIDTH_4X)
1220 *ib_width = IB_WIDTH_4X;
1221 else if (active_width & MLX5_IB_WIDTH_8X)
1222 *ib_width = IB_WIDTH_8X;
1223 else if (active_width & MLX5_IB_WIDTH_12X)
1224 *ib_width = IB_WIDTH_12X;
1225 else {
1226 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1227 (int)active_width);
1228 *ib_width = IB_WIDTH_4X;
1229 }
1230
1231 return;
1232 }
1233
1234 static int mlx5_mtu_to_ib_mtu(int mtu)
1235 {
1236 switch (mtu) {
1237 case 256: return 1;
1238 case 512: return 2;
1239 case 1024: return 3;
1240 case 2048: return 4;
1241 case 4096: return 5;
1242 default:
1243 pr_warn("invalid mtu\n");
1244 return -1;
1245 }
1246 }
1247
1248 enum ib_max_vl_num {
1249 __IB_MAX_VL_0 = 1,
1250 __IB_MAX_VL_0_1 = 2,
1251 __IB_MAX_VL_0_3 = 3,
1252 __IB_MAX_VL_0_7 = 4,
1253 __IB_MAX_VL_0_14 = 5,
1254 };
1255
1256 enum mlx5_vl_hw_cap {
1257 MLX5_VL_HW_0 = 1,
1258 MLX5_VL_HW_0_1 = 2,
1259 MLX5_VL_HW_0_2 = 3,
1260 MLX5_VL_HW_0_3 = 4,
1261 MLX5_VL_HW_0_4 = 5,
1262 MLX5_VL_HW_0_5 = 6,
1263 MLX5_VL_HW_0_6 = 7,
1264 MLX5_VL_HW_0_7 = 8,
1265 MLX5_VL_HW_0_14 = 15
1266 };
1267
1268 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1269 u8 *max_vl_num)
1270 {
1271 switch (vl_hw_cap) {
1272 case MLX5_VL_HW_0:
1273 *max_vl_num = __IB_MAX_VL_0;
1274 break;
1275 case MLX5_VL_HW_0_1:
1276 *max_vl_num = __IB_MAX_VL_0_1;
1277 break;
1278 case MLX5_VL_HW_0_3:
1279 *max_vl_num = __IB_MAX_VL_0_3;
1280 break;
1281 case MLX5_VL_HW_0_7:
1282 *max_vl_num = __IB_MAX_VL_0_7;
1283 break;
1284 case MLX5_VL_HW_0_14:
1285 *max_vl_num = __IB_MAX_VL_0_14;
1286 break;
1287
1288 default:
1289 return -EINVAL;
1290 }
1291
1292 return 0;
1293 }
1294
1295 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1296 struct ib_port_attr *props)
1297 {
1298 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1299 struct mlx5_core_dev *mdev = dev->mdev;
1300 struct mlx5_hca_vport_context *rep;
1301 u16 max_mtu;
1302 u16 oper_mtu;
1303 int err;
1304 u8 ib_link_width_oper;
1305 u8 vl_hw_cap;
1306
1307 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1308 if (!rep) {
1309 err = -ENOMEM;
1310 goto out;
1311 }
1312
1313
1314
1315 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1316 if (err)
1317 goto out;
1318
1319 props->lid = rep->lid;
1320 props->lmc = rep->lmc;
1321 props->sm_lid = rep->sm_lid;
1322 props->sm_sl = rep->sm_sl;
1323 props->state = rep->vport_state;
1324 props->phys_state = rep->port_physical_state;
1325 props->port_cap_flags = rep->cap_mask1;
1326 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1327 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1328 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1329 props->bad_pkey_cntr = rep->pkey_violation_counter;
1330 props->qkey_viol_cntr = rep->qkey_violation_counter;
1331 props->subnet_timeout = rep->subnet_timeout;
1332 props->init_type_reply = rep->init_type_reply;
1333
1334 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1335 props->port_cap_flags2 = rep->cap_mask2;
1336
1337 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1338 if (err)
1339 goto out;
1340
1341 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1342
1343 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1344 if (err)
1345 goto out;
1346
1347 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1348
1349 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1350
1351 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1352
1353 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1354
1355 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1356 if (err)
1357 goto out;
1358
1359 err = translate_max_vl_num(ibdev, vl_hw_cap,
1360 &props->max_vl_num);
1361 out:
1362 kfree(rep);
1363 return err;
1364 }
1365
1366 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1367 struct ib_port_attr *props)
1368 {
1369 unsigned int count;
1370 int ret;
1371
1372 switch (mlx5_get_vport_access_method(ibdev)) {
1373 case MLX5_VPORT_ACCESS_METHOD_MAD:
1374 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1375 break;
1376
1377 case MLX5_VPORT_ACCESS_METHOD_HCA:
1378 ret = mlx5_query_hca_port(ibdev, port, props);
1379 break;
1380
1381 case MLX5_VPORT_ACCESS_METHOD_NIC:
1382 ret = mlx5_query_port_roce(ibdev, port, props);
1383 break;
1384
1385 default:
1386 ret = -EINVAL;
1387 }
1388
1389 if (!ret && props) {
1390 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1391 struct mlx5_core_dev *mdev;
1392 bool put_mdev = true;
1393
1394 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1395 if (!mdev) {
1396
1397
1398
1399 mdev = dev->mdev;
1400 port = 1;
1401 put_mdev = false;
1402 }
1403 count = mlx5_core_reserved_gids_count(mdev);
1404 if (put_mdev)
1405 mlx5_ib_put_native_port_mdev(dev, port);
1406 props->gid_tbl_len -= count;
1407 }
1408 return ret;
1409 }
1410
1411 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1412 struct ib_port_attr *props)
1413 {
1414 int ret;
1415
1416
1417
1418
1419 ret = mlx5_query_port_roce(ibdev, port, props);
1420 if (ret || !props)
1421 return ret;
1422
1423
1424 props->gid_tbl_len = 0;
1425
1426 return ret;
1427 }
1428
1429 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1430 union ib_gid *gid)
1431 {
1432 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1433 struct mlx5_core_dev *mdev = dev->mdev;
1434
1435 switch (mlx5_get_vport_access_method(ibdev)) {
1436 case MLX5_VPORT_ACCESS_METHOD_MAD:
1437 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1438
1439 case MLX5_VPORT_ACCESS_METHOD_HCA:
1440 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1441
1442 default:
1443 return -EINVAL;
1444 }
1445
1446 }
1447
1448 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1449 u16 index, u16 *pkey)
1450 {
1451 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1452 struct mlx5_core_dev *mdev;
1453 bool put_mdev = true;
1454 u8 mdev_port_num;
1455 int err;
1456
1457 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1458 if (!mdev) {
1459
1460
1461
1462 put_mdev = false;
1463 mdev = dev->mdev;
1464 mdev_port_num = 1;
1465 }
1466
1467 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1468 index, pkey);
1469 if (put_mdev)
1470 mlx5_ib_put_native_port_mdev(dev, port);
1471
1472 return err;
1473 }
1474
1475 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1476 u16 *pkey)
1477 {
1478 switch (mlx5_get_vport_access_method(ibdev)) {
1479 case MLX5_VPORT_ACCESS_METHOD_MAD:
1480 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1481
1482 case MLX5_VPORT_ACCESS_METHOD_HCA:
1483 case MLX5_VPORT_ACCESS_METHOD_NIC:
1484 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1485 default:
1486 return -EINVAL;
1487 }
1488 }
1489
1490 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1491 struct ib_device_modify *props)
1492 {
1493 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1494 struct mlx5_reg_node_desc in;
1495 struct mlx5_reg_node_desc out;
1496 int err;
1497
1498 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1499 return -EOPNOTSUPP;
1500
1501 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1502 return 0;
1503
1504
1505
1506
1507
1508 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1509 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1510 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1511 if (err)
1512 return err;
1513
1514 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1515
1516 return err;
1517 }
1518
1519 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1520 u32 value)
1521 {
1522 struct mlx5_hca_vport_context ctx = {};
1523 struct mlx5_core_dev *mdev;
1524 u8 mdev_port_num;
1525 int err;
1526
1527 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1528 if (!mdev)
1529 return -ENODEV;
1530
1531 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1532 if (err)
1533 goto out;
1534
1535 if (~ctx.cap_mask1_perm & mask) {
1536 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1537 mask, ctx.cap_mask1_perm);
1538 err = -EINVAL;
1539 goto out;
1540 }
1541
1542 ctx.cap_mask1 = value;
1543 ctx.cap_mask1_perm = mask;
1544 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1545 0, &ctx);
1546
1547 out:
1548 mlx5_ib_put_native_port_mdev(dev, port_num);
1549
1550 return err;
1551 }
1552
1553 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1554 struct ib_port_modify *props)
1555 {
1556 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1557 struct ib_port_attr attr;
1558 u32 tmp;
1559 int err;
1560 u32 change_mask;
1561 u32 value;
1562 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1563 IB_LINK_LAYER_INFINIBAND);
1564
1565
1566
1567
1568 if (!is_ib)
1569 return 0;
1570
1571 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1572 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1573 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1574 return set_port_caps_atomic(dev, port, change_mask, value);
1575 }
1576
1577 mutex_lock(&dev->cap_mask_mutex);
1578
1579 err = ib_query_port(ibdev, port, &attr);
1580 if (err)
1581 goto out;
1582
1583 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1584 ~props->clr_port_cap_mask;
1585
1586 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1587
1588 out:
1589 mutex_unlock(&dev->cap_mask_mutex);
1590 return err;
1591 }
1592
1593 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1594 {
1595 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1596 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1597 }
1598
1599 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1600 {
1601
1602 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1603 return MLX5_MIN_DYN_BFREGS;
1604
1605 return MLX5_MAX_DYN_BFREGS;
1606 }
1607
1608 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1609 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1610 struct mlx5_bfreg_info *bfregi)
1611 {
1612 int uars_per_sys_page;
1613 int bfregs_per_sys_page;
1614 int ref_bfregs = req->total_num_bfregs;
1615
1616 if (req->total_num_bfregs == 0)
1617 return -EINVAL;
1618
1619 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1620 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1621
1622 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1623 return -ENOMEM;
1624
1625 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1626 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1627
1628 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1629 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1630 return -EINVAL;
1631
1632 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1633 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1634 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1635 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1636
1637 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1638 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1639 lib_uar_4k ? "yes" : "no", ref_bfregs,
1640 req->total_num_bfregs, bfregi->total_num_bfregs,
1641 bfregi->num_sys_pages);
1642
1643 return 0;
1644 }
1645
1646 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1647 {
1648 struct mlx5_bfreg_info *bfregi;
1649 int err;
1650 int i;
1651
1652 bfregi = &context->bfregi;
1653 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1654 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1655 if (err)
1656 goto error;
1657
1658 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1659 }
1660
1661 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1662 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1663
1664 return 0;
1665
1666 error:
1667 for (--i; i >= 0; i--)
1668 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1669 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1670
1671 return err;
1672 }
1673
1674 static void deallocate_uars(struct mlx5_ib_dev *dev,
1675 struct mlx5_ib_ucontext *context)
1676 {
1677 struct mlx5_bfreg_info *bfregi;
1678 int i;
1679
1680 bfregi = &context->bfregi;
1681 for (i = 0; i < bfregi->num_sys_pages; i++)
1682 if (i < bfregi->num_static_sys_pages ||
1683 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1684 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1685 }
1686
1687 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1688 {
1689 int err = 0;
1690
1691 mutex_lock(&dev->lb.mutex);
1692 if (td)
1693 dev->lb.user_td++;
1694 if (qp)
1695 dev->lb.qps++;
1696
1697 if (dev->lb.user_td == 2 ||
1698 dev->lb.qps == 1) {
1699 if (!dev->lb.enabled) {
1700 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1701 dev->lb.enabled = true;
1702 }
1703 }
1704
1705 mutex_unlock(&dev->lb.mutex);
1706
1707 return err;
1708 }
1709
1710 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1711 {
1712 mutex_lock(&dev->lb.mutex);
1713 if (td)
1714 dev->lb.user_td--;
1715 if (qp)
1716 dev->lb.qps--;
1717
1718 if (dev->lb.user_td == 1 &&
1719 dev->lb.qps == 0) {
1720 if (dev->lb.enabled) {
1721 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1722 dev->lb.enabled = false;
1723 }
1724 }
1725
1726 mutex_unlock(&dev->lb.mutex);
1727 }
1728
1729 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1730 u16 uid)
1731 {
1732 int err;
1733
1734 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1735 return 0;
1736
1737 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1738 if (err)
1739 return err;
1740
1741 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1742 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1743 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1744 return err;
1745
1746 return mlx5_ib_enable_lb(dev, true, false);
1747 }
1748
1749 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1750 u16 uid)
1751 {
1752 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1753 return;
1754
1755 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1756
1757 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1758 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1759 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1760 return;
1761
1762 mlx5_ib_disable_lb(dev, true, false);
1763 }
1764
1765 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1766 struct ib_udata *udata)
1767 {
1768 struct ib_device *ibdev = uctx->device;
1769 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1770 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1771 struct mlx5_ib_alloc_ucontext_resp resp = {};
1772 struct mlx5_core_dev *mdev = dev->mdev;
1773 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1774 struct mlx5_bfreg_info *bfregi;
1775 int ver;
1776 int err;
1777 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1778 max_cqe_version);
1779 u32 dump_fill_mkey;
1780 bool lib_uar_4k;
1781
1782 if (!dev->ib_active)
1783 return -EAGAIN;
1784
1785 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1786 ver = 0;
1787 else if (udata->inlen >= min_req_v2)
1788 ver = 2;
1789 else
1790 return -EINVAL;
1791
1792 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1793 if (err)
1794 return err;
1795
1796 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1797 return -EOPNOTSUPP;
1798
1799 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1800 return -EOPNOTSUPP;
1801
1802 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1803 MLX5_NON_FP_BFREGS_PER_UAR);
1804 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1805 return -EINVAL;
1806
1807 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1808 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1809 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1810 resp.cache_line_size = cache_line_size();
1811 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1812 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1813 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1814 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1815 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1816 resp.cqe_version = min_t(__u8,
1817 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1818 req.max_cqe_version);
1819 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1820 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1821 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1822 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1823 resp.response_length = min(offsetof(typeof(resp), response_length) +
1824 sizeof(resp.response_length), udata->outlen);
1825
1826 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1827 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1828 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1829 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1830 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1831 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1832 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1833 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1834 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1835
1836 }
1837
1838 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1839 bfregi = &context->bfregi;
1840
1841
1842 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1843 if (err)
1844 goto out_ctx;
1845
1846 mutex_init(&bfregi->lock);
1847 bfregi->lib_uar_4k = lib_uar_4k;
1848 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1849 GFP_KERNEL);
1850 if (!bfregi->count) {
1851 err = -ENOMEM;
1852 goto out_ctx;
1853 }
1854
1855 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1856 sizeof(*bfregi->sys_pages),
1857 GFP_KERNEL);
1858 if (!bfregi->sys_pages) {
1859 err = -ENOMEM;
1860 goto out_count;
1861 }
1862
1863 err = allocate_uars(dev, context);
1864 if (err)
1865 goto out_sys_pages;
1866
1867 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1868 err = mlx5_ib_devx_create(dev, true);
1869 if (err < 0)
1870 goto out_uars;
1871 context->devx_uid = err;
1872 }
1873
1874 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1875 context->devx_uid);
1876 if (err)
1877 goto out_devx;
1878
1879 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1880 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1881 if (err)
1882 goto out_mdev;
1883 }
1884
1885 INIT_LIST_HEAD(&context->db_page_list);
1886 mutex_init(&context->db_page_mutex);
1887
1888 resp.tot_bfregs = req.total_num_bfregs;
1889 resp.num_ports = dev->num_ports;
1890
1891 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1892 resp.response_length += sizeof(resp.cqe_version);
1893
1894 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1895 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1896 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1897 resp.response_length += sizeof(resp.cmds_supp_uhw);
1898 }
1899
1900 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1901 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1902 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1903 resp.eth_min_inline++;
1904 }
1905 resp.response_length += sizeof(resp.eth_min_inline);
1906 }
1907
1908 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1909 if (mdev->clock_info)
1910 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1911 resp.response_length += sizeof(resp.clock_info_versions);
1912 }
1913
1914
1915
1916
1917
1918
1919
1920 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1921 if (PAGE_SIZE <= 4096) {
1922 resp.comp_mask |=
1923 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1924 resp.hca_core_clock_offset =
1925 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1926 }
1927 resp.response_length += sizeof(resp.hca_core_clock_offset);
1928 }
1929
1930 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1931 resp.response_length += sizeof(resp.log_uar_size);
1932
1933 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1934 resp.response_length += sizeof(resp.num_uars_per_page);
1935
1936 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1937 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1938 resp.response_length += sizeof(resp.num_dyn_bfregs);
1939 }
1940
1941 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1942 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1943 resp.dump_fill_mkey = dump_fill_mkey;
1944 resp.comp_mask |=
1945 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1946 }
1947 resp.response_length += sizeof(resp.dump_fill_mkey);
1948 }
1949
1950 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1951 if (err)
1952 goto out_mdev;
1953
1954 bfregi->ver = ver;
1955 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1956 context->cqe_version = resp.cqe_version;
1957 context->lib_caps = req.lib_caps;
1958 print_lib_caps(dev, context->lib_caps);
1959
1960 if (dev->lag_active) {
1961 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
1962
1963 atomic_set(&context->tx_port_affinity,
1964 atomic_add_return(
1965 1, &dev->port[port].roce.tx_port_affinity));
1966 }
1967
1968 return 0;
1969
1970 out_mdev:
1971 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1972 out_devx:
1973 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1974 mlx5_ib_devx_destroy(dev, context->devx_uid);
1975
1976 out_uars:
1977 deallocate_uars(dev, context);
1978
1979 out_sys_pages:
1980 kfree(bfregi->sys_pages);
1981
1982 out_count:
1983 kfree(bfregi->count);
1984
1985 out_ctx:
1986 return err;
1987 }
1988
1989 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1990 {
1991 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1992 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1993 struct mlx5_bfreg_info *bfregi;
1994
1995 bfregi = &context->bfregi;
1996 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1997
1998 if (context->devx_uid)
1999 mlx5_ib_devx_destroy(dev, context->devx_uid);
2000
2001 deallocate_uars(dev, context);
2002 kfree(bfregi->sys_pages);
2003 kfree(bfregi->count);
2004 }
2005
2006 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2007 int uar_idx)
2008 {
2009 int fw_uars_per_page;
2010
2011 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2012
2013 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2014 }
2015
2016 static int get_command(unsigned long offset)
2017 {
2018 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2019 }
2020
2021 static int get_arg(unsigned long offset)
2022 {
2023 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2024 }
2025
2026 static int get_index(unsigned long offset)
2027 {
2028 return get_arg(offset);
2029 }
2030
2031
2032 static int get_extended_index(unsigned long offset)
2033 {
2034 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2035 }
2036
2037
2038 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2039 {
2040 }
2041
2042 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2043 {
2044 switch (cmd) {
2045 case MLX5_IB_MMAP_WC_PAGE:
2046 return "WC";
2047 case MLX5_IB_MMAP_REGULAR_PAGE:
2048 return "best effort WC";
2049 case MLX5_IB_MMAP_NC_PAGE:
2050 return "NC";
2051 case MLX5_IB_MMAP_DEVICE_MEM:
2052 return "Device Memory";
2053 default:
2054 return NULL;
2055 }
2056 }
2057
2058 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2059 struct vm_area_struct *vma,
2060 struct mlx5_ib_ucontext *context)
2061 {
2062 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2063 !(vma->vm_flags & VM_SHARED))
2064 return -EINVAL;
2065
2066 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2067 return -EOPNOTSUPP;
2068
2069 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2070 return -EPERM;
2071 vma->vm_flags &= ~VM_MAYWRITE;
2072
2073 if (!dev->mdev->clock_info)
2074 return -EOPNOTSUPP;
2075
2076 return vm_insert_page(vma, vma->vm_start,
2077 virt_to_page(dev->mdev->clock_info));
2078 }
2079
2080 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2081 struct vm_area_struct *vma,
2082 struct mlx5_ib_ucontext *context)
2083 {
2084 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2085 int err;
2086 unsigned long idx;
2087 phys_addr_t pfn;
2088 pgprot_t prot;
2089 u32 bfreg_dyn_idx = 0;
2090 u32 uar_index;
2091 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2092 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2093 bfregi->num_static_sys_pages;
2094
2095 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2096 return -EINVAL;
2097
2098 if (dyn_uar)
2099 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2100 else
2101 idx = get_index(vma->vm_pgoff);
2102
2103 if (idx >= max_valid_idx) {
2104 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2105 idx, max_valid_idx);
2106 return -EINVAL;
2107 }
2108
2109 switch (cmd) {
2110 case MLX5_IB_MMAP_WC_PAGE:
2111 case MLX5_IB_MMAP_ALLOC_WC:
2112
2113 #if defined(CONFIG_X86)
2114 if (!pat_enabled())
2115 return -EPERM;
2116 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2117 return -EPERM;
2118 #endif
2119
2120 case MLX5_IB_MMAP_REGULAR_PAGE:
2121
2122 prot = pgprot_writecombine(vma->vm_page_prot);
2123 break;
2124 case MLX5_IB_MMAP_NC_PAGE:
2125 prot = pgprot_noncached(vma->vm_page_prot);
2126 break;
2127 default:
2128 return -EINVAL;
2129 }
2130
2131 if (dyn_uar) {
2132 int uars_per_page;
2133
2134 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2135 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2136 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2137 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2138 bfreg_dyn_idx, bfregi->total_num_bfregs);
2139 return -EINVAL;
2140 }
2141
2142 mutex_lock(&bfregi->lock);
2143
2144
2145
2146 if (bfregi->count[bfreg_dyn_idx]) {
2147 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2148 mutex_unlock(&bfregi->lock);
2149 return -EINVAL;
2150 }
2151
2152 bfregi->count[bfreg_dyn_idx]++;
2153 mutex_unlock(&bfregi->lock);
2154
2155 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2156 if (err) {
2157 mlx5_ib_warn(dev, "UAR alloc failed\n");
2158 goto free_bfreg;
2159 }
2160 } else {
2161 uar_index = bfregi->sys_pages[idx];
2162 }
2163
2164 pfn = uar_index2pfn(dev, uar_index);
2165 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2166
2167 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2168 prot);
2169 if (err) {
2170 mlx5_ib_err(dev,
2171 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2172 err, mmap_cmd2str(cmd));
2173 goto err;
2174 }
2175
2176 if (dyn_uar)
2177 bfregi->sys_pages[idx] = uar_index;
2178 return 0;
2179
2180 err:
2181 if (!dyn_uar)
2182 return err;
2183
2184 mlx5_cmd_free_uar(dev->mdev, idx);
2185
2186 free_bfreg:
2187 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2188
2189 return err;
2190 }
2191
2192 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2193 {
2194 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2195 struct mlx5_ib_dev *dev = to_mdev(context->device);
2196 u16 page_idx = get_extended_index(vma->vm_pgoff);
2197 size_t map_size = vma->vm_end - vma->vm_start;
2198 u32 npages = map_size >> PAGE_SHIFT;
2199 phys_addr_t pfn;
2200
2201 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2202 page_idx + npages)
2203 return -EINVAL;
2204
2205 pfn = ((dev->mdev->bar_addr +
2206 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2207 PAGE_SHIFT) +
2208 page_idx;
2209 return rdma_user_mmap_io(context, vma, pfn, map_size,
2210 pgprot_writecombine(vma->vm_page_prot));
2211 }
2212
2213 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2214 {
2215 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2216 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2217 unsigned long command;
2218 phys_addr_t pfn;
2219
2220 command = get_command(vma->vm_pgoff);
2221 switch (command) {
2222 case MLX5_IB_MMAP_WC_PAGE:
2223 case MLX5_IB_MMAP_NC_PAGE:
2224 case MLX5_IB_MMAP_REGULAR_PAGE:
2225 case MLX5_IB_MMAP_ALLOC_WC:
2226 return uar_mmap(dev, command, vma, context);
2227
2228 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2229 return -ENOSYS;
2230
2231 case MLX5_IB_MMAP_CORE_CLOCK:
2232 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2233 return -EINVAL;
2234
2235 if (vma->vm_flags & VM_WRITE)
2236 return -EPERM;
2237 vma->vm_flags &= ~VM_MAYWRITE;
2238
2239
2240 if (PAGE_SIZE > 4096)
2241 return -EOPNOTSUPP;
2242
2243 pfn = (dev->mdev->iseg_base +
2244 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2245 PAGE_SHIFT;
2246 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2247 PAGE_SIZE,
2248 pgprot_noncached(vma->vm_page_prot));
2249 case MLX5_IB_MMAP_CLOCK_INFO:
2250 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2251
2252 case MLX5_IB_MMAP_DEVICE_MEM:
2253 return dm_mmap(ibcontext, vma);
2254
2255 default:
2256 return -EINVAL;
2257 }
2258
2259 return 0;
2260 }
2261
2262 static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2263 u32 type)
2264 {
2265 switch (type) {
2266 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2267 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2268 return -EOPNOTSUPP;
2269 break;
2270 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2271 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2272 if (!capable(CAP_SYS_RAWIO) ||
2273 !capable(CAP_NET_RAW))
2274 return -EPERM;
2275
2276 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2277 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2278 return -EOPNOTSUPP;
2279 break;
2280 }
2281
2282 return 0;
2283 }
2284
2285 static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2286 struct mlx5_ib_dm *dm,
2287 struct ib_dm_alloc_attr *attr,
2288 struct uverbs_attr_bundle *attrs)
2289 {
2290 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2291 u64 start_offset;
2292 u32 page_idx;
2293 int err;
2294
2295 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2296
2297 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2298 dm->size, attr->alignment);
2299 if (err)
2300 return err;
2301
2302 page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) -
2303 MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >>
2304 PAGE_SHIFT;
2305
2306 err = uverbs_copy_to(attrs,
2307 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2308 &page_idx, sizeof(page_idx));
2309 if (err)
2310 goto err_dealloc;
2311
2312 start_offset = dm->dev_addr & ~PAGE_MASK;
2313 err = uverbs_copy_to(attrs,
2314 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2315 &start_offset, sizeof(start_offset));
2316 if (err)
2317 goto err_dealloc;
2318
2319 bitmap_set(to_mucontext(ctx)->dm_pages, page_idx,
2320 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2321
2322 return 0;
2323
2324 err_dealloc:
2325 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2326
2327 return err;
2328 }
2329
2330 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2331 struct mlx5_ib_dm *dm,
2332 struct ib_dm_alloc_attr *attr,
2333 struct uverbs_attr_bundle *attrs,
2334 int type)
2335 {
2336 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev;
2337 u64 act_size;
2338 int err;
2339
2340
2341
2342
2343 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev));
2344 act_size = roundup_pow_of_two(act_size);
2345
2346 dm->size = act_size;
2347 err = mlx5_dm_sw_icm_alloc(dev, type, act_size,
2348 to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2349 &dm->icm_dm.obj_id);
2350 if (err)
2351 return err;
2352
2353 err = uverbs_copy_to(attrs,
2354 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2355 &dm->dev_addr, sizeof(dm->dev_addr));
2356 if (err)
2357 mlx5_dm_sw_icm_dealloc(dev, type, dm->size,
2358 to_mucontext(ctx)->devx_uid, dm->dev_addr,
2359 dm->icm_dm.obj_id);
2360
2361 return err;
2362 }
2363
2364 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2365 struct ib_ucontext *context,
2366 struct ib_dm_alloc_attr *attr,
2367 struct uverbs_attr_bundle *attrs)
2368 {
2369 struct mlx5_ib_dm *dm;
2370 enum mlx5_ib_uapi_dm_type type;
2371 int err;
2372
2373 err = uverbs_get_const_default(&type, attrs,
2374 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2375 MLX5_IB_UAPI_DM_TYPE_MEMIC);
2376 if (err)
2377 return ERR_PTR(err);
2378
2379 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2380 type, attr->length, attr->alignment);
2381
2382 err = check_dm_type_support(to_mdev(ibdev), type);
2383 if (err)
2384 return ERR_PTR(err);
2385
2386 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2387 if (!dm)
2388 return ERR_PTR(-ENOMEM);
2389
2390 dm->type = type;
2391
2392 switch (type) {
2393 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2394 err = handle_alloc_dm_memic(context, dm,
2395 attr,
2396 attrs);
2397 break;
2398 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2399 err = handle_alloc_dm_sw_icm(context, dm,
2400 attr, attrs,
2401 MLX5_SW_ICM_TYPE_STEERING);
2402 break;
2403 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2404 err = handle_alloc_dm_sw_icm(context, dm,
2405 attr, attrs,
2406 MLX5_SW_ICM_TYPE_HEADER_MODIFY);
2407 break;
2408 default:
2409 err = -EOPNOTSUPP;
2410 }
2411
2412 if (err)
2413 goto err_free;
2414
2415 return &dm->ibdm;
2416
2417 err_free:
2418 kfree(dm);
2419 return ERR_PTR(err);
2420 }
2421
2422 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
2423 {
2424 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2425 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
2426 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev;
2427 struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm;
2428 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2429 u32 page_idx;
2430 int ret;
2431
2432 switch (dm->type) {
2433 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2434 ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2435 if (ret)
2436 return ret;
2437
2438 page_idx = (dm->dev_addr - pci_resource_start(dev->pdev, 0) -
2439 MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr)) >>
2440 PAGE_SHIFT;
2441 bitmap_clear(ctx->dm_pages, page_idx,
2442 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2443 break;
2444 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2445 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING,
2446 dm->size, ctx->devx_uid, dm->dev_addr,
2447 dm->icm_dm.obj_id);
2448 if (ret)
2449 return ret;
2450 break;
2451 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2452 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY,
2453 dm->size, ctx->devx_uid, dm->dev_addr,
2454 dm->icm_dm.obj_id);
2455 if (ret)
2456 return ret;
2457 break;
2458 default:
2459 return -EOPNOTSUPP;
2460 }
2461
2462 kfree(dm);
2463
2464 return 0;
2465 }
2466
2467 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2468 {
2469 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2470 struct ib_device *ibdev = ibpd->device;
2471 struct mlx5_ib_alloc_pd_resp resp;
2472 int err;
2473 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2474 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2475 u16 uid = 0;
2476 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2477 udata, struct mlx5_ib_ucontext, ibucontext);
2478
2479 uid = context ? context->devx_uid : 0;
2480 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2481 MLX5_SET(alloc_pd_in, in, uid, uid);
2482 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2483 out, sizeof(out));
2484 if (err)
2485 return err;
2486
2487 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2488 pd->uid = uid;
2489 if (udata) {
2490 resp.pdn = pd->pdn;
2491 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2492 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2493 return -EFAULT;
2494 }
2495 }
2496
2497 return 0;
2498 }
2499
2500 static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2501 {
2502 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2503 struct mlx5_ib_pd *mpd = to_mpd(pd);
2504
2505 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2506 }
2507
2508 enum {
2509 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2510 MATCH_CRITERIA_ENABLE_MISC_BIT,
2511 MATCH_CRITERIA_ENABLE_INNER_BIT,
2512 MATCH_CRITERIA_ENABLE_MISC2_BIT
2513 };
2514
2515 #define HEADER_IS_ZERO(match_criteria, headers) \
2516 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2517 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
2518
2519 static u8 get_match_criteria_enable(u32 *match_criteria)
2520 {
2521 u8 match_criteria_enable;
2522
2523 match_criteria_enable =
2524 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2525 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2526 match_criteria_enable |=
2527 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2528 MATCH_CRITERIA_ENABLE_MISC_BIT;
2529 match_criteria_enable |=
2530 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2531 MATCH_CRITERIA_ENABLE_INNER_BIT;
2532 match_criteria_enable |=
2533 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2534 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2535
2536 return match_criteria_enable;
2537 }
2538
2539 static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2540 {
2541 u8 entry_mask;
2542 u8 entry_val;
2543 int err = 0;
2544
2545 if (!mask)
2546 goto out;
2547
2548 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2549 ip_protocol);
2550 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2551 ip_protocol);
2552 if (!entry_mask) {
2553 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2554 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2555 goto out;
2556 }
2557
2558 if (mask != entry_mask || val != entry_val)
2559 err = -EINVAL;
2560 out:
2561 return err;
2562 }
2563
2564 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2565 bool inner)
2566 {
2567 if (inner) {
2568 MLX5_SET(fte_match_set_misc,
2569 misc_c, inner_ipv6_flow_label, mask);
2570 MLX5_SET(fte_match_set_misc,
2571 misc_v, inner_ipv6_flow_label, val);
2572 } else {
2573 MLX5_SET(fte_match_set_misc,
2574 misc_c, outer_ipv6_flow_label, mask);
2575 MLX5_SET(fte_match_set_misc,
2576 misc_v, outer_ipv6_flow_label, val);
2577 }
2578 }
2579
2580 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2581 {
2582 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2583 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2584 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2585 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2586 }
2587
2588 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2589 {
2590 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2591 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2592 return -EOPNOTSUPP;
2593
2594 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2595 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2596 return -EOPNOTSUPP;
2597
2598 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2599 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2600 return -EOPNOTSUPP;
2601
2602 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2603 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2604 return -EOPNOTSUPP;
2605
2606 return 0;
2607 }
2608
2609 #define LAST_ETH_FIELD vlan_tag
2610 #define LAST_IB_FIELD sl
2611 #define LAST_IPV4_FIELD tos
2612 #define LAST_IPV6_FIELD traffic_class
2613 #define LAST_TCP_UDP_FIELD src_port
2614 #define LAST_TUNNEL_FIELD tunnel_id
2615 #define LAST_FLOW_TAG_FIELD tag_id
2616 #define LAST_DROP_FIELD size
2617 #define LAST_COUNTERS_FIELD counters
2618
2619
2620 #define FIELDS_NOT_SUPPORTED(filter, field)\
2621 memchr_inv((void *)&filter.field +\
2622 sizeof(filter.field), 0,\
2623 sizeof(filter) -\
2624 offsetof(typeof(filter), field) -\
2625 sizeof(filter.field))
2626
2627 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2628 bool is_egress,
2629 struct mlx5_flow_act *action)
2630 {
2631
2632 switch (maction->ib_action.type) {
2633 case IB_FLOW_ACTION_ESP:
2634 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2635 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2636 return -EINVAL;
2637
2638 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2639 action->action |= is_egress ?
2640 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2641 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2642 return 0;
2643 case IB_FLOW_ACTION_UNSPECIFIED:
2644 if (maction->flow_action_raw.sub_type ==
2645 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
2646 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2647 return -EINVAL;
2648 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2649 action->modify_hdr =
2650 maction->flow_action_raw.modify_hdr;
2651 return 0;
2652 }
2653 if (maction->flow_action_raw.sub_type ==
2654 MLX5_IB_FLOW_ACTION_DECAP) {
2655 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2656 return -EINVAL;
2657 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2658 return 0;
2659 }
2660 if (maction->flow_action_raw.sub_type ==
2661 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
2662 if (action->action &
2663 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2664 return -EINVAL;
2665 action->action |=
2666 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2667 action->pkt_reformat =
2668 maction->flow_action_raw.pkt_reformat;
2669 return 0;
2670 }
2671
2672 default:
2673 return -EOPNOTSUPP;
2674 }
2675 }
2676
2677 static int parse_flow_attr(struct mlx5_core_dev *mdev,
2678 struct mlx5_flow_spec *spec,
2679 const union ib_flow_spec *ib_spec,
2680 const struct ib_flow_attr *flow_attr,
2681 struct mlx5_flow_act *action, u32 prev_type)
2682 {
2683 struct mlx5_flow_context *flow_context = &spec->flow_context;
2684 u32 *match_c = spec->match_criteria;
2685 u32 *match_v = spec->match_value;
2686 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2687 misc_parameters);
2688 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2689 misc_parameters);
2690 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2691 misc_parameters_2);
2692 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2693 misc_parameters_2);
2694 void *headers_c;
2695 void *headers_v;
2696 int match_ipv;
2697 int ret;
2698
2699 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2700 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2701 inner_headers);
2702 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2703 inner_headers);
2704 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2705 ft_field_support.inner_ip_version);
2706 } else {
2707 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2708 outer_headers);
2709 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2710 outer_headers);
2711 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2712 ft_field_support.outer_ip_version);
2713 }
2714
2715 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2716 case IB_FLOW_SPEC_ETH:
2717 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2718 return -EOPNOTSUPP;
2719
2720 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2721 dmac_47_16),
2722 ib_spec->eth.mask.dst_mac);
2723 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2724 dmac_47_16),
2725 ib_spec->eth.val.dst_mac);
2726
2727 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2728 smac_47_16),
2729 ib_spec->eth.mask.src_mac);
2730 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2731 smac_47_16),
2732 ib_spec->eth.val.src_mac);
2733
2734 if (ib_spec->eth.mask.vlan_tag) {
2735 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2736 cvlan_tag, 1);
2737 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2738 cvlan_tag, 1);
2739
2740 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2741 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2742 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2743 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2744
2745 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2746 first_cfi,
2747 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2748 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2749 first_cfi,
2750 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2751
2752 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2753 first_prio,
2754 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2755 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2756 first_prio,
2757 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2758 }
2759 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2760 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2761 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2762 ethertype, ntohs(ib_spec->eth.val.ether_type));
2763 break;
2764 case IB_FLOW_SPEC_IPV4:
2765 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2766 return -EOPNOTSUPP;
2767
2768 if (match_ipv) {
2769 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2770 ip_version, 0xf);
2771 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2772 ip_version, MLX5_FS_IPV4_VERSION);
2773 } else {
2774 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2775 ethertype, 0xffff);
2776 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2777 ethertype, ETH_P_IP);
2778 }
2779
2780 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2781 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2782 &ib_spec->ipv4.mask.src_ip,
2783 sizeof(ib_spec->ipv4.mask.src_ip));
2784 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2785 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2786 &ib_spec->ipv4.val.src_ip,
2787 sizeof(ib_spec->ipv4.val.src_ip));
2788 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2789 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2790 &ib_spec->ipv4.mask.dst_ip,
2791 sizeof(ib_spec->ipv4.mask.dst_ip));
2792 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2793 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2794 &ib_spec->ipv4.val.dst_ip,
2795 sizeof(ib_spec->ipv4.val.dst_ip));
2796
2797 set_tos(headers_c, headers_v,
2798 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2799
2800 if (set_proto(headers_c, headers_v,
2801 ib_spec->ipv4.mask.proto,
2802 ib_spec->ipv4.val.proto))
2803 return -EINVAL;
2804 break;
2805 case IB_FLOW_SPEC_IPV6:
2806 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2807 return -EOPNOTSUPP;
2808
2809 if (match_ipv) {
2810 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2811 ip_version, 0xf);
2812 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2813 ip_version, MLX5_FS_IPV6_VERSION);
2814 } else {
2815 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2816 ethertype, 0xffff);
2817 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2818 ethertype, ETH_P_IPV6);
2819 }
2820
2821 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2822 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2823 &ib_spec->ipv6.mask.src_ip,
2824 sizeof(ib_spec->ipv6.mask.src_ip));
2825 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2826 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2827 &ib_spec->ipv6.val.src_ip,
2828 sizeof(ib_spec->ipv6.val.src_ip));
2829 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2830 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2831 &ib_spec->ipv6.mask.dst_ip,
2832 sizeof(ib_spec->ipv6.mask.dst_ip));
2833 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2834 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2835 &ib_spec->ipv6.val.dst_ip,
2836 sizeof(ib_spec->ipv6.val.dst_ip));
2837
2838 set_tos(headers_c, headers_v,
2839 ib_spec->ipv6.mask.traffic_class,
2840 ib_spec->ipv6.val.traffic_class);
2841
2842 if (set_proto(headers_c, headers_v,
2843 ib_spec->ipv6.mask.next_hdr,
2844 ib_spec->ipv6.val.next_hdr))
2845 return -EINVAL;
2846
2847 set_flow_label(misc_params_c, misc_params_v,
2848 ntohl(ib_spec->ipv6.mask.flow_label),
2849 ntohl(ib_spec->ipv6.val.flow_label),
2850 ib_spec->type & IB_FLOW_SPEC_INNER);
2851 break;
2852 case IB_FLOW_SPEC_ESP:
2853 if (ib_spec->esp.mask.seq)
2854 return -EOPNOTSUPP;
2855
2856 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2857 ntohl(ib_spec->esp.mask.spi));
2858 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2859 ntohl(ib_spec->esp.val.spi));
2860 break;
2861 case IB_FLOW_SPEC_TCP:
2862 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2863 LAST_TCP_UDP_FIELD))
2864 return -EOPNOTSUPP;
2865
2866 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2867 return -EINVAL;
2868
2869 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2870 ntohs(ib_spec->tcp_udp.mask.src_port));
2871 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2872 ntohs(ib_spec->tcp_udp.val.src_port));
2873
2874 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2875 ntohs(ib_spec->tcp_udp.mask.dst_port));
2876 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2877 ntohs(ib_spec->tcp_udp.val.dst_port));
2878 break;
2879 case IB_FLOW_SPEC_UDP:
2880 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2881 LAST_TCP_UDP_FIELD))
2882 return -EOPNOTSUPP;
2883
2884 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2885 return -EINVAL;
2886
2887 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2888 ntohs(ib_spec->tcp_udp.mask.src_port));
2889 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2890 ntohs(ib_spec->tcp_udp.val.src_port));
2891
2892 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2893 ntohs(ib_spec->tcp_udp.mask.dst_port));
2894 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2895 ntohs(ib_spec->tcp_udp.val.dst_port));
2896 break;
2897 case IB_FLOW_SPEC_GRE:
2898 if (ib_spec->gre.mask.c_ks_res0_ver)
2899 return -EOPNOTSUPP;
2900
2901 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2902 return -EINVAL;
2903
2904 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2905 0xff);
2906 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2907 IPPROTO_GRE);
2908
2909 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2910 ntohs(ib_spec->gre.mask.protocol));
2911 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2912 ntohs(ib_spec->gre.val.protocol));
2913
2914 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2915 gre_key.nvgre.hi),
2916 &ib_spec->gre.mask.key,
2917 sizeof(ib_spec->gre.mask.key));
2918 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2919 gre_key.nvgre.hi),
2920 &ib_spec->gre.val.key,
2921 sizeof(ib_spec->gre.val.key));
2922 break;
2923 case IB_FLOW_SPEC_MPLS:
2924 switch (prev_type) {
2925 case IB_FLOW_SPEC_UDP:
2926 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2927 ft_field_support.outer_first_mpls_over_udp),
2928 &ib_spec->mpls.mask.tag))
2929 return -EOPNOTSUPP;
2930
2931 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2932 outer_first_mpls_over_udp),
2933 &ib_spec->mpls.val.tag,
2934 sizeof(ib_spec->mpls.val.tag));
2935 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2936 outer_first_mpls_over_udp),
2937 &ib_spec->mpls.mask.tag,
2938 sizeof(ib_spec->mpls.mask.tag));
2939 break;
2940 case IB_FLOW_SPEC_GRE:
2941 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2942 ft_field_support.outer_first_mpls_over_gre),
2943 &ib_spec->mpls.mask.tag))
2944 return -EOPNOTSUPP;
2945
2946 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2947 outer_first_mpls_over_gre),
2948 &ib_spec->mpls.val.tag,
2949 sizeof(ib_spec->mpls.val.tag));
2950 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2951 outer_first_mpls_over_gre),
2952 &ib_spec->mpls.mask.tag,
2953 sizeof(ib_spec->mpls.mask.tag));
2954 break;
2955 default:
2956 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2957 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2958 ft_field_support.inner_first_mpls),
2959 &ib_spec->mpls.mask.tag))
2960 return -EOPNOTSUPP;
2961
2962 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2963 inner_first_mpls),
2964 &ib_spec->mpls.val.tag,
2965 sizeof(ib_spec->mpls.val.tag));
2966 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2967 inner_first_mpls),
2968 &ib_spec->mpls.mask.tag,
2969 sizeof(ib_spec->mpls.mask.tag));
2970 } else {
2971 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2972 ft_field_support.outer_first_mpls),
2973 &ib_spec->mpls.mask.tag))
2974 return -EOPNOTSUPP;
2975
2976 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2977 outer_first_mpls),
2978 &ib_spec->mpls.val.tag,
2979 sizeof(ib_spec->mpls.val.tag));
2980 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2981 outer_first_mpls),
2982 &ib_spec->mpls.mask.tag,
2983 sizeof(ib_spec->mpls.mask.tag));
2984 }
2985 }
2986 break;
2987 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2988 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2989 LAST_TUNNEL_FIELD))
2990 return -EOPNOTSUPP;
2991
2992 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2993 ntohl(ib_spec->tunnel.mask.tunnel_id));
2994 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2995 ntohl(ib_spec->tunnel.val.tunnel_id));
2996 break;
2997 case IB_FLOW_SPEC_ACTION_TAG:
2998 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2999 LAST_FLOW_TAG_FIELD))
3000 return -EOPNOTSUPP;
3001 if (ib_spec->flow_tag.tag_id >= BIT(24))
3002 return -EINVAL;
3003
3004 flow_context->flow_tag = ib_spec->flow_tag.tag_id;
3005 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
3006 break;
3007 case IB_FLOW_SPEC_ACTION_DROP:
3008 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
3009 LAST_DROP_FIELD))
3010 return -EOPNOTSUPP;
3011 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3012 break;
3013 case IB_FLOW_SPEC_ACTION_HANDLE:
3014 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3015 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
3016 if (ret)
3017 return ret;
3018 break;
3019 case IB_FLOW_SPEC_ACTION_COUNT:
3020 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3021 LAST_COUNTERS_FIELD))
3022 return -EOPNOTSUPP;
3023
3024
3025 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3026 return -EINVAL;
3027
3028 action->counters = ib_spec->flow_count.counters;
3029 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3030 break;
3031 default:
3032 return -EINVAL;
3033 }
3034
3035 return 0;
3036 }
3037
3038
3039
3040
3041
3042 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
3043 {
3044 union ib_flow_spec *flow_spec;
3045
3046 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
3047 ib_attr->num_of_specs < 1)
3048 return false;
3049
3050 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3051 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3052 struct ib_flow_spec_ipv4 *ipv4_spec;
3053
3054 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3055 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3056 return true;
3057
3058 return false;
3059 }
3060
3061 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3062 struct ib_flow_spec_eth *eth_spec;
3063
3064 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3065 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3066 is_multicast_ether_addr(eth_spec->val.dst_mac);
3067 }
3068
3069 return false;
3070 }
3071
3072 enum valid_spec {
3073 VALID_SPEC_INVALID,
3074 VALID_SPEC_VALID,
3075 VALID_SPEC_NA,
3076 };
3077
3078 static enum valid_spec
3079 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3080 const struct mlx5_flow_spec *spec,
3081 const struct mlx5_flow_act *flow_act,
3082 bool egress)
3083 {
3084 const u32 *match_c = spec->match_criteria;
3085 bool is_crypto =
3086 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3087 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3088 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3089 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3090
3091
3092
3093
3094
3095 if (!is_crypto)
3096 return VALID_SPEC_NA;
3097
3098 return is_crypto && is_ipsec &&
3099 (!egress || (!is_drop &&
3100 !(spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG))) ?
3101 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3102 }
3103
3104 static bool is_valid_spec(struct mlx5_core_dev *mdev,
3105 const struct mlx5_flow_spec *spec,
3106 const struct mlx5_flow_act *flow_act,
3107 bool egress)
3108 {
3109
3110 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3111 }
3112
3113 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3114 const struct ib_flow_attr *flow_attr,
3115 bool check_inner)
3116 {
3117 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
3118 int match_ipv = check_inner ?
3119 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3120 ft_field_support.inner_ip_version) :
3121 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3122 ft_field_support.outer_ip_version);
3123 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3124 bool ipv4_spec_valid, ipv6_spec_valid;
3125 unsigned int ip_spec_type = 0;
3126 bool has_ethertype = false;
3127 unsigned int spec_index;
3128 bool mask_valid = true;
3129 u16 eth_type = 0;
3130 bool type_valid;
3131
3132
3133 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3134 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
3135 ib_spec->eth.mask.ether_type) {
3136 mask_valid = (ib_spec->eth.mask.ether_type ==
3137 htons(0xffff));
3138 has_ethertype = true;
3139 eth_type = ntohs(ib_spec->eth.val.ether_type);
3140 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3141 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3142 ip_spec_type = ib_spec->type;
3143 }
3144 ib_spec = (void *)ib_spec + ib_spec->size;
3145 }
3146
3147 type_valid = (!has_ethertype) || (!ip_spec_type);
3148 if (!type_valid && mask_valid) {
3149 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3150 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3151 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3152 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
3153
3154 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3155 (((eth_type == ETH_P_MPLS_UC) ||
3156 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
3157 }
3158
3159 return type_valid;
3160 }
3161
3162 static bool is_valid_attr(struct mlx5_core_dev *mdev,
3163 const struct ib_flow_attr *flow_attr)
3164 {
3165 return is_valid_ethertype(mdev, flow_attr, false) &&
3166 is_valid_ethertype(mdev, flow_attr, true);
3167 }
3168
3169 static void put_flow_table(struct mlx5_ib_dev *dev,
3170 struct mlx5_ib_flow_prio *prio, bool ft_added)
3171 {
3172 prio->refcount -= !!ft_added;
3173 if (!prio->refcount) {
3174 mlx5_destroy_flow_table(prio->flow_table);
3175 prio->flow_table = NULL;
3176 }
3177 }
3178
3179 static void counters_clear_description(struct ib_counters *counters)
3180 {
3181 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3182
3183 mutex_lock(&mcounters->mcntrs_mutex);
3184 kfree(mcounters->counters_data);
3185 mcounters->counters_data = NULL;
3186 mcounters->cntrs_max_index = 0;
3187 mutex_unlock(&mcounters->mcntrs_mutex);
3188 }
3189
3190 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3191 {
3192 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3193 struct mlx5_ib_flow_handler,
3194 ibflow);
3195 struct mlx5_ib_flow_handler *iter, *tmp;
3196 struct mlx5_ib_dev *dev = handler->dev;
3197
3198 mutex_lock(&dev->flow_db->lock);
3199
3200 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
3201 mlx5_del_flow_rules(iter->rule);
3202 put_flow_table(dev, iter->prio, true);
3203 list_del(&iter->list);
3204 kfree(iter);
3205 }
3206
3207 mlx5_del_flow_rules(handler->rule);
3208 put_flow_table(dev, handler->prio, true);
3209 if (handler->ibcounters &&
3210 atomic_read(&handler->ibcounters->usecnt) == 1)
3211 counters_clear_description(handler->ibcounters);
3212
3213 mutex_unlock(&dev->flow_db->lock);
3214 if (handler->flow_matcher)
3215 atomic_dec(&handler->flow_matcher->usecnt);
3216 kfree(handler);
3217
3218 return 0;
3219 }
3220
3221 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3222 {
3223 priority *= 2;
3224 if (!dont_trap)
3225 priority++;
3226 return priority;
3227 }
3228
3229 enum flow_table_type {
3230 MLX5_IB_FT_RX,
3231 MLX5_IB_FT_TX
3232 };
3233
3234 #define MLX5_FS_MAX_TYPES 6
3235 #define MLX5_FS_MAX_ENTRIES BIT(16)
3236
3237 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3238 struct mlx5_ib_flow_prio *prio,
3239 int priority,
3240 int num_entries, int num_groups,
3241 u32 flags)
3242 {
3243 struct mlx5_flow_table *ft;
3244
3245 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3246 num_entries,
3247 num_groups,
3248 0, flags);
3249 if (IS_ERR(ft))
3250 return ERR_CAST(ft);
3251
3252 prio->flow_table = ft;
3253 prio->refcount = 0;
3254 return prio;
3255 }
3256
3257 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3258 struct ib_flow_attr *flow_attr,
3259 enum flow_table_type ft_type)
3260 {
3261 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3262 struct mlx5_flow_namespace *ns = NULL;
3263 struct mlx5_ib_flow_prio *prio;
3264 struct mlx5_flow_table *ft;
3265 int max_table_size;
3266 int num_entries;
3267 int num_groups;
3268 bool esw_encap;
3269 u32 flags = 0;
3270 int priority;
3271
3272 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3273 log_max_ft_size));
3274 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3275 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3276 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3277 enum mlx5_flow_namespace_type fn_type;
3278
3279 if (flow_is_multicast_only(flow_attr) &&
3280 !dont_trap)
3281 priority = MLX5_IB_FLOW_MCAST_PRIO;
3282 else
3283 priority = ib_prio_to_core_prio(flow_attr->priority,
3284 dont_trap);
3285 if (ft_type == MLX5_IB_FT_RX) {
3286 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3287 prio = &dev->flow_db->prios[priority];
3288 if (!dev->is_rep && !esw_encap &&
3289 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3290 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3291 if (!dev->is_rep && !esw_encap &&
3292 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3293 reformat_l3_tunnel_to_l2))
3294 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3295 } else {
3296 max_table_size =
3297 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3298 log_max_ft_size));
3299 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3300 prio = &dev->flow_db->egress_prios[priority];
3301 if (!dev->is_rep && !esw_encap &&
3302 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3303 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3304 }
3305 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
3306 num_entries = MLX5_FS_MAX_ENTRIES;
3307 num_groups = MLX5_FS_MAX_TYPES;
3308 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3309 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3310 ns = mlx5_get_flow_namespace(dev->mdev,
3311 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3312 build_leftovers_ft_param(&priority,
3313 &num_entries,
3314 &num_groups);
3315 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3316 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3317 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3318 allow_sniffer_and_nic_rx_shared_tir))
3319 return ERR_PTR(-ENOTSUPP);
3320
3321 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3322 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3323 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3324
3325 prio = &dev->flow_db->sniffer[ft_type];
3326 priority = 0;
3327 num_entries = 1;
3328 num_groups = 1;
3329 }
3330
3331 if (!ns)
3332 return ERR_PTR(-ENOTSUPP);
3333
3334 max_table_size = min_t(int, num_entries, max_table_size);
3335
3336 ft = prio->flow_table;
3337 if (!ft)
3338 return _get_prio(ns, prio, priority, max_table_size, num_groups,
3339 flags);
3340
3341 return prio;
3342 }
3343
3344 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3345 struct mlx5_flow_spec *spec,
3346 u32 underlay_qpn)
3347 {
3348 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3349 spec->match_criteria,
3350 misc_parameters);
3351 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3352 misc_parameters);
3353
3354 if (underlay_qpn &&
3355 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3356 ft_field_support.bth_dst_qp)) {
3357 MLX5_SET(fte_match_set_misc,
3358 misc_params_v, bth_dst_qp, underlay_qpn);
3359 MLX5_SET(fte_match_set_misc,
3360 misc_params_c, bth_dst_qp, 0xffffff);
3361 }
3362 }
3363
3364 static int read_flow_counters(struct ib_device *ibdev,
3365 struct mlx5_read_counters_attr *read_attr)
3366 {
3367 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3368 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3369
3370 return mlx5_fc_query(dev->mdev, fc,
3371 &read_attr->out[IB_COUNTER_PACKETS],
3372 &read_attr->out[IB_COUNTER_BYTES]);
3373 }
3374
3375
3376 #define FLOW_COUNTERS_NUM 2
3377 static int counters_set_description(struct ib_counters *counters,
3378 enum mlx5_ib_counters_type counters_type,
3379 struct mlx5_ib_flow_counters_desc *desc_data,
3380 u32 ncounters)
3381 {
3382 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3383 u32 cntrs_max_index = 0;
3384 int i;
3385
3386 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3387 return -EINVAL;
3388
3389
3390 mcounters->type = counters_type;
3391 mcounters->read_counters = read_flow_counters;
3392 mcounters->counters_num = FLOW_COUNTERS_NUM;
3393 mcounters->ncounters = ncounters;
3394
3395 for (i = 0; i < ncounters; i++) {
3396 if (desc_data[i].description > IB_COUNTER_BYTES)
3397 return -EINVAL;
3398
3399 if (cntrs_max_index <= desc_data[i].index)
3400 cntrs_max_index = desc_data[i].index + 1;
3401 }
3402
3403 mutex_lock(&mcounters->mcntrs_mutex);
3404 mcounters->counters_data = desc_data;
3405 mcounters->cntrs_max_index = cntrs_max_index;
3406 mutex_unlock(&mcounters->mcntrs_mutex);
3407
3408 return 0;
3409 }
3410
3411 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3412 static int flow_counters_set_data(struct ib_counters *ibcounters,
3413 struct mlx5_ib_create_flow *ucmd)
3414 {
3415 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3416 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3417 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3418 bool hw_hndl = false;
3419 int ret = 0;
3420
3421 if (ucmd && ucmd->ncounters_data != 0) {
3422 cntrs_data = ucmd->data;
3423 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3424 return -EINVAL;
3425
3426 desc_data = kcalloc(cntrs_data->ncounters,
3427 sizeof(*desc_data),
3428 GFP_KERNEL);
3429 if (!desc_data)
3430 return -ENOMEM;
3431
3432 if (copy_from_user(desc_data,
3433 u64_to_user_ptr(cntrs_data->counters_data),
3434 sizeof(*desc_data) * cntrs_data->ncounters)) {
3435 ret = -EFAULT;
3436 goto free;
3437 }
3438 }
3439
3440 if (!mcounters->hw_cntrs_hndl) {
3441 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3442 to_mdev(ibcounters->device)->mdev, false);
3443 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3444 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3445 goto free;
3446 }
3447 hw_hndl = true;
3448 }
3449
3450 if (desc_data) {
3451
3452 if (mcounters->cntrs_max_index) {
3453 ret = -EINVAL;
3454 goto free_hndl;
3455 }
3456
3457 ret = counters_set_description(ibcounters,
3458 MLX5_IB_COUNTERS_FLOW,
3459 desc_data,
3460 cntrs_data->ncounters);
3461 if (ret)
3462 goto free_hndl;
3463
3464 } else if (!mcounters->cntrs_max_index) {
3465
3466 ret = -EINVAL;
3467 goto free_hndl;
3468 }
3469
3470 return 0;
3471
3472 free_hndl:
3473 if (hw_hndl) {
3474 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3475 mcounters->hw_cntrs_hndl);
3476 mcounters->hw_cntrs_hndl = NULL;
3477 }
3478 free:
3479 kfree(desc_data);
3480 return ret;
3481 }
3482
3483 static void mlx5_ib_set_rule_source_port(struct mlx5_ib_dev *dev,
3484 struct mlx5_flow_spec *spec,
3485 struct mlx5_eswitch_rep *rep)
3486 {
3487 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
3488 void *misc;
3489
3490 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
3491 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3492 misc_parameters_2);
3493
3494 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
3495 mlx5_eswitch_get_vport_metadata_for_match(esw,
3496 rep->vport));
3497 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3498 misc_parameters_2);
3499
3500 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
3501 } else {
3502 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3503 misc_parameters);
3504
3505 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport);
3506
3507 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3508 misc_parameters);
3509
3510 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3511 }
3512 }
3513
3514 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3515 struct mlx5_ib_flow_prio *ft_prio,
3516 const struct ib_flow_attr *flow_attr,
3517 struct mlx5_flow_destination *dst,
3518 u32 underlay_qpn,
3519 struct mlx5_ib_create_flow *ucmd)
3520 {
3521 struct mlx5_flow_table *ft = ft_prio->flow_table;
3522 struct mlx5_ib_flow_handler *handler;
3523 struct mlx5_flow_act flow_act = {};
3524 struct mlx5_flow_spec *spec;
3525 struct mlx5_flow_destination dest_arr[2] = {};
3526 struct mlx5_flow_destination *rule_dst = dest_arr;
3527 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3528 unsigned int spec_index;
3529 u32 prev_type = 0;
3530 int err = 0;
3531 int dest_num = 0;
3532 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3533
3534 if (!is_valid_attr(dev->mdev, flow_attr))
3535 return ERR_PTR(-EINVAL);
3536
3537 if (dev->is_rep && is_egress)
3538 return ERR_PTR(-EINVAL);
3539
3540 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3541 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3542 if (!handler || !spec) {
3543 err = -ENOMEM;
3544 goto free;
3545 }
3546
3547 INIT_LIST_HEAD(&handler->list);
3548
3549 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3550 err = parse_flow_attr(dev->mdev, spec,
3551 ib_flow, flow_attr, &flow_act,
3552 prev_type);
3553 if (err < 0)
3554 goto free;
3555
3556 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3557 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3558 }
3559
3560 if (dst && !(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP)) {
3561 memcpy(&dest_arr[0], dst, sizeof(*dst));
3562 dest_num++;
3563 }
3564
3565 if (!flow_is_multicast_only(flow_attr))
3566 set_underlay_qp(dev, spec, underlay_qpn);
3567
3568 if (dev->is_rep) {
3569 struct mlx5_eswitch_rep *rep;
3570
3571 rep = dev->port[flow_attr->port - 1].rep;
3572 if (!rep) {
3573 err = -EINVAL;
3574 goto free;
3575 }
3576
3577 mlx5_ib_set_rule_source_port(dev, spec, rep);
3578 }
3579
3580 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3581
3582 if (is_egress &&
3583 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3584 err = -EINVAL;
3585 goto free;
3586 }
3587
3588 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3589 struct mlx5_ib_mcounters *mcounters;
3590
3591 err = flow_counters_set_data(flow_act.counters, ucmd);
3592 if (err)
3593 goto free;
3594
3595 mcounters = to_mcounters(flow_act.counters);
3596 handler->ibcounters = flow_act.counters;
3597 dest_arr[dest_num].type =
3598 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3599 dest_arr[dest_num].counter_id =
3600 mlx5_fc_id(mcounters->hw_cntrs_hndl);
3601 dest_num++;
3602 }
3603
3604 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3605 if (!dest_num)
3606 rule_dst = NULL;
3607 } else {
3608 if (is_egress)
3609 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3610 else
3611 flow_act.action |=
3612 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3613 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3614 }
3615
3616 if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG) &&
3617 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3618 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3619 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3620 spec->flow_context.flow_tag, flow_attr->type);
3621 err = -EINVAL;
3622 goto free;
3623 }
3624 handler->rule = mlx5_add_flow_rules(ft, spec,
3625 &flow_act,
3626 rule_dst, dest_num);
3627
3628 if (IS_ERR(handler->rule)) {
3629 err = PTR_ERR(handler->rule);
3630 goto free;
3631 }
3632
3633 ft_prio->refcount++;
3634 handler->prio = ft_prio;
3635 handler->dev = dev;
3636
3637 ft_prio->flow_table = ft;
3638 free:
3639 if (err && handler) {
3640 if (handler->ibcounters &&
3641 atomic_read(&handler->ibcounters->usecnt) == 1)
3642 counters_clear_description(handler->ibcounters);
3643 kfree(handler);
3644 }
3645 kvfree(spec);
3646 return err ? ERR_PTR(err) : handler;
3647 }
3648
3649 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3650 struct mlx5_ib_flow_prio *ft_prio,
3651 const struct ib_flow_attr *flow_attr,
3652 struct mlx5_flow_destination *dst)
3653 {
3654 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3655 }
3656
3657 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3658 struct mlx5_ib_flow_prio *ft_prio,
3659 struct ib_flow_attr *flow_attr,
3660 struct mlx5_flow_destination *dst)
3661 {
3662 struct mlx5_ib_flow_handler *handler_dst = NULL;
3663 struct mlx5_ib_flow_handler *handler = NULL;
3664
3665 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3666 if (!IS_ERR(handler)) {
3667 handler_dst = create_flow_rule(dev, ft_prio,
3668 flow_attr, dst);
3669 if (IS_ERR(handler_dst)) {
3670 mlx5_del_flow_rules(handler->rule);
3671 ft_prio->refcount--;
3672 kfree(handler);
3673 handler = handler_dst;
3674 } else {
3675 list_add(&handler_dst->list, &handler->list);
3676 }
3677 }
3678
3679 return handler;
3680 }
3681 enum {
3682 LEFTOVERS_MC,
3683 LEFTOVERS_UC,
3684 };
3685
3686 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3687 struct mlx5_ib_flow_prio *ft_prio,
3688 struct ib_flow_attr *flow_attr,
3689 struct mlx5_flow_destination *dst)
3690 {
3691 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3692 struct mlx5_ib_flow_handler *handler = NULL;
3693
3694 static struct {
3695 struct ib_flow_attr flow_attr;
3696 struct ib_flow_spec_eth eth_flow;
3697 } leftovers_specs[] = {
3698 [LEFTOVERS_MC] = {
3699 .flow_attr = {
3700 .num_of_specs = 1,
3701 .size = sizeof(leftovers_specs[0])
3702 },
3703 .eth_flow = {
3704 .type = IB_FLOW_SPEC_ETH,
3705 .size = sizeof(struct ib_flow_spec_eth),
3706 .mask = {.dst_mac = {0x1} },
3707 .val = {.dst_mac = {0x1} }
3708 }
3709 },
3710 [LEFTOVERS_UC] = {
3711 .flow_attr = {
3712 .num_of_specs = 1,
3713 .size = sizeof(leftovers_specs[0])
3714 },
3715 .eth_flow = {
3716 .type = IB_FLOW_SPEC_ETH,
3717 .size = sizeof(struct ib_flow_spec_eth),
3718 .mask = {.dst_mac = {0x1} },
3719 .val = {.dst_mac = {} }
3720 }
3721 }
3722 };
3723
3724 handler = create_flow_rule(dev, ft_prio,
3725 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3726 dst);
3727 if (!IS_ERR(handler) &&
3728 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3729 handler_ucast = create_flow_rule(dev, ft_prio,
3730 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3731 dst);
3732 if (IS_ERR(handler_ucast)) {
3733 mlx5_del_flow_rules(handler->rule);
3734 ft_prio->refcount--;
3735 kfree(handler);
3736 handler = handler_ucast;
3737 } else {
3738 list_add(&handler_ucast->list, &handler->list);
3739 }
3740 }
3741
3742 return handler;
3743 }
3744
3745 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3746 struct mlx5_ib_flow_prio *ft_rx,
3747 struct mlx5_ib_flow_prio *ft_tx,
3748 struct mlx5_flow_destination *dst)
3749 {
3750 struct mlx5_ib_flow_handler *handler_rx;
3751 struct mlx5_ib_flow_handler *handler_tx;
3752 int err;
3753 static const struct ib_flow_attr flow_attr = {
3754 .num_of_specs = 0,
3755 .size = sizeof(flow_attr)
3756 };
3757
3758 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3759 if (IS_ERR(handler_rx)) {
3760 err = PTR_ERR(handler_rx);
3761 goto err;
3762 }
3763
3764 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3765 if (IS_ERR(handler_tx)) {
3766 err = PTR_ERR(handler_tx);
3767 goto err_tx;
3768 }
3769
3770 list_add(&handler_tx->list, &handler_rx->list);
3771
3772 return handler_rx;
3773
3774 err_tx:
3775 mlx5_del_flow_rules(handler_rx->rule);
3776 ft_rx->refcount--;
3777 kfree(handler_rx);
3778 err:
3779 return ERR_PTR(err);
3780 }
3781
3782 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3783 struct ib_flow_attr *flow_attr,
3784 int domain,
3785 struct ib_udata *udata)
3786 {
3787 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3788 struct mlx5_ib_qp *mqp = to_mqp(qp);
3789 struct mlx5_ib_flow_handler *handler = NULL;
3790 struct mlx5_flow_destination *dst = NULL;
3791 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3792 struct mlx5_ib_flow_prio *ft_prio;
3793 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3794 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3795 size_t min_ucmd_sz, required_ucmd_sz;
3796 int err;
3797 int underlay_qpn;
3798
3799 if (udata && udata->inlen) {
3800 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3801 sizeof(ucmd_hdr.reserved);
3802 if (udata->inlen < min_ucmd_sz)
3803 return ERR_PTR(-EOPNOTSUPP);
3804
3805 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3806 if (err)
3807 return ERR_PTR(err);
3808
3809
3810 if (ucmd_hdr.ncounters_data > 1)
3811 return ERR_PTR(-EINVAL);
3812
3813 required_ucmd_sz = min_ucmd_sz +
3814 sizeof(struct mlx5_ib_flow_counters_data) *
3815 ucmd_hdr.ncounters_data;
3816 if (udata->inlen > required_ucmd_sz &&
3817 !ib_is_udata_cleared(udata, required_ucmd_sz,
3818 udata->inlen - required_ucmd_sz))
3819 return ERR_PTR(-EOPNOTSUPP);
3820
3821 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3822 if (!ucmd)
3823 return ERR_PTR(-ENOMEM);
3824
3825 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3826 if (err)
3827 goto free_ucmd;
3828 }
3829
3830 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3831 err = -ENOMEM;
3832 goto free_ucmd;
3833 }
3834
3835 if (domain != IB_FLOW_DOMAIN_USER ||
3836 flow_attr->port > dev->num_ports ||
3837 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3838 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3839 err = -EINVAL;
3840 goto free_ucmd;
3841 }
3842
3843 if (is_egress &&
3844 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3845 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3846 err = -EINVAL;
3847 goto free_ucmd;
3848 }
3849
3850 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3851 if (!dst) {
3852 err = -ENOMEM;
3853 goto free_ucmd;
3854 }
3855
3856 mutex_lock(&dev->flow_db->lock);
3857
3858 ft_prio = get_flow_table(dev, flow_attr,
3859 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3860 if (IS_ERR(ft_prio)) {
3861 err = PTR_ERR(ft_prio);
3862 goto unlock;
3863 }
3864 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3865 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3866 if (IS_ERR(ft_prio_tx)) {
3867 err = PTR_ERR(ft_prio_tx);
3868 ft_prio_tx = NULL;
3869 goto destroy_ft;
3870 }
3871 }
3872
3873 if (is_egress) {
3874 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3875 } else {
3876 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3877 if (mqp->flags & MLX5_IB_QP_RSS)
3878 dst->tir_num = mqp->rss_qp.tirn;
3879 else
3880 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3881 }
3882
3883 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3884 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3885 handler = create_dont_trap_rule(dev, ft_prio,
3886 flow_attr, dst);
3887 } else {
3888 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3889 mqp->underlay_qpn : 0;
3890 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3891 dst, underlay_qpn, ucmd);
3892 }
3893 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3894 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3895 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3896 dst);
3897 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3898 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3899 } else {
3900 err = -EINVAL;
3901 goto destroy_ft;
3902 }
3903
3904 if (IS_ERR(handler)) {
3905 err = PTR_ERR(handler);
3906 handler = NULL;
3907 goto destroy_ft;
3908 }
3909
3910 mutex_unlock(&dev->flow_db->lock);
3911 kfree(dst);
3912 kfree(ucmd);
3913
3914 return &handler->ibflow;
3915
3916 destroy_ft:
3917 put_flow_table(dev, ft_prio, false);
3918 if (ft_prio_tx)
3919 put_flow_table(dev, ft_prio_tx, false);
3920 unlock:
3921 mutex_unlock(&dev->flow_db->lock);
3922 kfree(dst);
3923 free_ucmd:
3924 kfree(ucmd);
3925 return ERR_PTR(err);
3926 }
3927
3928 static struct mlx5_ib_flow_prio *
3929 _get_flow_table(struct mlx5_ib_dev *dev,
3930 struct mlx5_ib_flow_matcher *fs_matcher,
3931 bool mcast)
3932 {
3933 struct mlx5_flow_namespace *ns = NULL;
3934 struct mlx5_ib_flow_prio *prio = NULL;
3935 int max_table_size = 0;
3936 bool esw_encap;
3937 u32 flags = 0;
3938 int priority;
3939
3940 if (mcast)
3941 priority = MLX5_IB_FLOW_MCAST_PRIO;
3942 else
3943 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3944
3945 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3946 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3947 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3948 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3949 log_max_ft_size));
3950 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
3951 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3952 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3953 reformat_l3_tunnel_to_l2) &&
3954 !esw_encap)
3955 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3956 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
3957 max_table_size = BIT(
3958 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
3959 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
3960 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3961 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3962 max_table_size = BIT(
3963 MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
3964 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap)
3965 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3966 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) &&
3967 esw_encap)
3968 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3969 priority = FDB_BYPASS_PATH;
3970 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX) {
3971 max_table_size =
3972 BIT(MLX5_CAP_FLOWTABLE_RDMA_RX(dev->mdev,
3973 log_max_ft_size));
3974 priority = fs_matcher->priority;
3975 }
3976
3977 max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
3978
3979 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
3980 if (!ns)
3981 return ERR_PTR(-ENOTSUPP);
3982
3983 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3984 prio = &dev->flow_db->prios[priority];
3985 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
3986 prio = &dev->flow_db->egress_prios[priority];
3987 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
3988 prio = &dev->flow_db->fdb;
3989 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX)
3990 prio = &dev->flow_db->rdma_rx[priority];
3991
3992 if (!prio)
3993 return ERR_PTR(-EINVAL);
3994
3995 if (prio->flow_table)
3996 return prio;
3997
3998 return _get_prio(ns, prio, priority, max_table_size,
3999 MLX5_FS_MAX_TYPES, flags);
4000 }
4001
4002 static struct mlx5_ib_flow_handler *
4003 _create_raw_flow_rule(struct mlx5_ib_dev *dev,
4004 struct mlx5_ib_flow_prio *ft_prio,
4005 struct mlx5_flow_destination *dst,
4006 struct mlx5_ib_flow_matcher *fs_matcher,
4007 struct mlx5_flow_context *flow_context,
4008 struct mlx5_flow_act *flow_act,
4009 void *cmd_in, int inlen,
4010 int dst_num)
4011 {
4012 struct mlx5_ib_flow_handler *handler;
4013 struct mlx5_flow_spec *spec;
4014 struct mlx5_flow_table *ft = ft_prio->flow_table;
4015 int err = 0;
4016
4017 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
4018 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
4019 if (!handler || !spec) {
4020 err = -ENOMEM;
4021 goto free;
4022 }
4023
4024 INIT_LIST_HEAD(&handler->list);
4025
4026 memcpy(spec->match_value, cmd_in, inlen);
4027 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
4028 fs_matcher->mask_len);
4029 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
4030 spec->flow_context = *flow_context;
4031
4032 handler->rule = mlx5_add_flow_rules(ft, spec,
4033 flow_act, dst, dst_num);
4034
4035 if (IS_ERR(handler->rule)) {
4036 err = PTR_ERR(handler->rule);
4037 goto free;
4038 }
4039
4040 ft_prio->refcount++;
4041 handler->prio = ft_prio;
4042 handler->dev = dev;
4043 ft_prio->flow_table = ft;
4044
4045 free:
4046 if (err)
4047 kfree(handler);
4048 kvfree(spec);
4049 return err ? ERR_PTR(err) : handler;
4050 }
4051
4052 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4053 void *match_v)
4054 {
4055 void *match_c;
4056 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4057 void *dmac, *dmac_mask;
4058 void *ipv4, *ipv4_mask;
4059
4060 if (!(fs_matcher->match_criteria_enable &
4061 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4062 return false;
4063
4064 match_c = fs_matcher->matcher_mask.match_params;
4065 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4066 outer_headers);
4067 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4068 outer_headers);
4069
4070 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4071 dmac_47_16);
4072 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4073 dmac_47_16);
4074
4075 if (is_multicast_ether_addr(dmac) &&
4076 is_multicast_ether_addr(dmac_mask))
4077 return true;
4078
4079 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4080 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4081
4082 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4083 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4084
4085 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4086 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4087 return true;
4088
4089 return false;
4090 }
4091
4092 struct mlx5_ib_flow_handler *
4093 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4094 struct mlx5_ib_flow_matcher *fs_matcher,
4095 struct mlx5_flow_context *flow_context,
4096 struct mlx5_flow_act *flow_act,
4097 u32 counter_id,
4098 void *cmd_in, int inlen, int dest_id,
4099 int dest_type)
4100 {
4101 struct mlx5_flow_destination *dst;
4102 struct mlx5_ib_flow_prio *ft_prio;
4103 struct mlx5_ib_flow_handler *handler;
4104 int dst_num = 0;
4105 bool mcast;
4106 int err;
4107
4108 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4109 return ERR_PTR(-EOPNOTSUPP);
4110
4111 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4112 return ERR_PTR(-ENOMEM);
4113
4114 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
4115 if (!dst)
4116 return ERR_PTR(-ENOMEM);
4117
4118 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4119 mutex_lock(&dev->flow_db->lock);
4120
4121 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
4122 if (IS_ERR(ft_prio)) {
4123 err = PTR_ERR(ft_prio);
4124 goto unlock;
4125 }
4126
4127 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
4128 dst[dst_num].type = dest_type;
4129 dst[dst_num].tir_num = dest_id;
4130 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4131 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
4132 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4133 dst[dst_num].ft_num = dest_id;
4134 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4135 } else {
4136 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
4137 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
4138 }
4139
4140 dst_num++;
4141
4142 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4143 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4144 dst[dst_num].counter_id = counter_id;
4145 dst_num++;
4146 }
4147
4148 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher,
4149 flow_context, flow_act,
4150 cmd_in, inlen, dst_num);
4151
4152 if (IS_ERR(handler)) {
4153 err = PTR_ERR(handler);
4154 goto destroy_ft;
4155 }
4156
4157 mutex_unlock(&dev->flow_db->lock);
4158 atomic_inc(&fs_matcher->usecnt);
4159 handler->flow_matcher = fs_matcher;
4160
4161 kfree(dst);
4162
4163 return handler;
4164
4165 destroy_ft:
4166 put_flow_table(dev, ft_prio, false);
4167 unlock:
4168 mutex_unlock(&dev->flow_db->lock);
4169 kfree(dst);
4170
4171 return ERR_PTR(err);
4172 }
4173
4174 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4175 {
4176 u32 flags = 0;
4177
4178 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4179 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4180
4181 return flags;
4182 }
4183
4184 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4185 static struct ib_flow_action *
4186 mlx5_ib_create_flow_action_esp(struct ib_device *device,
4187 const struct ib_flow_action_attrs_esp *attr,
4188 struct uverbs_attr_bundle *attrs)
4189 {
4190 struct mlx5_ib_dev *mdev = to_mdev(device);
4191 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4192 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4193 struct mlx5_ib_flow_action *action;
4194 u64 action_flags;
4195 u64 flags;
4196 int err = 0;
4197
4198 err = uverbs_get_flags64(
4199 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4200 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4201 if (err)
4202 return ERR_PTR(err);
4203
4204 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4205
4206
4207
4208
4209
4210 if (!attr->keymat || attr->replay || attr->encap ||
4211 attr->spi || attr->seq || attr->tfc_pad ||
4212 attr->hard_limit_pkts ||
4213 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4214 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4215 return ERR_PTR(-EOPNOTSUPP);
4216
4217 if (attr->keymat->protocol !=
4218 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4219 return ERR_PTR(-EOPNOTSUPP);
4220
4221 aes_gcm = &attr->keymat->keymat.aes_gcm;
4222
4223 if (aes_gcm->icv_len != 16 ||
4224 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4225 return ERR_PTR(-EOPNOTSUPP);
4226
4227 action = kmalloc(sizeof(*action), GFP_KERNEL);
4228 if (!action)
4229 return ERR_PTR(-ENOMEM);
4230
4231 action->esp_aes_gcm.ib_flags = attr->flags;
4232 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4233 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4234 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4235 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4236 sizeof(accel_attrs.keymat.aes_gcm.salt));
4237 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4238 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4239 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4240 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4241 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4242
4243 accel_attrs.esn = attr->esn;
4244 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4245 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4246 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4247 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4248
4249 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4250 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4251
4252 action->esp_aes_gcm.ctx =
4253 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4254 if (IS_ERR(action->esp_aes_gcm.ctx)) {
4255 err = PTR_ERR(action->esp_aes_gcm.ctx);
4256 goto err_parse;
4257 }
4258
4259 action->esp_aes_gcm.ib_flags = attr->flags;
4260
4261 return &action->ib_action;
4262
4263 err_parse:
4264 kfree(action);
4265 return ERR_PTR(err);
4266 }
4267
4268 static int
4269 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4270 const struct ib_flow_action_attrs_esp *attr,
4271 struct uverbs_attr_bundle *attrs)
4272 {
4273 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4274 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4275 int err = 0;
4276
4277 if (attr->keymat || attr->replay || attr->encap ||
4278 attr->spi || attr->seq || attr->tfc_pad ||
4279 attr->hard_limit_pkts ||
4280 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4281 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4282 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4283 return -EOPNOTSUPP;
4284
4285
4286
4287
4288 if (!(maction->esp_aes_gcm.ib_flags &
4289 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4290 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4291 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4292 return -EINVAL;
4293
4294 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4295 sizeof(accel_attrs));
4296
4297 accel_attrs.esn = attr->esn;
4298 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4299 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4300 else
4301 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4302
4303 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4304 &accel_attrs);
4305 if (err)
4306 return err;
4307
4308 maction->esp_aes_gcm.ib_flags &=
4309 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4310 maction->esp_aes_gcm.ib_flags |=
4311 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4312
4313 return 0;
4314 }
4315
4316 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4317 {
4318 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4319
4320 switch (action->type) {
4321 case IB_FLOW_ACTION_ESP:
4322
4323
4324
4325
4326 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4327 break;
4328 case IB_FLOW_ACTION_UNSPECIFIED:
4329 mlx5_ib_destroy_flow_action_raw(maction);
4330 break;
4331 default:
4332 WARN_ON(true);
4333 break;
4334 }
4335
4336 kfree(maction);
4337 return 0;
4338 }
4339
4340 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4341 {
4342 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4343 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
4344 int err;
4345 u16 uid;
4346
4347 uid = ibqp->pd ?
4348 to_mpd(ibqp->pd)->uid : 0;
4349
4350 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4351 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4352 return -EOPNOTSUPP;
4353 }
4354
4355 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4356 if (err)
4357 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4358 ibqp->qp_num, gid->raw);
4359
4360 return err;
4361 }
4362
4363 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4364 {
4365 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4366 int err;
4367 u16 uid;
4368
4369 uid = ibqp->pd ?
4370 to_mpd(ibqp->pd)->uid : 0;
4371 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4372 if (err)
4373 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4374 ibqp->qp_num, gid->raw);
4375
4376 return err;
4377 }
4378
4379 static int init_node_data(struct mlx5_ib_dev *dev)
4380 {
4381 int err;
4382
4383 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
4384 if (err)
4385 return err;
4386
4387 dev->mdev->rev_id = dev->mdev->pdev->revision;
4388
4389 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
4390 }
4391
4392 static ssize_t fw_pages_show(struct device *device,
4393 struct device_attribute *attr, char *buf)
4394 {
4395 struct mlx5_ib_dev *dev =
4396 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4397
4398 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
4399 }
4400 static DEVICE_ATTR_RO(fw_pages);
4401
4402 static ssize_t reg_pages_show(struct device *device,
4403 struct device_attribute *attr, char *buf)
4404 {
4405 struct mlx5_ib_dev *dev =
4406 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4407
4408 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
4409 }
4410 static DEVICE_ATTR_RO(reg_pages);
4411
4412 static ssize_t hca_type_show(struct device *device,
4413 struct device_attribute *attr, char *buf)
4414 {
4415 struct mlx5_ib_dev *dev =
4416 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4417
4418 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
4419 }
4420 static DEVICE_ATTR_RO(hca_type);
4421
4422 static ssize_t hw_rev_show(struct device *device,
4423 struct device_attribute *attr, char *buf)
4424 {
4425 struct mlx5_ib_dev *dev =
4426 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4427
4428 return sprintf(buf, "%x\n", dev->mdev->rev_id);
4429 }
4430 static DEVICE_ATTR_RO(hw_rev);
4431
4432 static ssize_t board_id_show(struct device *device,
4433 struct device_attribute *attr, char *buf)
4434 {
4435 struct mlx5_ib_dev *dev =
4436 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4437
4438 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
4439 dev->mdev->board_id);
4440 }
4441 static DEVICE_ATTR_RO(board_id);
4442
4443 static struct attribute *mlx5_class_attributes[] = {
4444 &dev_attr_hw_rev.attr,
4445 &dev_attr_hca_type.attr,
4446 &dev_attr_board_id.attr,
4447 &dev_attr_fw_pages.attr,
4448 &dev_attr_reg_pages.attr,
4449 NULL,
4450 };
4451
4452 static const struct attribute_group mlx5_attr_group = {
4453 .attrs = mlx5_class_attributes,
4454 };
4455
4456 static void pkey_change_handler(struct work_struct *work)
4457 {
4458 struct mlx5_ib_port_resources *ports =
4459 container_of(work, struct mlx5_ib_port_resources,
4460 pkey_change_work);
4461
4462 mutex_lock(&ports->devr->mutex);
4463 mlx5_ib_gsi_pkey_change(ports->gsi);
4464 mutex_unlock(&ports->devr->mutex);
4465 }
4466
4467 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4468 {
4469 struct mlx5_ib_qp *mqp;
4470 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4471 struct mlx5_core_cq *mcq;
4472 struct list_head cq_armed_list;
4473 unsigned long flags_qp;
4474 unsigned long flags_cq;
4475 unsigned long flags;
4476
4477 INIT_LIST_HEAD(&cq_armed_list);
4478
4479
4480 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4481 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4482 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4483 if (mqp->sq.tail != mqp->sq.head) {
4484 send_mcq = to_mcq(mqp->ibqp.send_cq);
4485 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4486 if (send_mcq->mcq.comp &&
4487 mqp->ibqp.send_cq->comp_handler) {
4488 if (!send_mcq->mcq.reset_notify_added) {
4489 send_mcq->mcq.reset_notify_added = 1;
4490 list_add_tail(&send_mcq->mcq.reset_notify,
4491 &cq_armed_list);
4492 }
4493 }
4494 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4495 }
4496 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4497 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4498
4499 if (!mqp->ibqp.srq) {
4500 if (mqp->rq.tail != mqp->rq.head) {
4501 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4502 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4503 if (recv_mcq->mcq.comp &&
4504 mqp->ibqp.recv_cq->comp_handler) {
4505 if (!recv_mcq->mcq.reset_notify_added) {
4506 recv_mcq->mcq.reset_notify_added = 1;
4507 list_add_tail(&recv_mcq->mcq.reset_notify,
4508 &cq_armed_list);
4509 }
4510 }
4511 spin_unlock_irqrestore(&recv_mcq->lock,
4512 flags_cq);
4513 }
4514 }
4515 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4516 }
4517
4518
4519
4520 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4521 mcq->comp(mcq, NULL);
4522 }
4523 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4524 }
4525
4526 static void delay_drop_handler(struct work_struct *work)
4527 {
4528 int err;
4529 struct mlx5_ib_delay_drop *delay_drop =
4530 container_of(work, struct mlx5_ib_delay_drop,
4531 delay_drop_work);
4532
4533 atomic_inc(&delay_drop->events_cnt);
4534
4535 mutex_lock(&delay_drop->lock);
4536 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4537 delay_drop->timeout);
4538 if (err) {
4539 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4540 delay_drop->timeout);
4541 delay_drop->activate = false;
4542 }
4543 mutex_unlock(&delay_drop->lock);
4544 }
4545
4546 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4547 struct ib_event *ibev)
4548 {
4549 u8 port = (eqe->data.port.port >> 4) & 0xf;
4550
4551 switch (eqe->sub_type) {
4552 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
4553 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4554 IB_LINK_LAYER_ETHERNET)
4555 schedule_work(&ibdev->delay_drop.delay_drop_work);
4556 break;
4557 default:
4558 return;
4559 }
4560 }
4561
4562 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4563 struct ib_event *ibev)
4564 {
4565 u8 port = (eqe->data.port.port >> 4) & 0xf;
4566
4567 ibev->element.port_num = port;
4568
4569 switch (eqe->sub_type) {
4570 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4571 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4572 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4573
4574
4575
4576 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4577 IB_LINK_LAYER_ETHERNET)
4578 return -EINVAL;
4579
4580 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4581 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4582 break;
4583
4584 case MLX5_PORT_CHANGE_SUBTYPE_LID:
4585 ibev->event = IB_EVENT_LID_CHANGE;
4586 break;
4587
4588 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4589 ibev->event = IB_EVENT_PKEY_CHANGE;
4590 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4591 break;
4592
4593 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4594 ibev->event = IB_EVENT_GID_CHANGE;
4595 break;
4596
4597 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4598 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4599 break;
4600 default:
4601 return -EINVAL;
4602 }
4603
4604 return 0;
4605 }
4606
4607 static void mlx5_ib_handle_event(struct work_struct *_work)
4608 {
4609 struct mlx5_ib_event_work *work =
4610 container_of(_work, struct mlx5_ib_event_work, work);
4611 struct mlx5_ib_dev *ibdev;
4612 struct ib_event ibev;
4613 bool fatal = false;
4614
4615 if (work->is_slave) {
4616 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
4617 if (!ibdev)
4618 goto out;
4619 } else {
4620 ibdev = work->dev;
4621 }
4622
4623 switch (work->event) {
4624 case MLX5_DEV_EVENT_SYS_ERROR:
4625 ibev.event = IB_EVENT_DEVICE_FATAL;
4626 mlx5_ib_handle_internal_error(ibdev);
4627 ibev.element.port_num = (u8)(unsigned long)work->param;
4628 fatal = true;
4629 break;
4630 case MLX5_EVENT_TYPE_PORT_CHANGE:
4631 if (handle_port_change(ibdev, work->param, &ibev))
4632 goto out;
4633 break;
4634 case MLX5_EVENT_TYPE_GENERAL_EVENT:
4635 handle_general_event(ibdev, work->param, &ibev);
4636
4637 default:
4638 goto out;
4639 }
4640
4641 ibev.device = &ibdev->ib_dev;
4642
4643 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4644 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
4645 goto out;
4646 }
4647
4648 if (ibdev->ib_active)
4649 ib_dispatch_event(&ibev);
4650
4651 if (fatal)
4652 ibdev->ib_active = false;
4653 out:
4654 kfree(work);
4655 }
4656
4657 static int mlx5_ib_event(struct notifier_block *nb,
4658 unsigned long event, void *param)
4659 {
4660 struct mlx5_ib_event_work *work;
4661
4662 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4663 if (!work)
4664 return NOTIFY_DONE;
4665
4666 INIT_WORK(&work->work, mlx5_ib_handle_event);
4667 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4668 work->is_slave = false;
4669 work->param = param;
4670 work->event = event;
4671
4672 queue_work(mlx5_ib_event_wq, &work->work);
4673
4674 return NOTIFY_OK;
4675 }
4676
4677 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4678 unsigned long event, void *param)
4679 {
4680 struct mlx5_ib_event_work *work;
4681
4682 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4683 if (!work)
4684 return NOTIFY_DONE;
4685
4686 INIT_WORK(&work->work, mlx5_ib_handle_event);
4687 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4688 work->is_slave = true;
4689 work->param = param;
4690 work->event = event;
4691 queue_work(mlx5_ib_event_wq, &work->work);
4692
4693 return NOTIFY_OK;
4694 }
4695
4696 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4697 {
4698 struct mlx5_hca_vport_context vport_ctx;
4699 int err;
4700 int port;
4701
4702 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
4703 dev->mdev->port_caps[port - 1].has_smi = false;
4704 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4705 MLX5_CAP_PORT_TYPE_IB) {
4706 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4707 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4708 port, 0,
4709 &vport_ctx);
4710 if (err) {
4711 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4712 port, err);
4713 return err;
4714 }
4715 dev->mdev->port_caps[port - 1].has_smi =
4716 vport_ctx.has_smi;
4717 } else {
4718 dev->mdev->port_caps[port - 1].has_smi = true;
4719 }
4720 }
4721 }
4722 return 0;
4723 }
4724
4725 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4726 {
4727 int port;
4728
4729 for (port = 1; port <= dev->num_ports; port++)
4730 mlx5_query_ext_port_caps(dev, port);
4731 }
4732
4733 static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4734 {
4735 struct ib_device_attr *dprops = NULL;
4736 struct ib_port_attr *pprops = NULL;
4737 int err = -ENOMEM;
4738
4739 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL);
4740 if (!pprops)
4741 goto out;
4742
4743 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4744 if (!dprops)
4745 goto out;
4746
4747 err = mlx5_ib_query_device(&dev->ib_dev, dprops, NULL);
4748 if (err) {
4749 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4750 goto out;
4751 }
4752
4753 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4754 if (err) {
4755 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4756 port, err);
4757 goto out;
4758 }
4759
4760 dev->mdev->port_caps[port - 1].pkey_table_len =
4761 dprops->max_pkeys;
4762 dev->mdev->port_caps[port - 1].gid_table_len =
4763 pprops->gid_tbl_len;
4764 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4765 port, dprops->max_pkeys, pprops->gid_tbl_len);
4766
4767 out:
4768 kfree(pprops);
4769 kfree(dprops);
4770
4771 return err;
4772 }
4773
4774 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4775 {
4776
4777
4778
4779 if (dev->is_rep)
4780 return __get_port_caps(dev, 1);
4781 return __get_port_caps(dev, port);
4782 }
4783
4784 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4785 {
4786 int err;
4787
4788 err = mlx5_mr_cache_cleanup(dev);
4789 if (err)
4790 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4791
4792 if (dev->umrc.qp)
4793 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
4794 if (dev->umrc.cq)
4795 ib_free_cq(dev->umrc.cq);
4796 if (dev->umrc.pd)
4797 ib_dealloc_pd(dev->umrc.pd);
4798 }
4799
4800 enum {
4801 MAX_UMR_WR = 128,
4802 };
4803
4804 static int create_umr_res(struct mlx5_ib_dev *dev)
4805 {
4806 struct ib_qp_init_attr *init_attr = NULL;
4807 struct ib_qp_attr *attr = NULL;
4808 struct ib_pd *pd;
4809 struct ib_cq *cq;
4810 struct ib_qp *qp;
4811 int ret;
4812
4813 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4814 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4815 if (!attr || !init_attr) {
4816 ret = -ENOMEM;
4817 goto error_0;
4818 }
4819
4820 pd = ib_alloc_pd(&dev->ib_dev, 0);
4821 if (IS_ERR(pd)) {
4822 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4823 ret = PTR_ERR(pd);
4824 goto error_0;
4825 }
4826
4827 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4828 if (IS_ERR(cq)) {
4829 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4830 ret = PTR_ERR(cq);
4831 goto error_2;
4832 }
4833
4834 init_attr->send_cq = cq;
4835 init_attr->recv_cq = cq;
4836 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4837 init_attr->cap.max_send_wr = MAX_UMR_WR;
4838 init_attr->cap.max_send_sge = 1;
4839 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4840 init_attr->port_num = 1;
4841 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4842 if (IS_ERR(qp)) {
4843 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4844 ret = PTR_ERR(qp);
4845 goto error_3;
4846 }
4847 qp->device = &dev->ib_dev;
4848 qp->real_qp = qp;
4849 qp->uobject = NULL;
4850 qp->qp_type = MLX5_IB_QPT_REG_UMR;
4851 qp->send_cq = init_attr->send_cq;
4852 qp->recv_cq = init_attr->recv_cq;
4853
4854 attr->qp_state = IB_QPS_INIT;
4855 attr->port_num = 1;
4856 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4857 IB_QP_PORT, NULL);
4858 if (ret) {
4859 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4860 goto error_4;
4861 }
4862
4863 memset(attr, 0, sizeof(*attr));
4864 attr->qp_state = IB_QPS_RTR;
4865 attr->path_mtu = IB_MTU_256;
4866
4867 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4868 if (ret) {
4869 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4870 goto error_4;
4871 }
4872
4873 memset(attr, 0, sizeof(*attr));
4874 attr->qp_state = IB_QPS_RTS;
4875 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4876 if (ret) {
4877 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4878 goto error_4;
4879 }
4880
4881 dev->umrc.qp = qp;
4882 dev->umrc.cq = cq;
4883 dev->umrc.pd = pd;
4884
4885 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4886 ret = mlx5_mr_cache_init(dev);
4887 if (ret) {
4888 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4889 goto error_4;
4890 }
4891
4892 kfree(attr);
4893 kfree(init_attr);
4894
4895 return 0;
4896
4897 error_4:
4898 mlx5_ib_destroy_qp(qp, NULL);
4899 dev->umrc.qp = NULL;
4900
4901 error_3:
4902 ib_free_cq(cq);
4903 dev->umrc.cq = NULL;
4904
4905 error_2:
4906 ib_dealloc_pd(pd);
4907 dev->umrc.pd = NULL;
4908
4909 error_0:
4910 kfree(attr);
4911 kfree(init_attr);
4912 return ret;
4913 }
4914
4915 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4916 {
4917 switch (umr_fence_cap) {
4918 case MLX5_CAP_UMR_FENCE_NONE:
4919 return MLX5_FENCE_MODE_NONE;
4920 case MLX5_CAP_UMR_FENCE_SMALL:
4921 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4922 default:
4923 return MLX5_FENCE_MODE_STRONG_ORDERING;
4924 }
4925 }
4926
4927 static int create_dev_resources(struct mlx5_ib_resources *devr)
4928 {
4929 struct ib_srq_init_attr attr;
4930 struct mlx5_ib_dev *dev;
4931 struct ib_device *ibdev;
4932 struct ib_cq_init_attr cq_attr = {.cqe = 1};
4933 int port;
4934 int ret = 0;
4935
4936 dev = container_of(devr, struct mlx5_ib_dev, devr);
4937 ibdev = &dev->ib_dev;
4938
4939 mutex_init(&devr->mutex);
4940
4941 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
4942 if (!devr->p0)
4943 return -ENOMEM;
4944
4945 devr->p0->device = ibdev;
4946 devr->p0->uobject = NULL;
4947 atomic_set(&devr->p0->usecnt, 0);
4948
4949 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
4950 if (ret)
4951 goto error0;
4952
4953 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
4954 if (!devr->c0) {
4955 ret = -ENOMEM;
4956 goto error1;
4957 }
4958
4959 devr->c0->device = &dev->ib_dev;
4960 atomic_set(&devr->c0->usecnt, 0);
4961
4962 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
4963 if (ret)
4964 goto err_create_cq;
4965
4966 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
4967 if (IS_ERR(devr->x0)) {
4968 ret = PTR_ERR(devr->x0);
4969 goto error2;
4970 }
4971 devr->x0->device = &dev->ib_dev;
4972 devr->x0->inode = NULL;
4973 atomic_set(&devr->x0->usecnt, 0);
4974 mutex_init(&devr->x0->tgt_qp_mutex);
4975 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4976
4977 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
4978 if (IS_ERR(devr->x1)) {
4979 ret = PTR_ERR(devr->x1);
4980 goto error3;
4981 }
4982 devr->x1->device = &dev->ib_dev;
4983 devr->x1->inode = NULL;
4984 atomic_set(&devr->x1->usecnt, 0);
4985 mutex_init(&devr->x1->tgt_qp_mutex);
4986 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4987
4988 memset(&attr, 0, sizeof(attr));
4989 attr.attr.max_sge = 1;
4990 attr.attr.max_wr = 1;
4991 attr.srq_type = IB_SRQT_XRC;
4992 attr.ext.cq = devr->c0;
4993 attr.ext.xrc.xrcd = devr->x0;
4994
4995 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
4996 if (!devr->s0) {
4997 ret = -ENOMEM;
4998 goto error4;
4999 }
5000
5001 devr->s0->device = &dev->ib_dev;
5002 devr->s0->pd = devr->p0;
5003 devr->s0->srq_type = IB_SRQT_XRC;
5004 devr->s0->ext.xrc.xrcd = devr->x0;
5005 devr->s0->ext.cq = devr->c0;
5006 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
5007 if (ret)
5008 goto err_create;
5009
5010 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
5011 atomic_inc(&devr->s0->ext.cq->usecnt);
5012 atomic_inc(&devr->p0->usecnt);
5013 atomic_set(&devr->s0->usecnt, 0);
5014
5015 memset(&attr, 0, sizeof(attr));
5016 attr.attr.max_sge = 1;
5017 attr.attr.max_wr = 1;
5018 attr.srq_type = IB_SRQT_BASIC;
5019 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5020 if (!devr->s1) {
5021 ret = -ENOMEM;
5022 goto error5;
5023 }
5024
5025 devr->s1->device = &dev->ib_dev;
5026 devr->s1->pd = devr->p0;
5027 devr->s1->srq_type = IB_SRQT_BASIC;
5028 devr->s1->ext.cq = devr->c0;
5029
5030 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
5031 if (ret)
5032 goto error6;
5033
5034 atomic_inc(&devr->p0->usecnt);
5035 atomic_set(&devr->s1->usecnt, 0);
5036
5037 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
5038 INIT_WORK(&devr->ports[port].pkey_change_work,
5039 pkey_change_handler);
5040 devr->ports[port].devr = devr;
5041 }
5042
5043 return 0;
5044
5045 error6:
5046 kfree(devr->s1);
5047 error5:
5048 mlx5_ib_destroy_srq(devr->s0, NULL);
5049 err_create:
5050 kfree(devr->s0);
5051 error4:
5052 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5053 error3:
5054 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5055 error2:
5056 mlx5_ib_destroy_cq(devr->c0, NULL);
5057 err_create_cq:
5058 kfree(devr->c0);
5059 error1:
5060 mlx5_ib_dealloc_pd(devr->p0, NULL);
5061 error0:
5062 kfree(devr->p0);
5063 return ret;
5064 }
5065
5066 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5067 {
5068 int port;
5069
5070 mlx5_ib_destroy_srq(devr->s1, NULL);
5071 kfree(devr->s1);
5072 mlx5_ib_destroy_srq(devr->s0, NULL);
5073 kfree(devr->s0);
5074 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5075 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5076 mlx5_ib_destroy_cq(devr->c0, NULL);
5077 kfree(devr->c0);
5078 mlx5_ib_dealloc_pd(devr->p0, NULL);
5079 kfree(devr->p0);
5080
5081
5082 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
5083 cancel_work_sync(&devr->ports[port].pkey_change_work);
5084 }
5085
5086 static u32 get_core_cap_flags(struct ib_device *ibdev,
5087 struct mlx5_hca_vport_context *rep)
5088 {
5089 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5090 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5091 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5092 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
5093 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
5094 u32 ret = 0;
5095
5096 if (rep->grh_required)
5097 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5098
5099 if (ll == IB_LINK_LAYER_INFINIBAND)
5100 return ret | RDMA_CORE_PORT_IBA_IB;
5101
5102 if (raw_support)
5103 ret |= RDMA_CORE_PORT_RAW_PACKET;
5104
5105 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
5106 return ret;
5107
5108 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
5109 return ret;
5110
5111 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5112 ret |= RDMA_CORE_PORT_IBA_ROCE;
5113
5114 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5115 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5116
5117 return ret;
5118 }
5119
5120 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5121 struct ib_port_immutable *immutable)
5122 {
5123 struct ib_port_attr attr;
5124 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5125 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
5126 struct mlx5_hca_vport_context rep = {0};
5127 int err;
5128
5129 err = ib_query_port(ibdev, port_num, &attr);
5130 if (err)
5131 return err;
5132
5133 if (ll == IB_LINK_LAYER_INFINIBAND) {
5134 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5135 &rep);
5136 if (err)
5137 return err;
5138 }
5139
5140 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5141 immutable->gid_tbl_len = attr.gid_tbl_len;
5142 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
5143 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
5144 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
5145
5146 return 0;
5147 }
5148
5149 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5150 struct ib_port_immutable *immutable)
5151 {
5152 struct ib_port_attr attr;
5153 int err;
5154
5155 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5156
5157 err = ib_query_port(ibdev, port_num, &attr);
5158 if (err)
5159 return err;
5160
5161 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5162 immutable->gid_tbl_len = attr.gid_tbl_len;
5163 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5164
5165 return 0;
5166 }
5167
5168 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
5169 {
5170 struct mlx5_ib_dev *dev =
5171 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
5172 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5173 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5174 fw_rev_sub(dev->mdev));
5175 }
5176
5177 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
5178 {
5179 struct mlx5_core_dev *mdev = dev->mdev;
5180 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5181 MLX5_FLOW_NAMESPACE_LAG);
5182 struct mlx5_flow_table *ft;
5183 int err;
5184
5185 if (!ns || !mlx5_lag_is_roce(mdev))
5186 return 0;
5187
5188 err = mlx5_cmd_create_vport_lag(mdev);
5189 if (err)
5190 return err;
5191
5192 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5193 if (IS_ERR(ft)) {
5194 err = PTR_ERR(ft);
5195 goto err_destroy_vport_lag;
5196 }
5197
5198 dev->flow_db->lag_demux_ft = ft;
5199 dev->lag_active = true;
5200 return 0;
5201
5202 err_destroy_vport_lag:
5203 mlx5_cmd_destroy_vport_lag(mdev);
5204 return err;
5205 }
5206
5207 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
5208 {
5209 struct mlx5_core_dev *mdev = dev->mdev;
5210
5211 if (dev->lag_active) {
5212 dev->lag_active = false;
5213
5214 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5215 dev->flow_db->lag_demux_ft = NULL;
5216
5217 mlx5_cmd_destroy_vport_lag(mdev);
5218 }
5219 }
5220
5221 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5222 {
5223 int err;
5224
5225 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5226 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
5227 if (err) {
5228 dev->port[port_num].roce.nb.notifier_call = NULL;
5229 return err;
5230 }
5231
5232 return 0;
5233 }
5234
5235 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5236 {
5237 if (dev->port[port_num].roce.nb.notifier_call) {
5238 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5239 dev->port[port_num].roce.nb.notifier_call = NULL;
5240 }
5241 }
5242
5243 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
5244 {
5245 int err;
5246
5247 if (MLX5_CAP_GEN(dev->mdev, roce)) {
5248 err = mlx5_nic_vport_enable_roce(dev->mdev);
5249 if (err)
5250 return err;
5251 }
5252
5253 err = mlx5_eth_lag_init(dev);
5254 if (err)
5255 goto err_disable_roce;
5256
5257 return 0;
5258
5259 err_disable_roce:
5260 if (MLX5_CAP_GEN(dev->mdev, roce))
5261 mlx5_nic_vport_disable_roce(dev->mdev);
5262
5263 return err;
5264 }
5265
5266 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
5267 {
5268 mlx5_eth_lag_cleanup(dev);
5269 if (MLX5_CAP_GEN(dev->mdev, roce))
5270 mlx5_nic_vport_disable_roce(dev->mdev);
5271 }
5272
5273 struct mlx5_ib_counter {
5274 const char *name;
5275 size_t offset;
5276 };
5277
5278 #define INIT_Q_COUNTER(_name) \
5279 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5280
5281 static const struct mlx5_ib_counter basic_q_cnts[] = {
5282 INIT_Q_COUNTER(rx_write_requests),
5283 INIT_Q_COUNTER(rx_read_requests),
5284 INIT_Q_COUNTER(rx_atomic_requests),
5285 INIT_Q_COUNTER(out_of_buffer),
5286 };
5287
5288 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
5289 INIT_Q_COUNTER(out_of_sequence),
5290 };
5291
5292 static const struct mlx5_ib_counter retrans_q_cnts[] = {
5293 INIT_Q_COUNTER(duplicate_request),
5294 INIT_Q_COUNTER(rnr_nak_retry_err),
5295 INIT_Q_COUNTER(packet_seq_err),
5296 INIT_Q_COUNTER(implied_nak_seq_err),
5297 INIT_Q_COUNTER(local_ack_timeout_err),
5298 };
5299
5300 #define INIT_CONG_COUNTER(_name) \
5301 { .name = #_name, .offset = \
5302 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5303
5304 static const struct mlx5_ib_counter cong_cnts[] = {
5305 INIT_CONG_COUNTER(rp_cnp_ignored),
5306 INIT_CONG_COUNTER(rp_cnp_handled),
5307 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5308 INIT_CONG_COUNTER(np_cnp_sent),
5309 };
5310
5311 static const struct mlx5_ib_counter extended_err_cnts[] = {
5312 INIT_Q_COUNTER(resp_local_length_error),
5313 INIT_Q_COUNTER(resp_cqe_error),
5314 INIT_Q_COUNTER(req_cqe_error),
5315 INIT_Q_COUNTER(req_remote_invalid_request),
5316 INIT_Q_COUNTER(req_remote_access_errors),
5317 INIT_Q_COUNTER(resp_remote_access_errors),
5318 INIT_Q_COUNTER(resp_cqe_flush_error),
5319 INIT_Q_COUNTER(req_cqe_flush_error),
5320 };
5321
5322 #define INIT_EXT_PPCNT_COUNTER(_name) \
5323 { .name = #_name, .offset = \
5324 MLX5_BYTE_OFF(ppcnt_reg, \
5325 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5326
5327 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5328 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5329 };
5330
5331 static bool is_mdev_switchdev_mode(const struct mlx5_core_dev *mdev)
5332 {
5333 return MLX5_ESWITCH_MANAGER(mdev) &&
5334 mlx5_ib_eswitch_mode(mdev->priv.eswitch) ==
5335 MLX5_ESWITCH_OFFLOADS;
5336 }
5337
5338 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
5339 {
5340 int num_cnt_ports;
5341 int i;
5342
5343 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
5344
5345 for (i = 0; i < num_cnt_ports; i++) {
5346 if (dev->port[i].cnts.set_id_valid)
5347 mlx5_core_dealloc_q_counter(dev->mdev,
5348 dev->port[i].cnts.set_id);
5349 kfree(dev->port[i].cnts.names);
5350 kfree(dev->port[i].cnts.offsets);
5351 }
5352 }
5353
5354 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5355 struct mlx5_ib_counters *cnts)
5356 {
5357 u32 num_counters;
5358
5359 num_counters = ARRAY_SIZE(basic_q_cnts);
5360
5361 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5362 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5363
5364 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5365 num_counters += ARRAY_SIZE(retrans_q_cnts);
5366
5367 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5368 num_counters += ARRAY_SIZE(extended_err_cnts);
5369
5370 cnts->num_q_counters = num_counters;
5371
5372 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5373 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5374 num_counters += ARRAY_SIZE(cong_cnts);
5375 }
5376 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5377 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5378 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5379 }
5380 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5381 if (!cnts->names)
5382 return -ENOMEM;
5383
5384 cnts->offsets = kcalloc(num_counters,
5385 sizeof(cnts->offsets), GFP_KERNEL);
5386 if (!cnts->offsets)
5387 goto err_names;
5388
5389 return 0;
5390
5391 err_names:
5392 kfree(cnts->names);
5393 cnts->names = NULL;
5394 return -ENOMEM;
5395 }
5396
5397 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5398 const char **names,
5399 size_t *offsets)
5400 {
5401 int i;
5402 int j = 0;
5403
5404 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5405 names[j] = basic_q_cnts[i].name;
5406 offsets[j] = basic_q_cnts[i].offset;
5407 }
5408
5409 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5410 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5411 names[j] = out_of_seq_q_cnts[i].name;
5412 offsets[j] = out_of_seq_q_cnts[i].offset;
5413 }
5414 }
5415
5416 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5417 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5418 names[j] = retrans_q_cnts[i].name;
5419 offsets[j] = retrans_q_cnts[i].offset;
5420 }
5421 }
5422
5423 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5424 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5425 names[j] = extended_err_cnts[i].name;
5426 offsets[j] = extended_err_cnts[i].offset;
5427 }
5428 }
5429
5430 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5431 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5432 names[j] = cong_cnts[i].name;
5433 offsets[j] = cong_cnts[i].offset;
5434 }
5435 }
5436
5437 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5438 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5439 names[j] = ext_ppcnt_cnts[i].name;
5440 offsets[j] = ext_ppcnt_cnts[i].offset;
5441 }
5442 }
5443 }
5444
5445 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
5446 {
5447 int num_cnt_ports;
5448 int err = 0;
5449 int i;
5450 bool is_shared;
5451
5452 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
5453 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
5454
5455 for (i = 0; i < num_cnt_ports; i++) {
5456 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5457 if (err)
5458 goto err_alloc;
5459
5460 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5461 dev->port[i].cnts.offsets);
5462
5463 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5464 &dev->port[i].cnts.set_id,
5465 is_shared ?
5466 MLX5_SHARED_RESOURCE_UID : 0);
5467 if (err) {
5468 mlx5_ib_warn(dev,
5469 "couldn't allocate queue counter for port %d, err %d\n",
5470 i + 1, err);
5471 goto err_alloc;
5472 }
5473 dev->port[i].cnts.set_id_valid = true;
5474 }
5475 return 0;
5476
5477 err_alloc:
5478 mlx5_ib_dealloc_counters(dev);
5479 return err;
5480 }
5481
5482 static const struct mlx5_ib_counters *get_counters(struct mlx5_ib_dev *dev,
5483 u8 port_num)
5484 {
5485 return is_mdev_switchdev_mode(dev->mdev) ? &dev->port[0].cnts :
5486 &dev->port[port_num].cnts;
5487 }
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498 u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num)
5499 {
5500 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num);
5501
5502 return cnts->set_id;
5503 }
5504
5505 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5506 u8 port_num)
5507 {
5508 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5509 const struct mlx5_ib_counters *cnts;
5510 bool is_switchdev = is_mdev_switchdev_mode(dev->mdev);
5511
5512 if ((is_switchdev && port_num) || (!is_switchdev && !port_num))
5513 return NULL;
5514
5515 cnts = get_counters(dev, port_num - 1);
5516
5517 return rdma_alloc_hw_stats_struct(cnts->names,
5518 cnts->num_q_counters +
5519 cnts->num_cong_counters +
5520 cnts->num_ext_ppcnt_counters,
5521 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5522 }
5523
5524 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5525 const struct mlx5_ib_counters *cnts,
5526 struct rdma_hw_stats *stats,
5527 u16 set_id)
5528 {
5529 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5530 void *out;
5531 __be32 val;
5532 int ret, i;
5533
5534 out = kvzalloc(outlen, GFP_KERNEL);
5535 if (!out)
5536 return -ENOMEM;
5537
5538 ret = mlx5_core_query_q_counter(mdev, set_id, 0, out, outlen);
5539 if (ret)
5540 goto free;
5541
5542 for (i = 0; i < cnts->num_q_counters; i++) {
5543 val = *(__be32 *)(out + cnts->offsets[i]);
5544 stats->value[i] = (u64)be32_to_cpu(val);
5545 }
5546
5547 free:
5548 kvfree(out);
5549 return ret;
5550 }
5551
5552 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5553 const struct mlx5_ib_counters *cnts,
5554 struct rdma_hw_stats *stats)
5555 {
5556 int offset = cnts->num_q_counters + cnts->num_cong_counters;
5557 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5558 int ret, i;
5559 void *out;
5560
5561 out = kvzalloc(sz, GFP_KERNEL);
5562 if (!out)
5563 return -ENOMEM;
5564
5565 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5566 if (ret)
5567 goto free;
5568
5569 for (i = 0; i < cnts->num_ext_ppcnt_counters; i++)
5570 stats->value[i + offset] =
5571 be64_to_cpup((__be64 *)(out +
5572 cnts->offsets[i + offset]));
5573 free:
5574 kvfree(out);
5575 return ret;
5576 }
5577
5578 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5579 struct rdma_hw_stats *stats,
5580 u8 port_num, int index)
5581 {
5582 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5583 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num - 1);
5584 struct mlx5_core_dev *mdev;
5585 int ret, num_counters;
5586 u8 mdev_port_num;
5587
5588 if (!stats)
5589 return -EINVAL;
5590
5591 num_counters = cnts->num_q_counters +
5592 cnts->num_cong_counters +
5593 cnts->num_ext_ppcnt_counters;
5594
5595
5596 ret = mlx5_ib_query_q_counters(dev->mdev, cnts, stats, cnts->set_id);
5597 if (ret)
5598 return ret;
5599
5600 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5601 ret = mlx5_ib_query_ext_ppcnt_counters(dev, cnts, stats);
5602 if (ret)
5603 return ret;
5604 }
5605
5606 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5607 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5608 &mdev_port_num);
5609 if (!mdev) {
5610
5611
5612
5613
5614 goto done;
5615 }
5616 ret = mlx5_lag_query_cong_counters(dev->mdev,
5617 stats->value +
5618 cnts->num_q_counters,
5619 cnts->num_cong_counters,
5620 cnts->offsets +
5621 cnts->num_q_counters);
5622
5623 mlx5_ib_put_native_port_mdev(dev, port_num);
5624 if (ret)
5625 return ret;
5626 }
5627
5628 done:
5629 return num_counters;
5630 }
5631
5632 static struct rdma_hw_stats *
5633 mlx5_ib_counter_alloc_stats(struct rdma_counter *counter)
5634 {
5635 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5636 const struct mlx5_ib_counters *cnts =
5637 get_counters(dev, counter->port - 1);
5638
5639 return rdma_alloc_hw_stats_struct(cnts->names,
5640 cnts->num_q_counters +
5641 cnts->num_cong_counters +
5642 cnts->num_ext_ppcnt_counters,
5643 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5644 }
5645
5646 static int mlx5_ib_counter_update_stats(struct rdma_counter *counter)
5647 {
5648 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5649 const struct mlx5_ib_counters *cnts =
5650 get_counters(dev, counter->port - 1);
5651
5652 return mlx5_ib_query_q_counters(dev->mdev, cnts,
5653 counter->stats, counter->id);
5654 }
5655
5656 static int mlx5_ib_counter_bind_qp(struct rdma_counter *counter,
5657 struct ib_qp *qp)
5658 {
5659 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5660 u16 cnt_set_id = 0;
5661 int err;
5662
5663 if (!counter->id) {
5664 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5665 &cnt_set_id,
5666 MLX5_SHARED_RESOURCE_UID);
5667 if (err)
5668 return err;
5669 counter->id = cnt_set_id;
5670 }
5671
5672 err = mlx5_ib_qp_set_counter(qp, counter);
5673 if (err)
5674 goto fail_set_counter;
5675
5676 return 0;
5677
5678 fail_set_counter:
5679 mlx5_core_dealloc_q_counter(dev->mdev, cnt_set_id);
5680 counter->id = 0;
5681
5682 return err;
5683 }
5684
5685 static int mlx5_ib_counter_unbind_qp(struct ib_qp *qp)
5686 {
5687 return mlx5_ib_qp_set_counter(qp, NULL);
5688 }
5689
5690 static int mlx5_ib_counter_dealloc(struct rdma_counter *counter)
5691 {
5692 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5693
5694 return mlx5_core_dealloc_q_counter(dev->mdev, counter->id);
5695 }
5696
5697 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5698 enum rdma_netdev_t type,
5699 struct rdma_netdev_alloc_params *params)
5700 {
5701 if (type != RDMA_NETDEV_IPOIB)
5702 return -EOPNOTSUPP;
5703
5704 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
5705 }
5706
5707 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5708 {
5709 if (!dev->delay_drop.dbg)
5710 return;
5711 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5712 kfree(dev->delay_drop.dbg);
5713 dev->delay_drop.dbg = NULL;
5714 }
5715
5716 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5717 {
5718 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5719 return;
5720
5721 cancel_work_sync(&dev->delay_drop.delay_drop_work);
5722 delay_drop_debugfs_cleanup(dev);
5723 }
5724
5725 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5726 size_t count, loff_t *pos)
5727 {
5728 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5729 char lbuf[20];
5730 int len;
5731
5732 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5733 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5734 }
5735
5736 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5737 size_t count, loff_t *pos)
5738 {
5739 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5740 u32 timeout;
5741 u32 var;
5742
5743 if (kstrtouint_from_user(buf, count, 0, &var))
5744 return -EFAULT;
5745
5746 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5747 1000);
5748 if (timeout != var)
5749 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5750 timeout);
5751
5752 delay_drop->timeout = timeout;
5753
5754 return count;
5755 }
5756
5757 static const struct file_operations fops_delay_drop_timeout = {
5758 .owner = THIS_MODULE,
5759 .open = simple_open,
5760 .write = delay_drop_timeout_write,
5761 .read = delay_drop_timeout_read,
5762 };
5763
5764 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5765 {
5766 struct mlx5_ib_dbg_delay_drop *dbg;
5767
5768 if (!mlx5_debugfs_root)
5769 return 0;
5770
5771 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5772 if (!dbg)
5773 return -ENOMEM;
5774
5775 dev->delay_drop.dbg = dbg;
5776
5777 dbg->dir_debugfs =
5778 debugfs_create_dir("delay_drop",
5779 dev->mdev->priv.dbg_root);
5780 if (!dbg->dir_debugfs)
5781 goto out_debugfs;
5782
5783 dbg->events_cnt_debugfs =
5784 debugfs_create_atomic_t("num_timeout_events", 0400,
5785 dbg->dir_debugfs,
5786 &dev->delay_drop.events_cnt);
5787 if (!dbg->events_cnt_debugfs)
5788 goto out_debugfs;
5789
5790 dbg->rqs_cnt_debugfs =
5791 debugfs_create_atomic_t("num_rqs", 0400,
5792 dbg->dir_debugfs,
5793 &dev->delay_drop.rqs_cnt);
5794 if (!dbg->rqs_cnt_debugfs)
5795 goto out_debugfs;
5796
5797 dbg->timeout_debugfs =
5798 debugfs_create_file("timeout", 0600,
5799 dbg->dir_debugfs,
5800 &dev->delay_drop,
5801 &fops_delay_drop_timeout);
5802 if (!dbg->timeout_debugfs)
5803 goto out_debugfs;
5804
5805 return 0;
5806
5807 out_debugfs:
5808 delay_drop_debugfs_cleanup(dev);
5809 return -ENOMEM;
5810 }
5811
5812 static void init_delay_drop(struct mlx5_ib_dev *dev)
5813 {
5814 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5815 return;
5816
5817 mutex_init(&dev->delay_drop.lock);
5818 dev->delay_drop.dev = dev;
5819 dev->delay_drop.activate = false;
5820 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5821 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5822 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5823 atomic_set(&dev->delay_drop.events_cnt, 0);
5824
5825 if (delay_drop_debugfs_init(dev))
5826 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
5827 }
5828
5829 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5830 struct mlx5_ib_multiport_info *mpi)
5831 {
5832 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5833 struct mlx5_ib_port *port = &ibdev->port[port_num];
5834 int comps;
5835 int err;
5836 int i;
5837
5838 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5839
5840 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5841
5842 spin_lock(&port->mp.mpi_lock);
5843 if (!mpi->ibdev) {
5844 spin_unlock(&port->mp.mpi_lock);
5845 return;
5846 }
5847
5848 mpi->ibdev = NULL;
5849
5850 spin_unlock(&port->mp.mpi_lock);
5851 if (mpi->mdev_events.notifier_call)
5852 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5853 mpi->mdev_events.notifier_call = NULL;
5854 mlx5_remove_netdev_notifier(ibdev, port_num);
5855 spin_lock(&port->mp.mpi_lock);
5856
5857 comps = mpi->mdev_refcnt;
5858 if (comps) {
5859 mpi->unaffiliate = true;
5860 init_completion(&mpi->unref_comp);
5861 spin_unlock(&port->mp.mpi_lock);
5862
5863 for (i = 0; i < comps; i++)
5864 wait_for_completion(&mpi->unref_comp);
5865
5866 spin_lock(&port->mp.mpi_lock);
5867 mpi->unaffiliate = false;
5868 }
5869
5870 port->mp.mpi = NULL;
5871
5872 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5873
5874 spin_unlock(&port->mp.mpi_lock);
5875
5876 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5877
5878 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5879
5880
5881
5882 if (err)
5883 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5884 port_num + 1);
5885
5886 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
5887 }
5888
5889 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5890 struct mlx5_ib_multiport_info *mpi)
5891 {
5892 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5893 int err;
5894
5895 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5896
5897 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5898 if (ibdev->port[port_num].mp.mpi) {
5899 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5900 port_num + 1);
5901 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5902 return false;
5903 }
5904
5905 ibdev->port[port_num].mp.mpi = mpi;
5906 mpi->ibdev = ibdev;
5907 mpi->mdev_events.notifier_call = NULL;
5908 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5909
5910 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5911 if (err)
5912 goto unbind;
5913
5914 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5915 if (err)
5916 goto unbind;
5917
5918 err = mlx5_add_netdev_notifier(ibdev, port_num);
5919 if (err) {
5920 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5921 port_num + 1);
5922 goto unbind;
5923 }
5924
5925 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5926 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5927
5928 mlx5_ib_init_cong_debugfs(ibdev, port_num);
5929
5930 return true;
5931
5932 unbind:
5933 mlx5_ib_unbind_slave_port(ibdev, mpi);
5934 return false;
5935 }
5936
5937 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5938 {
5939 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5940 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5941 port_num + 1);
5942 struct mlx5_ib_multiport_info *mpi;
5943 int err;
5944 int i;
5945
5946 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5947 return 0;
5948
5949 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5950 &dev->sys_image_guid);
5951 if (err)
5952 return err;
5953
5954 err = mlx5_nic_vport_enable_roce(dev->mdev);
5955 if (err)
5956 return err;
5957
5958 mutex_lock(&mlx5_ib_multiport_mutex);
5959 for (i = 0; i < dev->num_ports; i++) {
5960 bool bound = false;
5961
5962
5963 if (i == port_num) {
5964 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5965 if (!mpi) {
5966 mutex_unlock(&mlx5_ib_multiport_mutex);
5967 mlx5_nic_vport_disable_roce(dev->mdev);
5968 return -ENOMEM;
5969 }
5970
5971 mpi->is_master = true;
5972 mpi->mdev = dev->mdev;
5973 mpi->sys_image_guid = dev->sys_image_guid;
5974 dev->port[i].mp.mpi = mpi;
5975 mpi->ibdev = dev;
5976 mpi = NULL;
5977 continue;
5978 }
5979
5980 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5981 list) {
5982 if (dev->sys_image_guid == mpi->sys_image_guid &&
5983 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5984 bound = mlx5_ib_bind_slave_port(dev, mpi);
5985 }
5986
5987 if (bound) {
5988 dev_dbg(mpi->mdev->device,
5989 "removing port from unaffiliated list.\n");
5990 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5991 list_del(&mpi->list);
5992 break;
5993 }
5994 }
5995 if (!bound) {
5996 get_port_caps(dev, i + 1);
5997 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5998 i + 1);
5999 }
6000 }
6001
6002 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
6003 mutex_unlock(&mlx5_ib_multiport_mutex);
6004 return err;
6005 }
6006
6007 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
6008 {
6009 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6010 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
6011 port_num + 1);
6012 int i;
6013
6014 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
6015 return;
6016
6017 mutex_lock(&mlx5_ib_multiport_mutex);
6018 for (i = 0; i < dev->num_ports; i++) {
6019 if (dev->port[i].mp.mpi) {
6020
6021 if (i == port_num) {
6022 kfree(dev->port[i].mp.mpi);
6023 dev->port[i].mp.mpi = NULL;
6024 } else {
6025 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
6026 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
6027 }
6028 }
6029 }
6030
6031 mlx5_ib_dbg(dev, "removing from devlist\n");
6032 list_del(&dev->ib_dev_list);
6033 mutex_unlock(&mlx5_ib_multiport_mutex);
6034
6035 mlx5_nic_vport_disable_roce(dev->mdev);
6036 }
6037
6038 ADD_UVERBS_ATTRIBUTES_SIMPLE(
6039 mlx5_ib_dm,
6040 UVERBS_OBJECT_DM,
6041 UVERBS_METHOD_DM_ALLOC,
6042 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
6043 UVERBS_ATTR_TYPE(u64),
6044 UA_MANDATORY),
6045 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
6046 UVERBS_ATTR_TYPE(u16),
6047 UA_OPTIONAL),
6048 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
6049 enum mlx5_ib_uapi_dm_type,
6050 UA_OPTIONAL));
6051
6052 ADD_UVERBS_ATTRIBUTES_SIMPLE(
6053 mlx5_ib_flow_action,
6054 UVERBS_OBJECT_FLOW_ACTION,
6055 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
6056 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
6057 enum mlx5_ib_uapi_flow_action_flags));
6058
6059 static const struct uapi_definition mlx5_ib_defs[] = {
6060 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
6061 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
6062 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
6063 #endif
6064
6065 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
6066 &mlx5_ib_flow_action),
6067 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
6068 {}
6069 };
6070
6071 static int mlx5_ib_read_counters(struct ib_counters *counters,
6072 struct ib_counters_read_attr *read_attr,
6073 struct uverbs_attr_bundle *attrs)
6074 {
6075 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6076 struct mlx5_read_counters_attr mread_attr = {};
6077 struct mlx5_ib_flow_counters_desc *desc;
6078 int ret, i;
6079
6080 mutex_lock(&mcounters->mcntrs_mutex);
6081 if (mcounters->cntrs_max_index > read_attr->ncounters) {
6082 ret = -EINVAL;
6083 goto err_bound;
6084 }
6085
6086 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
6087 GFP_KERNEL);
6088 if (!mread_attr.out) {
6089 ret = -ENOMEM;
6090 goto err_bound;
6091 }
6092
6093 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
6094 mread_attr.flags = read_attr->flags;
6095 ret = mcounters->read_counters(counters->device, &mread_attr);
6096 if (ret)
6097 goto err_read;
6098
6099
6100
6101
6102 desc = mcounters->counters_data;
6103 for (i = 0; i < mcounters->ncounters; i++)
6104 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
6105
6106 err_read:
6107 kfree(mread_attr.out);
6108 err_bound:
6109 mutex_unlock(&mcounters->mcntrs_mutex);
6110 return ret;
6111 }
6112
6113 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
6114 {
6115 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6116
6117 counters_clear_description(counters);
6118 if (mcounters->hw_cntrs_hndl)
6119 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
6120 mcounters->hw_cntrs_hndl);
6121
6122 kfree(mcounters);
6123
6124 return 0;
6125 }
6126
6127 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
6128 struct uverbs_attr_bundle *attrs)
6129 {
6130 struct mlx5_ib_mcounters *mcounters;
6131
6132 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
6133 if (!mcounters)
6134 return ERR_PTR(-ENOMEM);
6135
6136 mutex_init(&mcounters->mcntrs_mutex);
6137
6138 return &mcounters->ibcntrs;
6139 }
6140
6141 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
6142 {
6143 mlx5_ib_cleanup_multiport_master(dev);
6144 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
6145 srcu_barrier(&dev->mr_srcu);
6146 cleanup_srcu_struct(&dev->mr_srcu);
6147 }
6148
6149 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
6150 }
6151
6152 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
6153 {
6154 struct mlx5_core_dev *mdev = dev->mdev;
6155 int err;
6156 int i;
6157
6158 for (i = 0; i < dev->num_ports; i++) {
6159 spin_lock_init(&dev->port[i].mp.mpi_lock);
6160 rwlock_init(&dev->port[i].roce.netdev_lock);
6161 dev->port[i].roce.dev = dev;
6162 dev->port[i].roce.native_port_num = i + 1;
6163 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
6164 }
6165
6166 mlx5_ib_internal_fill_odp_caps(dev);
6167
6168 err = mlx5_ib_init_multiport_master(dev);
6169 if (err)
6170 return err;
6171
6172 err = set_has_smi_cap(dev);
6173 if (err)
6174 return err;
6175
6176 if (!mlx5_core_mp_enabled(mdev)) {
6177 for (i = 1; i <= dev->num_ports; i++) {
6178 err = get_port_caps(dev, i);
6179 if (err)
6180 break;
6181 }
6182 } else {
6183 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6184 }
6185 if (err)
6186 goto err_mp;
6187
6188 if (mlx5_use_mad_ifc(dev))
6189 get_ext_port_caps(dev);
6190
6191 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
6192 dev->ib_dev.local_dma_lkey = 0 ;
6193 dev->ib_dev.phys_port_cnt = dev->num_ports;
6194 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
6195 dev->ib_dev.dev.parent = mdev->device;
6196
6197 mutex_init(&dev->cap_mask_mutex);
6198 INIT_LIST_HEAD(&dev->qp_list);
6199 spin_lock_init(&dev->reset_flow_resource_lock);
6200
6201 spin_lock_init(&dev->dm.lock);
6202 dev->dm.dev = mdev;
6203
6204 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
6205 err = init_srcu_struct(&dev->mr_srcu);
6206 if (err)
6207 goto err_mp;
6208 }
6209
6210 return 0;
6211
6212 err_mp:
6213 mlx5_ib_cleanup_multiport_master(dev);
6214
6215 return -ENOMEM;
6216 }
6217
6218 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6219 {
6220 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6221
6222 if (!dev->flow_db)
6223 return -ENOMEM;
6224
6225 mutex_init(&dev->flow_db->lock);
6226
6227 return 0;
6228 }
6229
6230 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6231 {
6232 kfree(dev->flow_db);
6233 }
6234
6235 static const struct ib_device_ops mlx5_ib_dev_ops = {
6236 .owner = THIS_MODULE,
6237 .driver_id = RDMA_DRIVER_MLX5,
6238 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
6239
6240 .add_gid = mlx5_ib_add_gid,
6241 .alloc_mr = mlx5_ib_alloc_mr,
6242 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
6243 .alloc_pd = mlx5_ib_alloc_pd,
6244 .alloc_ucontext = mlx5_ib_alloc_ucontext,
6245 .attach_mcast = mlx5_ib_mcg_attach,
6246 .check_mr_status = mlx5_ib_check_mr_status,
6247 .create_ah = mlx5_ib_create_ah,
6248 .create_counters = mlx5_ib_create_counters,
6249 .create_cq = mlx5_ib_create_cq,
6250 .create_flow = mlx5_ib_create_flow,
6251 .create_qp = mlx5_ib_create_qp,
6252 .create_srq = mlx5_ib_create_srq,
6253 .dealloc_pd = mlx5_ib_dealloc_pd,
6254 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6255 .del_gid = mlx5_ib_del_gid,
6256 .dereg_mr = mlx5_ib_dereg_mr,
6257 .destroy_ah = mlx5_ib_destroy_ah,
6258 .destroy_counters = mlx5_ib_destroy_counters,
6259 .destroy_cq = mlx5_ib_destroy_cq,
6260 .destroy_flow = mlx5_ib_destroy_flow,
6261 .destroy_flow_action = mlx5_ib_destroy_flow_action,
6262 .destroy_qp = mlx5_ib_destroy_qp,
6263 .destroy_srq = mlx5_ib_destroy_srq,
6264 .detach_mcast = mlx5_ib_mcg_detach,
6265 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6266 .drain_rq = mlx5_ib_drain_rq,
6267 .drain_sq = mlx5_ib_drain_sq,
6268 .get_dev_fw_str = get_dev_fw_str,
6269 .get_dma_mr = mlx5_ib_get_dma_mr,
6270 .get_link_layer = mlx5_ib_port_link_layer,
6271 .map_mr_sg = mlx5_ib_map_mr_sg,
6272 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
6273 .mmap = mlx5_ib_mmap,
6274 .modify_cq = mlx5_ib_modify_cq,
6275 .modify_device = mlx5_ib_modify_device,
6276 .modify_port = mlx5_ib_modify_port,
6277 .modify_qp = mlx5_ib_modify_qp,
6278 .modify_srq = mlx5_ib_modify_srq,
6279 .poll_cq = mlx5_ib_poll_cq,
6280 .post_recv = mlx5_ib_post_recv,
6281 .post_send = mlx5_ib_post_send,
6282 .post_srq_recv = mlx5_ib_post_srq_recv,
6283 .process_mad = mlx5_ib_process_mad,
6284 .query_ah = mlx5_ib_query_ah,
6285 .query_device = mlx5_ib_query_device,
6286 .query_gid = mlx5_ib_query_gid,
6287 .query_pkey = mlx5_ib_query_pkey,
6288 .query_qp = mlx5_ib_query_qp,
6289 .query_srq = mlx5_ib_query_srq,
6290 .read_counters = mlx5_ib_read_counters,
6291 .reg_user_mr = mlx5_ib_reg_user_mr,
6292 .req_notify_cq = mlx5_ib_arm_cq,
6293 .rereg_user_mr = mlx5_ib_rereg_user_mr,
6294 .resize_cq = mlx5_ib_resize_cq,
6295
6296 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
6297 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
6298 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
6299 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
6300 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
6301 };
6302
6303 static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6304 .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6305 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6306 };
6307
6308 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6309 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6310 };
6311
6312 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6313 .get_vf_config = mlx5_ib_get_vf_config,
6314 .get_vf_stats = mlx5_ib_get_vf_stats,
6315 .set_vf_guid = mlx5_ib_set_vf_guid,
6316 .set_vf_link_state = mlx5_ib_set_vf_link_state,
6317 };
6318
6319 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6320 .alloc_mw = mlx5_ib_alloc_mw,
6321 .dealloc_mw = mlx5_ib_dealloc_mw,
6322 };
6323
6324 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6325 .alloc_xrcd = mlx5_ib_alloc_xrcd,
6326 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6327 };
6328
6329 static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6330 .alloc_dm = mlx5_ib_alloc_dm,
6331 .dealloc_dm = mlx5_ib_dealloc_dm,
6332 .reg_dm_mr = mlx5_ib_reg_dm_mr,
6333 };
6334
6335 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
6336 {
6337 struct mlx5_core_dev *mdev = dev->mdev;
6338 int err;
6339
6340 dev->ib_dev.uverbs_cmd_mask =
6341 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
6342 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
6343 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
6344 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
6345 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
6346 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
6347 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
6348 (1ull << IB_USER_VERBS_CMD_REG_MR) |
6349 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
6350 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
6351 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6352 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
6353 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
6354 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
6355 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
6356 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6357 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
6358 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
6359 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
6360 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
6361 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
6362 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
6363 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
6364 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
6365 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
6366 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
6367 dev->ib_dev.uverbs_ex_cmd_mask =
6368 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
6369 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
6370 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
6371 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
6372 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
6373 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
6374 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6375
6376 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6377 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
6378 ib_set_device_ops(&dev->ib_dev,
6379 &mlx5_ib_dev_ipoib_enhanced_ops);
6380
6381 if (mlx5_core_is_pf(mdev))
6382 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
6383
6384 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6385
6386 if (MLX5_CAP_GEN(mdev, imaicl)) {
6387 dev->ib_dev.uverbs_cmd_mask |=
6388 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
6389 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
6390 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
6391 }
6392
6393 if (MLX5_CAP_GEN(mdev, xrc)) {
6394 dev->ib_dev.uverbs_cmd_mask |=
6395 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6396 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
6397 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
6398 }
6399
6400 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6401 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6402 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
6403 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
6404
6405 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
6406 MLX5_ACCEL_IPSEC_CAP_DEVICE)
6407 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
6408 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
6409
6410 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6411 dev->ib_dev.driver_def = mlx5_ib_defs;
6412
6413 err = init_node_data(dev);
6414 if (err)
6415 return err;
6416
6417 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
6418 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6419 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
6420 mutex_init(&dev->lb.mutex);
6421
6422 dev->ib_dev.use_cq_dim = true;
6423
6424 return 0;
6425 }
6426
6427 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6428 .get_port_immutable = mlx5_port_immutable,
6429 .query_port = mlx5_ib_query_port,
6430 };
6431
6432 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6433 {
6434 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
6435 return 0;
6436 }
6437
6438 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6439 .get_port_immutable = mlx5_port_rep_immutable,
6440 .query_port = mlx5_ib_rep_query_port,
6441 };
6442
6443 static int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
6444 {
6445 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
6446 return 0;
6447 }
6448
6449 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6450 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6451 .create_wq = mlx5_ib_create_wq,
6452 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6453 .destroy_wq = mlx5_ib_destroy_wq,
6454 .get_netdev = mlx5_ib_get_netdev,
6455 .modify_wq = mlx5_ib_modify_wq,
6456 };
6457
6458 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
6459 {
6460 u8 port_num;
6461
6462 dev->ib_dev.uverbs_ex_cmd_mask |=
6463 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6464 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6465 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6466 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6467 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
6468 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
6469
6470 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6471
6472
6473 return mlx5_add_netdev_notifier(dev, port_num);
6474 }
6475
6476 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6477 {
6478 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6479
6480 mlx5_remove_netdev_notifier(dev, port_num);
6481 }
6482
6483 static int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
6484 {
6485 struct mlx5_core_dev *mdev = dev->mdev;
6486 enum rdma_link_layer ll;
6487 int port_type_cap;
6488 int err = 0;
6489
6490 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6491 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6492
6493 if (ll == IB_LINK_LAYER_ETHERNET)
6494 err = mlx5_ib_stage_common_roce_init(dev);
6495
6496 return err;
6497 }
6498
6499 static void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
6500 {
6501 mlx5_ib_stage_common_roce_cleanup(dev);
6502 }
6503
6504 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6505 {
6506 struct mlx5_core_dev *mdev = dev->mdev;
6507 enum rdma_link_layer ll;
6508 int port_type_cap;
6509 int err;
6510
6511 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6512 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6513
6514 if (ll == IB_LINK_LAYER_ETHERNET) {
6515 err = mlx5_ib_stage_common_roce_init(dev);
6516 if (err)
6517 return err;
6518
6519 err = mlx5_enable_eth(dev);
6520 if (err)
6521 goto cleanup;
6522 }
6523
6524 return 0;
6525 cleanup:
6526 mlx5_ib_stage_common_roce_cleanup(dev);
6527
6528 return err;
6529 }
6530
6531 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6532 {
6533 struct mlx5_core_dev *mdev = dev->mdev;
6534 enum rdma_link_layer ll;
6535 int port_type_cap;
6536
6537 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6538 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6539
6540 if (ll == IB_LINK_LAYER_ETHERNET) {
6541 mlx5_disable_eth(dev);
6542 mlx5_ib_stage_common_roce_cleanup(dev);
6543 }
6544 }
6545
6546 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
6547 {
6548 return create_dev_resources(&dev->devr);
6549 }
6550
6551 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
6552 {
6553 destroy_dev_resources(&dev->devr);
6554 }
6555
6556 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6557 {
6558 return mlx5_ib_odp_init_one(dev);
6559 }
6560
6561 static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
6562 {
6563 mlx5_ib_odp_cleanup_one(dev);
6564 }
6565
6566 static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6567 .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6568 .get_hw_stats = mlx5_ib_get_hw_stats,
6569 .counter_bind_qp = mlx5_ib_counter_bind_qp,
6570 .counter_unbind_qp = mlx5_ib_counter_unbind_qp,
6571 .counter_dealloc = mlx5_ib_counter_dealloc,
6572 .counter_alloc_stats = mlx5_ib_counter_alloc_stats,
6573 .counter_update_stats = mlx5_ib_counter_update_stats,
6574 };
6575
6576 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
6577 {
6578 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6579 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
6580
6581 return mlx5_ib_alloc_counters(dev);
6582 }
6583
6584 return 0;
6585 }
6586
6587 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
6588 {
6589 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6590 mlx5_ib_dealloc_counters(dev);
6591 }
6592
6593 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6594 {
6595 mlx5_ib_init_cong_debugfs(dev,
6596 mlx5_core_native_port_num(dev->mdev) - 1);
6597 return 0;
6598 }
6599
6600 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6601 {
6602 mlx5_ib_cleanup_cong_debugfs(dev,
6603 mlx5_core_native_port_num(dev->mdev) - 1);
6604 }
6605
6606 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6607 {
6608 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
6609 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
6610 }
6611
6612 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6613 {
6614 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6615 }
6616
6617 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
6618 {
6619 int err;
6620
6621 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6622 if (err)
6623 return err;
6624
6625 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6626 if (err)
6627 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6628
6629 return err;
6630 }
6631
6632 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
6633 {
6634 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6635 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6636 }
6637
6638 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
6639 {
6640 const char *name;
6641
6642 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
6643 if (!mlx5_lag_is_roce(dev->mdev))
6644 name = "mlx5_%d";
6645 else
6646 name = "mlx5_bond_%d";
6647 return ib_register_device(&dev->ib_dev, name);
6648 }
6649
6650 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
6651 {
6652 destroy_umrc_res(dev);
6653 }
6654
6655 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
6656 {
6657 ib_unregister_device(&dev->ib_dev);
6658 }
6659
6660 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
6661 {
6662 return create_umr_res(dev);
6663 }
6664
6665 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6666 {
6667 init_delay_drop(dev);
6668
6669 return 0;
6670 }
6671
6672 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6673 {
6674 cancel_delay_drop(dev);
6675 }
6676
6677 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6678 {
6679 dev->mdev_events.notifier_call = mlx5_ib_event;
6680 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6681 return 0;
6682 }
6683
6684 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6685 {
6686 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6687 }
6688
6689 static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6690 {
6691 int uid;
6692
6693 uid = mlx5_ib_devx_create(dev, false);
6694 if (uid > 0) {
6695 dev->devx_whitelist_uid = uid;
6696 mlx5_ib_devx_init_event_table(dev);
6697 }
6698
6699 return 0;
6700 }
6701 static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6702 {
6703 if (dev->devx_whitelist_uid) {
6704 mlx5_ib_devx_cleanup_event_table(dev);
6705 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
6706 }
6707 }
6708
6709 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6710 const struct mlx5_ib_profile *profile,
6711 int stage)
6712 {
6713
6714 while (stage) {
6715 stage--;
6716 if (profile->stage[stage].cleanup)
6717 profile->stage[stage].cleanup(dev);
6718 }
6719
6720 kfree(dev->port);
6721 ib_dealloc_device(&dev->ib_dev);
6722 }
6723
6724 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6725 const struct mlx5_ib_profile *profile)
6726 {
6727 int err;
6728 int i;
6729
6730 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6731 if (profile->stage[i].init) {
6732 err = profile->stage[i].init(dev);
6733 if (err)
6734 goto err_out;
6735 }
6736 }
6737
6738 dev->profile = profile;
6739 dev->ib_active = true;
6740
6741 return dev;
6742
6743 err_out:
6744 __mlx5_ib_remove(dev, profile, i);
6745
6746 return NULL;
6747 }
6748
6749 static const struct mlx5_ib_profile pf_profile = {
6750 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6751 mlx5_ib_stage_init_init,
6752 mlx5_ib_stage_init_cleanup),
6753 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6754 mlx5_ib_stage_flow_db_init,
6755 mlx5_ib_stage_flow_db_cleanup),
6756 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6757 mlx5_ib_stage_caps_init,
6758 NULL),
6759 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6760 mlx5_ib_stage_non_default_cb,
6761 NULL),
6762 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6763 mlx5_ib_stage_roce_init,
6764 mlx5_ib_stage_roce_cleanup),
6765 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6766 mlx5_init_srq_table,
6767 mlx5_cleanup_srq_table),
6768 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6769 mlx5_ib_stage_dev_res_init,
6770 mlx5_ib_stage_dev_res_cleanup),
6771 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6772 mlx5_ib_stage_dev_notifier_init,
6773 mlx5_ib_stage_dev_notifier_cleanup),
6774 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6775 mlx5_ib_stage_odp_init,
6776 mlx5_ib_stage_odp_cleanup),
6777 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6778 mlx5_ib_stage_counters_init,
6779 mlx5_ib_stage_counters_cleanup),
6780 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6781 mlx5_ib_stage_cong_debugfs_init,
6782 mlx5_ib_stage_cong_debugfs_cleanup),
6783 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6784 mlx5_ib_stage_uar_init,
6785 mlx5_ib_stage_uar_cleanup),
6786 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6787 mlx5_ib_stage_bfrag_init,
6788 mlx5_ib_stage_bfrag_cleanup),
6789 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6790 NULL,
6791 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6792 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6793 mlx5_ib_stage_devx_init,
6794 mlx5_ib_stage_devx_cleanup),
6795 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6796 mlx5_ib_stage_ib_reg_init,
6797 mlx5_ib_stage_ib_reg_cleanup),
6798 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6799 mlx5_ib_stage_post_ib_reg_umr_init,
6800 NULL),
6801 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6802 mlx5_ib_stage_delay_drop_init,
6803 mlx5_ib_stage_delay_drop_cleanup),
6804 };
6805
6806 const struct mlx5_ib_profile uplink_rep_profile = {
6807 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6808 mlx5_ib_stage_init_init,
6809 mlx5_ib_stage_init_cleanup),
6810 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6811 mlx5_ib_stage_flow_db_init,
6812 mlx5_ib_stage_flow_db_cleanup),
6813 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6814 mlx5_ib_stage_caps_init,
6815 NULL),
6816 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6817 mlx5_ib_stage_rep_non_default_cb,
6818 NULL),
6819 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6820 mlx5_ib_stage_rep_roce_init,
6821 mlx5_ib_stage_rep_roce_cleanup),
6822 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6823 mlx5_init_srq_table,
6824 mlx5_cleanup_srq_table),
6825 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6826 mlx5_ib_stage_dev_res_init,
6827 mlx5_ib_stage_dev_res_cleanup),
6828 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6829 mlx5_ib_stage_dev_notifier_init,
6830 mlx5_ib_stage_dev_notifier_cleanup),
6831 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6832 mlx5_ib_stage_counters_init,
6833 mlx5_ib_stage_counters_cleanup),
6834 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6835 mlx5_ib_stage_uar_init,
6836 mlx5_ib_stage_uar_cleanup),
6837 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6838 mlx5_ib_stage_bfrag_init,
6839 mlx5_ib_stage_bfrag_cleanup),
6840 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6841 NULL,
6842 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6843 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6844 mlx5_ib_stage_devx_init,
6845 mlx5_ib_stage_devx_cleanup),
6846 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6847 mlx5_ib_stage_ib_reg_init,
6848 mlx5_ib_stage_ib_reg_cleanup),
6849 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6850 mlx5_ib_stage_post_ib_reg_umr_init,
6851 NULL),
6852 };
6853
6854 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
6855 {
6856 struct mlx5_ib_multiport_info *mpi;
6857 struct mlx5_ib_dev *dev;
6858 bool bound = false;
6859 int err;
6860
6861 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6862 if (!mpi)
6863 return NULL;
6864
6865 mpi->mdev = mdev;
6866
6867 err = mlx5_query_nic_vport_system_image_guid(mdev,
6868 &mpi->sys_image_guid);
6869 if (err) {
6870 kfree(mpi);
6871 return NULL;
6872 }
6873
6874 mutex_lock(&mlx5_ib_multiport_mutex);
6875 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6876 if (dev->sys_image_guid == mpi->sys_image_guid)
6877 bound = mlx5_ib_bind_slave_port(dev, mpi);
6878
6879 if (bound) {
6880 rdma_roce_rescan_device(&dev->ib_dev);
6881 break;
6882 }
6883 }
6884
6885 if (!bound) {
6886 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6887 dev_dbg(mdev->device,
6888 "no suitable IB device found to bind to, added to unaffiliated list.\n");
6889 }
6890 mutex_unlock(&mlx5_ib_multiport_mutex);
6891
6892 return mpi;
6893 }
6894
6895 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6896 {
6897 enum rdma_link_layer ll;
6898 struct mlx5_ib_dev *dev;
6899 int port_type_cap;
6900 int num_ports;
6901
6902 printk_once(KERN_INFO "%s", mlx5_version);
6903
6904 if (MLX5_ESWITCH_MANAGER(mdev) &&
6905 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
6906 if (!mlx5_core_mp_enabled(mdev))
6907 mlx5_ib_register_vport_reps(mdev);
6908 return mdev;
6909 }
6910
6911 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6912 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6913
6914 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6915 return mlx5_ib_add_slave_port(mdev);
6916
6917 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6918 MLX5_CAP_GEN(mdev, num_vhca_ports));
6919 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
6920 if (!dev)
6921 return NULL;
6922 dev->port = kcalloc(num_ports, sizeof(*dev->port),
6923 GFP_KERNEL);
6924 if (!dev->port) {
6925 ib_dealloc_device(&dev->ib_dev);
6926 return NULL;
6927 }
6928
6929 dev->mdev = mdev;
6930 dev->num_ports = num_ports;
6931
6932 return __mlx5_ib_add(dev, &pf_profile);
6933 }
6934
6935 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
6936 {
6937 struct mlx5_ib_multiport_info *mpi;
6938 struct mlx5_ib_dev *dev;
6939
6940 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
6941 mlx5_ib_unregister_vport_reps(mdev);
6942 return;
6943 }
6944
6945 if (mlx5_core_is_mp_slave(mdev)) {
6946 mpi = context;
6947 mutex_lock(&mlx5_ib_multiport_mutex);
6948 if (mpi->ibdev)
6949 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6950 list_del(&mpi->list);
6951 mutex_unlock(&mlx5_ib_multiport_mutex);
6952 kfree(mpi);
6953 return;
6954 }
6955
6956 dev = context;
6957 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6958 }
6959
6960 static struct mlx5_interface mlx5_ib_interface = {
6961 .add = mlx5_ib_add,
6962 .remove = mlx5_ib_remove,
6963 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
6964 };
6965
6966 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6967 {
6968 mutex_lock(&xlt_emergency_page_mutex);
6969 return xlt_emergency_page;
6970 }
6971
6972 void mlx5_ib_put_xlt_emergency_page(void)
6973 {
6974 mutex_unlock(&xlt_emergency_page_mutex);
6975 }
6976
6977 static int __init mlx5_ib_init(void)
6978 {
6979 int err;
6980
6981 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6982 if (!xlt_emergency_page)
6983 return -ENOMEM;
6984
6985 mutex_init(&xlt_emergency_page_mutex);
6986
6987 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6988 if (!mlx5_ib_event_wq) {
6989 free_page(xlt_emergency_page);
6990 return -ENOMEM;
6991 }
6992
6993 mlx5_ib_odp_init();
6994
6995 err = mlx5_register_interface(&mlx5_ib_interface);
6996
6997 return err;
6998 }
6999
7000 static void __exit mlx5_ib_cleanup(void)
7001 {
7002 mlx5_unregister_interface(&mlx5_ib_interface);
7003 destroy_workqueue(mlx5_ib_event_wq);
7004 mutex_destroy(&xlt_emergency_page_mutex);
7005 free_page(xlt_emergency_page);
7006 }
7007
7008 module_init(mlx5_ib_init);
7009 module_exit(mlx5_ib_cleanup);