This source file includes following definitions.
- mlx5_ib_cq_comp
- mlx5_ib_cq_event
- get_cqe
- sw_ownership_bit
- get_sw_cqe
- next_cqe_sw
- get_umr_comp
- handle_good_req
- handle_responder
- dump_cqe
- mlx5_handle_error_cqe
- handle_atomics
- free_cq_buf
- get_sig_err_item
- sw_comp
- mlx5_ib_poll_sw_comp
- mlx5_poll_one
- poll_soft_wc
- mlx5_ib_poll_cq
- mlx5_ib_arm_cq
- alloc_cq_frag_buf
- mini_cqe_res_format_to_hw
- create_cq_user
- destroy_cq_user
- init_cq_frag_buf
- create_cq_kernel
- destroy_cq_kernel
- notify_soft_wc_handler
- mlx5_ib_create_cq
- mlx5_ib_destroy_cq
- is_equal_rsn
- __mlx5_ib_cq_clean
- mlx5_ib_cq_clean
- mlx5_ib_modify_cq
- resize_user
- resize_kernel
- copy_resize_cqes
- mlx5_ib_resize_cq
- mlx5_ib_get_cqe_size
- mlx5_ib_generate_wc
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33 #include <linux/kref.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_user_verbs.h>
36 #include <rdma/ib_cache.h>
37 #include "mlx5_ib.h"
38 #include "srq.h"
39
40 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe)
41 {
42 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
43
44 ibcq->comp_handler(ibcq, ibcq->cq_context);
45 }
46
47 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
48 {
49 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
50 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
51 struct ib_cq *ibcq = &cq->ibcq;
52 struct ib_event event;
53
54 if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
55 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
56 type, mcq->cqn);
57 return;
58 }
59
60 if (ibcq->event_handler) {
61 event.device = &dev->ib_dev;
62 event.event = IB_EVENT_CQ_ERR;
63 event.element.cq = ibcq;
64 ibcq->event_handler(&event, ibcq->cq_context);
65 }
66 }
67
68 static void *get_cqe(struct mlx5_ib_cq *cq, int n)
69 {
70 return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n);
71 }
72
73 static u8 sw_ownership_bit(int n, int nent)
74 {
75 return (n & nent) ? 1 : 0;
76 }
77
78 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
79 {
80 void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
81 struct mlx5_cqe64 *cqe64;
82
83 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
84
85 if (likely(get_cqe_opcode(cqe64) != MLX5_CQE_INVALID) &&
86 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
87 return cqe;
88 } else {
89 return NULL;
90 }
91 }
92
93 static void *next_cqe_sw(struct mlx5_ib_cq *cq)
94 {
95 return get_sw_cqe(cq, cq->mcq.cons_index);
96 }
97
98 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
99 {
100 switch (wq->wr_data[idx]) {
101 case MLX5_IB_WR_UMR:
102 return 0;
103
104 case IB_WR_LOCAL_INV:
105 return IB_WC_LOCAL_INV;
106
107 case IB_WR_REG_MR:
108 return IB_WC_REG_MR;
109
110 default:
111 pr_warn("unknown completion status\n");
112 return 0;
113 }
114 }
115
116 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
117 struct mlx5_ib_wq *wq, int idx)
118 {
119 wc->wc_flags = 0;
120 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
121 case MLX5_OPCODE_RDMA_WRITE_IMM:
122 wc->wc_flags |= IB_WC_WITH_IMM;
123
124 case MLX5_OPCODE_RDMA_WRITE:
125 wc->opcode = IB_WC_RDMA_WRITE;
126 break;
127 case MLX5_OPCODE_SEND_IMM:
128 wc->wc_flags |= IB_WC_WITH_IMM;
129
130 case MLX5_OPCODE_SEND:
131 case MLX5_OPCODE_SEND_INVAL:
132 wc->opcode = IB_WC_SEND;
133 break;
134 case MLX5_OPCODE_RDMA_READ:
135 wc->opcode = IB_WC_RDMA_READ;
136 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
137 break;
138 case MLX5_OPCODE_ATOMIC_CS:
139 wc->opcode = IB_WC_COMP_SWAP;
140 wc->byte_len = 8;
141 break;
142 case MLX5_OPCODE_ATOMIC_FA:
143 wc->opcode = IB_WC_FETCH_ADD;
144 wc->byte_len = 8;
145 break;
146 case MLX5_OPCODE_ATOMIC_MASKED_CS:
147 wc->opcode = IB_WC_MASKED_COMP_SWAP;
148 wc->byte_len = 8;
149 break;
150 case MLX5_OPCODE_ATOMIC_MASKED_FA:
151 wc->opcode = IB_WC_MASKED_FETCH_ADD;
152 wc->byte_len = 8;
153 break;
154 case MLX5_OPCODE_UMR:
155 wc->opcode = get_umr_comp(wq, idx);
156 break;
157 }
158 }
159
160 enum {
161 MLX5_GRH_IN_BUFFER = 1,
162 MLX5_GRH_IN_CQE = 2,
163 };
164
165 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
166 struct mlx5_ib_qp *qp)
167 {
168 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
169 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
170 struct mlx5_ib_srq *srq;
171 struct mlx5_ib_wq *wq;
172 u16 wqe_ctr;
173 u8 roce_packet_type;
174 bool vlan_present;
175 u8 g;
176
177 if (qp->ibqp.srq || qp->ibqp.xrcd) {
178 struct mlx5_core_srq *msrq = NULL;
179
180 if (qp->ibqp.xrcd) {
181 msrq = mlx5_cmd_get_srq(dev, be32_to_cpu(cqe->srqn));
182 srq = to_mibsrq(msrq);
183 } else {
184 srq = to_msrq(qp->ibqp.srq);
185 }
186 if (srq) {
187 wqe_ctr = be16_to_cpu(cqe->wqe_counter);
188 wc->wr_id = srq->wrid[wqe_ctr];
189 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
190 if (msrq)
191 mlx5_core_res_put(&msrq->common);
192 }
193 } else {
194 wq = &qp->rq;
195 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
196 ++wq->tail;
197 }
198 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
199
200 switch (get_cqe_opcode(cqe)) {
201 case MLX5_CQE_RESP_WR_IMM:
202 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
203 wc->wc_flags = IB_WC_WITH_IMM;
204 wc->ex.imm_data = cqe->imm_inval_pkey;
205 break;
206 case MLX5_CQE_RESP_SEND:
207 wc->opcode = IB_WC_RECV;
208 wc->wc_flags = IB_WC_IP_CSUM_OK;
209 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
210 (cqe->hds_ip_ext & CQE_L4_OK))))
211 wc->wc_flags = 0;
212 break;
213 case MLX5_CQE_RESP_SEND_IMM:
214 wc->opcode = IB_WC_RECV;
215 wc->wc_flags = IB_WC_WITH_IMM;
216 wc->ex.imm_data = cqe->imm_inval_pkey;
217 break;
218 case MLX5_CQE_RESP_SEND_INV:
219 wc->opcode = IB_WC_RECV;
220 wc->wc_flags = IB_WC_WITH_INVALIDATE;
221 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
222 break;
223 }
224 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
225 wc->dlid_path_bits = cqe->ml_path;
226 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
227 wc->wc_flags |= g ? IB_WC_GRH : 0;
228 if (unlikely(is_qp1(qp->ibqp.qp_type))) {
229 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
230
231 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
232 &wc->pkey_index);
233 } else {
234 wc->pkey_index = 0;
235 }
236
237 if (ll != IB_LINK_LAYER_ETHERNET) {
238 wc->slid = be16_to_cpu(cqe->slid);
239 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
240 return;
241 }
242
243 wc->slid = 0;
244 vlan_present = cqe->l4_l3_hdr_type & 0x1;
245 roce_packet_type = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3;
246 if (vlan_present) {
247 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff;
248 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7;
249 wc->wc_flags |= IB_WC_WITH_VLAN;
250 } else {
251 wc->sl = 0;
252 }
253
254 switch (roce_packet_type) {
255 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
256 wc->network_hdr_type = RDMA_NETWORK_IB;
257 break;
258 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
259 wc->network_hdr_type = RDMA_NETWORK_IPV6;
260 break;
261 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
262 wc->network_hdr_type = RDMA_NETWORK_IPV4;
263 break;
264 }
265 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
266 }
267
268 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
269 {
270 mlx5_ib_warn(dev, "dump error cqe\n");
271 mlx5_dump_err_cqe(dev->mdev, cqe);
272 }
273
274 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
275 struct mlx5_err_cqe *cqe,
276 struct ib_wc *wc)
277 {
278 int dump = 1;
279
280 switch (cqe->syndrome) {
281 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
282 wc->status = IB_WC_LOC_LEN_ERR;
283 break;
284 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
285 wc->status = IB_WC_LOC_QP_OP_ERR;
286 break;
287 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
288 wc->status = IB_WC_LOC_PROT_ERR;
289 break;
290 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
291 dump = 0;
292 wc->status = IB_WC_WR_FLUSH_ERR;
293 break;
294 case MLX5_CQE_SYNDROME_MW_BIND_ERR:
295 wc->status = IB_WC_MW_BIND_ERR;
296 break;
297 case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
298 wc->status = IB_WC_BAD_RESP_ERR;
299 break;
300 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
301 wc->status = IB_WC_LOC_ACCESS_ERR;
302 break;
303 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
304 wc->status = IB_WC_REM_INV_REQ_ERR;
305 break;
306 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
307 wc->status = IB_WC_REM_ACCESS_ERR;
308 break;
309 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
310 wc->status = IB_WC_REM_OP_ERR;
311 break;
312 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
313 wc->status = IB_WC_RETRY_EXC_ERR;
314 dump = 0;
315 break;
316 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
317 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
318 dump = 0;
319 break;
320 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
321 wc->status = IB_WC_REM_ABORT_ERR;
322 break;
323 default:
324 wc->status = IB_WC_GENERAL_ERR;
325 break;
326 }
327
328 wc->vendor_err = cqe->vendor_err_synd;
329 if (dump)
330 dump_cqe(dev, cqe);
331 }
332
333 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
334 u16 tail, u16 head)
335 {
336 u16 idx;
337
338 do {
339 idx = tail & (qp->sq.wqe_cnt - 1);
340 if (idx == head)
341 break;
342
343 tail = qp->sq.w_list[idx].next;
344 } while (1);
345 tail = qp->sq.w_list[idx].next;
346 qp->sq.last_poll = tail;
347 }
348
349 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
350 {
351 mlx5_frag_buf_free(dev->mdev, &buf->frag_buf);
352 }
353
354 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
355 struct ib_sig_err *item)
356 {
357 u16 syndrome = be16_to_cpu(cqe->syndrome);
358
359 #define GUARD_ERR (1 << 13)
360 #define APPTAG_ERR (1 << 12)
361 #define REFTAG_ERR (1 << 11)
362
363 if (syndrome & GUARD_ERR) {
364 item->err_type = IB_SIG_BAD_GUARD;
365 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
366 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
367 } else
368 if (syndrome & REFTAG_ERR) {
369 item->err_type = IB_SIG_BAD_REFTAG;
370 item->expected = be32_to_cpu(cqe->expected_reftag);
371 item->actual = be32_to_cpu(cqe->actual_reftag);
372 } else
373 if (syndrome & APPTAG_ERR) {
374 item->err_type = IB_SIG_BAD_APPTAG;
375 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
376 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
377 } else {
378 pr_err("Got signature completion error with bad syndrome %04x\n",
379 syndrome);
380 }
381
382 item->sig_err_offset = be64_to_cpu(cqe->err_offset);
383 item->key = be32_to_cpu(cqe->mkey);
384 }
385
386 static void sw_comp(struct mlx5_ib_qp *qp, int num_entries, struct ib_wc *wc,
387 int *npolled, bool is_send)
388 {
389 struct mlx5_ib_wq *wq;
390 unsigned int cur;
391 int np;
392 int i;
393
394 wq = (is_send) ? &qp->sq : &qp->rq;
395 cur = wq->head - wq->tail;
396 np = *npolled;
397
398 if (cur == 0)
399 return;
400
401 for (i = 0; i < cur && np < num_entries; i++) {
402 unsigned int idx;
403
404 idx = (is_send) ? wq->last_poll : wq->tail;
405 idx &= (wq->wqe_cnt - 1);
406 wc->wr_id = wq->wrid[idx];
407 wc->status = IB_WC_WR_FLUSH_ERR;
408 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
409 wq->tail++;
410 if (is_send)
411 wq->last_poll = wq->w_list[idx].next;
412 np++;
413 wc->qp = &qp->ibqp;
414 wc++;
415 }
416 *npolled = np;
417 }
418
419 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
420 struct ib_wc *wc, int *npolled)
421 {
422 struct mlx5_ib_qp *qp;
423
424 *npolled = 0;
425
426 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
427 sw_comp(qp, num_entries, wc + *npolled, npolled, true);
428 if (*npolled >= num_entries)
429 return;
430 }
431
432 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
433 sw_comp(qp, num_entries, wc + *npolled, npolled, false);
434 if (*npolled >= num_entries)
435 return;
436 }
437 }
438
439 static int mlx5_poll_one(struct mlx5_ib_cq *cq,
440 struct mlx5_ib_qp **cur_qp,
441 struct ib_wc *wc)
442 {
443 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
444 struct mlx5_err_cqe *err_cqe;
445 struct mlx5_cqe64 *cqe64;
446 struct mlx5_core_qp *mqp;
447 struct mlx5_ib_wq *wq;
448 struct mlx5_sig_err_cqe *sig_err_cqe;
449 struct mlx5_core_mkey *mmkey;
450 struct mlx5_ib_mr *mr;
451 uint8_t opcode;
452 uint32_t qpn;
453 u16 wqe_ctr;
454 void *cqe;
455 int idx;
456
457 repoll:
458 cqe = next_cqe_sw(cq);
459 if (!cqe)
460 return -EAGAIN;
461
462 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
463
464 ++cq->mcq.cons_index;
465
466
467
468
469 rmb();
470
471 opcode = get_cqe_opcode(cqe64);
472 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
473 if (likely(cq->resize_buf)) {
474 free_cq_buf(dev, &cq->buf);
475 cq->buf = *cq->resize_buf;
476 kfree(cq->resize_buf);
477 cq->resize_buf = NULL;
478 goto repoll;
479 } else {
480 mlx5_ib_warn(dev, "unexpected resize cqe\n");
481 }
482 }
483
484 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
485 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
486
487
488
489
490 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
491 *cur_qp = to_mibqp(mqp);
492 }
493
494 wc->qp = &(*cur_qp)->ibqp;
495 switch (opcode) {
496 case MLX5_CQE_REQ:
497 wq = &(*cur_qp)->sq;
498 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
499 idx = wqe_ctr & (wq->wqe_cnt - 1);
500 handle_good_req(wc, cqe64, wq, idx);
501 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
502 wc->wr_id = wq->wrid[idx];
503 wq->tail = wq->wqe_head[idx] + 1;
504 wc->status = IB_WC_SUCCESS;
505 break;
506 case MLX5_CQE_RESP_WR_IMM:
507 case MLX5_CQE_RESP_SEND:
508 case MLX5_CQE_RESP_SEND_IMM:
509 case MLX5_CQE_RESP_SEND_INV:
510 handle_responder(wc, cqe64, *cur_qp);
511 wc->status = IB_WC_SUCCESS;
512 break;
513 case MLX5_CQE_RESIZE_CQ:
514 break;
515 case MLX5_CQE_REQ_ERR:
516 case MLX5_CQE_RESP_ERR:
517 err_cqe = (struct mlx5_err_cqe *)cqe64;
518 mlx5_handle_error_cqe(dev, err_cqe, wc);
519 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
520 opcode == MLX5_CQE_REQ_ERR ?
521 "Requestor" : "Responder", cq->mcq.cqn);
522 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
523 err_cqe->syndrome, err_cqe->vendor_err_synd);
524 if (opcode == MLX5_CQE_REQ_ERR) {
525 wq = &(*cur_qp)->sq;
526 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
527 idx = wqe_ctr & (wq->wqe_cnt - 1);
528 wc->wr_id = wq->wrid[idx];
529 wq->tail = wq->wqe_head[idx] + 1;
530 } else {
531 struct mlx5_ib_srq *srq;
532
533 if ((*cur_qp)->ibqp.srq) {
534 srq = to_msrq((*cur_qp)->ibqp.srq);
535 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
536 wc->wr_id = srq->wrid[wqe_ctr];
537 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
538 } else {
539 wq = &(*cur_qp)->rq;
540 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
541 ++wq->tail;
542 }
543 }
544 break;
545 case MLX5_CQE_SIG_ERR:
546 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
547
548 xa_lock(&dev->mdev->priv.mkey_table);
549 mmkey = xa_load(&dev->mdev->priv.mkey_table,
550 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
551 mr = to_mibmr(mmkey);
552 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
553 mr->sig->sig_err_exists = true;
554 mr->sig->sigerr_count++;
555
556 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
557 cq->mcq.cqn, mr->sig->err_item.key,
558 mr->sig->err_item.err_type,
559 mr->sig->err_item.sig_err_offset,
560 mr->sig->err_item.expected,
561 mr->sig->err_item.actual);
562
563 xa_unlock(&dev->mdev->priv.mkey_table);
564 goto repoll;
565 }
566
567 return 0;
568 }
569
570 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
571 struct ib_wc *wc, bool is_fatal_err)
572 {
573 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
574 struct mlx5_ib_wc *soft_wc, *next;
575 int npolled = 0;
576
577 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
578 if (npolled >= num_entries)
579 break;
580
581 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
582 cq->mcq.cqn);
583
584 if (unlikely(is_fatal_err)) {
585 soft_wc->wc.status = IB_WC_WR_FLUSH_ERR;
586 soft_wc->wc.vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
587 }
588 wc[npolled++] = soft_wc->wc;
589 list_del(&soft_wc->list);
590 kfree(soft_wc);
591 }
592
593 return npolled;
594 }
595
596 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
597 {
598 struct mlx5_ib_cq *cq = to_mcq(ibcq);
599 struct mlx5_ib_qp *cur_qp = NULL;
600 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
601 struct mlx5_core_dev *mdev = dev->mdev;
602 unsigned long flags;
603 int soft_polled = 0;
604 int npolled;
605
606 spin_lock_irqsave(&cq->lock, flags);
607 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
608
609 if (unlikely(!list_empty(&cq->wc_list)))
610 soft_polled = poll_soft_wc(cq, num_entries, wc, true);
611
612 mlx5_ib_poll_sw_comp(cq, num_entries - soft_polled,
613 wc + soft_polled, &npolled);
614 goto out;
615 }
616
617 if (unlikely(!list_empty(&cq->wc_list)))
618 soft_polled = poll_soft_wc(cq, num_entries, wc, false);
619
620 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
621 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled))
622 break;
623 }
624
625 if (npolled)
626 mlx5_cq_set_ci(&cq->mcq);
627 out:
628 spin_unlock_irqrestore(&cq->lock, flags);
629
630 return soft_polled + npolled;
631 }
632
633 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
634 {
635 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
636 struct mlx5_ib_cq *cq = to_mcq(ibcq);
637 void __iomem *uar_page = mdev->priv.uar->map;
638 unsigned long irq_flags;
639 int ret = 0;
640
641 spin_lock_irqsave(&cq->lock, irq_flags);
642 if (cq->notify_flags != IB_CQ_NEXT_COMP)
643 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
644
645 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
646 ret = 1;
647 spin_unlock_irqrestore(&cq->lock, irq_flags);
648
649 mlx5_cq_arm(&cq->mcq,
650 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
651 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
652 uar_page, to_mcq(ibcq)->mcq.cons_index);
653
654 return ret;
655 }
656
657 static int alloc_cq_frag_buf(struct mlx5_ib_dev *dev,
658 struct mlx5_ib_cq_buf *buf,
659 int nent,
660 int cqe_size)
661 {
662 struct mlx5_frag_buf *frag_buf = &buf->frag_buf;
663 u8 log_wq_stride = 6 + (cqe_size == 128 ? 1 : 0);
664 u8 log_wq_sz = ilog2(cqe_size);
665 int err;
666
667 err = mlx5_frag_buf_alloc_node(dev->mdev,
668 nent * cqe_size,
669 frag_buf,
670 dev->mdev->priv.numa_node);
671 if (err)
672 return err;
673
674 mlx5_init_fbc(frag_buf->frags, log_wq_stride, log_wq_sz, &buf->fbc);
675
676 buf->cqe_size = cqe_size;
677 buf->nent = nent;
678
679 return 0;
680 }
681
682 enum {
683 MLX5_CQE_RES_FORMAT_HASH = 0,
684 MLX5_CQE_RES_FORMAT_CSUM = 1,
685 MLX5_CQE_RES_FORMAT_CSUM_STRIDX = 3,
686 };
687
688 static int mini_cqe_res_format_to_hw(struct mlx5_ib_dev *dev, u8 format)
689 {
690 switch (format) {
691 case MLX5_IB_CQE_RES_FORMAT_HASH:
692 return MLX5_CQE_RES_FORMAT_HASH;
693 case MLX5_IB_CQE_RES_FORMAT_CSUM:
694 return MLX5_CQE_RES_FORMAT_CSUM;
695 case MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX:
696 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
697 return MLX5_CQE_RES_FORMAT_CSUM_STRIDX;
698 return -EOPNOTSUPP;
699 default:
700 return -EINVAL;
701 }
702 }
703
704 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
705 struct mlx5_ib_cq *cq, int entries, u32 **cqb,
706 int *cqe_size, int *index, int *inlen)
707 {
708 struct mlx5_ib_create_cq ucmd = {};
709 size_t ucmdlen;
710 int page_shift;
711 __be64 *pas;
712 int npages;
713 int ncont;
714 void *cqc;
715 int err;
716 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
717 udata, struct mlx5_ib_ucontext, ibucontext);
718
719 ucmdlen = udata->inlen < sizeof(ucmd) ?
720 (sizeof(ucmd) - sizeof(ucmd.flags)) : sizeof(ucmd);
721
722 if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
723 return -EFAULT;
724
725 if (ucmdlen == sizeof(ucmd) &&
726 (ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD)))
727 return -EINVAL;
728
729 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
730 return -EINVAL;
731
732 *cqe_size = ucmd.cqe_size;
733
734 cq->buf.umem =
735 ib_umem_get(udata, ucmd.buf_addr, entries * ucmd.cqe_size,
736 IB_ACCESS_LOCAL_WRITE, 1);
737 if (IS_ERR(cq->buf.umem)) {
738 err = PTR_ERR(cq->buf.umem);
739 return err;
740 }
741
742 err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &cq->db);
743 if (err)
744 goto err_umem;
745
746 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift,
747 &ncont, NULL);
748 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
749 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
750
751 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
752 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont;
753 *cqb = kvzalloc(*inlen, GFP_KERNEL);
754 if (!*cqb) {
755 err = -ENOMEM;
756 goto err_db;
757 }
758
759 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
760 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0);
761
762 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
763 MLX5_SET(cqc, cqc, log_page_size,
764 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
765
766 *index = context->bfregi.sys_pages[0];
767
768 if (ucmd.cqe_comp_en == 1) {
769 int mini_cqe_format;
770
771 if (!((*cqe_size == 128 &&
772 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) ||
773 (*cqe_size == 64 &&
774 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) {
775 err = -EOPNOTSUPP;
776 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n",
777 *cqe_size);
778 goto err_cqb;
779 }
780
781 mini_cqe_format =
782 mini_cqe_res_format_to_hw(dev,
783 ucmd.cqe_comp_res_format);
784 if (mini_cqe_format < 0) {
785 err = mini_cqe_format;
786 mlx5_ib_dbg(dev, "CQE compression res format %d error: %d\n",
787 ucmd.cqe_comp_res_format, err);
788 goto err_cqb;
789 }
790
791 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
792 MLX5_SET(cqc, cqc, mini_cqe_res_format, mini_cqe_format);
793 }
794
795 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) {
796 if (*cqe_size != 128 ||
797 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) {
798 err = -EOPNOTSUPP;
799 mlx5_ib_warn(dev,
800 "CQE padding is not supported for CQE size of %dB!\n",
801 *cqe_size);
802 goto err_cqb;
803 }
804
805 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD;
806 }
807
808 MLX5_SET(create_cq_in, *cqb, uid, context->devx_uid);
809 return 0;
810
811 err_cqb:
812 kvfree(*cqb);
813
814 err_db:
815 mlx5_ib_db_unmap_user(context, &cq->db);
816
817 err_umem:
818 ib_umem_release(cq->buf.umem);
819 return err;
820 }
821
822 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_udata *udata)
823 {
824 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
825 udata, struct mlx5_ib_ucontext, ibucontext);
826
827 mlx5_ib_db_unmap_user(context, &cq->db);
828 ib_umem_release(cq->buf.umem);
829 }
830
831 static void init_cq_frag_buf(struct mlx5_ib_cq *cq,
832 struct mlx5_ib_cq_buf *buf)
833 {
834 int i;
835 void *cqe;
836 struct mlx5_cqe64 *cqe64;
837
838 for (i = 0; i < buf->nent; i++) {
839 cqe = get_cqe(cq, i);
840 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
841 cqe64->op_own = MLX5_CQE_INVALID << 4;
842 }
843 }
844
845 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
846 int entries, int cqe_size,
847 u32 **cqb, int *index, int *inlen)
848 {
849 __be64 *pas;
850 void *cqc;
851 int err;
852
853 err = mlx5_db_alloc(dev->mdev, &cq->db);
854 if (err)
855 return err;
856
857 cq->mcq.set_ci_db = cq->db.db;
858 cq->mcq.arm_db = cq->db.db + 1;
859 cq->mcq.cqe_sz = cqe_size;
860
861 err = alloc_cq_frag_buf(dev, &cq->buf, entries, cqe_size);
862 if (err)
863 goto err_db;
864
865 init_cq_frag_buf(cq, &cq->buf);
866
867 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
868 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) *
869 cq->buf.frag_buf.npages;
870 *cqb = kvzalloc(*inlen, GFP_KERNEL);
871 if (!*cqb) {
872 err = -ENOMEM;
873 goto err_buf;
874 }
875
876 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
877 mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas);
878
879 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
880 MLX5_SET(cqc, cqc, log_page_size,
881 cq->buf.frag_buf.page_shift -
882 MLX5_ADAPTER_PAGE_SHIFT);
883
884 *index = dev->mdev->priv.uar->index;
885
886 return 0;
887
888 err_buf:
889 free_cq_buf(dev, &cq->buf);
890
891 err_db:
892 mlx5_db_free(dev->mdev, &cq->db);
893 return err;
894 }
895
896 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
897 {
898 free_cq_buf(dev, &cq->buf);
899 mlx5_db_free(dev->mdev, &cq->db);
900 }
901
902 static void notify_soft_wc_handler(struct work_struct *work)
903 {
904 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
905 notify_work);
906
907 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
908 }
909
910 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
911 struct ib_udata *udata)
912 {
913 struct ib_device *ibdev = ibcq->device;
914 int entries = attr->cqe;
915 int vector = attr->comp_vector;
916 struct mlx5_ib_dev *dev = to_mdev(ibdev);
917 struct mlx5_ib_cq *cq = to_mcq(ibcq);
918 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
919 int uninitialized_var(index);
920 int uninitialized_var(inlen);
921 u32 *cqb = NULL;
922 void *cqc;
923 int cqe_size;
924 unsigned int irqn;
925 int eqn;
926 int err;
927
928 if (entries < 0 ||
929 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
930 return -EINVAL;
931
932 if (check_cq_create_flags(attr->flags))
933 return -EOPNOTSUPP;
934
935 entries = roundup_pow_of_two(entries + 1);
936 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
937 return -EINVAL;
938
939 cq->ibcq.cqe = entries - 1;
940 mutex_init(&cq->resize_mutex);
941 spin_lock_init(&cq->lock);
942 cq->resize_buf = NULL;
943 cq->resize_umem = NULL;
944 cq->create_flags = attr->flags;
945 INIT_LIST_HEAD(&cq->list_send_qp);
946 INIT_LIST_HEAD(&cq->list_recv_qp);
947
948 if (udata) {
949 err = create_cq_user(dev, udata, cq, entries, &cqb, &cqe_size,
950 &index, &inlen);
951 if (err)
952 return err;
953 } else {
954 cqe_size = cache_line_size() == 128 ? 128 : 64;
955 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
956 &index, &inlen);
957 if (err)
958 return err;
959
960 INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
961 }
962
963 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
964 if (err)
965 goto err_cqb;
966
967 cq->cqe_size = cqe_size;
968
969 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context);
970 MLX5_SET(cqc, cqc, cqe_sz,
971 cqe_sz_to_mlx_sz(cqe_size,
972 cq->private_flags &
973 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
974 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
975 MLX5_SET(cqc, cqc, uar_page, index);
976 MLX5_SET(cqc, cqc, c_eqn, eqn);
977 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma);
978 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN)
979 MLX5_SET(cqc, cqc, oi, 1);
980
981 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen, out, sizeof(out));
982 if (err)
983 goto err_cqb;
984
985 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
986 cq->mcq.irqn = irqn;
987 if (udata)
988 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp;
989 else
990 cq->mcq.comp = mlx5_ib_cq_comp;
991 cq->mcq.event = mlx5_ib_cq_event;
992
993 INIT_LIST_HEAD(&cq->wc_list);
994
995 if (udata)
996 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
997 err = -EFAULT;
998 goto err_cmd;
999 }
1000
1001
1002 kvfree(cqb);
1003 return 0;
1004
1005 err_cmd:
1006 mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
1007
1008 err_cqb:
1009 kvfree(cqb);
1010 if (udata)
1011 destroy_cq_user(cq, udata);
1012 else
1013 destroy_cq_kernel(dev, cq);
1014 return err;
1015 }
1016
1017 void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata)
1018 {
1019 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1020 struct mlx5_ib_cq *mcq = to_mcq(cq);
1021
1022 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
1023 if (udata)
1024 destroy_cq_user(mcq, udata);
1025 else
1026 destroy_cq_kernel(dev, mcq);
1027 }
1028
1029 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
1030 {
1031 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
1032 }
1033
1034 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
1035 {
1036 struct mlx5_cqe64 *cqe64, *dest64;
1037 void *cqe, *dest;
1038 u32 prod_index;
1039 int nfreed = 0;
1040 u8 owner_bit;
1041
1042 if (!cq)
1043 return;
1044
1045
1046
1047
1048
1049
1050
1051 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
1052 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
1053 break;
1054
1055
1056
1057
1058 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
1059 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
1060 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
1061 if (is_equal_rsn(cqe64, rsn)) {
1062 if (srq && (ntohl(cqe64->srqn) & 0xffffff))
1063 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
1064 ++nfreed;
1065 } else if (nfreed) {
1066 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
1067 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
1068 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
1069 memcpy(dest, cqe, cq->mcq.cqe_sz);
1070 dest64->op_own = owner_bit |
1071 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
1072 }
1073 }
1074
1075 if (nfreed) {
1076 cq->mcq.cons_index += nfreed;
1077
1078
1079
1080 wmb();
1081 mlx5_cq_set_ci(&cq->mcq);
1082 }
1083 }
1084
1085 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
1086 {
1087 if (!cq)
1088 return;
1089
1090 spin_lock_irq(&cq->lock);
1091 __mlx5_ib_cq_clean(cq, qpn, srq);
1092 spin_unlock_irq(&cq->lock);
1093 }
1094
1095 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1096 {
1097 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1098 struct mlx5_ib_cq *mcq = to_mcq(cq);
1099 int err;
1100
1101 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
1102 return -EOPNOTSUPP;
1103
1104 if (cq_period > MLX5_MAX_CQ_PERIOD)
1105 return -EINVAL;
1106
1107 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq,
1108 cq_period, cq_count);
1109 if (err)
1110 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1111
1112 return err;
1113 }
1114
1115 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1116 int entries, struct ib_udata *udata, int *npas,
1117 int *page_shift, int *cqe_size)
1118 {
1119 struct mlx5_ib_resize_cq ucmd;
1120 struct ib_umem *umem;
1121 int err;
1122 int npages;
1123
1124 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1125 if (err)
1126 return err;
1127
1128 if (ucmd.reserved0 || ucmd.reserved1)
1129 return -EINVAL;
1130
1131
1132 if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1)
1133 return -EINVAL;
1134
1135 umem = ib_umem_get(udata, ucmd.buf_addr,
1136 (size_t)ucmd.cqe_size * entries,
1137 IB_ACCESS_LOCAL_WRITE, 1);
1138 if (IS_ERR(umem)) {
1139 err = PTR_ERR(umem);
1140 return err;
1141 }
1142
1143 mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift,
1144 npas, NULL);
1145
1146 cq->resize_umem = umem;
1147 *cqe_size = ucmd.cqe_size;
1148
1149 return 0;
1150 }
1151
1152 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1153 int entries, int cqe_size)
1154 {
1155 int err;
1156
1157 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1158 if (!cq->resize_buf)
1159 return -ENOMEM;
1160
1161 err = alloc_cq_frag_buf(dev, cq->resize_buf, entries, cqe_size);
1162 if (err)
1163 goto ex;
1164
1165 init_cq_frag_buf(cq, cq->resize_buf);
1166
1167 return 0;
1168
1169 ex:
1170 kfree(cq->resize_buf);
1171 return err;
1172 }
1173
1174 static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1175 {
1176 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1177 struct mlx5_cqe64 *scqe64;
1178 struct mlx5_cqe64 *dcqe64;
1179 void *start_cqe;
1180 void *scqe;
1181 void *dcqe;
1182 int ssize;
1183 int dsize;
1184 int i;
1185 u8 sw_own;
1186
1187 ssize = cq->buf.cqe_size;
1188 dsize = cq->resize_buf->cqe_size;
1189 if (ssize != dsize) {
1190 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1191 return -EINVAL;
1192 }
1193
1194 i = cq->mcq.cons_index;
1195 scqe = get_sw_cqe(cq, i);
1196 scqe64 = ssize == 64 ? scqe : scqe + 64;
1197 start_cqe = scqe;
1198 if (!scqe) {
1199 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1200 return -EINVAL;
1201 }
1202
1203 while (get_cqe_opcode(scqe64) != MLX5_CQE_RESIZE_CQ) {
1204 dcqe = mlx5_frag_buf_get_wqe(&cq->resize_buf->fbc,
1205 (i + 1) & cq->resize_buf->nent);
1206 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1207 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1208 memcpy(dcqe, scqe, dsize);
1209 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1210
1211 ++i;
1212 scqe = get_sw_cqe(cq, i);
1213 scqe64 = ssize == 64 ? scqe : scqe + 64;
1214 if (!scqe) {
1215 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1216 return -EINVAL;
1217 }
1218
1219 if (scqe == start_cqe) {
1220 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1221 cq->mcq.cqn);
1222 return -ENOMEM;
1223 }
1224 }
1225 ++cq->mcq.cons_index;
1226 return 0;
1227 }
1228
1229 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1230 {
1231 struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1232 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1233 void *cqc;
1234 u32 *in;
1235 int err;
1236 int npas;
1237 __be64 *pas;
1238 int page_shift;
1239 int inlen;
1240 int uninitialized_var(cqe_size);
1241 unsigned long flags;
1242
1243 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1244 pr_info("Firmware does not support resize CQ\n");
1245 return -ENOSYS;
1246 }
1247
1248 if (entries < 1 ||
1249 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) {
1250 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n",
1251 entries,
1252 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz));
1253 return -EINVAL;
1254 }
1255
1256 entries = roundup_pow_of_two(entries + 1);
1257 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1258 return -EINVAL;
1259
1260 if (entries == ibcq->cqe + 1)
1261 return 0;
1262
1263 mutex_lock(&cq->resize_mutex);
1264 if (udata) {
1265 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1266 &cqe_size);
1267 } else {
1268 cqe_size = 64;
1269 err = resize_kernel(dev, cq, entries, cqe_size);
1270 if (!err) {
1271 struct mlx5_frag_buf *frag_buf = &cq->resize_buf->frag_buf;
1272
1273 npas = frag_buf->npages;
1274 page_shift = frag_buf->page_shift;
1275 }
1276 }
1277
1278 if (err)
1279 goto ex;
1280
1281 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) +
1282 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas;
1283
1284 in = kvzalloc(inlen, GFP_KERNEL);
1285 if (!in) {
1286 err = -ENOMEM;
1287 goto ex_resize;
1288 }
1289
1290 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas);
1291 if (udata)
1292 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1293 pas, 0);
1294 else
1295 mlx5_fill_page_frag_array(&cq->resize_buf->frag_buf, pas);
1296
1297 MLX5_SET(modify_cq_in, in,
1298 modify_field_select_resize_field_select.resize_field_select.resize_field_select,
1299 MLX5_MODIFY_CQ_MASK_LOG_SIZE |
1300 MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1301 MLX5_MODIFY_CQ_MASK_PG_SIZE);
1302
1303 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
1304
1305 MLX5_SET(cqc, cqc, log_page_size,
1306 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1307 MLX5_SET(cqc, cqc, cqe_sz,
1308 cqe_sz_to_mlx_sz(cqe_size,
1309 cq->private_flags &
1310 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1311 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1312
1313 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE);
1314 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn);
1315
1316 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1317 if (err)
1318 goto ex_alloc;
1319
1320 if (udata) {
1321 cq->ibcq.cqe = entries - 1;
1322 ib_umem_release(cq->buf.umem);
1323 cq->buf.umem = cq->resize_umem;
1324 cq->resize_umem = NULL;
1325 } else {
1326 struct mlx5_ib_cq_buf tbuf;
1327 int resized = 0;
1328
1329 spin_lock_irqsave(&cq->lock, flags);
1330 if (cq->resize_buf) {
1331 err = copy_resize_cqes(cq);
1332 if (!err) {
1333 tbuf = cq->buf;
1334 cq->buf = *cq->resize_buf;
1335 kfree(cq->resize_buf);
1336 cq->resize_buf = NULL;
1337 resized = 1;
1338 }
1339 }
1340 cq->ibcq.cqe = entries - 1;
1341 spin_unlock_irqrestore(&cq->lock, flags);
1342 if (resized)
1343 free_cq_buf(dev, &tbuf);
1344 }
1345 mutex_unlock(&cq->resize_mutex);
1346
1347 kvfree(in);
1348 return 0;
1349
1350 ex_alloc:
1351 kvfree(in);
1352
1353 ex_resize:
1354 ib_umem_release(cq->resize_umem);
1355 if (!udata) {
1356 free_cq_buf(dev, cq->resize_buf);
1357 cq->resize_buf = NULL;
1358 }
1359 ex:
1360 mutex_unlock(&cq->resize_mutex);
1361 return err;
1362 }
1363
1364 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq)
1365 {
1366 struct mlx5_ib_cq *cq;
1367
1368 if (!ibcq)
1369 return 128;
1370
1371 cq = to_mcq(ibcq);
1372 return cq->cqe_size;
1373 }
1374
1375
1376 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1377 {
1378 struct mlx5_ib_wc *soft_wc;
1379 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1380 unsigned long flags;
1381
1382 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1383 if (!soft_wc)
1384 return -ENOMEM;
1385
1386 soft_wc->wc = *wc;
1387 spin_lock_irqsave(&cq->lock, flags);
1388 list_add_tail(&soft_wc->list, &cq->wc_list);
1389 if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1390 wc->status != IB_WC_SUCCESS) {
1391 cq->notify_flags = 0;
1392 schedule_work(&cq->notify_work);
1393 }
1394 spin_unlock_irqrestore(&cq->lock, flags);
1395
1396 return 0;
1397 }