This source file includes following definitions.
- to_mucontext
- mlx5_ib_create_qp_sqpn_qp1
- is_odp_mr
- to_mcounters
- to_mibcq
- to_mxrcd
- to_mdev
- mlx5_udata_to_mdev
- to_mcq
- to_mibqp
- to_mibrwq
- to_mibmr
- to_mpd
- to_msrq
- to_mqp
- to_mrwq
- to_mrwq_ind_table
- to_mibsrq
- to_mdm
- to_mmr
- to_mmw
- to_mflow_act
- mlx5_ib_internal_fill_odp_caps
- mlx5_ib_odp_init_one
- mlx5_ib_odp_cleanup_one
- mlx5_ib_odp_init
- mlx5_ib_odp_cleanup
- mlx5_odp_init_mr_cache_entry
- mlx5_odp_populate_klm
- mlx5_ib_advise_mr_prefetch
- mlx5_ib_invalidate_range
- mlx5_ib_devx_create
- mlx5_ib_devx_destroy
- mlx5_ib_devx_init_event_table
- mlx5_ib_devx_cleanup_event_table
- mlx5_ib_devx_is_flow_dest
- mlx5_ib_destroy_flow_action_raw
- init_query_mad
- convert_access
- is_qp1
- check_cq_create_flags
- verify_assign_uidx
- get_qp_user_index
- get_srq_user_index
- get_uars_per_sys_page
- get_num_static_uars
- mlx5_ib_can_use_umr
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33 #ifndef MLX5_IB_H
34 #define MLX5_IB_H
35
36 #include <linux/kernel.h>
37 #include <linux/sched.h>
38 #include <rdma/ib_verbs.h>
39 #include <rdma/ib_umem.h>
40 #include <rdma/ib_smi.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/fs.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/types.h>
46 #include <linux/mlx5/transobj.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/mlx5-abi.h>
49 #include <rdma/uverbs_ioctl.h>
50 #include <rdma/mlx5_user_ioctl_cmds.h>
51 #include <rdma/mlx5_user_ioctl_verbs.h>
52
53 #include "srq.h"
54
55 #define mlx5_ib_dbg(_dev, format, arg...) \
56 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
57 __LINE__, current->pid, ##arg)
58
59 #define mlx5_ib_err(_dev, format, arg...) \
60 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
61 __LINE__, current->pid, ##arg)
62
63 #define mlx5_ib_warn(_dev, format, arg...) \
64 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
65 __LINE__, current->pid, ##arg)
66
67 #define field_avail(type, fld, sz) (offsetof(type, fld) + \
68 sizeof(((type *)0)->fld) <= (sz))
69 #define MLX5_IB_DEFAULT_UIDX 0xffffff
70 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
71
72 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size)
73
74 enum {
75 MLX5_IB_MMAP_CMD_SHIFT = 8,
76 MLX5_IB_MMAP_CMD_MASK = 0xff,
77 };
78
79 enum {
80 MLX5_RES_SCAT_DATA32_CQE = 0x1,
81 MLX5_RES_SCAT_DATA64_CQE = 0x2,
82 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
83 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
84 };
85
86 enum mlx5_ib_mad_ifc_flags {
87 MLX5_MAD_IFC_IGNORE_MKEY = 1,
88 MLX5_MAD_IFC_IGNORE_BKEY = 2,
89 MLX5_MAD_IFC_NET_VIEW = 4,
90 };
91
92 enum {
93 MLX5_CROSS_CHANNEL_BFREG = 0,
94 };
95
96 enum {
97 MLX5_CQE_VERSION_V0,
98 MLX5_CQE_VERSION_V1,
99 };
100
101 enum {
102 MLX5_TM_MAX_RNDV_MSG_SIZE = 64,
103 MLX5_TM_MAX_SGE = 1,
104 };
105
106 enum {
107 MLX5_IB_INVALID_UAR_INDEX = BIT(31),
108 MLX5_IB_INVALID_BFREG = BIT(31),
109 };
110
111 enum {
112 MLX5_MAX_MEMIC_PAGES = 0x100,
113 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
114 };
115
116 enum {
117 MLX5_MEMIC_BASE_ALIGN = 6,
118 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
119 };
120
121 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) \
122 (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
123 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
124
125 struct mlx5_ib_ucontext {
126 struct ib_ucontext ibucontext;
127 struct list_head db_page_list;
128
129
130
131 struct mutex db_page_mutex;
132 struct mlx5_bfreg_info bfregi;
133 u8 cqe_version;
134
135 u32 tdn;
136
137 u64 lib_caps;
138 DECLARE_BITMAP(dm_pages, MLX5_MAX_MEMIC_PAGES);
139 u16 devx_uid;
140
141 atomic_t tx_port_affinity;
142 };
143
144 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
145 {
146 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
147 }
148
149 struct mlx5_ib_pd {
150 struct ib_pd ibpd;
151 u32 pdn;
152 u16 uid;
153 };
154
155 enum {
156 MLX5_IB_FLOW_ACTION_MODIFY_HEADER,
157 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT,
158 MLX5_IB_FLOW_ACTION_DECAP,
159 };
160
161 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
162 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
163 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
164 #error "Invalid number of bypass priorities"
165 #endif
166 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
167
168 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
169 #define MLX5_IB_NUM_SNIFFER_FTS 2
170 #define MLX5_IB_NUM_EGRESS_FTS 1
171 struct mlx5_ib_flow_prio {
172 struct mlx5_flow_table *flow_table;
173 unsigned int refcount;
174 };
175
176 struct mlx5_ib_flow_handler {
177 struct list_head list;
178 struct ib_flow ibflow;
179 struct mlx5_ib_flow_prio *prio;
180 struct mlx5_flow_handle *rule;
181 struct ib_counters *ibcounters;
182 struct mlx5_ib_dev *dev;
183 struct mlx5_ib_flow_matcher *flow_matcher;
184 };
185
186 struct mlx5_ib_flow_matcher {
187 struct mlx5_ib_match_params matcher_mask;
188 int mask_len;
189 enum mlx5_ib_flow_type flow_type;
190 enum mlx5_flow_namespace_type ns_type;
191 u16 priority;
192 struct mlx5_core_dev *mdev;
193 atomic_t usecnt;
194 u8 match_criteria_enable;
195 };
196
197 struct mlx5_ib_flow_db {
198 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
199 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT];
200 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
201 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS];
202 struct mlx5_ib_flow_prio fdb;
203 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT];
204 struct mlx5_flow_table *lag_demux_ft;
205
206
207
208
209
210 struct mutex lock;
211 };
212
213
214
215
216
217 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0)
218 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1)
219 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2)
220 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3)
221 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4)
222 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END
223
224 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
225
226
227
228
229 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
230 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3
231 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4
232 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
233
234 #define MLX5_IB_UMR_OCTOWORD 16
235 #define MLX5_IB_UMR_XLT_ALIGNMENT 64
236
237 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
238 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
239 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
240 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
241 #define MLX5_IB_UPD_XLT_PD BIT(4)
242 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
243 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
244
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247
248
249
250
251
252 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void)
253 {
254 return IB_QP_CREATE_RESERVED_START;
255 }
256
257 struct wr_list {
258 u16 opcode;
259 u16 next;
260 };
261
262 enum mlx5_ib_rq_flags {
263 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
264 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
265 };
266
267 struct mlx5_ib_wq {
268 struct mlx5_frag_buf_ctrl fbc;
269 u64 *wrid;
270 u32 *wr_data;
271 struct wr_list *w_list;
272 unsigned *wqe_head;
273 u16 unsig_count;
274
275
276
277 spinlock_t lock;
278 int wqe_cnt;
279 int max_post;
280 int max_gs;
281 int offset;
282 int wqe_shift;
283 unsigned head;
284 unsigned tail;
285 u16 cur_post;
286 u16 last_poll;
287 void *cur_edge;
288 };
289
290 enum mlx5_ib_wq_flags {
291 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
292 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
293 };
294
295 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
296 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
297 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
298 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
299
300 struct mlx5_ib_rwq {
301 struct ib_wq ibwq;
302 struct mlx5_core_qp core_qp;
303 u32 rq_num_pas;
304 u32 log_rq_stride;
305 u32 log_rq_size;
306 u32 rq_page_offset;
307 u32 log_page_size;
308 u32 log_num_strides;
309 u32 two_byte_shift_en;
310 u32 single_stride_log_num_of_bytes;
311 struct ib_umem *umem;
312 size_t buf_size;
313 unsigned int page_shift;
314 int create_type;
315 struct mlx5_db db;
316 u32 user_index;
317 u32 wqe_count;
318 u32 wqe_shift;
319 int wq_sig;
320 u32 create_flags;
321 };
322
323 enum {
324 MLX5_QP_USER,
325 MLX5_QP_KERNEL,
326 MLX5_QP_EMPTY
327 };
328
329 enum {
330 MLX5_WQ_USER,
331 MLX5_WQ_KERNEL
332 };
333
334 struct mlx5_ib_rwq_ind_table {
335 struct ib_rwq_ind_table ib_rwq_ind_tbl;
336 u32 rqtn;
337 u16 uid;
338 };
339
340 struct mlx5_ib_ubuffer {
341 struct ib_umem *umem;
342 int buf_size;
343 u64 buf_addr;
344 };
345
346 struct mlx5_ib_qp_base {
347 struct mlx5_ib_qp *container_mibqp;
348 struct mlx5_core_qp mqp;
349 struct mlx5_ib_ubuffer ubuffer;
350 };
351
352 struct mlx5_ib_qp_trans {
353 struct mlx5_ib_qp_base base;
354 u16 xrcdn;
355 u8 alt_port;
356 u8 atomic_rd_en;
357 u8 resp_depth;
358 };
359
360 struct mlx5_ib_rss_qp {
361 u32 tirn;
362 };
363
364 struct mlx5_ib_rq {
365 struct mlx5_ib_qp_base base;
366 struct mlx5_ib_wq *rq;
367 struct mlx5_ib_ubuffer ubuffer;
368 struct mlx5_db *doorbell;
369 u32 tirn;
370 u8 state;
371 u32 flags;
372 };
373
374 struct mlx5_ib_sq {
375 struct mlx5_ib_qp_base base;
376 struct mlx5_ib_wq *sq;
377 struct mlx5_ib_ubuffer ubuffer;
378 struct mlx5_db *doorbell;
379 struct mlx5_flow_handle *flow_rule;
380 u32 tisn;
381 u8 state;
382 };
383
384 struct mlx5_ib_raw_packet_qp {
385 struct mlx5_ib_sq sq;
386 struct mlx5_ib_rq rq;
387 };
388
389 struct mlx5_bf {
390 int buf_size;
391 unsigned long offset;
392 struct mlx5_sq_bfreg *bfreg;
393 };
394
395 struct mlx5_ib_dct {
396 struct mlx5_core_dct mdct;
397 u32 *in;
398 };
399
400 struct mlx5_ib_qp {
401 struct ib_qp ibqp;
402 union {
403 struct mlx5_ib_qp_trans trans_qp;
404 struct mlx5_ib_raw_packet_qp raw_packet_qp;
405 struct mlx5_ib_rss_qp rss_qp;
406 struct mlx5_ib_dct dct;
407 };
408 struct mlx5_frag_buf buf;
409
410 struct mlx5_db db;
411 struct mlx5_ib_wq rq;
412
413 u8 sq_signal_bits;
414 u8 next_fence;
415 struct mlx5_ib_wq sq;
416
417
418
419 struct mutex mutex;
420 u32 flags;
421 u8 port;
422 u8 state;
423 int wq_sig;
424 int scat_cqe;
425 int max_inline_data;
426 struct mlx5_bf bf;
427 int has_rq;
428
429
430
431
432 int bfregn;
433
434 int create_type;
435
436 struct list_head qps_list;
437 struct list_head cq_recv_list;
438 struct list_head cq_send_list;
439 struct mlx5_rate_limit rl;
440 u32 underlay_qpn;
441 u32 flags_en;
442
443 enum ib_qp_type qp_sub_type;
444
445
446
447 u32 counter_pending;
448 };
449
450 struct mlx5_ib_cq_buf {
451 struct mlx5_frag_buf_ctrl fbc;
452 struct mlx5_frag_buf frag_buf;
453 struct ib_umem *umem;
454 int cqe_size;
455 int nent;
456 };
457
458 enum mlx5_ib_qp_flags {
459 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO,
460 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
461 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL,
462 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND,
463 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV,
464 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5,
465
466 MLX5_IB_QP_SQPN_QP1 = 1 << 6,
467 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7,
468 MLX5_IB_QP_RSS = 1 << 8,
469 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9,
470 MLX5_IB_QP_UNDERLAY = 1 << 10,
471 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11,
472 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12,
473 MLX5_IB_QP_PACKET_BASED_CREDIT = 1 << 13,
474 };
475
476 struct mlx5_umr_wr {
477 struct ib_send_wr wr;
478 u64 virt_addr;
479 u64 offset;
480 struct ib_pd *pd;
481 unsigned int page_shift;
482 unsigned int xlt_size;
483 u64 length;
484 int access_flags;
485 u32 mkey;
486 u8 ignore_free_state:1;
487 };
488
489 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr)
490 {
491 return container_of(wr, struct mlx5_umr_wr, wr);
492 }
493
494 struct mlx5_shared_mr_info {
495 int mr_id;
496 struct ib_umem *umem;
497 };
498
499 enum mlx5_ib_cq_pr_flags {
500 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
501 };
502
503 struct mlx5_ib_cq {
504 struct ib_cq ibcq;
505 struct mlx5_core_cq mcq;
506 struct mlx5_ib_cq_buf buf;
507 struct mlx5_db db;
508
509
510
511 spinlock_t lock;
512
513
514
515 struct mutex resize_mutex;
516 struct mlx5_ib_cq_buf *resize_buf;
517 struct ib_umem *resize_umem;
518 int cqe_size;
519 struct list_head list_send_qp;
520 struct list_head list_recv_qp;
521 u32 create_flags;
522 struct list_head wc_list;
523 enum ib_cq_notify_flags notify_flags;
524 struct work_struct notify_work;
525 u16 private_flags;
526 };
527
528 struct mlx5_ib_wc {
529 struct ib_wc wc;
530 struct list_head list;
531 };
532
533 struct mlx5_ib_srq {
534 struct ib_srq ibsrq;
535 struct mlx5_core_srq msrq;
536 struct mlx5_frag_buf buf;
537 struct mlx5_db db;
538 struct mlx5_frag_buf_ctrl fbc;
539 u64 *wrid;
540
541
542 spinlock_t lock;
543 int head;
544 int tail;
545 u16 wqe_ctr;
546 struct ib_umem *umem;
547
548
549 struct mutex mutex;
550 int wq_sig;
551 };
552
553 struct mlx5_ib_xrcd {
554 struct ib_xrcd ibxrcd;
555 u32 xrcdn;
556 };
557
558 enum mlx5_ib_mtt_access_flags {
559 MLX5_IB_MTT_READ = (1 << 0),
560 MLX5_IB_MTT_WRITE = (1 << 1),
561 };
562
563 struct mlx5_ib_dm {
564 struct ib_dm ibdm;
565 phys_addr_t dev_addr;
566 u32 type;
567 size_t size;
568 union {
569 struct {
570 u32 obj_id;
571 } icm_dm;
572
573 };
574 };
575
576 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
577
578 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
579 IB_ACCESS_REMOTE_WRITE |\
580 IB_ACCESS_REMOTE_READ |\
581 IB_ACCESS_REMOTE_ATOMIC |\
582 IB_ZERO_BASED)
583
584 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
585 IB_ACCESS_REMOTE_WRITE |\
586 IB_ACCESS_REMOTE_READ |\
587 IB_ZERO_BASED)
588
589 struct mlx5_ib_mr {
590 struct ib_mr ibmr;
591 void *descs;
592 dma_addr_t desc_map;
593 int ndescs;
594 int data_length;
595 int meta_ndescs;
596 int meta_length;
597 int max_descs;
598 int desc_size;
599 int access_mode;
600 struct mlx5_core_mkey mmkey;
601 struct ib_umem *umem;
602 struct mlx5_shared_mr_info *smr_info;
603 struct list_head list;
604 int order;
605 bool allocated_from_cache;
606 int npages;
607 struct mlx5_ib_dev *dev;
608 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
609 struct mlx5_core_sig_ctx *sig;
610 unsigned int live;
611 void *descs_alloc;
612 int access_flags;
613
614 struct mlx5_ib_mr *parent;
615
616 struct mlx5_ib_mr *pi_mr;
617 struct mlx5_ib_mr *klm_mr;
618 struct mlx5_ib_mr *mtt_mr;
619 u64 data_iova;
620 u64 pi_iova;
621
622 atomic_t num_leaf_free;
623 wait_queue_head_t q_leaf_free;
624 struct mlx5_async_work cb_work;
625 atomic_t num_pending_prefetch;
626 };
627
628 static inline bool is_odp_mr(struct mlx5_ib_mr *mr)
629 {
630 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
631 mr->umem->is_odp;
632 }
633
634 struct mlx5_ib_mw {
635 struct ib_mw ibmw;
636 struct mlx5_core_mkey mmkey;
637 int ndescs;
638 };
639
640 struct mlx5_ib_devx_mr {
641 struct mlx5_core_mkey mmkey;
642 int ndescs;
643 };
644
645 struct mlx5_ib_umr_context {
646 struct ib_cqe cqe;
647 enum ib_wc_status status;
648 struct completion done;
649 };
650
651 struct umr_common {
652 struct ib_pd *pd;
653 struct ib_cq *cq;
654 struct ib_qp *qp;
655
656
657 struct semaphore sem;
658 };
659
660 enum {
661 MLX5_FMR_INVALID,
662 MLX5_FMR_VALID,
663 MLX5_FMR_BUSY,
664 };
665
666 struct mlx5_cache_ent {
667 struct list_head head;
668
669
670 spinlock_t lock;
671
672
673 char name[4];
674 u32 order;
675 u32 xlt;
676 u32 access_mode;
677 u32 page;
678
679 u32 size;
680 u32 cur;
681 u32 miss;
682 u32 limit;
683
684 struct mlx5_ib_dev *dev;
685 struct work_struct work;
686 struct delayed_work dwork;
687 int pending;
688 struct completion compl;
689 };
690
691 struct mlx5_mr_cache {
692 struct workqueue_struct *wq;
693 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
694 int stopped;
695 struct dentry *root;
696 unsigned long last_add;
697 };
698
699 struct mlx5_ib_gsi_qp;
700
701 struct mlx5_ib_port_resources {
702 struct mlx5_ib_resources *devr;
703 struct mlx5_ib_gsi_qp *gsi;
704 struct work_struct pkey_change_work;
705 };
706
707 struct mlx5_ib_resources {
708 struct ib_cq *c0;
709 struct ib_xrcd *x0;
710 struct ib_xrcd *x1;
711 struct ib_pd *p0;
712 struct ib_srq *s0;
713 struct ib_srq *s1;
714 struct mlx5_ib_port_resources ports[2];
715
716 struct mutex mutex;
717 };
718
719 struct mlx5_ib_counters {
720 const char **names;
721 size_t *offsets;
722 u32 num_q_counters;
723 u32 num_cong_counters;
724 u32 num_ext_ppcnt_counters;
725 u16 set_id;
726 bool set_id_valid;
727 };
728
729 struct mlx5_ib_multiport_info;
730
731 struct mlx5_ib_multiport {
732 struct mlx5_ib_multiport_info *mpi;
733
734 spinlock_t mpi_lock;
735 };
736
737 struct mlx5_roce {
738
739
740
741 rwlock_t netdev_lock;
742 struct net_device *netdev;
743 struct notifier_block nb;
744 atomic_t tx_port_affinity;
745 enum ib_port_state last_port_state;
746 struct mlx5_ib_dev *dev;
747 u8 native_port_num;
748 };
749
750 struct mlx5_ib_port {
751 struct mlx5_ib_counters cnts;
752 struct mlx5_ib_multiport mp;
753 struct mlx5_ib_dbg_cc_params *dbg_cc_params;
754 struct mlx5_roce roce;
755 struct mlx5_eswitch_rep *rep;
756 };
757
758 struct mlx5_ib_dbg_param {
759 int offset;
760 struct mlx5_ib_dev *dev;
761 struct dentry *dentry;
762 u8 port_num;
763 };
764
765 enum mlx5_ib_dbg_cc_types {
766 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
767 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
768 MLX5_IB_DBG_CC_RP_TIME_RESET,
769 MLX5_IB_DBG_CC_RP_BYTE_RESET,
770 MLX5_IB_DBG_CC_RP_THRESHOLD,
771 MLX5_IB_DBG_CC_RP_AI_RATE,
772 MLX5_IB_DBG_CC_RP_HAI_RATE,
773 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
774 MLX5_IB_DBG_CC_RP_MIN_RATE,
775 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
776 MLX5_IB_DBG_CC_RP_DCE_TCP_G,
777 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
778 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
779 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
780 MLX5_IB_DBG_CC_RP_GD,
781 MLX5_IB_DBG_CC_NP_CNP_DSCP,
782 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
783 MLX5_IB_DBG_CC_NP_CNP_PRIO,
784 MLX5_IB_DBG_CC_MAX,
785 };
786
787 struct mlx5_ib_dbg_cc_params {
788 struct dentry *root;
789 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX];
790 };
791
792 enum {
793 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
794 };
795
796 struct mlx5_ib_dbg_delay_drop {
797 struct dentry *dir_debugfs;
798 struct dentry *rqs_cnt_debugfs;
799 struct dentry *events_cnt_debugfs;
800 struct dentry *timeout_debugfs;
801 };
802
803 struct mlx5_ib_delay_drop {
804 struct mlx5_ib_dev *dev;
805 struct work_struct delay_drop_work;
806
807 struct mutex lock;
808 u32 timeout;
809 bool activate;
810 atomic_t events_cnt;
811 atomic_t rqs_cnt;
812 struct mlx5_ib_dbg_delay_drop *dbg;
813 };
814
815 enum mlx5_ib_stages {
816 MLX5_IB_STAGE_INIT,
817 MLX5_IB_STAGE_FLOW_DB,
818 MLX5_IB_STAGE_CAPS,
819 MLX5_IB_STAGE_NON_DEFAULT_CB,
820 MLX5_IB_STAGE_ROCE,
821 MLX5_IB_STAGE_SRQ,
822 MLX5_IB_STAGE_DEVICE_RESOURCES,
823 MLX5_IB_STAGE_DEVICE_NOTIFIER,
824 MLX5_IB_STAGE_ODP,
825 MLX5_IB_STAGE_COUNTERS,
826 MLX5_IB_STAGE_CONG_DEBUGFS,
827 MLX5_IB_STAGE_UAR,
828 MLX5_IB_STAGE_BFREG,
829 MLX5_IB_STAGE_PRE_IB_REG_UMR,
830 MLX5_IB_STAGE_WHITELIST_UID,
831 MLX5_IB_STAGE_IB_REG,
832 MLX5_IB_STAGE_POST_IB_REG_UMR,
833 MLX5_IB_STAGE_DELAY_DROP,
834 MLX5_IB_STAGE_CLASS_ATTR,
835 MLX5_IB_STAGE_MAX,
836 };
837
838 struct mlx5_ib_stage {
839 int (*init)(struct mlx5_ib_dev *dev);
840 void (*cleanup)(struct mlx5_ib_dev *dev);
841 };
842
843 #define STAGE_CREATE(_stage, _init, _cleanup) \
844 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
845
846 struct mlx5_ib_profile {
847 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
848 };
849
850 struct mlx5_ib_multiport_info {
851 struct list_head list;
852 struct mlx5_ib_dev *ibdev;
853 struct mlx5_core_dev *mdev;
854 struct notifier_block mdev_events;
855 struct completion unref_comp;
856 u64 sys_image_guid;
857 u32 mdev_refcnt;
858 bool is_master;
859 bool unaffiliate;
860 };
861
862 struct mlx5_ib_flow_action {
863 struct ib_flow_action ib_action;
864 union {
865 struct {
866 u64 ib_flags;
867 struct mlx5_accel_esp_xfrm *ctx;
868 } esp_aes_gcm;
869 struct {
870 struct mlx5_ib_dev *dev;
871 u32 sub_type;
872 union {
873 struct mlx5_modify_hdr *modify_hdr;
874 struct mlx5_pkt_reformat *pkt_reformat;
875 };
876 } flow_action_raw;
877 };
878 };
879
880 struct mlx5_dm {
881 struct mlx5_core_dev *dev;
882
883
884
885
886 spinlock_t lock;
887 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
888 };
889
890 struct mlx5_read_counters_attr {
891 struct mlx5_fc *hw_cntrs_hndl;
892 u64 *out;
893 u32 flags;
894 };
895
896 enum mlx5_ib_counters_type {
897 MLX5_IB_COUNTERS_FLOW,
898 };
899
900 struct mlx5_ib_mcounters {
901 struct ib_counters ibcntrs;
902 enum mlx5_ib_counters_type type;
903
904 u32 counters_num;
905 struct mlx5_fc *hw_cntrs_hndl;
906
907 int (*read_counters)(struct ib_device *ibdev,
908 struct mlx5_read_counters_attr *read_attr);
909
910 u32 cntrs_max_index;
911
912 u32 ncounters;
913
914 struct mlx5_ib_flow_counters_desc *counters_data;
915
916 struct mutex mcntrs_mutex;
917 };
918
919 static inline struct mlx5_ib_mcounters *
920 to_mcounters(struct ib_counters *ibcntrs)
921 {
922 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs);
923 }
924
925 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
926 bool is_egress,
927 struct mlx5_flow_act *action);
928 struct mlx5_ib_lb_state {
929
930 struct mutex mutex;
931 u32 user_td;
932 int qps;
933 bool enabled;
934 };
935
936 struct mlx5_ib_pf_eq {
937 struct notifier_block irq_nb;
938 struct mlx5_ib_dev *dev;
939 struct mlx5_eq *core;
940 struct work_struct work;
941 spinlock_t lock;
942 struct workqueue_struct *wq;
943 mempool_t *pool;
944 };
945
946 struct mlx5_devx_event_table {
947 struct mlx5_nb devx_nb;
948
949 struct mutex event_xa_lock;
950 struct xarray event_xa;
951 };
952
953 struct mlx5_ib_dev {
954 struct ib_device ib_dev;
955 struct mlx5_core_dev *mdev;
956 struct notifier_block mdev_events;
957 int num_ports;
958
959
960 struct mutex cap_mask_mutex;
961 bool ib_active;
962 struct umr_common umrc;
963
964
965 struct mlx5_ib_resources devr;
966 struct mlx5_mr_cache cache;
967 struct timer_list delay_timer;
968
969 struct mutex slow_path_mutex;
970 int fill_delay;
971 struct ib_odp_caps odp_caps;
972 u64 odp_max_size;
973 struct mlx5_ib_pf_eq odp_pf_eq;
974
975
976
977
978
979 struct srcu_struct mr_srcu;
980 u32 null_mkey;
981 struct mlx5_ib_flow_db *flow_db;
982
983 spinlock_t reset_flow_resource_lock;
984 struct list_head qp_list;
985
986 struct mlx5_ib_port *port;
987 struct mlx5_sq_bfreg bfreg;
988 struct mlx5_sq_bfreg fp_bfreg;
989 struct mlx5_ib_delay_drop delay_drop;
990 const struct mlx5_ib_profile *profile;
991 bool is_rep;
992 int lag_active;
993
994 struct mlx5_ib_lb_state lb;
995 u8 umr_fence;
996 struct list_head ib_dev_list;
997 u64 sys_image_guid;
998 struct mlx5_dm dm;
999 u16 devx_whitelist_uid;
1000 struct mlx5_srq_table srq_table;
1001 struct mlx5_async_ctx async_ctx;
1002 struct mlx5_devx_event_table devx_event_table;
1003 };
1004
1005 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
1006 {
1007 return container_of(mcq, struct mlx5_ib_cq, mcq);
1008 }
1009
1010 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
1011 {
1012 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
1013 }
1014
1015 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
1016 {
1017 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
1018 }
1019
1020 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata)
1021 {
1022 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1023 udata, struct mlx5_ib_ucontext, ibucontext);
1024
1025 return to_mdev(context->ibucontext.device);
1026 }
1027
1028 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
1029 {
1030 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
1031 }
1032
1033 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
1034 {
1035 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
1036 }
1037
1038 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
1039 {
1040 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
1041 }
1042
1043 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey)
1044 {
1045 return container_of(mmkey, struct mlx5_ib_mr, mmkey);
1046 }
1047
1048 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
1049 {
1050 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
1051 }
1052
1053 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
1054 {
1055 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
1056 }
1057
1058 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
1059 {
1060 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
1061 }
1062
1063 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
1064 {
1065 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
1066 }
1067
1068 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
1069 {
1070 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
1071 }
1072
1073 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
1074 {
1075 return container_of(msrq, struct mlx5_ib_srq, msrq);
1076 }
1077
1078 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm)
1079 {
1080 return container_of(ibdm, struct mlx5_ib_dm, ibdm);
1081 }
1082
1083 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
1084 {
1085 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
1086 }
1087
1088 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
1089 {
1090 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
1091 }
1092
1093 static inline struct mlx5_ib_flow_action *
1094 to_mflow_act(struct ib_flow_action *ibact)
1095 {
1096 return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
1097 }
1098
1099 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context,
1100 struct ib_udata *udata, unsigned long virt,
1101 struct mlx5_db *db);
1102 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
1103 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1104 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1105 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
1106 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_attr *ah_attr, u32 flags,
1107 struct ib_udata *udata);
1108 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1109 void mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags);
1110 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr,
1111 struct ib_udata *udata);
1112 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1113 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
1114 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
1115 void mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata);
1116 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1117 const struct ib_recv_wr **bad_wr);
1118 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1119 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1120 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1121 struct ib_qp_init_attr *init_attr,
1122 struct ib_udata *udata);
1123 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1124 int attr_mask, struct ib_udata *udata);
1125 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1126 struct ib_qp_init_attr *qp_init_attr);
1127 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata);
1128 void mlx5_ib_drain_sq(struct ib_qp *qp);
1129 void mlx5_ib_drain_rq(struct ib_qp *qp);
1130 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1131 const struct ib_send_wr **bad_wr);
1132 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
1133 const struct ib_recv_wr **bad_wr);
1134 int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1135 int buflen, size_t *bc);
1136 int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1137 int buflen, size_t *bc);
1138 int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index,
1139 void *buffer, int buflen, size_t *bc);
1140 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1141 struct ib_udata *udata);
1142 void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
1143 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1144 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1145 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
1146 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
1147 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
1148 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1149 u64 virt_addr, int access_flags,
1150 struct ib_udata *udata);
1151 int mlx5_ib_advise_mr(struct ib_pd *pd,
1152 enum ib_uverbs_advise_mr_advice advice,
1153 u32 flags,
1154 struct ib_sge *sg_list,
1155 u32 num_sge,
1156 struct uverbs_attr_bundle *attrs);
1157 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
1158 struct ib_udata *udata);
1159 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1160 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
1161 int page_shift, int flags);
1162 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1163 struct ib_udata *udata,
1164 int access_flags);
1165 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1166 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1167 u64 length, u64 virt_addr, int access_flags,
1168 struct ib_pd *pd, struct ib_udata *udata);
1169 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1170 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1171 u32 max_num_sg, struct ib_udata *udata);
1172 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd,
1173 u32 max_num_sg,
1174 u32 max_num_meta_sg);
1175 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1176 unsigned int *sg_offset);
1177 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
1178 int data_sg_nents, unsigned int *data_sg_offset,
1179 struct scatterlist *meta_sg, int meta_sg_nents,
1180 unsigned int *meta_sg_offset);
1181 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
1182 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1183 const struct ib_mad_hdr *in, size_t in_mad_size,
1184 struct ib_mad_hdr *out, size_t *out_mad_size,
1185 u16 *out_mad_pkey_index);
1186 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
1187 struct ib_udata *udata);
1188 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1189 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
1190 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
1191 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
1192 struct ib_smp *out_mad);
1193 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1194 __be64 *sys_image_guid);
1195 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1196 u16 *max_pkeys);
1197 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1198 u32 *vendor_id);
1199 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1200 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1201 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
1202 u16 *pkey);
1203 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
1204 union ib_gid *gid);
1205 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
1206 struct ib_port_attr *props);
1207 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1208 struct ib_port_attr *props);
1209 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
1210 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
1211 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr,
1212 unsigned long max_page_shift,
1213 int *count, int *shift,
1214 int *ncont, int *order);
1215 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1216 int page_shift, size_t offset, size_t num_pages,
1217 __be64 *pas, int access_flags);
1218 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1219 int page_shift, __be64 *pas, int access_flags);
1220 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1221 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq);
1222 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
1223 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
1224
1225 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry);
1226 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
1227 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1228 struct ib_mr_status *mr_status);
1229 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1230 struct ib_wq_init_attr *init_attr,
1231 struct ib_udata *udata);
1232 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata);
1233 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1234 u32 wq_attr_mask, struct ib_udata *udata);
1235 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
1236 struct ib_rwq_ind_table_init_attr *init_attr,
1237 struct ib_udata *udata);
1238 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1239 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev);
1240 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
1241 struct ib_ucontext *context,
1242 struct ib_dm_alloc_attr *attr,
1243 struct uverbs_attr_bundle *attrs);
1244 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs);
1245 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1246 struct ib_dm_mr_attr *attr,
1247 struct uverbs_attr_bundle *attrs);
1248
1249 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1250 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
1251 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1252 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev);
1253 int __init mlx5_ib_odp_init(void);
1254 void mlx5_ib_odp_cleanup(void);
1255 void mlx5_ib_invalidate_range(struct ib_umem_odp *umem_odp, unsigned long start,
1256 unsigned long end);
1257 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent);
1258 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
1259 size_t nentries, struct mlx5_ib_mr *mr, int flags);
1260
1261 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1262 enum ib_uverbs_advise_mr_advice advice,
1263 u32 flags, struct ib_sge *sg_list, u32 num_sge);
1264 #else
1265 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
1266 {
1267 return;
1268 }
1269
1270 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
1271 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {}
1272 static inline int mlx5_ib_odp_init(void) { return 0; }
1273 static inline void mlx5_ib_odp_cleanup(void) {}
1274 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {}
1275 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
1276 size_t nentries, struct mlx5_ib_mr *mr,
1277 int flags) {}
1278
1279 static inline int
1280 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1281 enum ib_uverbs_advise_mr_advice advice, u32 flags,
1282 struct ib_sge *sg_list, u32 num_sge)
1283 {
1284 return -EOPNOTSUPP;
1285 }
1286 static inline void mlx5_ib_invalidate_range(struct ib_umem_odp *umem_odp,
1287 unsigned long start,
1288 unsigned long end){};
1289 #endif
1290
1291
1292 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1293 const struct mlx5_ib_profile *profile,
1294 int stage);
1295 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
1296 const struct mlx5_ib_profile *profile);
1297
1298 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1299 u8 port, struct ifla_vf_info *info);
1300 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1301 u8 port, int state);
1302 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1303 u8 port, struct ifla_vf_stats *stats);
1304 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port,
1305 u64 guid, int type);
1306
1307 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
1308 const struct ib_gid_attr *attr);
1309
1310 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1311 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1312
1313
1314 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd,
1315 struct ib_qp_init_attr *init_attr);
1316 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp);
1317 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1318 int attr_mask);
1319 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1320 int qp_attr_mask,
1321 struct ib_qp_init_attr *qp_init_attr);
1322 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr,
1323 const struct ib_send_wr **bad_wr);
1324 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr,
1325 const struct ib_recv_wr **bad_wr);
1326 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1327
1328 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1329
1330 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1331 int bfregn);
1332 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1333 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1334 u8 ib_port_num,
1335 u8 *native_port_num);
1336 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1337 u8 port_num);
1338
1339 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
1340 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user);
1341 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid);
1342 void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev);
1343 void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev);
1344 const struct uverbs_object_tree_def *mlx5_ib_get_devx_tree(void);
1345 extern const struct uapi_definition mlx5_ib_devx_defs[];
1346 extern const struct uapi_definition mlx5_ib_flow_defs[];
1347 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add(
1348 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher,
1349 struct mlx5_flow_context *flow_context,
1350 struct mlx5_flow_act *flow_act, u32 counter_id,
1351 void *cmd_in, int inlen, int dest_id, int dest_type);
1352 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type);
1353 bool mlx5_ib_devx_is_flow_counter(void *obj, u32 *counter_id);
1354 int mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root);
1355 void mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction);
1356 #else
1357 static inline int
1358 mlx5_ib_devx_create(struct mlx5_ib_dev *dev,
1359 bool is_user) { return -EOPNOTSUPP; }
1360 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) {}
1361 static inline void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev) {}
1362 static inline void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev) {}
1363 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id,
1364 int *dest_type)
1365 {
1366 return false;
1367 }
1368 static inline void
1369 mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction)
1370 {
1371 return;
1372 };
1373 #endif
1374 static inline void init_query_mad(struct ib_smp *mad)
1375 {
1376 mad->base_version = 1;
1377 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1378 mad->class_version = 1;
1379 mad->method = IB_MGMT_METHOD_GET;
1380 }
1381
1382 static inline u8 convert_access(int acc)
1383 {
1384 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
1385 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
1386 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
1387 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
1388 MLX5_PERM_LOCAL_READ;
1389 }
1390
1391 static inline int is_qp1(enum ib_qp_type qp_type)
1392 {
1393 return qp_type == MLX5_IB_QPT_HW_GSI;
1394 }
1395
1396 #define MLX5_MAX_UMR_SHIFT 16
1397 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
1398
1399 static inline u32 check_cq_create_flags(u32 flags)
1400 {
1401
1402
1403
1404
1405 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1406 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1407 }
1408
1409 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1410 u32 *user_index)
1411 {
1412 if (cqe_version) {
1413 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1414 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1415 return -EINVAL;
1416 *user_index = cmd_uidx;
1417 } else {
1418 *user_index = MLX5_IB_DEFAULT_UIDX;
1419 }
1420
1421 return 0;
1422 }
1423
1424 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1425 struct mlx5_ib_create_qp *ucmd,
1426 int inlen,
1427 u32 *user_index)
1428 {
1429 u8 cqe_version = ucontext->cqe_version;
1430
1431 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) &&
1432 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1433 return 0;
1434
1435 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) !=
1436 !!cqe_version))
1437 return -EINVAL;
1438
1439 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1440 }
1441
1442 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1443 struct mlx5_ib_create_srq *ucmd,
1444 int inlen,
1445 u32 *user_index)
1446 {
1447 u8 cqe_version = ucontext->cqe_version;
1448
1449 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) &&
1450 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1451 return 0;
1452
1453 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) !=
1454 !!cqe_version))
1455 return -EINVAL;
1456
1457 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1458 }
1459
1460 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1461 {
1462 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1463 MLX5_UARS_IN_PAGE : 1;
1464 }
1465
1466 static inline int get_num_static_uars(struct mlx5_ib_dev *dev,
1467 struct mlx5_bfreg_info *bfregi)
1468 {
1469 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages;
1470 }
1471
1472 unsigned long mlx5_ib_get_xlt_emergency_page(void);
1473 void mlx5_ib_put_xlt_emergency_page(void);
1474
1475 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1476 struct mlx5_bfreg_info *bfregi, u32 bfregn,
1477 bool dyn_bfreg);
1478
1479 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter);
1480 u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num);
1481
1482 static inline bool mlx5_ib_can_use_umr(struct mlx5_ib_dev *dev,
1483 bool do_modify_atomic)
1484 {
1485 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
1486 return false;
1487
1488 if (do_modify_atomic &&
1489 MLX5_CAP_GEN(dev->mdev, atomic) &&
1490 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))
1491 return false;
1492
1493 return true;
1494 }
1495 #endif