root/arch/mips/include/asm/sgi/pi1.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * pi1.h: Definitions for SGI PI1 parallel port
   4  */
   5 
   6 #ifndef _SGI_PI1_H
   7 #define _SGI_PI1_H
   8 
   9 struct pi1_regs {
  10         u8 _data[3];
  11         volatile u8 data;
  12         u8 _ctrl[3];
  13         volatile u8 ctrl;
  14 #define PI1_CTRL_STROBE_N       0x01
  15 #define PI1_CTRL_AFD_N          0x02
  16 #define PI1_CTRL_INIT_N         0x04
  17 #define PI1_CTRL_SLIN_N         0x08
  18 #define PI1_CTRL_IRQ_ENA        0x10
  19 #define PI1_CTRL_DIR            0x20
  20 #define PI1_CTRL_SEL            0x40
  21         u8 _status[3];
  22         volatile u8 status;
  23 #define PI1_STAT_DEVID          0x03    /* bits 0-1 */
  24 #define PI1_STAT_NOINK          0x04    /* SGI MODE only */
  25 #define PI1_STAT_ERROR          0x08
  26 #define PI1_STAT_ONLINE         0x10
  27 #define PI1_STAT_PE             0x20
  28 #define PI1_STAT_ACK            0x40
  29 #define PI1_STAT_BUSY           0x80
  30         u8 _dmactrl[3];
  31         volatile u8 dmactrl;
  32 #define PI1_DMACTRL_FIFO_EMPTY  0x01    /* fifo empty R/O */
  33 #define PI1_DMACTRL_ABORT       0x02    /* reset DMA and internal fifo W/O */
  34 #define PI1_DMACTRL_STDMODE     0x00    /* bits 2-3 */
  35 #define PI1_DMACTRL_SGIMODE     0x04    /* bits 2-3 */
  36 #define PI1_DMACTRL_RICOHMODE   0x08    /* bits 2-3 */
  37 #define PI1_DMACTRL_HPMODE      0x0c    /* bits 2-3 */
  38 #define PI1_DMACTRL_BLKMODE     0x10    /* block mode */
  39 #define PI1_DMACTRL_FIFO_CLEAR  0x20    /* clear fifo W/O */
  40 #define PI1_DMACTRL_READ        0x40    /* read */
  41 #define PI1_DMACTRL_RUN         0x80    /* pedal to the metal */
  42         u8 _intstat[3];
  43         volatile u8 intstat;
  44 #define PI1_INTSTAT_ACK         0x04
  45 #define PI1_INTSTAT_FEMPTY      0x08
  46 #define PI1_INTSTAT_NOINK       0x10
  47 #define PI1_INTSTAT_ONLINE      0x20
  48 #define PI1_INTSTAT_ERR         0x40
  49 #define PI1_INTSTAT_PE          0x80
  50         u8 _intmask[3];
  51         volatile u8 intmask;            /* enabled low, reset high*/
  52 #define PI1_INTMASK_ACK         0x04
  53 #define PI1_INTMASK_FIFO_EMPTY  0x08
  54 #define PI1_INTMASK_NOINK       0x10
  55 #define PI1_INTMASK_ONLINE      0x20
  56 #define PI1_INTMASK_ERR         0x40
  57 #define PI1_INTMASK_PE          0x80
  58         u8 _timer1[3];
  59         volatile u8 timer1;
  60 #define PI1_TIME1               0x27
  61         u8 _timer2[3];
  62         volatile u8 timer2;
  63 #define PI1_TIME2               0x13
  64         u8 _timer3[3];
  65         volatile u8 timer3;
  66 #define PI1_TIME3               0x10
  67         u8 _timer4[3];
  68         volatile u8 timer4;
  69 #define PI1_TIME4               0x00
  70 };
  71 
  72 #endif