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37 #define QIB_7220_Revision_OFFS 0x0
38 #define QIB_7220_Revision_R_Simulator_LSB 0x3F
39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1
40 #define QIB_7220_Revision_R_Emulation_LSB 0x3E
41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1
42 #define QIB_7220_Revision_R_Emulation_Revcode_LSB 0x28
43 #define QIB_7220_Revision_R_Emulation_Revcode_RMASK 0x3FFFFF
44 #define QIB_7220_Revision_BoardID_LSB 0x20
45 #define QIB_7220_Revision_BoardID_RMASK 0xFF
46 #define QIB_7220_Revision_R_SW_LSB 0x18
47 #define QIB_7220_Revision_R_SW_RMASK 0xFF
48 #define QIB_7220_Revision_R_Arch_LSB 0x10
49 #define QIB_7220_Revision_R_Arch_RMASK 0xFF
50 #define QIB_7220_Revision_R_ChipRevMajor_LSB 0x8
51 #define QIB_7220_Revision_R_ChipRevMajor_RMASK 0xFF
52 #define QIB_7220_Revision_R_ChipRevMinor_LSB 0x0
53 #define QIB_7220_Revision_R_ChipRevMinor_RMASK 0xFF
54
55 #define QIB_7220_Control_OFFS 0x8
56 #define QIB_7220_Control_SyncResetExceptPcieIRAMRST_LSB 0x7
57 #define QIB_7220_Control_SyncResetExceptPcieIRAMRST_RMASK 0x1
58 #define QIB_7220_Control_PCIECplQDiagEn_LSB 0x6
59 #define QIB_7220_Control_PCIECplQDiagEn_RMASK 0x1
60 #define QIB_7220_Control_Reserved_LSB 0x5
61 #define QIB_7220_Control_Reserved_RMASK 0x1
62 #define QIB_7220_Control_TxLatency_LSB 0x4
63 #define QIB_7220_Control_TxLatency_RMASK 0x1
64 #define QIB_7220_Control_PCIERetryBufDiagEn_LSB 0x3
65 #define QIB_7220_Control_PCIERetryBufDiagEn_RMASK 0x1
66 #define QIB_7220_Control_LinkEn_LSB 0x2
67 #define QIB_7220_Control_LinkEn_RMASK 0x1
68 #define QIB_7220_Control_FreezeMode_LSB 0x1
69 #define QIB_7220_Control_FreezeMode_RMASK 0x1
70 #define QIB_7220_Control_SyncReset_LSB 0x0
71 #define QIB_7220_Control_SyncReset_RMASK 0x1
72
73 #define QIB_7220_PageAlign_OFFS 0x10
74
75 #define QIB_7220_PortCnt_OFFS 0x18
76
77 #define QIB_7220_SendRegBase_OFFS 0x30
78
79 #define QIB_7220_UserRegBase_OFFS 0x38
80
81 #define QIB_7220_CntrRegBase_OFFS 0x40
82
83 #define QIB_7220_Scratch_OFFS 0x48
84
85 #define QIB_7220_IntMask_OFFS 0x68
86 #define QIB_7220_IntMask_SDmaIntMask_LSB 0x3F
87 #define QIB_7220_IntMask_SDmaIntMask_RMASK 0x1
88 #define QIB_7220_IntMask_SDmaDisabledMasked_LSB 0x3E
89 #define QIB_7220_IntMask_SDmaDisabledMasked_RMASK 0x1
90 #define QIB_7220_IntMask_Reserved_LSB 0x31
91 #define QIB_7220_IntMask_Reserved_RMASK 0x1FFF
92 #define QIB_7220_IntMask_RcvUrg16IntMask_LSB 0x30
93 #define QIB_7220_IntMask_RcvUrg16IntMask_RMASK 0x1
94 #define QIB_7220_IntMask_RcvUrg15IntMask_LSB 0x2F
95 #define QIB_7220_IntMask_RcvUrg15IntMask_RMASK 0x1
96 #define QIB_7220_IntMask_RcvUrg14IntMask_LSB 0x2E
97 #define QIB_7220_IntMask_RcvUrg14IntMask_RMASK 0x1
98 #define QIB_7220_IntMask_RcvUrg13IntMask_LSB 0x2D
99 #define QIB_7220_IntMask_RcvUrg13IntMask_RMASK 0x1
100 #define QIB_7220_IntMask_RcvUrg12IntMask_LSB 0x2C
101 #define QIB_7220_IntMask_RcvUrg12IntMask_RMASK 0x1
102 #define QIB_7220_IntMask_RcvUrg11IntMask_LSB 0x2B
103 #define QIB_7220_IntMask_RcvUrg11IntMask_RMASK 0x1
104 #define QIB_7220_IntMask_RcvUrg10IntMask_LSB 0x2A
105 #define QIB_7220_IntMask_RcvUrg10IntMask_RMASK 0x1
106 #define QIB_7220_IntMask_RcvUrg9IntMask_LSB 0x29
107 #define QIB_7220_IntMask_RcvUrg9IntMask_RMASK 0x1
108 #define QIB_7220_IntMask_RcvUrg8IntMask_LSB 0x28
109 #define QIB_7220_IntMask_RcvUrg8IntMask_RMASK 0x1
110 #define QIB_7220_IntMask_RcvUrg7IntMask_LSB 0x27
111 #define QIB_7220_IntMask_RcvUrg7IntMask_RMASK 0x1
112 #define QIB_7220_IntMask_RcvUrg6IntMask_LSB 0x26
113 #define QIB_7220_IntMask_RcvUrg6IntMask_RMASK 0x1
114 #define QIB_7220_IntMask_RcvUrg5IntMask_LSB 0x25
115 #define QIB_7220_IntMask_RcvUrg5IntMask_RMASK 0x1
116 #define QIB_7220_IntMask_RcvUrg4IntMask_LSB 0x24
117 #define QIB_7220_IntMask_RcvUrg4IntMask_RMASK 0x1
118 #define QIB_7220_IntMask_RcvUrg3IntMask_LSB 0x23
119 #define QIB_7220_IntMask_RcvUrg3IntMask_RMASK 0x1
120 #define QIB_7220_IntMask_RcvUrg2IntMask_LSB 0x22
121 #define QIB_7220_IntMask_RcvUrg2IntMask_RMASK 0x1
122 #define QIB_7220_IntMask_RcvUrg1IntMask_LSB 0x21
123 #define QIB_7220_IntMask_RcvUrg1IntMask_RMASK 0x1
124 #define QIB_7220_IntMask_RcvUrg0IntMask_LSB 0x20
125 #define QIB_7220_IntMask_RcvUrg0IntMask_RMASK 0x1
126 #define QIB_7220_IntMask_ErrorIntMask_LSB 0x1F
127 #define QIB_7220_IntMask_ErrorIntMask_RMASK 0x1
128 #define QIB_7220_IntMask_PioSetIntMask_LSB 0x1E
129 #define QIB_7220_IntMask_PioSetIntMask_RMASK 0x1
130 #define QIB_7220_IntMask_PioBufAvailIntMask_LSB 0x1D
131 #define QIB_7220_IntMask_PioBufAvailIntMask_RMASK 0x1
132 #define QIB_7220_IntMask_assertGPIOIntMask_LSB 0x1C
133 #define QIB_7220_IntMask_assertGPIOIntMask_RMASK 0x1
134 #define QIB_7220_IntMask_IBSerdesTrimDoneIntMask_LSB 0x1B
135 #define QIB_7220_IntMask_IBSerdesTrimDoneIntMask_RMASK 0x1
136 #define QIB_7220_IntMask_JIntMask_LSB 0x1A
137 #define QIB_7220_IntMask_JIntMask_RMASK 0x1
138 #define QIB_7220_IntMask_Reserved1_LSB 0x11
139 #define QIB_7220_IntMask_Reserved1_RMASK 0x1FF
140 #define QIB_7220_IntMask_RcvAvail16IntMask_LSB 0x10
141 #define QIB_7220_IntMask_RcvAvail16IntMask_RMASK 0x1
142 #define QIB_7220_IntMask_RcvAvail15IntMask_LSB 0xF
143 #define QIB_7220_IntMask_RcvAvail15IntMask_RMASK 0x1
144 #define QIB_7220_IntMask_RcvAvail14IntMask_LSB 0xE
145 #define QIB_7220_IntMask_RcvAvail14IntMask_RMASK 0x1
146 #define QIB_7220_IntMask_RcvAvail13IntMask_LSB 0xD
147 #define QIB_7220_IntMask_RcvAvail13IntMask_RMASK 0x1
148 #define QIB_7220_IntMask_RcvAvail12IntMask_LSB 0xC
149 #define QIB_7220_IntMask_RcvAvail12IntMask_RMASK 0x1
150 #define QIB_7220_IntMask_RcvAvail11IntMask_LSB 0xB
151 #define QIB_7220_IntMask_RcvAvail11IntMask_RMASK 0x1
152 #define QIB_7220_IntMask_RcvAvail10IntMask_LSB 0xA
153 #define QIB_7220_IntMask_RcvAvail10IntMask_RMASK 0x1
154 #define QIB_7220_IntMask_RcvAvail9IntMask_LSB 0x9
155 #define QIB_7220_IntMask_RcvAvail9IntMask_RMASK 0x1
156 #define QIB_7220_IntMask_RcvAvail8IntMask_LSB 0x8
157 #define QIB_7220_IntMask_RcvAvail8IntMask_RMASK 0x1
158 #define QIB_7220_IntMask_RcvAvail7IntMask_LSB 0x7
159 #define QIB_7220_IntMask_RcvAvail7IntMask_RMASK 0x1
160 #define QIB_7220_IntMask_RcvAvail6IntMask_LSB 0x6
161 #define QIB_7220_IntMask_RcvAvail6IntMask_RMASK 0x1
162 #define QIB_7220_IntMask_RcvAvail5IntMask_LSB 0x5
163 #define QIB_7220_IntMask_RcvAvail5IntMask_RMASK 0x1
164 #define QIB_7220_IntMask_RcvAvail4IntMask_LSB 0x4
165 #define QIB_7220_IntMask_RcvAvail4IntMask_RMASK 0x1
166 #define QIB_7220_IntMask_RcvAvail3IntMask_LSB 0x3
167 #define QIB_7220_IntMask_RcvAvail3IntMask_RMASK 0x1
168 #define QIB_7220_IntMask_RcvAvail2IntMask_LSB 0x2
169 #define QIB_7220_IntMask_RcvAvail2IntMask_RMASK 0x1
170 #define QIB_7220_IntMask_RcvAvail1IntMask_LSB 0x1
171 #define QIB_7220_IntMask_RcvAvail1IntMask_RMASK 0x1
172 #define QIB_7220_IntMask_RcvAvail0IntMask_LSB 0x0
173 #define QIB_7220_IntMask_RcvAvail0IntMask_RMASK 0x1
174
175 #define QIB_7220_IntStatus_OFFS 0x70
176 #define QIB_7220_IntStatus_SDmaInt_LSB 0x3F
177 #define QIB_7220_IntStatus_SDmaInt_RMASK 0x1
178 #define QIB_7220_IntStatus_SDmaDisabled_LSB 0x3E
179 #define QIB_7220_IntStatus_SDmaDisabled_RMASK 0x1
180 #define QIB_7220_IntStatus_Reserved_LSB 0x31
181 #define QIB_7220_IntStatus_Reserved_RMASK 0x1FFF
182 #define QIB_7220_IntStatus_RcvUrg16_LSB 0x30
183 #define QIB_7220_IntStatus_RcvUrg16_RMASK 0x1
184 #define QIB_7220_IntStatus_RcvUrg15_LSB 0x2F
185 #define QIB_7220_IntStatus_RcvUrg15_RMASK 0x1
186 #define QIB_7220_IntStatus_RcvUrg14_LSB 0x2E
187 #define QIB_7220_IntStatus_RcvUrg14_RMASK 0x1
188 #define QIB_7220_IntStatus_RcvUrg13_LSB 0x2D
189 #define QIB_7220_IntStatus_RcvUrg13_RMASK 0x1
190 #define QIB_7220_IntStatus_RcvUrg12_LSB 0x2C
191 #define QIB_7220_IntStatus_RcvUrg12_RMASK 0x1
192 #define QIB_7220_IntStatus_RcvUrg11_LSB 0x2B
193 #define QIB_7220_IntStatus_RcvUrg11_RMASK 0x1
194 #define QIB_7220_IntStatus_RcvUrg10_LSB 0x2A
195 #define QIB_7220_IntStatus_RcvUrg10_RMASK 0x1
196 #define QIB_7220_IntStatus_RcvUrg9_LSB 0x29
197 #define QIB_7220_IntStatus_RcvUrg9_RMASK 0x1
198 #define QIB_7220_IntStatus_RcvUrg8_LSB 0x28
199 #define QIB_7220_IntStatus_RcvUrg8_RMASK 0x1
200 #define QIB_7220_IntStatus_RcvUrg7_LSB 0x27
201 #define QIB_7220_IntStatus_RcvUrg7_RMASK 0x1
202 #define QIB_7220_IntStatus_RcvUrg6_LSB 0x26
203 #define QIB_7220_IntStatus_RcvUrg6_RMASK 0x1
204 #define QIB_7220_IntStatus_RcvUrg5_LSB 0x25
205 #define QIB_7220_IntStatus_RcvUrg5_RMASK 0x1
206 #define QIB_7220_IntStatus_RcvUrg4_LSB 0x24
207 #define QIB_7220_IntStatus_RcvUrg4_RMASK 0x1
208 #define QIB_7220_IntStatus_RcvUrg3_LSB 0x23
209 #define QIB_7220_IntStatus_RcvUrg3_RMASK 0x1
210 #define QIB_7220_IntStatus_RcvUrg2_LSB 0x22
211 #define QIB_7220_IntStatus_RcvUrg2_RMASK 0x1
212 #define QIB_7220_IntStatus_RcvUrg1_LSB 0x21
213 #define QIB_7220_IntStatus_RcvUrg1_RMASK 0x1
214 #define QIB_7220_IntStatus_RcvUrg0_LSB 0x20
215 #define QIB_7220_IntStatus_RcvUrg0_RMASK 0x1
216 #define QIB_7220_IntStatus_Error_LSB 0x1F
217 #define QIB_7220_IntStatus_Error_RMASK 0x1
218 #define QIB_7220_IntStatus_PioSent_LSB 0x1E
219 #define QIB_7220_IntStatus_PioSent_RMASK 0x1
220 #define QIB_7220_IntStatus_PioBufAvail_LSB 0x1D
221 #define QIB_7220_IntStatus_PioBufAvail_RMASK 0x1
222 #define QIB_7220_IntStatus_assertGPIO_LSB 0x1C
223 #define QIB_7220_IntStatus_assertGPIO_RMASK 0x1
224 #define QIB_7220_IntStatus_IBSerdesTrimDone_LSB 0x1B
225 #define QIB_7220_IntStatus_IBSerdesTrimDone_RMASK 0x1
226 #define QIB_7220_IntStatus_JInt_LSB 0x1A
227 #define QIB_7220_IntStatus_JInt_RMASK 0x1
228 #define QIB_7220_IntStatus_Reserved1_LSB 0x11
229 #define QIB_7220_IntStatus_Reserved1_RMASK 0x1FF
230 #define QIB_7220_IntStatus_RcvAvail16_LSB 0x10
231 #define QIB_7220_IntStatus_RcvAvail16_RMASK 0x1
232 #define QIB_7220_IntStatus_RcvAvail15_LSB 0xF
233 #define QIB_7220_IntStatus_RcvAvail15_RMASK 0x1
234 #define QIB_7220_IntStatus_RcvAvail14_LSB 0xE
235 #define QIB_7220_IntStatus_RcvAvail14_RMASK 0x1
236 #define QIB_7220_IntStatus_RcvAvail13_LSB 0xD
237 #define QIB_7220_IntStatus_RcvAvail13_RMASK 0x1
238 #define QIB_7220_IntStatus_RcvAvail12_LSB 0xC
239 #define QIB_7220_IntStatus_RcvAvail12_RMASK 0x1
240 #define QIB_7220_IntStatus_RcvAvail11_LSB 0xB
241 #define QIB_7220_IntStatus_RcvAvail11_RMASK 0x1
242 #define QIB_7220_IntStatus_RcvAvail10_LSB 0xA
243 #define QIB_7220_IntStatus_RcvAvail10_RMASK 0x1
244 #define QIB_7220_IntStatus_RcvAvail9_LSB 0x9
245 #define QIB_7220_IntStatus_RcvAvail9_RMASK 0x1
246 #define QIB_7220_IntStatus_RcvAvail8_LSB 0x8
247 #define QIB_7220_IntStatus_RcvAvail8_RMASK 0x1
248 #define QIB_7220_IntStatus_RcvAvail7_LSB 0x7
249 #define QIB_7220_IntStatus_RcvAvail7_RMASK 0x1
250 #define QIB_7220_IntStatus_RcvAvail6_LSB 0x6
251 #define QIB_7220_IntStatus_RcvAvail6_RMASK 0x1
252 #define QIB_7220_IntStatus_RcvAvail5_LSB 0x5
253 #define QIB_7220_IntStatus_RcvAvail5_RMASK 0x1
254 #define QIB_7220_IntStatus_RcvAvail4_LSB 0x4
255 #define QIB_7220_IntStatus_RcvAvail4_RMASK 0x1
256 #define QIB_7220_IntStatus_RcvAvail3_LSB 0x3
257 #define QIB_7220_IntStatus_RcvAvail3_RMASK 0x1
258 #define QIB_7220_IntStatus_RcvAvail2_LSB 0x2
259 #define QIB_7220_IntStatus_RcvAvail2_RMASK 0x1
260 #define QIB_7220_IntStatus_RcvAvail1_LSB 0x1
261 #define QIB_7220_IntStatus_RcvAvail1_RMASK 0x1
262 #define QIB_7220_IntStatus_RcvAvail0_LSB 0x0
263 #define QIB_7220_IntStatus_RcvAvail0_RMASK 0x1
264
265 #define QIB_7220_IntClear_OFFS 0x78
266 #define QIB_7220_IntClear_SDmaIntClear_LSB 0x3F
267 #define QIB_7220_IntClear_SDmaIntClear_RMASK 0x1
268 #define QIB_7220_IntClear_SDmaDisabledClear_LSB 0x3E
269 #define QIB_7220_IntClear_SDmaDisabledClear_RMASK 0x1
270 #define QIB_7220_IntClear_Reserved_LSB 0x31
271 #define QIB_7220_IntClear_Reserved_RMASK 0x1FFF
272 #define QIB_7220_IntClear_RcvUrg16IntClear_LSB 0x30
273 #define QIB_7220_IntClear_RcvUrg16IntClear_RMASK 0x1
274 #define QIB_7220_IntClear_RcvUrg15IntClear_LSB 0x2F
275 #define QIB_7220_IntClear_RcvUrg15IntClear_RMASK 0x1
276 #define QIB_7220_IntClear_RcvUrg14IntClear_LSB 0x2E
277 #define QIB_7220_IntClear_RcvUrg14IntClear_RMASK 0x1
278 #define QIB_7220_IntClear_RcvUrg13IntClear_LSB 0x2D
279 #define QIB_7220_IntClear_RcvUrg13IntClear_RMASK 0x1
280 #define QIB_7220_IntClear_RcvUrg12IntClear_LSB 0x2C
281 #define QIB_7220_IntClear_RcvUrg12IntClear_RMASK 0x1
282 #define QIB_7220_IntClear_RcvUrg11IntClear_LSB 0x2B
283 #define QIB_7220_IntClear_RcvUrg11IntClear_RMASK 0x1
284 #define QIB_7220_IntClear_RcvUrg10IntClear_LSB 0x2A
285 #define QIB_7220_IntClear_RcvUrg10IntClear_RMASK 0x1
286 #define QIB_7220_IntClear_RcvUrg9IntClear_LSB 0x29
287 #define QIB_7220_IntClear_RcvUrg9IntClear_RMASK 0x1
288 #define QIB_7220_IntClear_RcvUrg8IntClear_LSB 0x28
289 #define QIB_7220_IntClear_RcvUrg8IntClear_RMASK 0x1
290 #define QIB_7220_IntClear_RcvUrg7IntClear_LSB 0x27
291 #define QIB_7220_IntClear_RcvUrg7IntClear_RMASK 0x1
292 #define QIB_7220_IntClear_RcvUrg6IntClear_LSB 0x26
293 #define QIB_7220_IntClear_RcvUrg6IntClear_RMASK 0x1
294 #define QIB_7220_IntClear_RcvUrg5IntClear_LSB 0x25
295 #define QIB_7220_IntClear_RcvUrg5IntClear_RMASK 0x1
296 #define QIB_7220_IntClear_RcvUrg4IntClear_LSB 0x24
297 #define QIB_7220_IntClear_RcvUrg4IntClear_RMASK 0x1
298 #define QIB_7220_IntClear_RcvUrg3IntClear_LSB 0x23
299 #define QIB_7220_IntClear_RcvUrg3IntClear_RMASK 0x1
300 #define QIB_7220_IntClear_RcvUrg2IntClear_LSB 0x22
301 #define QIB_7220_IntClear_RcvUrg2IntClear_RMASK 0x1
302 #define QIB_7220_IntClear_RcvUrg1IntClear_LSB 0x21
303 #define QIB_7220_IntClear_RcvUrg1IntClear_RMASK 0x1
304 #define QIB_7220_IntClear_RcvUrg0IntClear_LSB 0x20
305 #define QIB_7220_IntClear_RcvUrg0IntClear_RMASK 0x1
306 #define QIB_7220_IntClear_ErrorIntClear_LSB 0x1F
307 #define QIB_7220_IntClear_ErrorIntClear_RMASK 0x1
308 #define QIB_7220_IntClear_PioSetIntClear_LSB 0x1E
309 #define QIB_7220_IntClear_PioSetIntClear_RMASK 0x1
310 #define QIB_7220_IntClear_PioBufAvailIntClear_LSB 0x1D
311 #define QIB_7220_IntClear_PioBufAvailIntClear_RMASK 0x1
312 #define QIB_7220_IntClear_assertGPIOIntClear_LSB 0x1C
313 #define QIB_7220_IntClear_assertGPIOIntClear_RMASK 0x1
314 #define QIB_7220_IntClear_IBSerdesTrimDoneClear_LSB 0x1B
315 #define QIB_7220_IntClear_IBSerdesTrimDoneClear_RMASK 0x1
316 #define QIB_7220_IntClear_JIntClear_LSB 0x1A
317 #define QIB_7220_IntClear_JIntClear_RMASK 0x1
318 #define QIB_7220_IntClear_Reserved1_LSB 0x11
319 #define QIB_7220_IntClear_Reserved1_RMASK 0x1FF
320 #define QIB_7220_IntClear_RcvAvail16IntClear_LSB 0x10
321 #define QIB_7220_IntClear_RcvAvail16IntClear_RMASK 0x1
322 #define QIB_7220_IntClear_RcvAvail15IntClear_LSB 0xF
323 #define QIB_7220_IntClear_RcvAvail15IntClear_RMASK 0x1
324 #define QIB_7220_IntClear_RcvAvail14IntClear_LSB 0xE
325 #define QIB_7220_IntClear_RcvAvail14IntClear_RMASK 0x1
326 #define QIB_7220_IntClear_RcvAvail13IntClear_LSB 0xD
327 #define QIB_7220_IntClear_RcvAvail13IntClear_RMASK 0x1
328 #define QIB_7220_IntClear_RcvAvail12IntClear_LSB 0xC
329 #define QIB_7220_IntClear_RcvAvail12IntClear_RMASK 0x1
330 #define QIB_7220_IntClear_RcvAvail11IntClear_LSB 0xB
331 #define QIB_7220_IntClear_RcvAvail11IntClear_RMASK 0x1
332 #define QIB_7220_IntClear_RcvAvail10IntClear_LSB 0xA
333 #define QIB_7220_IntClear_RcvAvail10IntClear_RMASK 0x1
334 #define QIB_7220_IntClear_RcvAvail9IntClear_LSB 0x9
335 #define QIB_7220_IntClear_RcvAvail9IntClear_RMASK 0x1
336 #define QIB_7220_IntClear_RcvAvail8IntClear_LSB 0x8
337 #define QIB_7220_IntClear_RcvAvail8IntClear_RMASK 0x1
338 #define QIB_7220_IntClear_RcvAvail7IntClear_LSB 0x7
339 #define QIB_7220_IntClear_RcvAvail7IntClear_RMASK 0x1
340 #define QIB_7220_IntClear_RcvAvail6IntClear_LSB 0x6
341 #define QIB_7220_IntClear_RcvAvail6IntClear_RMASK 0x1
342 #define QIB_7220_IntClear_RcvAvail5IntClear_LSB 0x5
343 #define QIB_7220_IntClear_RcvAvail5IntClear_RMASK 0x1
344 #define QIB_7220_IntClear_RcvAvail4IntClear_LSB 0x4
345 #define QIB_7220_IntClear_RcvAvail4IntClear_RMASK 0x1
346 #define QIB_7220_IntClear_RcvAvail3IntClear_LSB 0x3
347 #define QIB_7220_IntClear_RcvAvail3IntClear_RMASK 0x1
348 #define QIB_7220_IntClear_RcvAvail2IntClear_LSB 0x2
349 #define QIB_7220_IntClear_RcvAvail2IntClear_RMASK 0x1
350 #define QIB_7220_IntClear_RcvAvail1IntClear_LSB 0x1
351 #define QIB_7220_IntClear_RcvAvail1IntClear_RMASK 0x1
352 #define QIB_7220_IntClear_RcvAvail0IntClear_LSB 0x0
353 #define QIB_7220_IntClear_RcvAvail0IntClear_RMASK 0x1
354
355 #define QIB_7220_ErrMask_OFFS 0x80
356 #define QIB_7220_ErrMask_Reserved_LSB 0x36
357 #define QIB_7220_ErrMask_Reserved_RMASK 0x3FF
358 #define QIB_7220_ErrMask_InvalidEEPCmdMask_LSB 0x35
359 #define QIB_7220_ErrMask_InvalidEEPCmdMask_RMASK 0x1
360 #define QIB_7220_ErrMask_SDmaDescAddrMisalignErrMask_LSB 0x34
361 #define QIB_7220_ErrMask_SDmaDescAddrMisalignErrMask_RMASK 0x1
362 #define QIB_7220_ErrMask_HardwareErrMask_LSB 0x33
363 #define QIB_7220_ErrMask_HardwareErrMask_RMASK 0x1
364 #define QIB_7220_ErrMask_ResetNegatedMask_LSB 0x32
365 #define QIB_7220_ErrMask_ResetNegatedMask_RMASK 0x1
366 #define QIB_7220_ErrMask_InvalidAddrErrMask_LSB 0x31
367 #define QIB_7220_ErrMask_InvalidAddrErrMask_RMASK 0x1
368 #define QIB_7220_ErrMask_IBStatusChangedMask_LSB 0x30
369 #define QIB_7220_ErrMask_IBStatusChangedMask_RMASK 0x1
370 #define QIB_7220_ErrMask_SDmaUnexpDataErrMask_LSB 0x2F
371 #define QIB_7220_ErrMask_SDmaUnexpDataErrMask_RMASK 0x1
372 #define QIB_7220_ErrMask_SDmaMissingDwErrMask_LSB 0x2E
373 #define QIB_7220_ErrMask_SDmaMissingDwErrMask_RMASK 0x1
374 #define QIB_7220_ErrMask_SDmaDwEnErrMask_LSB 0x2D
375 #define QIB_7220_ErrMask_SDmaDwEnErrMask_RMASK 0x1
376 #define QIB_7220_ErrMask_SDmaRpyTagErrMask_LSB 0x2C
377 #define QIB_7220_ErrMask_SDmaRpyTagErrMask_RMASK 0x1
378 #define QIB_7220_ErrMask_SDma1stDescErrMask_LSB 0x2B
379 #define QIB_7220_ErrMask_SDma1stDescErrMask_RMASK 0x1
380 #define QIB_7220_ErrMask_SDmaBaseErrMask_LSB 0x2A
381 #define QIB_7220_ErrMask_SDmaBaseErrMask_RMASK 0x1
382 #define QIB_7220_ErrMask_SDmaTailOutOfBoundErrMask_LSB 0x29
383 #define QIB_7220_ErrMask_SDmaTailOutOfBoundErrMask_RMASK 0x1
384 #define QIB_7220_ErrMask_SDmaOutOfBoundErrMask_LSB 0x28
385 #define QIB_7220_ErrMask_SDmaOutOfBoundErrMask_RMASK 0x1
386 #define QIB_7220_ErrMask_SDmaGenMismatchErrMask_LSB 0x27
387 #define QIB_7220_ErrMask_SDmaGenMismatchErrMask_RMASK 0x1
388 #define QIB_7220_ErrMask_SendBufMisuseErrMask_LSB 0x26
389 #define QIB_7220_ErrMask_SendBufMisuseErrMask_RMASK 0x1
390 #define QIB_7220_ErrMask_SendUnsupportedVLErrMask_LSB 0x25
391 #define QIB_7220_ErrMask_SendUnsupportedVLErrMask_RMASK 0x1
392 #define QIB_7220_ErrMask_SendUnexpectedPktNumErrMask_LSB 0x24
393 #define QIB_7220_ErrMask_SendUnexpectedPktNumErrMask_RMASK 0x1
394 #define QIB_7220_ErrMask_SendPioArmLaunchErrMask_LSB 0x23
395 #define QIB_7220_ErrMask_SendPioArmLaunchErrMask_RMASK 0x1
396 #define QIB_7220_ErrMask_SendDroppedDataPktErrMask_LSB 0x22
397 #define QIB_7220_ErrMask_SendDroppedDataPktErrMask_RMASK 0x1
398 #define QIB_7220_ErrMask_SendDroppedSmpPktErrMask_LSB 0x21
399 #define QIB_7220_ErrMask_SendDroppedSmpPktErrMask_RMASK 0x1
400 #define QIB_7220_ErrMask_SendPktLenErrMask_LSB 0x20
401 #define QIB_7220_ErrMask_SendPktLenErrMask_RMASK 0x1
402 #define QIB_7220_ErrMask_SendUnderRunErrMask_LSB 0x1F
403 #define QIB_7220_ErrMask_SendUnderRunErrMask_RMASK 0x1
404 #define QIB_7220_ErrMask_SendMaxPktLenErrMask_LSB 0x1E
405 #define QIB_7220_ErrMask_SendMaxPktLenErrMask_RMASK 0x1
406 #define QIB_7220_ErrMask_SendMinPktLenErrMask_LSB 0x1D
407 #define QIB_7220_ErrMask_SendMinPktLenErrMask_RMASK 0x1
408 #define QIB_7220_ErrMask_SDmaDisabledErrMask_LSB 0x1C
409 #define QIB_7220_ErrMask_SDmaDisabledErrMask_RMASK 0x1
410 #define QIB_7220_ErrMask_SendSpecialTriggerErrMask_LSB 0x1B
411 #define QIB_7220_ErrMask_SendSpecialTriggerErrMask_RMASK 0x1
412 #define QIB_7220_ErrMask_Reserved1_LSB 0x12
413 #define QIB_7220_ErrMask_Reserved1_RMASK 0x1FF
414 #define QIB_7220_ErrMask_RcvIBLostLinkErrMask_LSB 0x11
415 #define QIB_7220_ErrMask_RcvIBLostLinkErrMask_RMASK 0x1
416 #define QIB_7220_ErrMask_RcvHdrErrMask_LSB 0x10
417 #define QIB_7220_ErrMask_RcvHdrErrMask_RMASK 0x1
418 #define QIB_7220_ErrMask_RcvHdrLenErrMask_LSB 0xF
419 #define QIB_7220_ErrMask_RcvHdrLenErrMask_RMASK 0x1
420 #define QIB_7220_ErrMask_RcvBadTidErrMask_LSB 0xE
421 #define QIB_7220_ErrMask_RcvBadTidErrMask_RMASK 0x1
422 #define QIB_7220_ErrMask_RcvHdrFullErrMask_LSB 0xD
423 #define QIB_7220_ErrMask_RcvHdrFullErrMask_RMASK 0x1
424 #define QIB_7220_ErrMask_RcvEgrFullErrMask_LSB 0xC
425 #define QIB_7220_ErrMask_RcvEgrFullErrMask_RMASK 0x1
426 #define QIB_7220_ErrMask_RcvBadVersionErrMask_LSB 0xB
427 #define QIB_7220_ErrMask_RcvBadVersionErrMask_RMASK 0x1
428 #define QIB_7220_ErrMask_RcvIBFlowErrMask_LSB 0xA
429 #define QIB_7220_ErrMask_RcvIBFlowErrMask_RMASK 0x1
430 #define QIB_7220_ErrMask_RcvEBPErrMask_LSB 0x9
431 #define QIB_7220_ErrMask_RcvEBPErrMask_RMASK 0x1
432 #define QIB_7220_ErrMask_RcvUnsupportedVLErrMask_LSB 0x8
433 #define QIB_7220_ErrMask_RcvUnsupportedVLErrMask_RMASK 0x1
434 #define QIB_7220_ErrMask_RcvUnexpectedCharErrMask_LSB 0x7
435 #define QIB_7220_ErrMask_RcvUnexpectedCharErrMask_RMASK 0x1
436 #define QIB_7220_ErrMask_RcvShortPktLenErrMask_LSB 0x6
437 #define QIB_7220_ErrMask_RcvShortPktLenErrMask_RMASK 0x1
438 #define QIB_7220_ErrMask_RcvLongPktLenErrMask_LSB 0x5
439 #define QIB_7220_ErrMask_RcvLongPktLenErrMask_RMASK 0x1
440 #define QIB_7220_ErrMask_RcvMaxPktLenErrMask_LSB 0x4
441 #define QIB_7220_ErrMask_RcvMaxPktLenErrMask_RMASK 0x1
442 #define QIB_7220_ErrMask_RcvMinPktLenErrMask_LSB 0x3
443 #define QIB_7220_ErrMask_RcvMinPktLenErrMask_RMASK 0x1
444 #define QIB_7220_ErrMask_RcvICRCErrMask_LSB 0x2
445 #define QIB_7220_ErrMask_RcvICRCErrMask_RMASK 0x1
446 #define QIB_7220_ErrMask_RcvVCRCErrMask_LSB 0x1
447 #define QIB_7220_ErrMask_RcvVCRCErrMask_RMASK 0x1
448 #define QIB_7220_ErrMask_RcvFormatErrMask_LSB 0x0
449 #define QIB_7220_ErrMask_RcvFormatErrMask_RMASK 0x1
450
451 #define QIB_7220_ErrStatus_OFFS 0x88
452 #define QIB_7220_ErrStatus_Reserved_LSB 0x36
453 #define QIB_7220_ErrStatus_Reserved_RMASK 0x3FF
454 #define QIB_7220_ErrStatus_InvalidEEPCmdErr_LSB 0x35
455 #define QIB_7220_ErrStatus_InvalidEEPCmdErr_RMASK 0x1
456 #define QIB_7220_ErrStatus_SDmaDescAddrMisalignErr_LSB 0x34
457 #define QIB_7220_ErrStatus_SDmaDescAddrMisalignErr_RMASK 0x1
458 #define QIB_7220_ErrStatus_HardwareErr_LSB 0x33
459 #define QIB_7220_ErrStatus_HardwareErr_RMASK 0x1
460 #define QIB_7220_ErrStatus_ResetNegated_LSB 0x32
461 #define QIB_7220_ErrStatus_ResetNegated_RMASK 0x1
462 #define QIB_7220_ErrStatus_InvalidAddrErr_LSB 0x31
463 #define QIB_7220_ErrStatus_InvalidAddrErr_RMASK 0x1
464 #define QIB_7220_ErrStatus_IBStatusChanged_LSB 0x30
465 #define QIB_7220_ErrStatus_IBStatusChanged_RMASK 0x1
466 #define QIB_7220_ErrStatus_SDmaUnexpDataErr_LSB 0x2F
467 #define QIB_7220_ErrStatus_SDmaUnexpDataErr_RMASK 0x1
468 #define QIB_7220_ErrStatus_SDmaMissingDwErr_LSB 0x2E
469 #define QIB_7220_ErrStatus_SDmaMissingDwErr_RMASK 0x1
470 #define QIB_7220_ErrStatus_SDmaDwEnErr_LSB 0x2D
471 #define QIB_7220_ErrStatus_SDmaDwEnErr_RMASK 0x1
472 #define QIB_7220_ErrStatus_SDmaRpyTagErr_LSB 0x2C
473 #define QIB_7220_ErrStatus_SDmaRpyTagErr_RMASK 0x1
474 #define QIB_7220_ErrStatus_SDma1stDescErr_LSB 0x2B
475 #define QIB_7220_ErrStatus_SDma1stDescErr_RMASK 0x1
476 #define QIB_7220_ErrStatus_SDmaBaseErr_LSB 0x2A
477 #define QIB_7220_ErrStatus_SDmaBaseErr_RMASK 0x1
478 #define QIB_7220_ErrStatus_SDmaTailOutOfBoundErr_LSB 0x29
479 #define QIB_7220_ErrStatus_SDmaTailOutOfBoundErr_RMASK 0x1
480 #define QIB_7220_ErrStatus_SDmaOutOfBoundErr_LSB 0x28
481 #define QIB_7220_ErrStatus_SDmaOutOfBoundErr_RMASK 0x1
482 #define QIB_7220_ErrStatus_SDmaGenMismatchErr_LSB 0x27
483 #define QIB_7220_ErrStatus_SDmaGenMismatchErr_RMASK 0x1
484 #define QIB_7220_ErrStatus_SendBufMisuseErr_LSB 0x26
485 #define QIB_7220_ErrStatus_SendBufMisuseErr_RMASK 0x1
486 #define QIB_7220_ErrStatus_SendUnsupportedVLErr_LSB 0x25
487 #define QIB_7220_ErrStatus_SendUnsupportedVLErr_RMASK 0x1
488 #define QIB_7220_ErrStatus_SendUnexpectedPktNumErr_LSB 0x24
489 #define QIB_7220_ErrStatus_SendUnexpectedPktNumErr_RMASK 0x1
490 #define QIB_7220_ErrStatus_SendPioArmLaunchErr_LSB 0x23
491 #define QIB_7220_ErrStatus_SendPioArmLaunchErr_RMASK 0x1
492 #define QIB_7220_ErrStatus_SendDroppedDataPktErr_LSB 0x22
493 #define QIB_7220_ErrStatus_SendDroppedDataPktErr_RMASK 0x1
494 #define QIB_7220_ErrStatus_SendDroppedSmpPktErr_LSB 0x21
495 #define QIB_7220_ErrStatus_SendDroppedSmpPktErr_RMASK 0x1
496 #define QIB_7220_ErrStatus_SendPktLenErr_LSB 0x20
497 #define QIB_7220_ErrStatus_SendPktLenErr_RMASK 0x1
498 #define QIB_7220_ErrStatus_SendUnderRunErr_LSB 0x1F
499 #define QIB_7220_ErrStatus_SendUnderRunErr_RMASK 0x1
500 #define QIB_7220_ErrStatus_SendMaxPktLenErr_LSB 0x1E
501 #define QIB_7220_ErrStatus_SendMaxPktLenErr_RMASK 0x1
502 #define QIB_7220_ErrStatus_SendMinPktLenErr_LSB 0x1D
503 #define QIB_7220_ErrStatus_SendMinPktLenErr_RMASK 0x1
504 #define QIB_7220_ErrStatus_SDmaDisabledErr_LSB 0x1C
505 #define QIB_7220_ErrStatus_SDmaDisabledErr_RMASK 0x1
506 #define QIB_7220_ErrStatus_SendSpecialTriggerErr_LSB 0x1B
507 #define QIB_7220_ErrStatus_SendSpecialTriggerErr_RMASK 0x1
508 #define QIB_7220_ErrStatus_Reserved1_LSB 0x12
509 #define QIB_7220_ErrStatus_Reserved1_RMASK 0x1FF
510 #define QIB_7220_ErrStatus_RcvIBLostLinkErr_LSB 0x11
511 #define QIB_7220_ErrStatus_RcvIBLostLinkErr_RMASK 0x1
512 #define QIB_7220_ErrStatus_RcvHdrErr_LSB 0x10
513 #define QIB_7220_ErrStatus_RcvHdrErr_RMASK 0x1
514 #define QIB_7220_ErrStatus_RcvHdrLenErr_LSB 0xF
515 #define QIB_7220_ErrStatus_RcvHdrLenErr_RMASK 0x1
516 #define QIB_7220_ErrStatus_RcvBadTidErr_LSB 0xE
517 #define QIB_7220_ErrStatus_RcvBadTidErr_RMASK 0x1
518 #define QIB_7220_ErrStatus_RcvHdrFullErr_LSB 0xD
519 #define QIB_7220_ErrStatus_RcvHdrFullErr_RMASK 0x1
520 #define QIB_7220_ErrStatus_RcvEgrFullErr_LSB 0xC
521 #define QIB_7220_ErrStatus_RcvEgrFullErr_RMASK 0x1
522 #define QIB_7220_ErrStatus_RcvBadVersionErr_LSB 0xB
523 #define QIB_7220_ErrStatus_RcvBadVersionErr_RMASK 0x1
524 #define QIB_7220_ErrStatus_RcvIBFlowErr_LSB 0xA
525 #define QIB_7220_ErrStatus_RcvIBFlowErr_RMASK 0x1
526 #define QIB_7220_ErrStatus_RcvEBPErr_LSB 0x9
527 #define QIB_7220_ErrStatus_RcvEBPErr_RMASK 0x1
528 #define QIB_7220_ErrStatus_RcvUnsupportedVLErr_LSB 0x8
529 #define QIB_7220_ErrStatus_RcvUnsupportedVLErr_RMASK 0x1
530 #define QIB_7220_ErrStatus_RcvUnexpectedCharErr_LSB 0x7
531 #define QIB_7220_ErrStatus_RcvUnexpectedCharErr_RMASK 0x1
532 #define QIB_7220_ErrStatus_RcvShortPktLenErr_LSB 0x6
533 #define QIB_7220_ErrStatus_RcvShortPktLenErr_RMASK 0x1
534 #define QIB_7220_ErrStatus_RcvLongPktLenErr_LSB 0x5
535 #define QIB_7220_ErrStatus_RcvLongPktLenErr_RMASK 0x1
536 #define QIB_7220_ErrStatus_RcvMaxPktLenErr_LSB 0x4
537 #define QIB_7220_ErrStatus_RcvMaxPktLenErr_RMASK 0x1
538 #define QIB_7220_ErrStatus_RcvMinPktLenErr_LSB 0x3
539 #define QIB_7220_ErrStatus_RcvMinPktLenErr_RMASK 0x1
540 #define QIB_7220_ErrStatus_RcvICRCErr_LSB 0x2
541 #define QIB_7220_ErrStatus_RcvICRCErr_RMASK 0x1
542 #define QIB_7220_ErrStatus_RcvVCRCErr_LSB 0x1
543 #define QIB_7220_ErrStatus_RcvVCRCErr_RMASK 0x1
544 #define QIB_7220_ErrStatus_RcvFormatErr_LSB 0x0
545 #define QIB_7220_ErrStatus_RcvFormatErr_RMASK 0x1
546
547 #define QIB_7220_ErrClear_OFFS 0x90
548 #define QIB_7220_ErrClear_Reserved_LSB 0x36
549 #define QIB_7220_ErrClear_Reserved_RMASK 0x3FF
550 #define QIB_7220_ErrClear_InvalidEEPCmdErrClear_LSB 0x35
551 #define QIB_7220_ErrClear_InvalidEEPCmdErrClear_RMASK 0x1
552 #define QIB_7220_ErrClear_SDmaDescAddrMisalignErrClear_LSB 0x34
553 #define QIB_7220_ErrClear_SDmaDescAddrMisalignErrClear_RMASK 0x1
554 #define QIB_7220_ErrClear_HardwareErrClear_LSB 0x33
555 #define QIB_7220_ErrClear_HardwareErrClear_RMASK 0x1
556 #define QIB_7220_ErrClear_ResetNegatedClear_LSB 0x32
557 #define QIB_7220_ErrClear_ResetNegatedClear_RMASK 0x1
558 #define QIB_7220_ErrClear_InvalidAddrErrClear_LSB 0x31
559 #define QIB_7220_ErrClear_InvalidAddrErrClear_RMASK 0x1
560 #define QIB_7220_ErrClear_IBStatusChangedClear_LSB 0x30
561 #define QIB_7220_ErrClear_IBStatusChangedClear_RMASK 0x1
562 #define QIB_7220_ErrClear_SDmaUnexpDataErrClear_LSB 0x2F
563 #define QIB_7220_ErrClear_SDmaUnexpDataErrClear_RMASK 0x1
564 #define QIB_7220_ErrClear_SDmaMissingDwErrClear_LSB 0x2E
565 #define QIB_7220_ErrClear_SDmaMissingDwErrClear_RMASK 0x1
566 #define QIB_7220_ErrClear_SDmaDwEnErrClear_LSB 0x2D
567 #define QIB_7220_ErrClear_SDmaDwEnErrClear_RMASK 0x1
568 #define QIB_7220_ErrClear_SDmaRpyTagErrClear_LSB 0x2C
569 #define QIB_7220_ErrClear_SDmaRpyTagErrClear_RMASK 0x1
570 #define QIB_7220_ErrClear_SDma1stDescErrClear_LSB 0x2B
571 #define QIB_7220_ErrClear_SDma1stDescErrClear_RMASK 0x1
572 #define QIB_7220_ErrClear_SDmaBaseErrClear_LSB 0x2A
573 #define QIB_7220_ErrClear_SDmaBaseErrClear_RMASK 0x1
574 #define QIB_7220_ErrClear_SDmaTailOutOfBoundErrClear_LSB 0x29
575 #define QIB_7220_ErrClear_SDmaTailOutOfBoundErrClear_RMASK 0x1
576 #define QIB_7220_ErrClear_SDmaOutOfBoundErrClear_LSB 0x28
577 #define QIB_7220_ErrClear_SDmaOutOfBoundErrClear_RMASK 0x1
578 #define QIB_7220_ErrClear_SDmaGenMismatchErrClear_LSB 0x27
579 #define QIB_7220_ErrClear_SDmaGenMismatchErrClear_RMASK 0x1
580 #define QIB_7220_ErrClear_SendBufMisuseErrClear_LSB 0x26
581 #define QIB_7220_ErrClear_SendBufMisuseErrClear_RMASK 0x1
582 #define QIB_7220_ErrClear_SendUnsupportedVLErrClear_LSB 0x25
583 #define QIB_7220_ErrClear_SendUnsupportedVLErrClear_RMASK 0x1
584 #define QIB_7220_ErrClear_SendUnexpectedPktNumErrClear_LSB 0x24
585 #define QIB_7220_ErrClear_SendUnexpectedPktNumErrClear_RMASK 0x1
586 #define QIB_7220_ErrClear_SendPioArmLaunchErrClear_LSB 0x23
587 #define QIB_7220_ErrClear_SendPioArmLaunchErrClear_RMASK 0x1
588 #define QIB_7220_ErrClear_SendDroppedDataPktErrClear_LSB 0x22
589 #define QIB_7220_ErrClear_SendDroppedDataPktErrClear_RMASK 0x1
590 #define QIB_7220_ErrClear_SendDroppedSmpPktErrClear_LSB 0x21
591 #define QIB_7220_ErrClear_SendDroppedSmpPktErrClear_RMASK 0x1
592 #define QIB_7220_ErrClear_SendPktLenErrClear_LSB 0x20
593 #define QIB_7220_ErrClear_SendPktLenErrClear_RMASK 0x1
594 #define QIB_7220_ErrClear_SendUnderRunErrClear_LSB 0x1F
595 #define QIB_7220_ErrClear_SendUnderRunErrClear_RMASK 0x1
596 #define QIB_7220_ErrClear_SendMaxPktLenErrClear_LSB 0x1E
597 #define QIB_7220_ErrClear_SendMaxPktLenErrClear_RMASK 0x1
598 #define QIB_7220_ErrClear_SendMinPktLenErrClear_LSB 0x1D
599 #define QIB_7220_ErrClear_SendMinPktLenErrClear_RMASK 0x1
600 #define QIB_7220_ErrClear_SDmaDisabledErrClear_LSB 0x1C
601 #define QIB_7220_ErrClear_SDmaDisabledErrClear_RMASK 0x1
602 #define QIB_7220_ErrClear_SendSpecialTriggerErrClear_LSB 0x1B
603 #define QIB_7220_ErrClear_SendSpecialTriggerErrClear_RMASK 0x1
604 #define QIB_7220_ErrClear_Reserved1_LSB 0x12
605 #define QIB_7220_ErrClear_Reserved1_RMASK 0x1FF
606 #define QIB_7220_ErrClear_RcvIBLostLinkErrClear_LSB 0x11
607 #define QIB_7220_ErrClear_RcvIBLostLinkErrClear_RMASK 0x1
608 #define QIB_7220_ErrClear_RcvHdrErrClear_LSB 0x10
609 #define QIB_7220_ErrClear_RcvHdrErrClear_RMASK 0x1
610 #define QIB_7220_ErrClear_RcvHdrLenErrClear_LSB 0xF
611 #define QIB_7220_ErrClear_RcvHdrLenErrClear_RMASK 0x1
612 #define QIB_7220_ErrClear_RcvBadTidErrClear_LSB 0xE
613 #define QIB_7220_ErrClear_RcvBadTidErrClear_RMASK 0x1
614 #define QIB_7220_ErrClear_RcvHdrFullErrClear_LSB 0xD
615 #define QIB_7220_ErrClear_RcvHdrFullErrClear_RMASK 0x1
616 #define QIB_7220_ErrClear_RcvEgrFullErrClear_LSB 0xC
617 #define QIB_7220_ErrClear_RcvEgrFullErrClear_RMASK 0x1
618 #define QIB_7220_ErrClear_RcvBadVersionErrClear_LSB 0xB
619 #define QIB_7220_ErrClear_RcvBadVersionErrClear_RMASK 0x1
620 #define QIB_7220_ErrClear_RcvIBFlowErrClear_LSB 0xA
621 #define QIB_7220_ErrClear_RcvIBFlowErrClear_RMASK 0x1
622 #define QIB_7220_ErrClear_RcvEBPErrClear_LSB 0x9
623 #define QIB_7220_ErrClear_RcvEBPErrClear_RMASK 0x1
624 #define QIB_7220_ErrClear_RcvUnsupportedVLErrClear_LSB 0x8
625 #define QIB_7220_ErrClear_RcvUnsupportedVLErrClear_RMASK 0x1
626 #define QIB_7220_ErrClear_RcvUnexpectedCharErrClear_LSB 0x7
627 #define QIB_7220_ErrClear_RcvUnexpectedCharErrClear_RMASK 0x1
628 #define QIB_7220_ErrClear_RcvShortPktLenErrClear_LSB 0x6
629 #define QIB_7220_ErrClear_RcvShortPktLenErrClear_RMASK 0x1
630 #define QIB_7220_ErrClear_RcvLongPktLenErrClear_LSB 0x5
631 #define QIB_7220_ErrClear_RcvLongPktLenErrClear_RMASK 0x1
632 #define QIB_7220_ErrClear_RcvMaxPktLenErrClear_LSB 0x4
633 #define QIB_7220_ErrClear_RcvMaxPktLenErrClear_RMASK 0x1
634 #define QIB_7220_ErrClear_RcvMinPktLenErrClear_LSB 0x3
635 #define QIB_7220_ErrClear_RcvMinPktLenErrClear_RMASK 0x1
636 #define QIB_7220_ErrClear_RcvICRCErrClear_LSB 0x2
637 #define QIB_7220_ErrClear_RcvICRCErrClear_RMASK 0x1
638 #define QIB_7220_ErrClear_RcvVCRCErrClear_LSB 0x1
639 #define QIB_7220_ErrClear_RcvVCRCErrClear_RMASK 0x1
640 #define QIB_7220_ErrClear_RcvFormatErrClear_LSB 0x0
641 #define QIB_7220_ErrClear_RcvFormatErrClear_RMASK 0x1
642
643 #define QIB_7220_HwErrMask_OFFS 0x98
644 #define QIB_7220_HwErrMask_IBCBusFromSPCParityErrMask_LSB 0x3F
645 #define QIB_7220_HwErrMask_IBCBusFromSPCParityErrMask_RMASK 0x1
646 #define QIB_7220_HwErrMask_IBCBusToSPCParityErrMask_LSB 0x3E
647 #define QIB_7220_HwErrMask_IBCBusToSPCParityErrMask_RMASK 0x1
648 #define QIB_7220_HwErrMask_Clk_uC_PLLNotLockedMask_LSB 0x3D
649 #define QIB_7220_HwErrMask_Clk_uC_PLLNotLockedMask_RMASK 0x1
650 #define QIB_7220_HwErrMask_IBSerdesPClkNotDetectMask_LSB 0x3C
651 #define QIB_7220_HwErrMask_IBSerdesPClkNotDetectMask_RMASK 0x1
652 #define QIB_7220_HwErrMask_PCIESerdesQ3PClkNotDetectMask_LSB 0x3B
653 #define QIB_7220_HwErrMask_PCIESerdesQ3PClkNotDetectMask_RMASK 0x1
654 #define QIB_7220_HwErrMask_PCIESerdesQ2PClkNotDetectMask_LSB 0x3A
655 #define QIB_7220_HwErrMask_PCIESerdesQ2PClkNotDetectMask_RMASK 0x1
656 #define QIB_7220_HwErrMask_PCIESerdesQ1PClkNotDetectMask_LSB 0x39
657 #define QIB_7220_HwErrMask_PCIESerdesQ1PClkNotDetectMask_RMASK 0x1
658 #define QIB_7220_HwErrMask_PCIESerdesQ0PClkNotDetectMask_LSB 0x38
659 #define QIB_7220_HwErrMask_PCIESerdesQ0PClkNotDetectMask_RMASK 0x1
660 #define QIB_7220_HwErrMask_Reserved_LSB 0x37
661 #define QIB_7220_HwErrMask_Reserved_RMASK 0x1
662 #define QIB_7220_HwErrMask_PowerOnBISTFailedMask_LSB 0x36
663 #define QIB_7220_HwErrMask_PowerOnBISTFailedMask_RMASK 0x1
664 #define QIB_7220_HwErrMask_Reserved1_LSB 0x33
665 #define QIB_7220_HwErrMask_Reserved1_RMASK 0x7
666 #define QIB_7220_HwErrMask_RXEMemParityErrMask_LSB 0x2C
667 #define QIB_7220_HwErrMask_RXEMemParityErrMask_RMASK 0x7F
668 #define QIB_7220_HwErrMask_TXEMemParityErrMask_LSB 0x28
669 #define QIB_7220_HwErrMask_TXEMemParityErrMask_RMASK 0xF
670 #define QIB_7220_HwErrMask_DDSRXEQMemoryParityErrMask_LSB 0x27
671 #define QIB_7220_HwErrMask_DDSRXEQMemoryParityErrMask_RMASK 0x1
672 #define QIB_7220_HwErrMask_IB_uC_MemoryParityErrMask_LSB 0x26
673 #define QIB_7220_HwErrMask_IB_uC_MemoryParityErrMask_RMASK 0x1
674 #define QIB_7220_HwErrMask_PCIEOct1_uC_MemoryParityErrMask_LSB 0x25
675 #define QIB_7220_HwErrMask_PCIEOct1_uC_MemoryParityErrMask_RMASK 0x1
676 #define QIB_7220_HwErrMask_PCIEOct0_uC_MemoryParityErrMask_LSB 0x24
677 #define QIB_7220_HwErrMask_PCIEOct0_uC_MemoryParityErrMask_RMASK 0x1
678 #define QIB_7220_HwErrMask_Reserved2_LSB 0x22
679 #define QIB_7220_HwErrMask_Reserved2_RMASK 0x3
680 #define QIB_7220_HwErrMask_PCIeBusParityErrMask_LSB 0x1F
681 #define QIB_7220_HwErrMask_PCIeBusParityErrMask_RMASK 0x7
682 #define QIB_7220_HwErrMask_PcieCplTimeoutMask_LSB 0x1E
683 #define QIB_7220_HwErrMask_PcieCplTimeoutMask_RMASK 0x1
684 #define QIB_7220_HwErrMask_PoisonedTLPMask_LSB 0x1D
685 #define QIB_7220_HwErrMask_PoisonedTLPMask_RMASK 0x1
686 #define QIB_7220_HwErrMask_SDmaMemReadErrMask_LSB 0x1C
687 #define QIB_7220_HwErrMask_SDmaMemReadErrMask_RMASK 0x1
688 #define QIB_7220_HwErrMask_Reserved3_LSB 0x8
689 #define QIB_7220_HwErrMask_Reserved3_RMASK 0xFFFFF
690 #define QIB_7220_HwErrMask_PCIeMemParityErrMask_LSB 0x0
691 #define QIB_7220_HwErrMask_PCIeMemParityErrMask_RMASK 0xFF
692
693 #define QIB_7220_HwErrStatus_OFFS 0xA0
694 #define QIB_7220_HwErrStatus_IBCBusFromSPCParityErr_LSB 0x3F
695 #define QIB_7220_HwErrStatus_IBCBusFromSPCParityErr_RMASK 0x1
696 #define QIB_7220_HwErrStatus_IBCBusToSPCParityErr_LSB 0x3E
697 #define QIB_7220_HwErrStatus_IBCBusToSPCParityErr_RMASK 0x1
698 #define QIB_7220_HwErrStatus_Clk_uC_PLLNotLocked_LSB 0x3D
699 #define QIB_7220_HwErrStatus_Clk_uC_PLLNotLocked_RMASK 0x1
700 #define QIB_7220_HwErrStatus_IBSerdesPClkNotDetect_LSB 0x3C
701 #define QIB_7220_HwErrStatus_IBSerdesPClkNotDetect_RMASK 0x1
702 #define QIB_7220_HwErrStatus_PCIESerdesQ3PClkNotDetect_LSB 0x3B
703 #define QIB_7220_HwErrStatus_PCIESerdesQ3PClkNotDetect_RMASK 0x1
704 #define QIB_7220_HwErrStatus_PCIESerdesQ2PClkNotDetect_LSB 0x3A
705 #define QIB_7220_HwErrStatus_PCIESerdesQ2PClkNotDetect_RMASK 0x1
706 #define QIB_7220_HwErrStatus_PCIESerdesQ1PClkNotDetect_LSB 0x39
707 #define QIB_7220_HwErrStatus_PCIESerdesQ1PClkNotDetect_RMASK 0x1
708 #define QIB_7220_HwErrStatus_PCIESerdesQ0PClkNotDetect_LSB 0x38
709 #define QIB_7220_HwErrStatus_PCIESerdesQ0PClkNotDetect_RMASK 0x1
710 #define QIB_7220_HwErrStatus_Reserved_LSB 0x37
711 #define QIB_7220_HwErrStatus_Reserved_RMASK 0x1
712 #define QIB_7220_HwErrStatus_PowerOnBISTFailed_LSB 0x36
713 #define QIB_7220_HwErrStatus_PowerOnBISTFailed_RMASK 0x1
714 #define QIB_7220_HwErrStatus_Reserved1_LSB 0x33
715 #define QIB_7220_HwErrStatus_Reserved1_RMASK 0x7
716 #define QIB_7220_HwErrStatus_RXEMemParity_LSB 0x2C
717 #define QIB_7220_HwErrStatus_RXEMemParity_RMASK 0x7F
718 #define QIB_7220_HwErrStatus_TXEMemParity_LSB 0x28
719 #define QIB_7220_HwErrStatus_TXEMemParity_RMASK 0xF
720 #define QIB_7220_HwErrStatus_DDSRXEQMemoryParityErr_LSB 0x27
721 #define QIB_7220_HwErrStatus_DDSRXEQMemoryParityErr_RMASK 0x1
722 #define QIB_7220_HwErrStatus_IB_uC_MemoryParityErr_LSB 0x26
723 #define QIB_7220_HwErrStatus_IB_uC_MemoryParityErr_RMASK 0x1
724 #define QIB_7220_HwErrStatus_PCIE_uC_Oct1MemoryParityErr_LSB 0x25
725 #define QIB_7220_HwErrStatus_PCIE_uC_Oct1MemoryParityErr_RMASK 0x1
726 #define QIB_7220_HwErrStatus_PCIE_uC_Oct0MemoryParityErr_LSB 0x24
727 #define QIB_7220_HwErrStatus_PCIE_uC_Oct0MemoryParityErr_RMASK 0x1
728 #define QIB_7220_HwErrStatus_Reserved2_LSB 0x22
729 #define QIB_7220_HwErrStatus_Reserved2_RMASK 0x3
730 #define QIB_7220_HwErrStatus_PCIeBusParity_LSB 0x1F
731 #define QIB_7220_HwErrStatus_PCIeBusParity_RMASK 0x7
732 #define QIB_7220_HwErrStatus_PcieCplTimeout_LSB 0x1E
733 #define QIB_7220_HwErrStatus_PcieCplTimeout_RMASK 0x1
734 #define QIB_7220_HwErrStatus_PoisenedTLP_LSB 0x1D
735 #define QIB_7220_HwErrStatus_PoisenedTLP_RMASK 0x1
736 #define QIB_7220_HwErrStatus_SDmaMemReadErr_LSB 0x1C
737 #define QIB_7220_HwErrStatus_SDmaMemReadErr_RMASK 0x1
738 #define QIB_7220_HwErrStatus_Reserved3_LSB 0x8
739 #define QIB_7220_HwErrStatus_Reserved3_RMASK 0xFFFFF
740 #define QIB_7220_HwErrStatus_PCIeMemParity_LSB 0x0
741 #define QIB_7220_HwErrStatus_PCIeMemParity_RMASK 0xFF
742
743 #define QIB_7220_HwErrClear_OFFS 0xA8
744 #define QIB_7220_HwErrClear_IBCBusFromSPCParityErrClear_LSB 0x3F
745 #define QIB_7220_HwErrClear_IBCBusFromSPCParityErrClear_RMASK 0x1
746 #define QIB_7220_HwErrClear_IBCBusToSPCparityErrClear_LSB 0x3E
747 #define QIB_7220_HwErrClear_IBCBusToSPCparityErrClear_RMASK 0x1
748 #define QIB_7220_HwErrClear_Clk_uC_PLLNotLockedClear_LSB 0x3D
749 #define QIB_7220_HwErrClear_Clk_uC_PLLNotLockedClear_RMASK 0x1
750 #define QIB_7220_HwErrClear_IBSerdesPClkNotDetectClear_LSB 0x3C
751 #define QIB_7220_HwErrClear_IBSerdesPClkNotDetectClear_RMASK 0x1
752 #define QIB_7220_HwErrClear_PCIESerdesQ3PClkNotDetectClear_LSB 0x3B
753 #define QIB_7220_HwErrClear_PCIESerdesQ3PClkNotDetectClear_RMASK 0x1
754 #define QIB_7220_HwErrClear_PCIESerdesQ2PClkNotDetectClear_LSB 0x3A
755 #define QIB_7220_HwErrClear_PCIESerdesQ2PClkNotDetectClear_RMASK 0x1
756 #define QIB_7220_HwErrClear_PCIESerdesQ1PClkNotDetectClear_LSB 0x39
757 #define QIB_7220_HwErrClear_PCIESerdesQ1PClkNotDetectClear_RMASK 0x1
758 #define QIB_7220_HwErrClear_PCIESerdesQ0PClkNotDetectClear_LSB 0x38
759 #define QIB_7220_HwErrClear_PCIESerdesQ0PClkNotDetectClear_RMASK 0x1
760 #define QIB_7220_HwErrClear_Reserved_LSB 0x37
761 #define QIB_7220_HwErrClear_Reserved_RMASK 0x1
762 #define QIB_7220_HwErrClear_PowerOnBISTFailedClear_LSB 0x36
763 #define QIB_7220_HwErrClear_PowerOnBISTFailedClear_RMASK 0x1
764 #define QIB_7220_HwErrClear_Reserved1_LSB 0x33
765 #define QIB_7220_HwErrClear_Reserved1_RMASK 0x7
766 #define QIB_7220_HwErrClear_RXEMemParityClear_LSB 0x2C
767 #define QIB_7220_HwErrClear_RXEMemParityClear_RMASK 0x7F
768 #define QIB_7220_HwErrClear_TXEMemParityClear_LSB 0x28
769 #define QIB_7220_HwErrClear_TXEMemParityClear_RMASK 0xF
770 #define QIB_7220_HwErrClear_DDSRXEQMemoryParityErrClear_LSB 0x27
771 #define QIB_7220_HwErrClear_DDSRXEQMemoryParityErrClear_RMASK 0x1
772 #define QIB_7220_HwErrClear_IB_uC_MemoryParityErrClear_LSB 0x26
773 #define QIB_7220_HwErrClear_IB_uC_MemoryParityErrClear_RMASK 0x1
774 #define QIB_7220_HwErrClear_PCIE_uC_Oct1MemoryParityErrClear_LSB 0x25
775 #define QIB_7220_HwErrClear_PCIE_uC_Oct1MemoryParityErrClear_RMASK 0x1
776 #define QIB_7220_HwErrClear_PCIE_uC_Oct0MemoryParityErrClear_LSB 0x24
777 #define QIB_7220_HwErrClear_PCIE_uC_Oct0MemoryParityErrClear_RMASK 0x1
778 #define QIB_7220_HwErrClear_Reserved2_LSB 0x22
779 #define QIB_7220_HwErrClear_Reserved2_RMASK 0x3
780 #define QIB_7220_HwErrClear_PCIeBusParityClr_LSB 0x1F
781 #define QIB_7220_HwErrClear_PCIeBusParityClr_RMASK 0x7
782 #define QIB_7220_HwErrClear_PcieCplTimeoutClear_LSB 0x1E
783 #define QIB_7220_HwErrClear_PcieCplTimeoutClear_RMASK 0x1
784 #define QIB_7220_HwErrClear_PoisonedTLPClear_LSB 0x1D
785 #define QIB_7220_HwErrClear_PoisonedTLPClear_RMASK 0x1
786 #define QIB_7220_HwErrClear_SDmaMemReadErrClear_LSB 0x1C
787 #define QIB_7220_HwErrClear_SDmaMemReadErrClear_RMASK 0x1
788 #define QIB_7220_HwErrClear_Reserved3_LSB 0x8
789 #define QIB_7220_HwErrClear_Reserved3_RMASK 0xFFFFF
790 #define QIB_7220_HwErrClear_PCIeMemParityClr_LSB 0x0
791 #define QIB_7220_HwErrClear_PCIeMemParityClr_RMASK 0xFF
792
793 #define QIB_7220_HwDiagCtrl_OFFS 0xB0
794 #define QIB_7220_HwDiagCtrl_ForceIBCBusFromSPCParityErr_LSB 0x3F
795 #define QIB_7220_HwDiagCtrl_ForceIBCBusFromSPCParityErr_RMASK 0x1
796 #define QIB_7220_HwDiagCtrl_ForceIBCBusToSPCParityErr_LSB 0x3E
797 #define QIB_7220_HwDiagCtrl_ForceIBCBusToSPCParityErr_RMASK 0x1
798 #define QIB_7220_HwDiagCtrl_CounterWrEnable_LSB 0x3D
799 #define QIB_7220_HwDiagCtrl_CounterWrEnable_RMASK 0x1
800 #define QIB_7220_HwDiagCtrl_CounterDisable_LSB 0x3C
801 #define QIB_7220_HwDiagCtrl_CounterDisable_RMASK 0x1
802 #define QIB_7220_HwDiagCtrl_Reserved_LSB 0x33
803 #define QIB_7220_HwDiagCtrl_Reserved_RMASK 0x1FF
804 #define QIB_7220_HwDiagCtrl_ForceRxMemParityErr_LSB 0x2C
805 #define QIB_7220_HwDiagCtrl_ForceRxMemParityErr_RMASK 0x7F
806 #define QIB_7220_HwDiagCtrl_ForceTxMemparityErr_LSB 0x28
807 #define QIB_7220_HwDiagCtrl_ForceTxMemparityErr_RMASK 0xF
808 #define QIB_7220_HwDiagCtrl_ForceDDSRXEQMemoryParityErr_LSB 0x27
809 #define QIB_7220_HwDiagCtrl_ForceDDSRXEQMemoryParityErr_RMASK 0x1
810 #define QIB_7220_HwDiagCtrl_ForceIB_uC_MemoryParityErr_LSB 0x26
811 #define QIB_7220_HwDiagCtrl_ForceIB_uC_MemoryParityErr_RMASK 0x1
812 #define QIB_7220_HwDiagCtrl_ForcePCIE_uC_Oct1MemoryParityErr_LSB 0x25
813 #define QIB_7220_HwDiagCtrl_ForcePCIE_uC_Oct1MemoryParityErr_RMASK 0x1
814 #define QIB_7220_HwDiagCtrl_ForcePCIE_uC_Oct0MemoryParityErr_LSB 0x24
815 #define QIB_7220_HwDiagCtrl_ForcePCIE_uC_Oct0MemoryParityErr_RMASK 0x1
816 #define QIB_7220_HwDiagCtrl_Reserved1_LSB 0x23
817 #define QIB_7220_HwDiagCtrl_Reserved1_RMASK 0x1
818 #define QIB_7220_HwDiagCtrl_forcePCIeBusParity_LSB 0x1F
819 #define QIB_7220_HwDiagCtrl_forcePCIeBusParity_RMASK 0xF
820 #define QIB_7220_HwDiagCtrl_Reserved2_LSB 0x8
821 #define QIB_7220_HwDiagCtrl_Reserved2_RMASK 0x7FFFFF
822 #define QIB_7220_HwDiagCtrl_forcePCIeMemParity_LSB 0x0
823 #define QIB_7220_HwDiagCtrl_forcePCIeMemParity_RMASK 0xFF
824
825 #define QIB_7220_REG_0000B8_OFFS 0xB8
826
827 #define QIB_7220_IBCStatus_OFFS 0xC0
828 #define QIB_7220_IBCStatus_TxCreditOk_LSB 0x1F
829 #define QIB_7220_IBCStatus_TxCreditOk_RMASK 0x1
830 #define QIB_7220_IBCStatus_TxReady_LSB 0x1E
831 #define QIB_7220_IBCStatus_TxReady_RMASK 0x1
832 #define QIB_7220_IBCStatus_Reserved_LSB 0xE
833 #define QIB_7220_IBCStatus_Reserved_RMASK 0xFFFF
834 #define QIB_7220_IBCStatus_IBTxLaneReversed_LSB 0xD
835 #define QIB_7220_IBCStatus_IBTxLaneReversed_RMASK 0x1
836 #define QIB_7220_IBCStatus_IBRxLaneReversed_LSB 0xC
837 #define QIB_7220_IBCStatus_IBRxLaneReversed_RMASK 0x1
838 #define QIB_7220_IBCStatus_IB_SERDES_TRIM_DONE_LSB 0xB
839 #define QIB_7220_IBCStatus_IB_SERDES_TRIM_DONE_RMASK 0x1
840 #define QIB_7220_IBCStatus_DDS_RXEQ_FAIL_LSB 0xA
841 #define QIB_7220_IBCStatus_DDS_RXEQ_FAIL_RMASK 0x1
842 #define QIB_7220_IBCStatus_LinkWidthActive_LSB 0x9
843 #define QIB_7220_IBCStatus_LinkWidthActive_RMASK 0x1
844 #define QIB_7220_IBCStatus_LinkSpeedActive_LSB 0x8
845 #define QIB_7220_IBCStatus_LinkSpeedActive_RMASK 0x1
846 #define QIB_7220_IBCStatus_LinkState_LSB 0x5
847 #define QIB_7220_IBCStatus_LinkState_RMASK 0x7
848 #define QIB_7220_IBCStatus_LinkTrainingState_LSB 0x0
849 #define QIB_7220_IBCStatus_LinkTrainingState_RMASK 0x1F
850
851 #define QIB_7220_IBCCtrl_OFFS 0xC8
852 #define QIB_7220_IBCCtrl_Loopback_LSB 0x3F
853 #define QIB_7220_IBCCtrl_Loopback_RMASK 0x1
854 #define QIB_7220_IBCCtrl_LinkDownDefaultState_LSB 0x3E
855 #define QIB_7220_IBCCtrl_LinkDownDefaultState_RMASK 0x1
856 #define QIB_7220_IBCCtrl_Reserved_LSB 0x2B
857 #define QIB_7220_IBCCtrl_Reserved_RMASK 0x7FFFF
858 #define QIB_7220_IBCCtrl_CreditScale_LSB 0x28
859 #define QIB_7220_IBCCtrl_CreditScale_RMASK 0x7
860 #define QIB_7220_IBCCtrl_OverrunThreshold_LSB 0x24
861 #define QIB_7220_IBCCtrl_OverrunThreshold_RMASK 0xF
862 #define QIB_7220_IBCCtrl_PhyerrThreshold_LSB 0x20
863 #define QIB_7220_IBCCtrl_PhyerrThreshold_RMASK 0xF
864 #define QIB_7220_IBCCtrl_MaxPktLen_LSB 0x15
865 #define QIB_7220_IBCCtrl_MaxPktLen_RMASK 0x7FF
866 #define QIB_7220_IBCCtrl_LinkCmd_LSB 0x13
867 #define QIB_7220_IBCCtrl_LinkCmd_RMASK 0x3
868 #define QIB_7220_IBCCtrl_LinkInitCmd_LSB 0x10
869 #define QIB_7220_IBCCtrl_LinkInitCmd_RMASK 0x7
870 #define QIB_7220_IBCCtrl_FlowCtrlWaterMark_LSB 0x8
871 #define QIB_7220_IBCCtrl_FlowCtrlWaterMark_RMASK 0xFF
872 #define QIB_7220_IBCCtrl_FlowCtrlPeriod_LSB 0x0
873 #define QIB_7220_IBCCtrl_FlowCtrlPeriod_RMASK 0xFF
874
875 #define QIB_7220_EXTStatus_OFFS 0xD0
876 #define QIB_7220_EXTStatus_GPIOIn_LSB 0x30
877 #define QIB_7220_EXTStatus_GPIOIn_RMASK 0xFFFF
878 #define QIB_7220_EXTStatus_Reserved_LSB 0x20
879 #define QIB_7220_EXTStatus_Reserved_RMASK 0xFFFF
880 #define QIB_7220_EXTStatus_Reserved1_LSB 0x10
881 #define QIB_7220_EXTStatus_Reserved1_RMASK 0xFFFF
882 #define QIB_7220_EXTStatus_MemBISTDisabled_LSB 0xF
883 #define QIB_7220_EXTStatus_MemBISTDisabled_RMASK 0x1
884 #define QIB_7220_EXTStatus_MemBISTEndTest_LSB 0xE
885 #define QIB_7220_EXTStatus_MemBISTEndTest_RMASK 0x1
886 #define QIB_7220_EXTStatus_Reserved2_LSB 0x0
887 #define QIB_7220_EXTStatus_Reserved2_RMASK 0x3FFF
888
889 #define QIB_7220_EXTCtrl_OFFS 0xD8
890 #define QIB_7220_EXTCtrl_GPIOOe_LSB 0x30
891 #define QIB_7220_EXTCtrl_GPIOOe_RMASK 0xFFFF
892 #define QIB_7220_EXTCtrl_GPIOInvert_LSB 0x20
893 #define QIB_7220_EXTCtrl_GPIOInvert_RMASK 0xFFFF
894 #define QIB_7220_EXTCtrl_Reserved_LSB 0x4
895 #define QIB_7220_EXTCtrl_Reserved_RMASK 0xFFFFFFF
896 #define QIB_7220_EXTCtrl_LEDPriPortGreenOn_LSB 0x3
897 #define QIB_7220_EXTCtrl_LEDPriPortGreenOn_RMASK 0x1
898 #define QIB_7220_EXTCtrl_LEDPriPortYellowOn_LSB 0x2
899 #define QIB_7220_EXTCtrl_LEDPriPortYellowOn_RMASK 0x1
900 #define QIB_7220_EXTCtrl_LEDGblOkGreenOn_LSB 0x1
901 #define QIB_7220_EXTCtrl_LEDGblOkGreenOn_RMASK 0x1
902 #define QIB_7220_EXTCtrl_LEDGblErrRedOff_LSB 0x0
903 #define QIB_7220_EXTCtrl_LEDGblErrRedOff_RMASK 0x1
904
905 #define QIB_7220_GPIOOut_OFFS 0xE0
906
907 #define QIB_7220_GPIOMask_OFFS 0xE8
908
909 #define QIB_7220_GPIOStatus_OFFS 0xF0
910
911 #define QIB_7220_GPIOClear_OFFS 0xF8
912
913 #define QIB_7220_RcvCtrl_OFFS 0x100
914 #define QIB_7220_RcvCtrl_Reserved_LSB 0x27
915 #define QIB_7220_RcvCtrl_Reserved_RMASK 0x1FFFFFF
916 #define QIB_7220_RcvCtrl_RcvQPMapEnable_LSB 0x26
917 #define QIB_7220_RcvCtrl_RcvQPMapEnable_RMASK 0x1
918 #define QIB_7220_RcvCtrl_PortCfg_LSB 0x24
919 #define QIB_7220_RcvCtrl_PortCfg_RMASK 0x3
920 #define QIB_7220_RcvCtrl_TailUpd_LSB 0x23
921 #define QIB_7220_RcvCtrl_TailUpd_RMASK 0x1
922 #define QIB_7220_RcvCtrl_RcvPartitionKeyDisable_LSB 0x22
923 #define QIB_7220_RcvCtrl_RcvPartitionKeyDisable_RMASK 0x1
924 #define QIB_7220_RcvCtrl_IntrAvail_LSB 0x11
925 #define QIB_7220_RcvCtrl_IntrAvail_RMASK 0x1FFFF
926 #define QIB_7220_RcvCtrl_PortEnable_LSB 0x0
927 #define QIB_7220_RcvCtrl_PortEnable_RMASK 0x1FFFF
928
929 #define QIB_7220_RcvBTHQP_OFFS 0x108
930 #define QIB_7220_RcvBTHQP_Reserved_LSB 0x18
931 #define QIB_7220_RcvBTHQP_Reserved_RMASK 0xFF
932 #define QIB_7220_RcvBTHQP_RcvBTHQP_LSB 0x0
933 #define QIB_7220_RcvBTHQP_RcvBTHQP_RMASK 0xFFFFFF
934
935 #define QIB_7220_RcvHdrSize_OFFS 0x110
936
937 #define QIB_7220_RcvHdrCnt_OFFS 0x118
938
939 #define QIB_7220_RcvHdrEntSize_OFFS 0x120
940
941 #define QIB_7220_RcvTIDBase_OFFS 0x128
942
943 #define QIB_7220_RcvTIDCnt_OFFS 0x130
944
945 #define QIB_7220_RcvEgrBase_OFFS 0x138
946
947 #define QIB_7220_RcvEgrCnt_OFFS 0x140
948
949 #define QIB_7220_RcvBufBase_OFFS 0x148
950
951 #define QIB_7220_RcvBufSize_OFFS 0x150
952
953 #define QIB_7220_RxIntMemBase_OFFS 0x158
954
955 #define QIB_7220_RxIntMemSize_OFFS 0x160
956
957 #define QIB_7220_RcvPartitionKey_OFFS 0x168
958
959 #define QIB_7220_RcvQPMulticastPort_OFFS 0x170
960 #define QIB_7220_RcvQPMulticastPort_Reserved_LSB 0x5
961 #define QIB_7220_RcvQPMulticastPort_Reserved_RMASK 0x7FFFFFFFFFFFFFF
962 #define QIB_7220_RcvQPMulticastPort_RcvQpMcPort_LSB 0x0
963 #define QIB_7220_RcvQPMulticastPort_RcvQpMcPort_RMASK 0x1F
964
965 #define QIB_7220_RcvPktLEDCnt_OFFS 0x178
966 #define QIB_7220_RcvPktLEDCnt_ONperiod_LSB 0x20
967 #define QIB_7220_RcvPktLEDCnt_ONperiod_RMASK 0xFFFFFFFF
968 #define QIB_7220_RcvPktLEDCnt_OFFperiod_LSB 0x0
969 #define QIB_7220_RcvPktLEDCnt_OFFperiod_RMASK 0xFFFFFFFF
970
971 #define QIB_7220_IBCDDRCtrl_OFFS 0x180
972 #define QIB_7220_IBCDDRCtrl_IB_DLID_MASK_LSB 0x30
973 #define QIB_7220_IBCDDRCtrl_IB_DLID_MASK_RMASK 0xFFFF
974 #define QIB_7220_IBCDDRCtrl_IB_DLID_LSB 0x20
975 #define QIB_7220_IBCDDRCtrl_IB_DLID_RMASK 0xFFFF
976 #define QIB_7220_IBCDDRCtrl_Reserved_LSB 0x1B
977 #define QIB_7220_IBCDDRCtrl_Reserved_RMASK 0x1F
978 #define QIB_7220_IBCDDRCtrl_HRTBT_REQ_LSB 0x1A
979 #define QIB_7220_IBCDDRCtrl_HRTBT_REQ_RMASK 0x1
980 #define QIB_7220_IBCDDRCtrl_HRTBT_PORT_LSB 0x12
981 #define QIB_7220_IBCDDRCtrl_HRTBT_PORT_RMASK 0xFF
982 #define QIB_7220_IBCDDRCtrl_HRTBT_AUTO_LSB 0x11
983 #define QIB_7220_IBCDDRCtrl_HRTBT_AUTO_RMASK 0x1
984 #define QIB_7220_IBCDDRCtrl_HRTBT_ENB_LSB 0x10
985 #define QIB_7220_IBCDDRCtrl_HRTBT_ENB_RMASK 0x1
986 #define QIB_7220_IBCDDRCtrl_SD_DDS_LSB 0xC
987 #define QIB_7220_IBCDDRCtrl_SD_DDS_RMASK 0xF
988 #define QIB_7220_IBCDDRCtrl_SD_DDSV_LSB 0xB
989 #define QIB_7220_IBCDDRCtrl_SD_DDSV_RMASK 0x1
990 #define QIB_7220_IBCDDRCtrl_SD_ADD_ENB_LSB 0xA
991 #define QIB_7220_IBCDDRCtrl_SD_ADD_ENB_RMASK 0x1
992 #define QIB_7220_IBCDDRCtrl_SD_RX_EQUAL_ENABLE_LSB 0x9
993 #define QIB_7220_IBCDDRCtrl_SD_RX_EQUAL_ENABLE_RMASK 0x1
994 #define QIB_7220_IBCDDRCtrl_IB_LANE_REV_SUPPORTED_LSB 0x8
995 #define QIB_7220_IBCDDRCtrl_IB_LANE_REV_SUPPORTED_RMASK 0x1
996 #define QIB_7220_IBCDDRCtrl_IB_POLARITY_REV_SUPP_LSB 0x7
997 #define QIB_7220_IBCDDRCtrl_IB_POLARITY_REV_SUPP_RMASK 0x1
998 #define QIB_7220_IBCDDRCtrl_IB_NUM_CHANNELS_LSB 0x5
999 #define QIB_7220_IBCDDRCtrl_IB_NUM_CHANNELS_RMASK 0x3
1000 #define QIB_7220_IBCDDRCtrl_SD_SPEED_QDR_LSB 0x4
1001 #define QIB_7220_IBCDDRCtrl_SD_SPEED_QDR_RMASK 0x1
1002 #define QIB_7220_IBCDDRCtrl_SD_SPEED_DDR_LSB 0x3
1003 #define QIB_7220_IBCDDRCtrl_SD_SPEED_DDR_RMASK 0x1
1004 #define QIB_7220_IBCDDRCtrl_SD_SPEED_SDR_LSB 0x2
1005 #define QIB_7220_IBCDDRCtrl_SD_SPEED_SDR_RMASK 0x1
1006 #define QIB_7220_IBCDDRCtrl_SD_SPEED_LSB 0x1
1007 #define QIB_7220_IBCDDRCtrl_SD_SPEED_RMASK 0x1
1008 #define QIB_7220_IBCDDRCtrl_IB_ENHANCED_MODE_LSB 0x0
1009 #define QIB_7220_IBCDDRCtrl_IB_ENHANCED_MODE_RMASK 0x1
1010
1011 #define QIB_7220_HRTBT_GUID_OFFS 0x188
1012
1013 #define QIB_7220_IBCDDRCtrl2_OFFS 0x1A0
1014 #define QIB_7220_IBCDDRCtrl2_IB_BACK_PORCH_LSB 0x5
1015 #define QIB_7220_IBCDDRCtrl2_IB_BACK_PORCH_RMASK 0x1F
1016 #define QIB_7220_IBCDDRCtrl2_IB_FRONT_PORCH_LSB 0x0
1017 #define QIB_7220_IBCDDRCtrl2_IB_FRONT_PORCH_RMASK 0x1F
1018
1019 #define QIB_7220_IBCDDRStatus_OFFS 0x1A8
1020 #define QIB_7220_IBCDDRStatus_heartbeat_timed_out_LSB 0x24
1021 #define QIB_7220_IBCDDRStatus_heartbeat_timed_out_RMASK 0x1
1022 #define QIB_7220_IBCDDRStatus_heartbeat_crosstalk_LSB 0x20
1023 #define QIB_7220_IBCDDRStatus_heartbeat_crosstalk_RMASK 0xF
1024 #define QIB_7220_IBCDDRStatus_RxEqLocalDevice_LSB 0x1E
1025 #define QIB_7220_IBCDDRStatus_RxEqLocalDevice_RMASK 0x3
1026 #define QIB_7220_IBCDDRStatus_ReqDDSLocalFromRmt_LSB 0x1A
1027 #define QIB_7220_IBCDDRStatus_ReqDDSLocalFromRmt_RMASK 0xF
1028 #define QIB_7220_IBCDDRStatus_LinkRoundTripLatency_LSB 0x0
1029 #define QIB_7220_IBCDDRStatus_LinkRoundTripLatency_RMASK 0x3FFFFFF
1030
1031 #define QIB_7220_JIntReload_OFFS 0x1B0
1032 #define QIB_7220_JIntReload_J_limit_reload_LSB 0x10
1033 #define QIB_7220_JIntReload_J_limit_reload_RMASK 0xFFFF
1034 #define QIB_7220_JIntReload_J_reload_LSB 0x0
1035 #define QIB_7220_JIntReload_J_reload_RMASK 0xFFFF
1036
1037 #define QIB_7220_IBNCModeCtrl_OFFS 0x1B8
1038 #define QIB_7220_IBNCModeCtrl_Reserved_LSB 0x1A
1039 #define QIB_7220_IBNCModeCtrl_Reserved_RMASK 0x3FFFFFFFFF
1040 #define QIB_7220_IBNCModeCtrl_TSMCode_TS2_LSB 0x11
1041 #define QIB_7220_IBNCModeCtrl_TSMCode_TS2_RMASK 0x1FF
1042 #define QIB_7220_IBNCModeCtrl_TSMCode_TS1_LSB 0x8
1043 #define QIB_7220_IBNCModeCtrl_TSMCode_TS1_RMASK 0x1FF
1044 #define QIB_7220_IBNCModeCtrl_Reserved1_LSB 0x3
1045 #define QIB_7220_IBNCModeCtrl_Reserved1_RMASK 0x1F
1046 #define QIB_7220_IBNCModeCtrl_TSMEnable_ignore_TSM_on_rx_LSB 0x2
1047 #define QIB_7220_IBNCModeCtrl_TSMEnable_ignore_TSM_on_rx_RMASK 0x1
1048 #define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS2_LSB 0x1
1049 #define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS2_RMASK 0x1
1050 #define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS1_LSB 0x0
1051 #define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS1_RMASK 0x1
1052
1053 #define QIB_7220_SendCtrl_OFFS 0x1C0
1054 #define QIB_7220_SendCtrl_Disarm_LSB 0x1F
1055 #define QIB_7220_SendCtrl_Disarm_RMASK 0x1
1056 #define QIB_7220_SendCtrl_Reserved_LSB 0x1D
1057 #define QIB_7220_SendCtrl_Reserved_RMASK 0x3
1058 #define QIB_7220_SendCtrl_AvailUpdThld_LSB 0x18
1059 #define QIB_7220_SendCtrl_AvailUpdThld_RMASK 0x1F
1060 #define QIB_7220_SendCtrl_DisarmPIOBuf_LSB 0x10
1061 #define QIB_7220_SendCtrl_DisarmPIOBuf_RMASK 0xFF
1062 #define QIB_7220_SendCtrl_Reserved1_LSB 0xD
1063 #define QIB_7220_SendCtrl_Reserved1_RMASK 0x7
1064 #define QIB_7220_SendCtrl_SDmaHalt_LSB 0xC
1065 #define QIB_7220_SendCtrl_SDmaHalt_RMASK 0x1
1066 #define QIB_7220_SendCtrl_SDmaEnable_LSB 0xB
1067 #define QIB_7220_SendCtrl_SDmaEnable_RMASK 0x1
1068 #define QIB_7220_SendCtrl_SDmaSingleDescriptor_LSB 0xA
1069 #define QIB_7220_SendCtrl_SDmaSingleDescriptor_RMASK 0x1
1070 #define QIB_7220_SendCtrl_SDmaIntEnable_LSB 0x9
1071 #define QIB_7220_SendCtrl_SDmaIntEnable_RMASK 0x1
1072 #define QIB_7220_SendCtrl_Reserved2_LSB 0x5
1073 #define QIB_7220_SendCtrl_Reserved2_RMASK 0xF
1074 #define QIB_7220_SendCtrl_SSpecialTriggerEn_LSB 0x4
1075 #define QIB_7220_SendCtrl_SSpecialTriggerEn_RMASK 0x1
1076 #define QIB_7220_SendCtrl_SPioEnable_LSB 0x3
1077 #define QIB_7220_SendCtrl_SPioEnable_RMASK 0x1
1078 #define QIB_7220_SendCtrl_SendBufAvailUpd_LSB 0x2
1079 #define QIB_7220_SendCtrl_SendBufAvailUpd_RMASK 0x1
1080 #define QIB_7220_SendCtrl_SendIntBufAvail_LSB 0x1
1081 #define QIB_7220_SendCtrl_SendIntBufAvail_RMASK 0x1
1082 #define QIB_7220_SendCtrl_Abort_LSB 0x0
1083 #define QIB_7220_SendCtrl_Abort_RMASK 0x1
1084
1085 #define QIB_7220_SendBufBase_OFFS 0x1C8
1086 #define QIB_7220_SendBufBase_Reserved_LSB 0x35
1087 #define QIB_7220_SendBufBase_Reserved_RMASK 0x7FF
1088 #define QIB_7220_SendBufBase_BaseAddr_LargePIO_LSB 0x20
1089 #define QIB_7220_SendBufBase_BaseAddr_LargePIO_RMASK 0x1FFFFF
1090 #define QIB_7220_SendBufBase_Reserved1_LSB 0x15
1091 #define QIB_7220_SendBufBase_Reserved1_RMASK 0x7FF
1092 #define QIB_7220_SendBufBase_BaseAddr_SmallPIO_LSB 0x0
1093 #define QIB_7220_SendBufBase_BaseAddr_SmallPIO_RMASK 0x1FFFFF
1094
1095 #define QIB_7220_SendBufSize_OFFS 0x1D0
1096 #define QIB_7220_SendBufSize_Reserved_LSB 0x2D
1097 #define QIB_7220_SendBufSize_Reserved_RMASK 0xFFFFF
1098 #define QIB_7220_SendBufSize_Size_LargePIO_LSB 0x20
1099 #define QIB_7220_SendBufSize_Size_LargePIO_RMASK 0x1FFF
1100 #define QIB_7220_SendBufSize_Reserved1_LSB 0xC
1101 #define QIB_7220_SendBufSize_Reserved1_RMASK 0xFFFFF
1102 #define QIB_7220_SendBufSize_Size_SmallPIO_LSB 0x0
1103 #define QIB_7220_SendBufSize_Size_SmallPIO_RMASK 0xFFF
1104
1105 #define QIB_7220_SendBufCnt_OFFS 0x1D8
1106 #define QIB_7220_SendBufCnt_Reserved_LSB 0x24
1107 #define QIB_7220_SendBufCnt_Reserved_RMASK 0xFFFFFFF
1108 #define QIB_7220_SendBufCnt_Num_LargeBuffers_LSB 0x20
1109 #define QIB_7220_SendBufCnt_Num_LargeBuffers_RMASK 0xF
1110 #define QIB_7220_SendBufCnt_Reserved1_LSB 0x9
1111 #define QIB_7220_SendBufCnt_Reserved1_RMASK 0x7FFFFF
1112 #define QIB_7220_SendBufCnt_Num_SmallBuffers_LSB 0x0
1113 #define QIB_7220_SendBufCnt_Num_SmallBuffers_RMASK 0x1FF
1114
1115 #define QIB_7220_SendBufAvailAddr_OFFS 0x1E0
1116 #define QIB_7220_SendBufAvailAddr_SendBufAvailAddr_LSB 0x6
1117 #define QIB_7220_SendBufAvailAddr_SendBufAvailAddr_RMASK 0x3FFFFFFFF
1118 #define QIB_7220_SendBufAvailAddr_Reserved_LSB 0x0
1119 #define QIB_7220_SendBufAvailAddr_Reserved_RMASK 0x3F
1120
1121 #define QIB_7220_TxIntMemBase_OFFS 0x1E8
1122
1123 #define QIB_7220_TxIntMemSize_OFFS 0x1F0
1124
1125 #define QIB_7220_SendDmaBase_OFFS 0x1F8
1126 #define QIB_7220_SendDmaBase_Reserved_LSB 0x30
1127 #define QIB_7220_SendDmaBase_Reserved_RMASK 0xFFFF
1128 #define QIB_7220_SendDmaBase_SendDmaBase_LSB 0x0
1129 #define QIB_7220_SendDmaBase_SendDmaBase_RMASK 0xFFFFFFFFFFFF
1130
1131 #define QIB_7220_SendDmaLenGen_OFFS 0x200
1132 #define QIB_7220_SendDmaLenGen_Reserved_LSB 0x13
1133 #define QIB_7220_SendDmaLenGen_Reserved_RMASK 0x1FFFFFFFFFFF
1134 #define QIB_7220_SendDmaLenGen_Generation_LSB 0x10
1135 #define QIB_7220_SendDmaLenGen_Generation_MSB 0x12
1136 #define QIB_7220_SendDmaLenGen_Generation_RMASK 0x7
1137 #define QIB_7220_SendDmaLenGen_Length_LSB 0x0
1138 #define QIB_7220_SendDmaLenGen_Length_RMASK 0xFFFF
1139
1140 #define QIB_7220_SendDmaTail_OFFS 0x208
1141 #define QIB_7220_SendDmaTail_Reserved_LSB 0x10
1142 #define QIB_7220_SendDmaTail_Reserved_RMASK 0xFFFFFFFFFFFF
1143 #define QIB_7220_SendDmaTail_SendDmaTail_LSB 0x0
1144 #define QIB_7220_SendDmaTail_SendDmaTail_RMASK 0xFFFF
1145
1146 #define QIB_7220_SendDmaHead_OFFS 0x210
1147 #define QIB_7220_SendDmaHead_Reserved_LSB 0x30
1148 #define QIB_7220_SendDmaHead_Reserved_RMASK 0xFFFF
1149 #define QIB_7220_SendDmaHead_InternalSendDmaHead_LSB 0x20
1150 #define QIB_7220_SendDmaHead_InternalSendDmaHead_RMASK 0xFFFF
1151 #define QIB_7220_SendDmaHead_Reserved1_LSB 0x10
1152 #define QIB_7220_SendDmaHead_Reserved1_RMASK 0xFFFF
1153 #define QIB_7220_SendDmaHead_SendDmaHead_LSB 0x0
1154 #define QIB_7220_SendDmaHead_SendDmaHead_RMASK 0xFFFF
1155
1156 #define QIB_7220_SendDmaHeadAddr_OFFS 0x218
1157 #define QIB_7220_SendDmaHeadAddr_Reserved_LSB 0x30
1158 #define QIB_7220_SendDmaHeadAddr_Reserved_RMASK 0xFFFF
1159 #define QIB_7220_SendDmaHeadAddr_SendDmaHeadAddr_LSB 0x0
1160 #define QIB_7220_SendDmaHeadAddr_SendDmaHeadAddr_RMASK 0xFFFFFFFFFFFF
1161
1162 #define QIB_7220_SendDmaBufMask0_OFFS 0x220
1163 #define QIB_7220_SendDmaBufMask0_BufMask_63_0_LSB 0x0
1164 #define QIB_7220_SendDmaBufMask0_BufMask_63_0_RMASK 0x0
1165
1166 #define QIB_7220_SendDmaStatus_OFFS 0x238
1167 #define QIB_7220_SendDmaStatus_ScoreBoardDrainInProg_LSB 0x3F
1168 #define QIB_7220_SendDmaStatus_ScoreBoardDrainInProg_RMASK 0x1
1169 #define QIB_7220_SendDmaStatus_AbortInProg_LSB 0x3E
1170 #define QIB_7220_SendDmaStatus_AbortInProg_RMASK 0x1
1171 #define QIB_7220_SendDmaStatus_InternalSDmaEnable_LSB 0x3D
1172 #define QIB_7220_SendDmaStatus_InternalSDmaEnable_RMASK 0x1
1173 #define QIB_7220_SendDmaStatus_ScbDescIndex_13_0_LSB 0x2F
1174 #define QIB_7220_SendDmaStatus_ScbDescIndex_13_0_RMASK 0x3FFF
1175 #define QIB_7220_SendDmaStatus_RpyLowAddr_6_0_LSB 0x28
1176 #define QIB_7220_SendDmaStatus_RpyLowAddr_6_0_RMASK 0x7F
1177 #define QIB_7220_SendDmaStatus_RpyTag_7_0_LSB 0x20
1178 #define QIB_7220_SendDmaStatus_RpyTag_7_0_RMASK 0xFF
1179 #define QIB_7220_SendDmaStatus_ScbFull_LSB 0x1F
1180 #define QIB_7220_SendDmaStatus_ScbFull_RMASK 0x1
1181 #define QIB_7220_SendDmaStatus_ScbEmpty_LSB 0x1E
1182 #define QIB_7220_SendDmaStatus_ScbEmpty_RMASK 0x1
1183 #define QIB_7220_SendDmaStatus_ScbEntryValid_LSB 0x1D
1184 #define QIB_7220_SendDmaStatus_ScbEntryValid_RMASK 0x1
1185 #define QIB_7220_SendDmaStatus_ScbFetchDescFlag_LSB 0x1C
1186 #define QIB_7220_SendDmaStatus_ScbFetchDescFlag_RMASK 0x1
1187 #define QIB_7220_SendDmaStatus_SplFifoReadyToGo_LSB 0x1B
1188 #define QIB_7220_SendDmaStatus_SplFifoReadyToGo_RMASK 0x1
1189 #define QIB_7220_SendDmaStatus_SplFifoDisarmed_LSB 0x1A
1190 #define QIB_7220_SendDmaStatus_SplFifoDisarmed_RMASK 0x1
1191 #define QIB_7220_SendDmaStatus_SplFifoEmpty_LSB 0x19
1192 #define QIB_7220_SendDmaStatus_SplFifoEmpty_RMASK 0x1
1193 #define QIB_7220_SendDmaStatus_SplFifoFull_LSB 0x18
1194 #define QIB_7220_SendDmaStatus_SplFifoFull_RMASK 0x1
1195 #define QIB_7220_SendDmaStatus_SplFifoBufNum_LSB 0x10
1196 #define QIB_7220_SendDmaStatus_SplFifoBufNum_RMASK 0xFF
1197 #define QIB_7220_SendDmaStatus_SplFifoDescIndex_LSB 0x0
1198 #define QIB_7220_SendDmaStatus_SplFifoDescIndex_RMASK 0xFFFF
1199
1200 #define QIB_7220_SendBufErr0_OFFS 0x240
1201 #define QIB_7220_SendBufErr0_SendBufErr_63_0_LSB 0x0
1202 #define QIB_7220_SendBufErr0_SendBufErr_63_0_RMASK 0x0
1203
1204 #define QIB_7220_RcvHdrAddr0_OFFS 0x270
1205 #define QIB_7220_RcvHdrAddr0_RcvHdrAddr0_LSB 0x2
1206 #define QIB_7220_RcvHdrAddr0_RcvHdrAddr0_RMASK 0x3FFFFFFFFF
1207 #define QIB_7220_RcvHdrAddr0_Reserved_LSB 0x0
1208 #define QIB_7220_RcvHdrAddr0_Reserved_RMASK 0x3
1209
1210 #define QIB_7220_RcvHdrTailAddr0_OFFS 0x300
1211 #define QIB_7220_RcvHdrTailAddr0_RcvHdrTailAddr0_LSB 0x2
1212 #define QIB_7220_RcvHdrTailAddr0_RcvHdrTailAddr0_RMASK 0x3FFFFFFFFF
1213 #define QIB_7220_RcvHdrTailAddr0_Reserved_LSB 0x0
1214 #define QIB_7220_RcvHdrTailAddr0_Reserved_RMASK 0x3
1215
1216 #define QIB_7220_ibsd_epb_access_ctrl_OFFS 0x3C0
1217 #define QIB_7220_ibsd_epb_access_ctrl_sw_ib_epb_req_granted_LSB 0x8
1218 #define QIB_7220_ibsd_epb_access_ctrl_sw_ib_epb_req_granted_RMASK 0x1
1219 #define QIB_7220_ibsd_epb_access_ctrl_Reserved_LSB 0x1
1220 #define QIB_7220_ibsd_epb_access_ctrl_Reserved_RMASK 0x7F
1221 #define QIB_7220_ibsd_epb_access_ctrl_sw_ib_epb_req_LSB 0x0
1222 #define QIB_7220_ibsd_epb_access_ctrl_sw_ib_epb_req_RMASK 0x1
1223
1224 #define QIB_7220_ibsd_epb_transaction_reg_OFFS 0x3C8
1225 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_rdy_LSB 0x1F
1226 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_rdy_RMASK 0x1
1227 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_req_error_LSB 0x1E
1228 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_req_error_RMASK 0x1
1229 #define QIB_7220_ibsd_epb_transaction_reg_Reserved_LSB 0x1D
1230 #define QIB_7220_ibsd_epb_transaction_reg_Reserved_RMASK 0x1
1231 #define QIB_7220_ibsd_epb_transaction_reg_mem_data_parity_LSB 0x1C
1232 #define QIB_7220_ibsd_epb_transaction_reg_mem_data_parity_RMASK 0x1
1233 #define QIB_7220_ibsd_epb_transaction_reg_Reserved1_LSB 0x1B
1234 #define QIB_7220_ibsd_epb_transaction_reg_Reserved1_RMASK 0x1
1235 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_cs_LSB 0x19
1236 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_cs_RMASK 0x3
1237 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_read_write_LSB 0x18
1238 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_read_write_RMASK 0x1
1239 #define QIB_7220_ibsd_epb_transaction_reg_Reserved2_LSB 0x17
1240 #define QIB_7220_ibsd_epb_transaction_reg_Reserved2_RMASK 0x1
1241 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_address_LSB 0x8
1242 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_address_RMASK 0x7FFF
1243 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_data_LSB 0x0
1244 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_data_RMASK 0xFF
1245
1246 #define QIB_7220_XGXSCfg_OFFS 0x3D8
1247 #define QIB_7220_XGXSCfg_sel_link_down_for_fctrl_lane_sync_reset_LSB 0x3F
1248 #define QIB_7220_XGXSCfg_sel_link_down_for_fctrl_lane_sync_reset_RMASK 0x1
1249 #define QIB_7220_XGXSCfg_Reserved_LSB 0x13
1250 #define QIB_7220_XGXSCfg_Reserved_RMASK 0xFFFFFFFFFFF
1251 #define QIB_7220_XGXSCfg_link_sync_mask_LSB 0x9
1252 #define QIB_7220_XGXSCfg_link_sync_mask_RMASK 0x3FF
1253 #define QIB_7220_XGXSCfg_Reserved1_LSB 0x3
1254 #define QIB_7220_XGXSCfg_Reserved1_RMASK 0x3F
1255 #define QIB_7220_XGXSCfg_xcv_reset_LSB 0x2
1256 #define QIB_7220_XGXSCfg_xcv_reset_RMASK 0x1
1257 #define QIB_7220_XGXSCfg_Reserved2_LSB 0x1
1258 #define QIB_7220_XGXSCfg_Reserved2_RMASK 0x1
1259 #define QIB_7220_XGXSCfg_tx_rx_reset_LSB 0x0
1260 #define QIB_7220_XGXSCfg_tx_rx_reset_RMASK 0x1
1261
1262 #define QIB_7220_IBSerDesCtrl_OFFS 0x3E0
1263 #define QIB_7220_IBSerDesCtrl_Reserved_LSB 0x2D
1264 #define QIB_7220_IBSerDesCtrl_Reserved_RMASK 0x7FFFF
1265 #define QIB_7220_IBSerDesCtrl_INT_uC_LSB 0x2C
1266 #define QIB_7220_IBSerDesCtrl_INT_uC_RMASK 0x1
1267 #define QIB_7220_IBSerDesCtrl_CKSEL_uC_LSB 0x2A
1268 #define QIB_7220_IBSerDesCtrl_CKSEL_uC_RMASK 0x3
1269 #define QIB_7220_IBSerDesCtrl_PLLN_LSB 0x28
1270 #define QIB_7220_IBSerDesCtrl_PLLN_RMASK 0x3
1271 #define QIB_7220_IBSerDesCtrl_PLLM_LSB 0x25
1272 #define QIB_7220_IBSerDesCtrl_PLLM_RMASK 0x7
1273 #define QIB_7220_IBSerDesCtrl_TXOBPD_LSB 0x24
1274 #define QIB_7220_IBSerDesCtrl_TXOBPD_RMASK 0x1
1275 #define QIB_7220_IBSerDesCtrl_TWC_LSB 0x23
1276 #define QIB_7220_IBSerDesCtrl_TWC_RMASK 0x1
1277 #define QIB_7220_IBSerDesCtrl_RXIDLE_LSB 0x22
1278 #define QIB_7220_IBSerDesCtrl_RXIDLE_RMASK 0x1
1279 #define QIB_7220_IBSerDesCtrl_RXINV_LSB 0x21
1280 #define QIB_7220_IBSerDesCtrl_RXINV_RMASK 0x1
1281 #define QIB_7220_IBSerDesCtrl_TXINV_LSB 0x20
1282 #define QIB_7220_IBSerDesCtrl_TXINV_RMASK 0x1
1283 #define QIB_7220_IBSerDesCtrl_Reserved1_LSB 0x12
1284 #define QIB_7220_IBSerDesCtrl_Reserved1_RMASK 0x3FFF
1285 #define QIB_7220_IBSerDesCtrl_NumSerDesRegsToWrForRXEQ_LSB 0xD
1286 #define QIB_7220_IBSerDesCtrl_NumSerDesRegsToWrForRXEQ_RMASK 0x1F
1287 #define QIB_7220_IBSerDesCtrl_NumSerDesRegsToWrForDDS_LSB 0x8
1288 #define QIB_7220_IBSerDesCtrl_NumSerDesRegsToWrForDDS_RMASK 0x1F
1289 #define QIB_7220_IBSerDesCtrl_Reserved2_LSB 0x1
1290 #define QIB_7220_IBSerDesCtrl_Reserved2_RMASK 0x7F
1291 #define QIB_7220_IBSerDesCtrl_ResetIB_uC_Core_LSB 0x0
1292 #define QIB_7220_IBSerDesCtrl_ResetIB_uC_Core_RMASK 0x1
1293
1294 #define QIB_7220_pciesd_epb_access_ctrl_OFFS 0x400
1295 #define QIB_7220_pciesd_epb_access_ctrl_sw_pcie_epb_req_granted_LSB 0x8
1296 #define QIB_7220_pciesd_epb_access_ctrl_sw_pcie_epb_req_granted_RMASK 0x1
1297 #define QIB_7220_pciesd_epb_access_ctrl_Reserved_LSB 0x3
1298 #define QIB_7220_pciesd_epb_access_ctrl_Reserved_RMASK 0x1F
1299 #define QIB_7220_pciesd_epb_access_ctrl_sw_pcieepb_star_en_LSB 0x1
1300 #define QIB_7220_pciesd_epb_access_ctrl_sw_pcieepb_star_en_RMASK 0x3
1301 #define QIB_7220_pciesd_epb_access_ctrl_sw_pcie_epb_req_LSB 0x0
1302 #define QIB_7220_pciesd_epb_access_ctrl_sw_pcie_epb_req_RMASK 0x1
1303
1304 #define QIB_7220_pciesd_epb_transaction_reg_OFFS 0x408
1305 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_rdy_LSB 0x1F
1306 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_rdy_RMASK 0x1
1307 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_req_error_LSB 0x1E
1308 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_req_error_RMASK 0x1
1309 #define QIB_7220_pciesd_epb_transaction_reg_Reserved_LSB 0x1D
1310 #define QIB_7220_pciesd_epb_transaction_reg_Reserved_RMASK 0x1
1311 #define QIB_7220_pciesd_epb_transaction_reg_mem_data_parity_LSB 0x1C
1312 #define QIB_7220_pciesd_epb_transaction_reg_mem_data_parity_RMASK 0x1
1313 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_cs_LSB 0x19
1314 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_cs_RMASK 0x7
1315 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_read_write_LSB 0x18
1316 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_read_write_RMASK 0x1
1317 #define QIB_7220_pciesd_epb_transaction_reg_Reserved1_LSB 0x17
1318 #define QIB_7220_pciesd_epb_transaction_reg_Reserved1_RMASK 0x1
1319 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_address_LSB 0x8
1320 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_address_RMASK 0x7FFF
1321 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_data_LSB 0x0
1322 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_data_RMASK 0xFF
1323
1324 #define QIB_7220_SerDes_DDSRXEQ0_OFFS 0x500
1325 #define QIB_7220_SerDes_DDSRXEQ0_reg_addr_LSB 0x4
1326 #define QIB_7220_SerDes_DDSRXEQ0_reg_addr_RMASK 0x3F
1327 #define QIB_7220_SerDes_DDSRXEQ0_element_num_LSB 0x0
1328 #define QIB_7220_SerDes_DDSRXEQ0_element_num_RMASK 0xF
1329
1330 #define QIB_7220_LBIntCnt_OFFS 0x13000
1331
1332 #define QIB_7220_LBFlowStallCnt_OFFS 0x13008
1333
1334 #define QIB_7220_TxSDmaDescCnt_OFFS 0x13010
1335
1336 #define QIB_7220_TxUnsupVLErrCnt_OFFS 0x13018
1337
1338 #define QIB_7220_TxDataPktCnt_OFFS 0x13020
1339
1340 #define QIB_7220_TxFlowPktCnt_OFFS 0x13028
1341
1342 #define QIB_7220_TxDwordCnt_OFFS 0x13030
1343
1344 #define QIB_7220_TxLenErrCnt_OFFS 0x13038
1345
1346 #define QIB_7220_TxMaxMinLenErrCnt_OFFS 0x13040
1347
1348 #define QIB_7220_TxUnderrunCnt_OFFS 0x13048
1349
1350 #define QIB_7220_TxFlowStallCnt_OFFS 0x13050
1351
1352 #define QIB_7220_TxDroppedPktCnt_OFFS 0x13058
1353
1354 #define QIB_7220_RxDroppedPktCnt_OFFS 0x13060
1355
1356 #define QIB_7220_RxDataPktCnt_OFFS 0x13068
1357
1358 #define QIB_7220_RxFlowPktCnt_OFFS 0x13070
1359
1360 #define QIB_7220_RxDwordCnt_OFFS 0x13078
1361
1362 #define QIB_7220_RxLenErrCnt_OFFS 0x13080
1363
1364 #define QIB_7220_RxMaxMinLenErrCnt_OFFS 0x13088
1365
1366 #define QIB_7220_RxICRCErrCnt_OFFS 0x13090
1367
1368 #define QIB_7220_RxVCRCErrCnt_OFFS 0x13098
1369
1370 #define QIB_7220_RxFlowCtrlViolCnt_OFFS 0x130A0
1371
1372 #define QIB_7220_RxVersionErrCnt_OFFS 0x130A8
1373
1374 #define QIB_7220_RxLinkMalformCnt_OFFS 0x130B0
1375
1376 #define QIB_7220_RxEBPCnt_OFFS 0x130B8
1377
1378 #define QIB_7220_RxLPCRCErrCnt_OFFS 0x130C0
1379
1380 #define QIB_7220_RxBufOvflCnt_OFFS 0x130C8
1381
1382 #define QIB_7220_RxTIDFullErrCnt_OFFS 0x130D0
1383
1384 #define QIB_7220_RxTIDValidErrCnt_OFFS 0x130D8
1385
1386 #define QIB_7220_RxPKeyMismatchCnt_OFFS 0x130E0
1387
1388 #define QIB_7220_RxP0HdrEgrOvflCnt_OFFS 0x130E8
1389
1390 #define QIB_7220_IBStatusChangeCnt_OFFS 0x13170
1391
1392 #define QIB_7220_IBLinkErrRecoveryCnt_OFFS 0x13178
1393
1394 #define QIB_7220_IBLinkDownedCnt_OFFS 0x13180
1395
1396 #define QIB_7220_IBSymbolErrCnt_OFFS 0x13188
1397
1398 #define QIB_7220_RxVL15DroppedPktCnt_OFFS 0x13190
1399
1400 #define QIB_7220_RxOtherLocalPhyErrCnt_OFFS 0x13198
1401
1402 #define QIB_7220_PcieRetryBufDiagQwordCnt_OFFS 0x131A0
1403
1404 #define QIB_7220_ExcessBufferOvflCnt_OFFS 0x131A8
1405
1406 #define QIB_7220_LocalLinkIntegrityErrCnt_OFFS 0x131B0
1407
1408 #define QIB_7220_RxVlErrCnt_OFFS 0x131B8
1409
1410 #define QIB_7220_RxDlidFltrCnt_OFFS 0x131C0
1411
1412 #define QIB_7220_CNT_0131C8_OFFS 0x131C8
1413
1414 #define QIB_7220_PSStat_OFFS 0x13200
1415
1416 #define QIB_7220_PSStart_OFFS 0x13208
1417
1418 #define QIB_7220_PSInterval_OFFS 0x13210
1419
1420 #define QIB_7220_PSRcvDataCount_OFFS 0x13218
1421
1422 #define QIB_7220_PSRcvPktsCount_OFFS 0x13220
1423
1424 #define QIB_7220_PSXmitDataCount_OFFS 0x13228
1425
1426 #define QIB_7220_PSXmitPktsCount_OFFS 0x13230
1427
1428 #define QIB_7220_PSXmitWaitCount_OFFS 0x13238
1429
1430 #define QIB_7220_CNT_013240_OFFS 0x13240
1431
1432 #define QIB_7220_RcvEgrArray_OFFS 0x14000
1433
1434 #define QIB_7220_MEM_038000_OFFS 0x38000
1435
1436 #define QIB_7220_RcvTIDArray0_OFFS 0x53000
1437
1438 #define QIB_7220_PIOLaunchFIFO_OFFS 0x64000
1439
1440 #define QIB_7220_MEM_064480_OFFS 0x64480
1441
1442 #define QIB_7220_SendPIOpbcCache_OFFS 0x64800
1443
1444 #define QIB_7220_MEM_064C80_OFFS 0x64C80
1445
1446 #define QIB_7220_PreLaunchFIFO_OFFS 0x65000
1447
1448 #define QIB_7220_MEM_065080_OFFS 0x65080
1449
1450 #define QIB_7220_ScoreBoard_OFFS 0x65400
1451
1452 #define QIB_7220_MEM_065440_OFFS 0x65440
1453
1454 #define QIB_7220_DescriptorFIFO_OFFS 0x65800
1455
1456 #define QIB_7220_MEM_065880_OFFS 0x65880
1457
1458 #define QIB_7220_RcvBuf1_OFFS 0x72000
1459
1460 #define QIB_7220_MEM_074800_OFFS 0x74800
1461
1462 #define QIB_7220_RcvBuf2_OFFS 0x75000
1463
1464 #define QIB_7220_MEM_076400_OFFS 0x76400
1465
1466 #define QIB_7220_RcvFlags_OFFS 0x77000
1467
1468 #define QIB_7220_MEM_078400_OFFS 0x78400
1469
1470 #define QIB_7220_RcvLookupBuf1_OFFS 0x79000
1471
1472 #define QIB_7220_MEM_07A400_OFFS 0x7A400
1473
1474 #define QIB_7220_RcvDMADatBuf_OFFS 0x7B000
1475
1476 #define QIB_7220_RcvDMAHdrBuf_OFFS 0x7B800
1477
1478 #define QIB_7220_MiscRXEIntMem_OFFS 0x7C000
1479
1480 #define QIB_7220_MEM_07D400_OFFS 0x7D400
1481
1482 #define QIB_7220_PCIERcvBuf_OFFS 0x80000
1483
1484 #define QIB_7220_PCIERetryBuf_OFFS 0x84000
1485
1486 #define QIB_7220_PCIERcvBufRdToWrAddr_OFFS 0x88000
1487
1488 #define QIB_7220_PCIECplBuf_OFFS 0x90000
1489
1490 #define QIB_7220_IBSerDesMappTable_OFFS 0x94000
1491
1492 #define QIB_7220_MEM_095000_OFFS 0x95000
1493
1494 #define QIB_7220_SendBuf0_MA_OFFS 0x100000
1495
1496 #define QIB_7220_MEM_1A0000_OFFS 0x1A0000