root/drivers/infiniband/hw/qib/qib_6120_regs.h

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   1 /*
   2  * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 
  33 /* This file is mechanically generated from RTL. Any hand-edits will be lost! */
  34 
  35 #define QIB_6120_Revision_OFFS 0x0
  36 #define QIB_6120_Revision_R_Simulator_LSB 0x3F
  37 #define QIB_6120_Revision_R_Simulator_RMASK 0x1
  38 #define QIB_6120_Revision_Reserved_LSB 0x28
  39 #define QIB_6120_Revision_Reserved_RMASK 0x7FFFFF
  40 #define QIB_6120_Revision_BoardID_LSB 0x20
  41 #define QIB_6120_Revision_BoardID_RMASK 0xFF
  42 #define QIB_6120_Revision_R_SW_LSB 0x18
  43 #define QIB_6120_Revision_R_SW_RMASK 0xFF
  44 #define QIB_6120_Revision_R_Arch_LSB 0x10
  45 #define QIB_6120_Revision_R_Arch_RMASK 0xFF
  46 #define QIB_6120_Revision_R_ChipRevMajor_LSB 0x8
  47 #define QIB_6120_Revision_R_ChipRevMajor_RMASK 0xFF
  48 #define QIB_6120_Revision_R_ChipRevMinor_LSB 0x0
  49 #define QIB_6120_Revision_R_ChipRevMinor_RMASK 0xFF
  50 
  51 #define QIB_6120_Control_OFFS 0x8
  52 #define QIB_6120_Control_TxLatency_LSB 0x4
  53 #define QIB_6120_Control_TxLatency_RMASK 0x1
  54 #define QIB_6120_Control_PCIERetryBufDiagEn_LSB 0x3
  55 #define QIB_6120_Control_PCIERetryBufDiagEn_RMASK 0x1
  56 #define QIB_6120_Control_LinkEn_LSB 0x2
  57 #define QIB_6120_Control_LinkEn_RMASK 0x1
  58 #define QIB_6120_Control_FreezeMode_LSB 0x1
  59 #define QIB_6120_Control_FreezeMode_RMASK 0x1
  60 #define QIB_6120_Control_SyncReset_LSB 0x0
  61 #define QIB_6120_Control_SyncReset_RMASK 0x1
  62 
  63 #define QIB_6120_PageAlign_OFFS 0x10
  64 
  65 #define QIB_6120_PortCnt_OFFS 0x18
  66 
  67 #define QIB_6120_SendRegBase_OFFS 0x30
  68 
  69 #define QIB_6120_UserRegBase_OFFS 0x38
  70 
  71 #define QIB_6120_CntrRegBase_OFFS 0x40
  72 
  73 #define QIB_6120_Scratch_OFFS 0x48
  74 #define QIB_6120_Scratch_TopHalf_LSB 0x20
  75 #define QIB_6120_Scratch_TopHalf_RMASK 0xFFFFFFFF
  76 #define QIB_6120_Scratch_BottomHalf_LSB 0x0
  77 #define QIB_6120_Scratch_BottomHalf_RMASK 0xFFFFFFFF
  78 
  79 #define QIB_6120_IntBlocked_OFFS 0x60
  80 #define QIB_6120_IntBlocked_ErrorIntBlocked_LSB 0x1F
  81 #define QIB_6120_IntBlocked_ErrorIntBlocked_RMASK 0x1
  82 #define QIB_6120_IntBlocked_PioSetIntBlocked_LSB 0x1E
  83 #define QIB_6120_IntBlocked_PioSetIntBlocked_RMASK 0x1
  84 #define QIB_6120_IntBlocked_PioBufAvailIntBlocked_LSB 0x1D
  85 #define QIB_6120_IntBlocked_PioBufAvailIntBlocked_RMASK 0x1
  86 #define QIB_6120_IntBlocked_assertGPIOIntBlocked_LSB 0x1C
  87 #define QIB_6120_IntBlocked_assertGPIOIntBlocked_RMASK 0x1
  88 #define QIB_6120_IntBlocked_Reserved_LSB 0xF
  89 #define QIB_6120_IntBlocked_Reserved_RMASK 0x1FFF
  90 #define QIB_6120_IntBlocked_RcvAvail4IntBlocked_LSB 0x10
  91 #define QIB_6120_IntBlocked_RcvAvail4IntBlocked_RMASK 0x1
  92 #define QIB_6120_IntBlocked_RcvAvail3IntBlocked_LSB 0xF
  93 #define QIB_6120_IntBlocked_RcvAvail3IntBlocked_RMASK 0x1
  94 #define QIB_6120_IntBlocked_RcvAvail2IntBlocked_LSB 0xE
  95 #define QIB_6120_IntBlocked_RcvAvail2IntBlocked_RMASK 0x1
  96 #define QIB_6120_IntBlocked_RcvAvail1IntBlocked_LSB 0xD
  97 #define QIB_6120_IntBlocked_RcvAvail1IntBlocked_RMASK 0x1
  98 #define QIB_6120_IntBlocked_RcvAvail0IntBlocked_LSB 0xC
  99 #define QIB_6120_IntBlocked_RcvAvail0IntBlocked_RMASK 0x1
 100 #define QIB_6120_IntBlocked_Reserved1_LSB 0x5
 101 #define QIB_6120_IntBlocked_Reserved1_RMASK 0x7F
 102 #define QIB_6120_IntBlocked_RcvUrg4IntBlocked_LSB 0x4
 103 #define QIB_6120_IntBlocked_RcvUrg4IntBlocked_RMASK 0x1
 104 #define QIB_6120_IntBlocked_RcvUrg3IntBlocked_LSB 0x3
 105 #define QIB_6120_IntBlocked_RcvUrg3IntBlocked_RMASK 0x1
 106 #define QIB_6120_IntBlocked_RcvUrg2IntBlocked_LSB 0x2
 107 #define QIB_6120_IntBlocked_RcvUrg2IntBlocked_RMASK 0x1
 108 #define QIB_6120_IntBlocked_RcvUrg1IntBlocked_LSB 0x1
 109 #define QIB_6120_IntBlocked_RcvUrg1IntBlocked_RMASK 0x1
 110 #define QIB_6120_IntBlocked_RcvUrg0IntBlocked_LSB 0x0
 111 #define QIB_6120_IntBlocked_RcvUrg0IntBlocked_RMASK 0x1
 112 
 113 #define QIB_6120_IntMask_OFFS 0x68
 114 #define QIB_6120_IntMask_ErrorIntMask_LSB 0x1F
 115 #define QIB_6120_IntMask_ErrorIntMask_RMASK 0x1
 116 #define QIB_6120_IntMask_PioSetIntMask_LSB 0x1E
 117 #define QIB_6120_IntMask_PioSetIntMask_RMASK 0x1
 118 #define QIB_6120_IntMask_PioBufAvailIntMask_LSB 0x1D
 119 #define QIB_6120_IntMask_PioBufAvailIntMask_RMASK 0x1
 120 #define QIB_6120_IntMask_assertGPIOIntMask_LSB 0x1C
 121 #define QIB_6120_IntMask_assertGPIOIntMask_RMASK 0x1
 122 #define QIB_6120_IntMask_Reserved_LSB 0x11
 123 #define QIB_6120_IntMask_Reserved_RMASK 0x7FF
 124 #define QIB_6120_IntMask_RcvAvail4IntMask_LSB 0x10
 125 #define QIB_6120_IntMask_RcvAvail4IntMask_RMASK 0x1
 126 #define QIB_6120_IntMask_RcvAvail3IntMask_LSB 0xF
 127 #define QIB_6120_IntMask_RcvAvail3IntMask_RMASK 0x1
 128 #define QIB_6120_IntMask_RcvAvail2IntMask_LSB 0xE
 129 #define QIB_6120_IntMask_RcvAvail2IntMask_RMASK 0x1
 130 #define QIB_6120_IntMask_RcvAvail1IntMask_LSB 0xD
 131 #define QIB_6120_IntMask_RcvAvail1IntMask_RMASK 0x1
 132 #define QIB_6120_IntMask_RcvAvail0IntMask_LSB 0xC
 133 #define QIB_6120_IntMask_RcvAvail0IntMask_RMASK 0x1
 134 #define QIB_6120_IntMask_Reserved1_LSB 0x5
 135 #define QIB_6120_IntMask_Reserved1_RMASK 0x7F
 136 #define QIB_6120_IntMask_RcvUrg4IntMask_LSB 0x4
 137 #define QIB_6120_IntMask_RcvUrg4IntMask_RMASK 0x1
 138 #define QIB_6120_IntMask_RcvUrg3IntMask_LSB 0x3
 139 #define QIB_6120_IntMask_RcvUrg3IntMask_RMASK 0x1
 140 #define QIB_6120_IntMask_RcvUrg2IntMask_LSB 0x2
 141 #define QIB_6120_IntMask_RcvUrg2IntMask_RMASK 0x1
 142 #define QIB_6120_IntMask_RcvUrg1IntMask_LSB 0x1
 143 #define QIB_6120_IntMask_RcvUrg1IntMask_RMASK 0x1
 144 #define QIB_6120_IntMask_RcvUrg0IntMask_LSB 0x0
 145 #define QIB_6120_IntMask_RcvUrg0IntMask_RMASK 0x1
 146 
 147 #define QIB_6120_IntStatus_OFFS 0x70
 148 #define QIB_6120_IntStatus_Error_LSB 0x1F
 149 #define QIB_6120_IntStatus_Error_RMASK 0x1
 150 #define QIB_6120_IntStatus_PioSent_LSB 0x1E
 151 #define QIB_6120_IntStatus_PioSent_RMASK 0x1
 152 #define QIB_6120_IntStatus_PioBufAvail_LSB 0x1D
 153 #define QIB_6120_IntStatus_PioBufAvail_RMASK 0x1
 154 #define QIB_6120_IntStatus_assertGPIO_LSB 0x1C
 155 #define QIB_6120_IntStatus_assertGPIO_RMASK 0x1
 156 #define QIB_6120_IntStatus_Reserved_LSB 0xF
 157 #define QIB_6120_IntStatus_Reserved_RMASK 0x1FFF
 158 #define QIB_6120_IntStatus_RcvAvail4_LSB 0x10
 159 #define QIB_6120_IntStatus_RcvAvail4_RMASK 0x1
 160 #define QIB_6120_IntStatus_RcvAvail3_LSB 0xF
 161 #define QIB_6120_IntStatus_RcvAvail3_RMASK 0x1
 162 #define QIB_6120_IntStatus_RcvAvail2_LSB 0xE
 163 #define QIB_6120_IntStatus_RcvAvail2_RMASK 0x1
 164 #define QIB_6120_IntStatus_RcvAvail1_LSB 0xD
 165 #define QIB_6120_IntStatus_RcvAvail1_RMASK 0x1
 166 #define QIB_6120_IntStatus_RcvAvail0_LSB 0xC
 167 #define QIB_6120_IntStatus_RcvAvail0_RMASK 0x1
 168 #define QIB_6120_IntStatus_Reserved1_LSB 0x5
 169 #define QIB_6120_IntStatus_Reserved1_RMASK 0x7F
 170 #define QIB_6120_IntStatus_RcvUrg4_LSB 0x4
 171 #define QIB_6120_IntStatus_RcvUrg4_RMASK 0x1
 172 #define QIB_6120_IntStatus_RcvUrg3_LSB 0x3
 173 #define QIB_6120_IntStatus_RcvUrg3_RMASK 0x1
 174 #define QIB_6120_IntStatus_RcvUrg2_LSB 0x2
 175 #define QIB_6120_IntStatus_RcvUrg2_RMASK 0x1
 176 #define QIB_6120_IntStatus_RcvUrg1_LSB 0x1
 177 #define QIB_6120_IntStatus_RcvUrg1_RMASK 0x1
 178 #define QIB_6120_IntStatus_RcvUrg0_LSB 0x0
 179 #define QIB_6120_IntStatus_RcvUrg0_RMASK 0x1
 180 
 181 #define QIB_6120_IntClear_OFFS 0x78
 182 #define QIB_6120_IntClear_ErrorIntClear_LSB 0x1F
 183 #define QIB_6120_IntClear_ErrorIntClear_RMASK 0x1
 184 #define QIB_6120_IntClear_PioSetIntClear_LSB 0x1E
 185 #define QIB_6120_IntClear_PioSetIntClear_RMASK 0x1
 186 #define QIB_6120_IntClear_PioBufAvailIntClear_LSB 0x1D
 187 #define QIB_6120_IntClear_PioBufAvailIntClear_RMASK 0x1
 188 #define QIB_6120_IntClear_assertGPIOIntClear_LSB 0x1C
 189 #define QIB_6120_IntClear_assertGPIOIntClear_RMASK 0x1
 190 #define QIB_6120_IntClear_Reserved_LSB 0xF
 191 #define QIB_6120_IntClear_Reserved_RMASK 0x1FFF
 192 #define QIB_6120_IntClear_RcvAvail4IntClear_LSB 0x10
 193 #define QIB_6120_IntClear_RcvAvail4IntClear_RMASK 0x1
 194 #define QIB_6120_IntClear_RcvAvail3IntClear_LSB 0xF
 195 #define QIB_6120_IntClear_RcvAvail3IntClear_RMASK 0x1
 196 #define QIB_6120_IntClear_RcvAvail2IntClear_LSB 0xE
 197 #define QIB_6120_IntClear_RcvAvail2IntClear_RMASK 0x1
 198 #define QIB_6120_IntClear_RcvAvail1IntClear_LSB 0xD
 199 #define QIB_6120_IntClear_RcvAvail1IntClear_RMASK 0x1
 200 #define QIB_6120_IntClear_RcvAvail0IntClear_LSB 0xC
 201 #define QIB_6120_IntClear_RcvAvail0IntClear_RMASK 0x1
 202 #define QIB_6120_IntClear_Reserved1_LSB 0x5
 203 #define QIB_6120_IntClear_Reserved1_RMASK 0x7F
 204 #define QIB_6120_IntClear_RcvUrg4IntClear_LSB 0x4
 205 #define QIB_6120_IntClear_RcvUrg4IntClear_RMASK 0x1
 206 #define QIB_6120_IntClear_RcvUrg3IntClear_LSB 0x3
 207 #define QIB_6120_IntClear_RcvUrg3IntClear_RMASK 0x1
 208 #define QIB_6120_IntClear_RcvUrg2IntClear_LSB 0x2
 209 #define QIB_6120_IntClear_RcvUrg2IntClear_RMASK 0x1
 210 #define QIB_6120_IntClear_RcvUrg1IntClear_LSB 0x1
 211 #define QIB_6120_IntClear_RcvUrg1IntClear_RMASK 0x1
 212 #define QIB_6120_IntClear_RcvUrg0IntClear_LSB 0x0
 213 #define QIB_6120_IntClear_RcvUrg0IntClear_RMASK 0x1
 214 
 215 #define QIB_6120_ErrMask_OFFS 0x80
 216 #define QIB_6120_ErrMask_Reserved_LSB 0x34
 217 #define QIB_6120_ErrMask_Reserved_RMASK 0xFFF
 218 #define QIB_6120_ErrMask_HardwareErrMask_LSB 0x33
 219 #define QIB_6120_ErrMask_HardwareErrMask_RMASK 0x1
 220 #define QIB_6120_ErrMask_ResetNegatedMask_LSB 0x32
 221 #define QIB_6120_ErrMask_ResetNegatedMask_RMASK 0x1
 222 #define QIB_6120_ErrMask_InvalidAddrErrMask_LSB 0x31
 223 #define QIB_6120_ErrMask_InvalidAddrErrMask_RMASK 0x1
 224 #define QIB_6120_ErrMask_IBStatusChangedMask_LSB 0x30
 225 #define QIB_6120_ErrMask_IBStatusChangedMask_RMASK 0x1
 226 #define QIB_6120_ErrMask_Reserved1_LSB 0x26
 227 #define QIB_6120_ErrMask_Reserved1_RMASK 0x3FF
 228 #define QIB_6120_ErrMask_SendUnsupportedVLErrMask_LSB 0x25
 229 #define QIB_6120_ErrMask_SendUnsupportedVLErrMask_RMASK 0x1
 230 #define QIB_6120_ErrMask_SendUnexpectedPktNumErrMask_LSB 0x24
 231 #define QIB_6120_ErrMask_SendUnexpectedPktNumErrMask_RMASK 0x1
 232 #define QIB_6120_ErrMask_SendPioArmLaunchErrMask_LSB 0x23
 233 #define QIB_6120_ErrMask_SendPioArmLaunchErrMask_RMASK 0x1
 234 #define QIB_6120_ErrMask_SendDroppedDataPktErrMask_LSB 0x22
 235 #define QIB_6120_ErrMask_SendDroppedDataPktErrMask_RMASK 0x1
 236 #define QIB_6120_ErrMask_SendDroppedSmpPktErrMask_LSB 0x21
 237 #define QIB_6120_ErrMask_SendDroppedSmpPktErrMask_RMASK 0x1
 238 #define QIB_6120_ErrMask_SendPktLenErrMask_LSB 0x20
 239 #define QIB_6120_ErrMask_SendPktLenErrMask_RMASK 0x1
 240 #define QIB_6120_ErrMask_SendUnderRunErrMask_LSB 0x1F
 241 #define QIB_6120_ErrMask_SendUnderRunErrMask_RMASK 0x1
 242 #define QIB_6120_ErrMask_SendMaxPktLenErrMask_LSB 0x1E
 243 #define QIB_6120_ErrMask_SendMaxPktLenErrMask_RMASK 0x1
 244 #define QIB_6120_ErrMask_SendMinPktLenErrMask_LSB 0x1D
 245 #define QIB_6120_ErrMask_SendMinPktLenErrMask_RMASK 0x1
 246 #define QIB_6120_ErrMask_Reserved2_LSB 0x12
 247 #define QIB_6120_ErrMask_Reserved2_RMASK 0x7FF
 248 #define QIB_6120_ErrMask_RcvIBLostLinkErrMask_LSB 0x11
 249 #define QIB_6120_ErrMask_RcvIBLostLinkErrMask_RMASK 0x1
 250 #define QIB_6120_ErrMask_RcvHdrErrMask_LSB 0x10
 251 #define QIB_6120_ErrMask_RcvHdrErrMask_RMASK 0x1
 252 #define QIB_6120_ErrMask_RcvHdrLenErrMask_LSB 0xF
 253 #define QIB_6120_ErrMask_RcvHdrLenErrMask_RMASK 0x1
 254 #define QIB_6120_ErrMask_RcvBadTidErrMask_LSB 0xE
 255 #define QIB_6120_ErrMask_RcvBadTidErrMask_RMASK 0x1
 256 #define QIB_6120_ErrMask_RcvHdrFullErrMask_LSB 0xD
 257 #define QIB_6120_ErrMask_RcvHdrFullErrMask_RMASK 0x1
 258 #define QIB_6120_ErrMask_RcvEgrFullErrMask_LSB 0xC
 259 #define QIB_6120_ErrMask_RcvEgrFullErrMask_RMASK 0x1
 260 #define QIB_6120_ErrMask_RcvBadVersionErrMask_LSB 0xB
 261 #define QIB_6120_ErrMask_RcvBadVersionErrMask_RMASK 0x1
 262 #define QIB_6120_ErrMask_RcvIBFlowErrMask_LSB 0xA
 263 #define QIB_6120_ErrMask_RcvIBFlowErrMask_RMASK 0x1
 264 #define QIB_6120_ErrMask_RcvEBPErrMask_LSB 0x9
 265 #define QIB_6120_ErrMask_RcvEBPErrMask_RMASK 0x1
 266 #define QIB_6120_ErrMask_RcvUnsupportedVLErrMask_LSB 0x8
 267 #define QIB_6120_ErrMask_RcvUnsupportedVLErrMask_RMASK 0x1
 268 #define QIB_6120_ErrMask_RcvUnexpectedCharErrMask_LSB 0x7
 269 #define QIB_6120_ErrMask_RcvUnexpectedCharErrMask_RMASK 0x1
 270 #define QIB_6120_ErrMask_RcvShortPktLenErrMask_LSB 0x6
 271 #define QIB_6120_ErrMask_RcvShortPktLenErrMask_RMASK 0x1
 272 #define QIB_6120_ErrMask_RcvLongPktLenErrMask_LSB 0x5
 273 #define QIB_6120_ErrMask_RcvLongPktLenErrMask_RMASK 0x1
 274 #define QIB_6120_ErrMask_RcvMaxPktLenErrMask_LSB 0x4
 275 #define QIB_6120_ErrMask_RcvMaxPktLenErrMask_RMASK 0x1
 276 #define QIB_6120_ErrMask_RcvMinPktLenErrMask_LSB 0x3
 277 #define QIB_6120_ErrMask_RcvMinPktLenErrMask_RMASK 0x1
 278 #define QIB_6120_ErrMask_RcvICRCErrMask_LSB 0x2
 279 #define QIB_6120_ErrMask_RcvICRCErrMask_RMASK 0x1
 280 #define QIB_6120_ErrMask_RcvVCRCErrMask_LSB 0x1
 281 #define QIB_6120_ErrMask_RcvVCRCErrMask_RMASK 0x1
 282 #define QIB_6120_ErrMask_RcvFormatErrMask_LSB 0x0
 283 #define QIB_6120_ErrMask_RcvFormatErrMask_RMASK 0x1
 284 
 285 #define QIB_6120_ErrStatus_OFFS 0x88
 286 #define QIB_6120_ErrStatus_Reserved_LSB 0x34
 287 #define QIB_6120_ErrStatus_Reserved_RMASK 0xFFF
 288 #define QIB_6120_ErrStatus_HardwareErr_LSB 0x33
 289 #define QIB_6120_ErrStatus_HardwareErr_RMASK 0x1
 290 #define QIB_6120_ErrStatus_ResetNegated_LSB 0x32
 291 #define QIB_6120_ErrStatus_ResetNegated_RMASK 0x1
 292 #define QIB_6120_ErrStatus_InvalidAddrErr_LSB 0x31
 293 #define QIB_6120_ErrStatus_InvalidAddrErr_RMASK 0x1
 294 #define QIB_6120_ErrStatus_IBStatusChanged_LSB 0x30
 295 #define QIB_6120_ErrStatus_IBStatusChanged_RMASK 0x1
 296 #define QIB_6120_ErrStatus_Reserved1_LSB 0x26
 297 #define QIB_6120_ErrStatus_Reserved1_RMASK 0x3FF
 298 #define QIB_6120_ErrStatus_SendUnsupportedVLErr_LSB 0x25
 299 #define QIB_6120_ErrStatus_SendUnsupportedVLErr_RMASK 0x1
 300 #define QIB_6120_ErrStatus_SendUnexpectedPktNumErr_LSB 0x24
 301 #define QIB_6120_ErrStatus_SendUnexpectedPktNumErr_RMASK 0x1
 302 #define QIB_6120_ErrStatus_SendPioArmLaunchErr_LSB 0x23
 303 #define QIB_6120_ErrStatus_SendPioArmLaunchErr_RMASK 0x1
 304 #define QIB_6120_ErrStatus_SendDroppedDataPktErr_LSB 0x22
 305 #define QIB_6120_ErrStatus_SendDroppedDataPktErr_RMASK 0x1
 306 #define QIB_6120_ErrStatus_SendDroppedSmpPktErr_LSB 0x21
 307 #define QIB_6120_ErrStatus_SendDroppedSmpPktErr_RMASK 0x1
 308 #define QIB_6120_ErrStatus_SendPktLenErr_LSB 0x20
 309 #define QIB_6120_ErrStatus_SendPktLenErr_RMASK 0x1
 310 #define QIB_6120_ErrStatus_SendUnderRunErr_LSB 0x1F
 311 #define QIB_6120_ErrStatus_SendUnderRunErr_RMASK 0x1
 312 #define QIB_6120_ErrStatus_SendMaxPktLenErr_LSB 0x1E
 313 #define QIB_6120_ErrStatus_SendMaxPktLenErr_RMASK 0x1
 314 #define QIB_6120_ErrStatus_SendMinPktLenErr_LSB 0x1D
 315 #define QIB_6120_ErrStatus_SendMinPktLenErr_RMASK 0x1
 316 #define QIB_6120_ErrStatus_Reserved2_LSB 0x12
 317 #define QIB_6120_ErrStatus_Reserved2_RMASK 0x7FF
 318 #define QIB_6120_ErrStatus_RcvIBLostLinkErr_LSB 0x11
 319 #define QIB_6120_ErrStatus_RcvIBLostLinkErr_RMASK 0x1
 320 #define QIB_6120_ErrStatus_RcvHdrErr_LSB 0x10
 321 #define QIB_6120_ErrStatus_RcvHdrErr_RMASK 0x1
 322 #define QIB_6120_ErrStatus_RcvHdrLenErr_LSB 0xF
 323 #define QIB_6120_ErrStatus_RcvHdrLenErr_RMASK 0x1
 324 #define QIB_6120_ErrStatus_RcvBadTidErr_LSB 0xE
 325 #define QIB_6120_ErrStatus_RcvBadTidErr_RMASK 0x1
 326 #define QIB_6120_ErrStatus_RcvHdrFullErr_LSB 0xD
 327 #define QIB_6120_ErrStatus_RcvHdrFullErr_RMASK 0x1
 328 #define QIB_6120_ErrStatus_RcvEgrFullErr_LSB 0xC
 329 #define QIB_6120_ErrStatus_RcvEgrFullErr_RMASK 0x1
 330 #define QIB_6120_ErrStatus_RcvBadVersionErr_LSB 0xB
 331 #define QIB_6120_ErrStatus_RcvBadVersionErr_RMASK 0x1
 332 #define QIB_6120_ErrStatus_RcvIBFlowErr_LSB 0xA
 333 #define QIB_6120_ErrStatus_RcvIBFlowErr_RMASK 0x1
 334 #define QIB_6120_ErrStatus_RcvEBPErr_LSB 0x9
 335 #define QIB_6120_ErrStatus_RcvEBPErr_RMASK 0x1
 336 #define QIB_6120_ErrStatus_RcvUnsupportedVLErr_LSB 0x8
 337 #define QIB_6120_ErrStatus_RcvUnsupportedVLErr_RMASK 0x1
 338 #define QIB_6120_ErrStatus_RcvUnexpectedCharErr_LSB 0x7
 339 #define QIB_6120_ErrStatus_RcvUnexpectedCharErr_RMASK 0x1
 340 #define QIB_6120_ErrStatus_RcvShortPktLenErr_LSB 0x6
 341 #define QIB_6120_ErrStatus_RcvShortPktLenErr_RMASK 0x1
 342 #define QIB_6120_ErrStatus_RcvLongPktLenErr_LSB 0x5
 343 #define QIB_6120_ErrStatus_RcvLongPktLenErr_RMASK 0x1
 344 #define QIB_6120_ErrStatus_RcvMaxPktLenErr_LSB 0x4
 345 #define QIB_6120_ErrStatus_RcvMaxPktLenErr_RMASK 0x1
 346 #define QIB_6120_ErrStatus_RcvMinPktLenErr_LSB 0x3
 347 #define QIB_6120_ErrStatus_RcvMinPktLenErr_RMASK 0x1
 348 #define QIB_6120_ErrStatus_RcvICRCErr_LSB 0x2
 349 #define QIB_6120_ErrStatus_RcvICRCErr_RMASK 0x1
 350 #define QIB_6120_ErrStatus_RcvVCRCErr_LSB 0x1
 351 #define QIB_6120_ErrStatus_RcvVCRCErr_RMASK 0x1
 352 #define QIB_6120_ErrStatus_RcvFormatErr_LSB 0x0
 353 #define QIB_6120_ErrStatus_RcvFormatErr_RMASK 0x1
 354 
 355 #define QIB_6120_ErrClear_OFFS 0x90
 356 #define QIB_6120_ErrClear_Reserved_LSB 0x34
 357 #define QIB_6120_ErrClear_Reserved_RMASK 0xFFF
 358 #define QIB_6120_ErrClear_HardwareErrClear_LSB 0x33
 359 #define QIB_6120_ErrClear_HardwareErrClear_RMASK 0x1
 360 #define QIB_6120_ErrClear_ResetNegatedClear_LSB 0x32
 361 #define QIB_6120_ErrClear_ResetNegatedClear_RMASK 0x1
 362 #define QIB_6120_ErrClear_InvalidAddrErrClear_LSB 0x31
 363 #define QIB_6120_ErrClear_InvalidAddrErrClear_RMASK 0x1
 364 #define QIB_6120_ErrClear_IBStatusChangedClear_LSB 0x30
 365 #define QIB_6120_ErrClear_IBStatusChangedClear_RMASK 0x1
 366 #define QIB_6120_ErrClear_Reserved1_LSB 0x26
 367 #define QIB_6120_ErrClear_Reserved1_RMASK 0x3FF
 368 #define QIB_6120_ErrClear_SendUnsupportedVLErrClear_LSB 0x25
 369 #define QIB_6120_ErrClear_SendUnsupportedVLErrClear_RMASK 0x1
 370 #define QIB_6120_ErrClear_SendUnexpectedPktNumErrClear_LSB 0x24
 371 #define QIB_6120_ErrClear_SendUnexpectedPktNumErrClear_RMASK 0x1
 372 #define QIB_6120_ErrClear_SendPioArmLaunchErrClear_LSB 0x23
 373 #define QIB_6120_ErrClear_SendPioArmLaunchErrClear_RMASK 0x1
 374 #define QIB_6120_ErrClear_SendDroppedDataPktErrClear_LSB 0x22
 375 #define QIB_6120_ErrClear_SendDroppedDataPktErrClear_RMASK 0x1
 376 #define QIB_6120_ErrClear_SendDroppedSmpPktErrClear_LSB 0x21
 377 #define QIB_6120_ErrClear_SendDroppedSmpPktErrClear_RMASK 0x1
 378 #define QIB_6120_ErrClear_SendPktLenErrClear_LSB 0x20
 379 #define QIB_6120_ErrClear_SendPktLenErrClear_RMASK 0x1
 380 #define QIB_6120_ErrClear_SendUnderRunErrClear_LSB 0x1F
 381 #define QIB_6120_ErrClear_SendUnderRunErrClear_RMASK 0x1
 382 #define QIB_6120_ErrClear_SendMaxPktLenErrClear_LSB 0x1E
 383 #define QIB_6120_ErrClear_SendMaxPktLenErrClear_RMASK 0x1
 384 #define QIB_6120_ErrClear_SendMinPktLenErrClear_LSB 0x1D
 385 #define QIB_6120_ErrClear_SendMinPktLenErrClear_RMASK 0x1
 386 #define QIB_6120_ErrClear_Reserved2_LSB 0x12
 387 #define QIB_6120_ErrClear_Reserved2_RMASK 0x7FF
 388 #define QIB_6120_ErrClear_RcvIBLostLinkErrClear_LSB 0x11
 389 #define QIB_6120_ErrClear_RcvIBLostLinkErrClear_RMASK 0x1
 390 #define QIB_6120_ErrClear_RcvHdrErrClear_LSB 0x10
 391 #define QIB_6120_ErrClear_RcvHdrErrClear_RMASK 0x1
 392 #define QIB_6120_ErrClear_RcvHdrLenErrClear_LSB 0xF
 393 #define QIB_6120_ErrClear_RcvHdrLenErrClear_RMASK 0x1
 394 #define QIB_6120_ErrClear_RcvBadTidErrClear_LSB 0xE
 395 #define QIB_6120_ErrClear_RcvBadTidErrClear_RMASK 0x1
 396 #define QIB_6120_ErrClear_RcvHdrFullErrClear_LSB 0xD
 397 #define QIB_6120_ErrClear_RcvHdrFullErrClear_RMASK 0x1
 398 #define QIB_6120_ErrClear_RcvEgrFullErrClear_LSB 0xC
 399 #define QIB_6120_ErrClear_RcvEgrFullErrClear_RMASK 0x1
 400 #define QIB_6120_ErrClear_RcvBadVersionErrClear_LSB 0xB
 401 #define QIB_6120_ErrClear_RcvBadVersionErrClear_RMASK 0x1
 402 #define QIB_6120_ErrClear_RcvIBFlowErrClear_LSB 0xA
 403 #define QIB_6120_ErrClear_RcvIBFlowErrClear_RMASK 0x1
 404 #define QIB_6120_ErrClear_RcvEBPErrClear_LSB 0x9
 405 #define QIB_6120_ErrClear_RcvEBPErrClear_RMASK 0x1
 406 #define QIB_6120_ErrClear_RcvUnsupportedVLErrClear_LSB 0x8
 407 #define QIB_6120_ErrClear_RcvUnsupportedVLErrClear_RMASK 0x1
 408 #define QIB_6120_ErrClear_RcvUnexpectedCharErrClear_LSB 0x7
 409 #define QIB_6120_ErrClear_RcvUnexpectedCharErrClear_RMASK 0x1
 410 #define QIB_6120_ErrClear_RcvShortPktLenErrClear_LSB 0x6
 411 #define QIB_6120_ErrClear_RcvShortPktLenErrClear_RMASK 0x1
 412 #define QIB_6120_ErrClear_RcvLongPktLenErrClear_LSB 0x5
 413 #define QIB_6120_ErrClear_RcvLongPktLenErrClear_RMASK 0x1
 414 #define QIB_6120_ErrClear_RcvMaxPktLenErrClear_LSB 0x4
 415 #define QIB_6120_ErrClear_RcvMaxPktLenErrClear_RMASK 0x1
 416 #define QIB_6120_ErrClear_RcvMinPktLenErrClear_LSB 0x3
 417 #define QIB_6120_ErrClear_RcvMinPktLenErrClear_RMASK 0x1
 418 #define QIB_6120_ErrClear_RcvICRCErrClear_LSB 0x2
 419 #define QIB_6120_ErrClear_RcvICRCErrClear_RMASK 0x1
 420 #define QIB_6120_ErrClear_RcvVCRCErrClear_LSB 0x1
 421 #define QIB_6120_ErrClear_RcvVCRCErrClear_RMASK 0x1
 422 #define QIB_6120_ErrClear_RcvFormatErrClear_LSB 0x0
 423 #define QIB_6120_ErrClear_RcvFormatErrClear_RMASK 0x1
 424 
 425 #define QIB_6120_HwErrMask_OFFS 0x98
 426 #define QIB_6120_HwErrMask_IBCBusFromSPCParityErrMask_LSB 0x3F
 427 #define QIB_6120_HwErrMask_IBCBusFromSPCParityErrMask_RMASK 0x1
 428 #define QIB_6120_HwErrMask_IBCBusToSPCParityErrMask_LSB 0x3E
 429 #define QIB_6120_HwErrMask_IBCBusToSPCParityErrMask_RMASK 0x1
 430 #define QIB_6120_HwErrMask_Reserved_LSB 0x3D
 431 #define QIB_6120_HwErrMask_Reserved_RMASK 0x1
 432 #define QIB_6120_HwErrMask_IBSerdesPClkNotDetectMask_LSB 0x3C
 433 #define QIB_6120_HwErrMask_IBSerdesPClkNotDetectMask_RMASK 0x1
 434 #define QIB_6120_HwErrMask_PCIESerdesQ0PClkNotDetectMask_LSB 0x3B
 435 #define QIB_6120_HwErrMask_PCIESerdesQ0PClkNotDetectMask_RMASK 0x1
 436 #define QIB_6120_HwErrMask_PCIESerdesQ1PClkNotDetectMask_LSB 0x3A
 437 #define QIB_6120_HwErrMask_PCIESerdesQ1PClkNotDetectMask_RMASK 0x1
 438 #define QIB_6120_HwErrMask_Reserved1_LSB 0x39
 439 #define QIB_6120_HwErrMask_Reserved1_RMASK 0x1
 440 #define QIB_6120_HwErrMask_IBPLLrfSlipMask_LSB 0x38
 441 #define QIB_6120_HwErrMask_IBPLLrfSlipMask_RMASK 0x1
 442 #define QIB_6120_HwErrMask_IBPLLfbSlipMask_LSB 0x37
 443 #define QIB_6120_HwErrMask_IBPLLfbSlipMask_RMASK 0x1
 444 #define QIB_6120_HwErrMask_PowerOnBISTFailedMask_LSB 0x36
 445 #define QIB_6120_HwErrMask_PowerOnBISTFailedMask_RMASK 0x1
 446 #define QIB_6120_HwErrMask_Reserved2_LSB 0x33
 447 #define QIB_6120_HwErrMask_Reserved2_RMASK 0x7
 448 #define QIB_6120_HwErrMask_RXEMemParityErrMask_LSB 0x2C
 449 #define QIB_6120_HwErrMask_RXEMemParityErrMask_RMASK 0x7F
 450 #define QIB_6120_HwErrMask_TXEMemParityErrMask_LSB 0x28
 451 #define QIB_6120_HwErrMask_TXEMemParityErrMask_RMASK 0xF
 452 #define QIB_6120_HwErrMask_Reserved3_LSB 0x22
 453 #define QIB_6120_HwErrMask_Reserved3_RMASK 0x3F
 454 #define QIB_6120_HwErrMask_PCIeBusParityErrMask_LSB 0x1F
 455 #define QIB_6120_HwErrMask_PCIeBusParityErrMask_RMASK 0x7
 456 #define QIB_6120_HwErrMask_PcieCplTimeoutMask_LSB 0x1E
 457 #define QIB_6120_HwErrMask_PcieCplTimeoutMask_RMASK 0x1
 458 #define QIB_6120_HwErrMask_PoisonedTLPMask_LSB 0x1D
 459 #define QIB_6120_HwErrMask_PoisonedTLPMask_RMASK 0x1
 460 #define QIB_6120_HwErrMask_Reserved4_LSB 0x6
 461 #define QIB_6120_HwErrMask_Reserved4_RMASK 0x7FFFFF
 462 #define QIB_6120_HwErrMask_PCIeMemParityErrMask_LSB 0x0
 463 #define QIB_6120_HwErrMask_PCIeMemParityErrMask_RMASK 0x3F
 464 
 465 #define QIB_6120_HwErrStatus_OFFS 0xA0
 466 #define QIB_6120_HwErrStatus_IBCBusFromSPCParityErr_LSB 0x3F
 467 #define QIB_6120_HwErrStatus_IBCBusFromSPCParityErr_RMASK 0x1
 468 #define QIB_6120_HwErrStatus_IBCBusToSPCParityErr_LSB 0x3E
 469 #define QIB_6120_HwErrStatus_IBCBusToSPCParityErr_RMASK 0x1
 470 #define QIB_6120_HwErrStatus_Reserved_LSB 0x3D
 471 #define QIB_6120_HwErrStatus_Reserved_RMASK 0x1
 472 #define QIB_6120_HwErrStatus_IBSerdesPClkNotDetect_LSB 0x3C
 473 #define QIB_6120_HwErrStatus_IBSerdesPClkNotDetect_RMASK 0x1
 474 #define QIB_6120_HwErrStatus_PCIESerdesQ0PClkNotDetect_LSB 0x3B
 475 #define QIB_6120_HwErrStatus_PCIESerdesQ0PClkNotDetect_RMASK 0x1
 476 #define QIB_6120_HwErrStatus_PCIESerdesQ1PClkNotDetect_LSB 0x3A
 477 #define QIB_6120_HwErrStatus_PCIESerdesQ1PClkNotDetect_RMASK 0x1
 478 #define QIB_6120_HwErrStatus_Reserved1_LSB 0x39
 479 #define QIB_6120_HwErrStatus_Reserved1_RMASK 0x1
 480 #define QIB_6120_HwErrStatus_IBPLLrfSlip_LSB 0x38
 481 #define QIB_6120_HwErrStatus_IBPLLrfSlip_RMASK 0x1
 482 #define QIB_6120_HwErrStatus_IBPLLfbSlip_LSB 0x37
 483 #define QIB_6120_HwErrStatus_IBPLLfbSlip_RMASK 0x1
 484 #define QIB_6120_HwErrStatus_PowerOnBISTFailed_LSB 0x36
 485 #define QIB_6120_HwErrStatus_PowerOnBISTFailed_RMASK 0x1
 486 #define QIB_6120_HwErrStatus_Reserved2_LSB 0x33
 487 #define QIB_6120_HwErrStatus_Reserved2_RMASK 0x7
 488 #define QIB_6120_HwErrStatus_RXEMemParity_LSB 0x2C
 489 #define QIB_6120_HwErrStatus_RXEMemParity_RMASK 0x7F
 490 #define QIB_6120_HwErrStatus_TXEMemParity_LSB 0x28
 491 #define QIB_6120_HwErrStatus_TXEMemParity_RMASK 0xF
 492 #define QIB_6120_HwErrStatus_Reserved3_LSB 0x22
 493 #define QIB_6120_HwErrStatus_Reserved3_RMASK 0x3F
 494 #define QIB_6120_HwErrStatus_PCIeBusParity_LSB 0x1F
 495 #define QIB_6120_HwErrStatus_PCIeBusParity_RMASK 0x7
 496 #define QIB_6120_HwErrStatus_PcieCplTimeout_LSB 0x1E
 497 #define QIB_6120_HwErrStatus_PcieCplTimeout_RMASK 0x1
 498 #define QIB_6120_HwErrStatus_PoisenedTLP_LSB 0x1D
 499 #define QIB_6120_HwErrStatus_PoisenedTLP_RMASK 0x1
 500 #define QIB_6120_HwErrStatus_Reserved4_LSB 0x6
 501 #define QIB_6120_HwErrStatus_Reserved4_RMASK 0x7FFFFF
 502 #define QIB_6120_HwErrStatus_PCIeMemParity_LSB 0x0
 503 #define QIB_6120_HwErrStatus_PCIeMemParity_RMASK 0x3F
 504 
 505 #define QIB_6120_HwErrClear_OFFS 0xA8
 506 #define QIB_6120_HwErrClear_IBCBusFromSPCParityErrClear_LSB 0x3F
 507 #define QIB_6120_HwErrClear_IBCBusFromSPCParityErrClear_RMASK 0x1
 508 #define QIB_6120_HwErrClear_IBCBusToSPCparityErrClear_LSB 0x3E
 509 #define QIB_6120_HwErrClear_IBCBusToSPCparityErrClear_RMASK 0x1
 510 #define QIB_6120_HwErrClear_Reserved_LSB 0x3D
 511 #define QIB_6120_HwErrClear_Reserved_RMASK 0x1
 512 #define QIB_6120_HwErrClear_IBSerdesPClkNotDetectClear_LSB 0x3C
 513 #define QIB_6120_HwErrClear_IBSerdesPClkNotDetectClear_RMASK 0x1
 514 #define QIB_6120_HwErrClear_PCIESerdesQ0PClkNotDetectClear_LSB 0x3B
 515 #define QIB_6120_HwErrClear_PCIESerdesQ0PClkNotDetectClear_RMASK 0x1
 516 #define QIB_6120_HwErrClear_PCIESerdesQ1PClkNotDetectClear_LSB 0x3A
 517 #define QIB_6120_HwErrClear_PCIESerdesQ1PClkNotDetectClear_RMASK 0x1
 518 #define QIB_6120_HwErrClear_Reserved1_LSB 0x39
 519 #define QIB_6120_HwErrClear_Reserved1_RMASK 0x1
 520 #define QIB_6120_HwErrClear_IBPLLrfSlipClear_LSB 0x38
 521 #define QIB_6120_HwErrClear_IBPLLrfSlipClear_RMASK 0x1
 522 #define QIB_6120_HwErrClear_IBPLLfbSlipClear_LSB 0x37
 523 #define QIB_6120_HwErrClear_IBPLLfbSlipClear_RMASK 0x1
 524 #define QIB_6120_HwErrClear_PowerOnBISTFailedClear_LSB 0x36
 525 #define QIB_6120_HwErrClear_PowerOnBISTFailedClear_RMASK 0x1
 526 #define QIB_6120_HwErrClear_Reserved2_LSB 0x33
 527 #define QIB_6120_HwErrClear_Reserved2_RMASK 0x7
 528 #define QIB_6120_HwErrClear_RXEMemParityClear_LSB 0x2C
 529 #define QIB_6120_HwErrClear_RXEMemParityClear_RMASK 0x7F
 530 #define QIB_6120_HwErrClear_TXEMemParityClear_LSB 0x28
 531 #define QIB_6120_HwErrClear_TXEMemParityClear_RMASK 0xF
 532 #define QIB_6120_HwErrClear_Reserved3_LSB 0x22
 533 #define QIB_6120_HwErrClear_Reserved3_RMASK 0x3F
 534 #define QIB_6120_HwErrClear_PCIeBusParityClr_LSB 0x1F
 535 #define QIB_6120_HwErrClear_PCIeBusParityClr_RMASK 0x7
 536 #define QIB_6120_HwErrClear_PcieCplTimeoutClear_LSB 0x1E
 537 #define QIB_6120_HwErrClear_PcieCplTimeoutClear_RMASK 0x1
 538 #define QIB_6120_HwErrClear_PoisonedTLPClear_LSB 0x1D
 539 #define QIB_6120_HwErrClear_PoisonedTLPClear_RMASK 0x1
 540 #define QIB_6120_HwErrClear_Reserved4_LSB 0x6
 541 #define QIB_6120_HwErrClear_Reserved4_RMASK 0x7FFFFF
 542 #define QIB_6120_HwErrClear_PCIeMemParityClr_LSB 0x0
 543 #define QIB_6120_HwErrClear_PCIeMemParityClr_RMASK 0x3F
 544 
 545 #define QIB_6120_HwDiagCtrl_OFFS 0xB0
 546 #define QIB_6120_HwDiagCtrl_ForceIBCBusFromSPCParityErr_LSB 0x3F
 547 #define QIB_6120_HwDiagCtrl_ForceIBCBusFromSPCParityErr_RMASK 0x1
 548 #define QIB_6120_HwDiagCtrl_ForceIBCBusToSPCParityErr_LSB 0x3E
 549 #define QIB_6120_HwDiagCtrl_ForceIBCBusToSPCParityErr_RMASK 0x1
 550 #define QIB_6120_HwDiagCtrl_CounterWrEnable_LSB 0x3D
 551 #define QIB_6120_HwDiagCtrl_CounterWrEnable_RMASK 0x1
 552 #define QIB_6120_HwDiagCtrl_CounterDisable_LSB 0x3C
 553 #define QIB_6120_HwDiagCtrl_CounterDisable_RMASK 0x1
 554 #define QIB_6120_HwDiagCtrl_Reserved_LSB 0x33
 555 #define QIB_6120_HwDiagCtrl_Reserved_RMASK 0x1FF
 556 #define QIB_6120_HwDiagCtrl_ForceRxMemParityErr_LSB 0x2C
 557 #define QIB_6120_HwDiagCtrl_ForceRxMemParityErr_RMASK 0x7F
 558 #define QIB_6120_HwDiagCtrl_ForceTxMemparityErr_LSB 0x28
 559 #define QIB_6120_HwDiagCtrl_ForceTxMemparityErr_RMASK 0xF
 560 #define QIB_6120_HwDiagCtrl_Reserved1_LSB 0x23
 561 #define QIB_6120_HwDiagCtrl_Reserved1_RMASK 0x1F
 562 #define QIB_6120_HwDiagCtrl_forcePCIeBusParity_LSB 0x1F
 563 #define QIB_6120_HwDiagCtrl_forcePCIeBusParity_RMASK 0xF
 564 #define QIB_6120_HwDiagCtrl_Reserved2_LSB 0x6
 565 #define QIB_6120_HwDiagCtrl_Reserved2_RMASK 0x1FFFFFF
 566 #define QIB_6120_HwDiagCtrl_forcePCIeMemParity_LSB 0x0
 567 #define QIB_6120_HwDiagCtrl_forcePCIeMemParity_RMASK 0x3F
 568 
 569 #define QIB_6120_IBCStatus_OFFS 0xC0
 570 #define QIB_6120_IBCStatus_TxCreditOk_LSB 0x1F
 571 #define QIB_6120_IBCStatus_TxCreditOk_RMASK 0x1
 572 #define QIB_6120_IBCStatus_TxReady_LSB 0x1E
 573 #define QIB_6120_IBCStatus_TxReady_RMASK 0x1
 574 #define QIB_6120_IBCStatus_Reserved_LSB 0x7
 575 #define QIB_6120_IBCStatus_Reserved_RMASK 0x7FFFFF
 576 #define QIB_6120_IBCStatus_LinkState_LSB 0x4
 577 #define QIB_6120_IBCStatus_LinkState_RMASK 0x7
 578 #define QIB_6120_IBCStatus_LinkTrainingState_LSB 0x0
 579 #define QIB_6120_IBCStatus_LinkTrainingState_RMASK 0xF
 580 
 581 #define QIB_6120_IBCCtrl_OFFS 0xC8
 582 #define QIB_6120_IBCCtrl_Loopback_LSB 0x3F
 583 #define QIB_6120_IBCCtrl_Loopback_RMASK 0x1
 584 #define QIB_6120_IBCCtrl_LinkDownDefaultState_LSB 0x3E
 585 #define QIB_6120_IBCCtrl_LinkDownDefaultState_RMASK 0x1
 586 #define QIB_6120_IBCCtrl_Reserved_LSB 0x2B
 587 #define QIB_6120_IBCCtrl_Reserved_RMASK 0x7FFFF
 588 #define QIB_6120_IBCCtrl_CreditScale_LSB 0x28
 589 #define QIB_6120_IBCCtrl_CreditScale_RMASK 0x7
 590 #define QIB_6120_IBCCtrl_OverrunThreshold_LSB 0x24
 591 #define QIB_6120_IBCCtrl_OverrunThreshold_RMASK 0xF
 592 #define QIB_6120_IBCCtrl_PhyerrThreshold_LSB 0x20
 593 #define QIB_6120_IBCCtrl_PhyerrThreshold_RMASK 0xF
 594 #define QIB_6120_IBCCtrl_Reserved1_LSB 0x1F
 595 #define QIB_6120_IBCCtrl_Reserved1_RMASK 0x1
 596 #define QIB_6120_IBCCtrl_MaxPktLen_LSB 0x14
 597 #define QIB_6120_IBCCtrl_MaxPktLen_RMASK 0x7FF
 598 #define QIB_6120_IBCCtrl_LinkCmd_LSB 0x12
 599 #define QIB_6120_IBCCtrl_LinkCmd_RMASK 0x3
 600 #define QIB_6120_IBCCtrl_LinkInitCmd_LSB 0x10
 601 #define QIB_6120_IBCCtrl_LinkInitCmd_RMASK 0x3
 602 #define QIB_6120_IBCCtrl_FlowCtrlWaterMark_LSB 0x8
 603 #define QIB_6120_IBCCtrl_FlowCtrlWaterMark_RMASK 0xFF
 604 #define QIB_6120_IBCCtrl_FlowCtrlPeriod_LSB 0x0
 605 #define QIB_6120_IBCCtrl_FlowCtrlPeriod_RMASK 0xFF
 606 
 607 #define QIB_6120_EXTStatus_OFFS 0xD0
 608 #define QIB_6120_EXTStatus_GPIOIn_LSB 0x30
 609 #define QIB_6120_EXTStatus_GPIOIn_RMASK 0xFFFF
 610 #define QIB_6120_EXTStatus_Reserved_LSB 0x20
 611 #define QIB_6120_EXTStatus_Reserved_RMASK 0xFFFF
 612 #define QIB_6120_EXTStatus_Reserved1_LSB 0x10
 613 #define QIB_6120_EXTStatus_Reserved1_RMASK 0xFFFF
 614 #define QIB_6120_EXTStatus_MemBISTFoundErr_LSB 0xF
 615 #define QIB_6120_EXTStatus_MemBISTFoundErr_RMASK 0x1
 616 #define QIB_6120_EXTStatus_MemBISTEndTest_LSB 0xE
 617 #define QIB_6120_EXTStatus_MemBISTEndTest_RMASK 0x1
 618 #define QIB_6120_EXTStatus_Reserved2_LSB 0x0
 619 #define QIB_6120_EXTStatus_Reserved2_RMASK 0x3FFF
 620 
 621 #define QIB_6120_EXTCtrl_OFFS 0xD8
 622 #define QIB_6120_EXTCtrl_GPIOOe_LSB 0x30
 623 #define QIB_6120_EXTCtrl_GPIOOe_RMASK 0xFFFF
 624 #define QIB_6120_EXTCtrl_GPIOInvert_LSB 0x20
 625 #define QIB_6120_EXTCtrl_GPIOInvert_RMASK 0xFFFF
 626 #define QIB_6120_EXTCtrl_Reserved_LSB 0x4
 627 #define QIB_6120_EXTCtrl_Reserved_RMASK 0xFFFFFFF
 628 #define QIB_6120_EXTCtrl_LEDPriPortGreenOn_LSB 0x3
 629 #define QIB_6120_EXTCtrl_LEDPriPortGreenOn_RMASK 0x1
 630 #define QIB_6120_EXTCtrl_LEDPriPortYellowOn_LSB 0x2
 631 #define QIB_6120_EXTCtrl_LEDPriPortYellowOn_RMASK 0x1
 632 #define QIB_6120_EXTCtrl_LEDGblOkGreenOn_LSB 0x1
 633 #define QIB_6120_EXTCtrl_LEDGblOkGreenOn_RMASK 0x1
 634 #define QIB_6120_EXTCtrl_LEDGblErrRedOff_LSB 0x0
 635 #define QIB_6120_EXTCtrl_LEDGblErrRedOff_RMASK 0x1
 636 
 637 #define QIB_6120_GPIOOut_OFFS 0xE0
 638 
 639 #define QIB_6120_GPIOMask_OFFS 0xE8
 640 
 641 #define QIB_6120_GPIOStatus_OFFS 0xF0
 642 
 643 #define QIB_6120_GPIOClear_OFFS 0xF8
 644 
 645 #define QIB_6120_RcvCtrl_OFFS 0x100
 646 #define QIB_6120_RcvCtrl_TailUpd_LSB 0x1F
 647 #define QIB_6120_RcvCtrl_TailUpd_RMASK 0x1
 648 #define QIB_6120_RcvCtrl_RcvPartitionKeyDisable_LSB 0x1E
 649 #define QIB_6120_RcvCtrl_RcvPartitionKeyDisable_RMASK 0x1
 650 #define QIB_6120_RcvCtrl_Reserved_LSB 0x15
 651 #define QIB_6120_RcvCtrl_Reserved_RMASK 0x1FF
 652 #define QIB_6120_RcvCtrl_IntrAvail_LSB 0x10
 653 #define QIB_6120_RcvCtrl_IntrAvail_RMASK 0x1F
 654 #define QIB_6120_RcvCtrl_Reserved1_LSB 0x9
 655 #define QIB_6120_RcvCtrl_Reserved1_RMASK 0x7F
 656 #define QIB_6120_RcvCtrl_Reserved2_LSB 0x5
 657 #define QIB_6120_RcvCtrl_Reserved2_RMASK 0xF
 658 #define QIB_6120_RcvCtrl_PortEnable_LSB 0x0
 659 #define QIB_6120_RcvCtrl_PortEnable_RMASK 0x1F
 660 
 661 #define QIB_6120_RcvBTHQP_OFFS 0x108
 662 #define QIB_6120_RcvBTHQP_BTHQP_Mask_LSB 0x1E
 663 #define QIB_6120_RcvBTHQP_BTHQP_Mask_RMASK 0x3
 664 #define QIB_6120_RcvBTHQP_Reserved_LSB 0x18
 665 #define QIB_6120_RcvBTHQP_Reserved_RMASK 0x3F
 666 #define QIB_6120_RcvBTHQP_RcvBTHQP_LSB 0x0
 667 #define QIB_6120_RcvBTHQP_RcvBTHQP_RMASK 0xFFFFFF
 668 
 669 #define QIB_6120_RcvHdrSize_OFFS 0x110
 670 
 671 #define QIB_6120_RcvHdrCnt_OFFS 0x118
 672 
 673 #define QIB_6120_RcvHdrEntSize_OFFS 0x120
 674 
 675 #define QIB_6120_RcvTIDBase_OFFS 0x128
 676 
 677 #define QIB_6120_RcvTIDCnt_OFFS 0x130
 678 
 679 #define QIB_6120_RcvEgrBase_OFFS 0x138
 680 
 681 #define QIB_6120_RcvEgrCnt_OFFS 0x140
 682 
 683 #define QIB_6120_RcvBufBase_OFFS 0x148
 684 
 685 #define QIB_6120_RcvBufSize_OFFS 0x150
 686 
 687 #define QIB_6120_RxIntMemBase_OFFS 0x158
 688 
 689 #define QIB_6120_RxIntMemSize_OFFS 0x160
 690 
 691 #define QIB_6120_RcvPartitionKey_OFFS 0x168
 692 
 693 #define QIB_6120_RcvPktLEDCnt_OFFS 0x178
 694 #define QIB_6120_RcvPktLEDCnt_ONperiod_LSB 0x20
 695 #define QIB_6120_RcvPktLEDCnt_ONperiod_RMASK 0xFFFFFFFF
 696 #define QIB_6120_RcvPktLEDCnt_OFFperiod_LSB 0x0
 697 #define QIB_6120_RcvPktLEDCnt_OFFperiod_RMASK 0xFFFFFFFF
 698 
 699 #define QIB_6120_SendCtrl_OFFS 0x1C0
 700 #define QIB_6120_SendCtrl_Disarm_LSB 0x1F
 701 #define QIB_6120_SendCtrl_Disarm_RMASK 0x1
 702 #define QIB_6120_SendCtrl_Reserved_LSB 0x17
 703 #define QIB_6120_SendCtrl_Reserved_RMASK 0xFF
 704 #define QIB_6120_SendCtrl_DisarmPIOBuf_LSB 0x10
 705 #define QIB_6120_SendCtrl_DisarmPIOBuf_RMASK 0x7F
 706 #define QIB_6120_SendCtrl_Reserved1_LSB 0x4
 707 #define QIB_6120_SendCtrl_Reserved1_RMASK 0xFFF
 708 #define QIB_6120_SendCtrl_PIOEnable_LSB 0x3
 709 #define QIB_6120_SendCtrl_PIOEnable_RMASK 0x1
 710 #define QIB_6120_SendCtrl_PIOBufAvailUpd_LSB 0x2
 711 #define QIB_6120_SendCtrl_PIOBufAvailUpd_RMASK 0x1
 712 #define QIB_6120_SendCtrl_PIOIntBufAvail_LSB 0x1
 713 #define QIB_6120_SendCtrl_PIOIntBufAvail_RMASK 0x1
 714 #define QIB_6120_SendCtrl_Abort_LSB 0x0
 715 #define QIB_6120_SendCtrl_Abort_RMASK 0x1
 716 
 717 #define QIB_6120_SendPIOBufBase_OFFS 0x1C8
 718 #define QIB_6120_SendPIOBufBase_Reserved_LSB 0x35
 719 #define QIB_6120_SendPIOBufBase_Reserved_RMASK 0x7FF
 720 #define QIB_6120_SendPIOBufBase_BaseAddr_LargePIO_LSB 0x20
 721 #define QIB_6120_SendPIOBufBase_BaseAddr_LargePIO_RMASK 0x1FFFFF
 722 #define QIB_6120_SendPIOBufBase_Reserved1_LSB 0x15
 723 #define QIB_6120_SendPIOBufBase_Reserved1_RMASK 0x7FF
 724 #define QIB_6120_SendPIOBufBase_BaseAddr_SmallPIO_LSB 0x0
 725 #define QIB_6120_SendPIOBufBase_BaseAddr_SmallPIO_RMASK 0x1FFFFF
 726 
 727 #define QIB_6120_SendPIOSize_OFFS 0x1D0
 728 #define QIB_6120_SendPIOSize_Reserved_LSB 0x2D
 729 #define QIB_6120_SendPIOSize_Reserved_RMASK 0xFFFFF
 730 #define QIB_6120_SendPIOSize_Size_LargePIO_LSB 0x20
 731 #define QIB_6120_SendPIOSize_Size_LargePIO_RMASK 0x1FFF
 732 #define QIB_6120_SendPIOSize_Reserved1_LSB 0xC
 733 #define QIB_6120_SendPIOSize_Reserved1_RMASK 0xFFFFF
 734 #define QIB_6120_SendPIOSize_Size_SmallPIO_LSB 0x0
 735 #define QIB_6120_SendPIOSize_Size_SmallPIO_RMASK 0xFFF
 736 
 737 #define QIB_6120_SendPIOBufCnt_OFFS 0x1D8
 738 #define QIB_6120_SendPIOBufCnt_Reserved_LSB 0x24
 739 #define QIB_6120_SendPIOBufCnt_Reserved_RMASK 0xFFFFFFF
 740 #define QIB_6120_SendPIOBufCnt_Num_LargePIO_LSB 0x20
 741 #define QIB_6120_SendPIOBufCnt_Num_LargePIO_RMASK 0xF
 742 #define QIB_6120_SendPIOBufCnt_Reserved1_LSB 0x9
 743 #define QIB_6120_SendPIOBufCnt_Reserved1_RMASK 0x7FFFFF
 744 #define QIB_6120_SendPIOBufCnt_Num_SmallPIO_LSB 0x0
 745 #define QIB_6120_SendPIOBufCnt_Num_SmallPIO_RMASK 0x1FF
 746 
 747 #define QIB_6120_SendPIOAvailAddr_OFFS 0x1E0
 748 #define QIB_6120_SendPIOAvailAddr_SendPIOAvailAddr_LSB 0x6
 749 #define QIB_6120_SendPIOAvailAddr_SendPIOAvailAddr_RMASK 0x3FFFFFFFF
 750 #define QIB_6120_SendPIOAvailAddr_Reserved_LSB 0x0
 751 #define QIB_6120_SendPIOAvailAddr_Reserved_RMASK 0x3F
 752 
 753 #define QIB_6120_SendBufErr0_OFFS 0x240
 754 #define QIB_6120_SendBufErr0_SendBufErrPIO_63_0_LSB 0x0
 755 #define QIB_6120_SendBufErr0_SendBufErrPIO_63_0_RMASK 0x0
 756 
 757 #define QIB_6120_RcvHdrAddr0_OFFS 0x280
 758 #define QIB_6120_RcvHdrAddr0_RcvHdrAddr0_LSB 0x2
 759 #define QIB_6120_RcvHdrAddr0_RcvHdrAddr0_RMASK 0x3FFFFFFFFF
 760 #define QIB_6120_RcvHdrAddr0_Reserved_LSB 0x0
 761 #define QIB_6120_RcvHdrAddr0_Reserved_RMASK 0x3
 762 
 763 #define QIB_6120_RcvHdrTailAddr0_OFFS 0x300
 764 #define QIB_6120_RcvHdrTailAddr0_RcvHdrTailAddr0_LSB 0x2
 765 #define QIB_6120_RcvHdrTailAddr0_RcvHdrTailAddr0_RMASK 0x3FFFFFFFFF
 766 #define QIB_6120_RcvHdrTailAddr0_Reserved_LSB 0x0
 767 #define QIB_6120_RcvHdrTailAddr0_Reserved_RMASK 0x3
 768 
 769 #define QIB_6120_SerdesCfg0_OFFS 0x3C0
 770 #define QIB_6120_SerdesCfg0_DisableIBTxIdleDetect_LSB 0x3F
 771 #define QIB_6120_SerdesCfg0_DisableIBTxIdleDetect_RMASK 0x1
 772 #define QIB_6120_SerdesCfg0_Reserved_LSB 0x38
 773 #define QIB_6120_SerdesCfg0_Reserved_RMASK 0x7F
 774 #define QIB_6120_SerdesCfg0_RxEqCtl_LSB 0x36
 775 #define QIB_6120_SerdesCfg0_RxEqCtl_RMASK 0x3
 776 #define QIB_6120_SerdesCfg0_TxTermAdj_LSB 0x34
 777 #define QIB_6120_SerdesCfg0_TxTermAdj_RMASK 0x3
 778 #define QIB_6120_SerdesCfg0_RxTermAdj_LSB 0x32
 779 #define QIB_6120_SerdesCfg0_RxTermAdj_RMASK 0x3
 780 #define QIB_6120_SerdesCfg0_TermAdj1_LSB 0x31
 781 #define QIB_6120_SerdesCfg0_TermAdj1_RMASK 0x1
 782 #define QIB_6120_SerdesCfg0_TermAdj0_LSB 0x30
 783 #define QIB_6120_SerdesCfg0_TermAdj0_RMASK 0x1
 784 #define QIB_6120_SerdesCfg0_LPBKA_LSB 0x2F
 785 #define QIB_6120_SerdesCfg0_LPBKA_RMASK 0x1
 786 #define QIB_6120_SerdesCfg0_LPBKB_LSB 0x2E
 787 #define QIB_6120_SerdesCfg0_LPBKB_RMASK 0x1
 788 #define QIB_6120_SerdesCfg0_LPBKC_LSB 0x2D
 789 #define QIB_6120_SerdesCfg0_LPBKC_RMASK 0x1
 790 #define QIB_6120_SerdesCfg0_LPBKD_LSB 0x2C
 791 #define QIB_6120_SerdesCfg0_LPBKD_RMASK 0x1
 792 #define QIB_6120_SerdesCfg0_PW_LSB 0x2B
 793 #define QIB_6120_SerdesCfg0_PW_RMASK 0x1
 794 #define QIB_6120_SerdesCfg0_RefSel_LSB 0x29
 795 #define QIB_6120_SerdesCfg0_RefSel_RMASK 0x3
 796 #define QIB_6120_SerdesCfg0_ParReset_LSB 0x28
 797 #define QIB_6120_SerdesCfg0_ParReset_RMASK 0x1
 798 #define QIB_6120_SerdesCfg0_ParLPBK_LSB 0x27
 799 #define QIB_6120_SerdesCfg0_ParLPBK_RMASK 0x1
 800 #define QIB_6120_SerdesCfg0_OffsetEn_LSB 0x26
 801 #define QIB_6120_SerdesCfg0_OffsetEn_RMASK 0x1
 802 #define QIB_6120_SerdesCfg0_Offset_LSB 0x1E
 803 #define QIB_6120_SerdesCfg0_Offset_RMASK 0xFF
 804 #define QIB_6120_SerdesCfg0_L2PwrDn_LSB 0x1D
 805 #define QIB_6120_SerdesCfg0_L2PwrDn_RMASK 0x1
 806 #define QIB_6120_SerdesCfg0_ResetPLL_LSB 0x1C
 807 #define QIB_6120_SerdesCfg0_ResetPLL_RMASK 0x1
 808 #define QIB_6120_SerdesCfg0_RxTermEnX_LSB 0x18
 809 #define QIB_6120_SerdesCfg0_RxTermEnX_RMASK 0xF
 810 #define QIB_6120_SerdesCfg0_BeaconTxEnX_LSB 0x14
 811 #define QIB_6120_SerdesCfg0_BeaconTxEnX_RMASK 0xF
 812 #define QIB_6120_SerdesCfg0_RxDetEnX_LSB 0x10
 813 #define QIB_6120_SerdesCfg0_RxDetEnX_RMASK 0xF
 814 #define QIB_6120_SerdesCfg0_TxIdeEnX_LSB 0xC
 815 #define QIB_6120_SerdesCfg0_TxIdeEnX_RMASK 0xF
 816 #define QIB_6120_SerdesCfg0_RxIdleEnX_LSB 0x8
 817 #define QIB_6120_SerdesCfg0_RxIdleEnX_RMASK 0xF
 818 #define QIB_6120_SerdesCfg0_L1PwrDnA_LSB 0x7
 819 #define QIB_6120_SerdesCfg0_L1PwrDnA_RMASK 0x1
 820 #define QIB_6120_SerdesCfg0_L1PwrDnB_LSB 0x6
 821 #define QIB_6120_SerdesCfg0_L1PwrDnB_RMASK 0x1
 822 #define QIB_6120_SerdesCfg0_L1PwrDnC_LSB 0x5
 823 #define QIB_6120_SerdesCfg0_L1PwrDnC_RMASK 0x1
 824 #define QIB_6120_SerdesCfg0_L1PwrDnD_LSB 0x4
 825 #define QIB_6120_SerdesCfg0_L1PwrDnD_RMASK 0x1
 826 #define QIB_6120_SerdesCfg0_ResetA_LSB 0x3
 827 #define QIB_6120_SerdesCfg0_ResetA_RMASK 0x1
 828 #define QIB_6120_SerdesCfg0_ResetB_LSB 0x2
 829 #define QIB_6120_SerdesCfg0_ResetB_RMASK 0x1
 830 #define QIB_6120_SerdesCfg0_ResetC_LSB 0x1
 831 #define QIB_6120_SerdesCfg0_ResetC_RMASK 0x1
 832 #define QIB_6120_SerdesCfg0_ResetD_LSB 0x0
 833 #define QIB_6120_SerdesCfg0_ResetD_RMASK 0x1
 834 
 835 #define QIB_6120_SerdesStat_OFFS 0x3D0
 836 #define QIB_6120_SerdesStat_Reserved_LSB 0xC
 837 #define QIB_6120_SerdesStat_Reserved_RMASK 0xFFFFFFFFFFFFF
 838 #define QIB_6120_SerdesStat_BeaconDetA_LSB 0xB
 839 #define QIB_6120_SerdesStat_BeaconDetA_RMASK 0x1
 840 #define QIB_6120_SerdesStat_BeaconDetB_LSB 0xA
 841 #define QIB_6120_SerdesStat_BeaconDetB_RMASK 0x1
 842 #define QIB_6120_SerdesStat_BeaconDetC_LSB 0x9
 843 #define QIB_6120_SerdesStat_BeaconDetC_RMASK 0x1
 844 #define QIB_6120_SerdesStat_BeaconDetD_LSB 0x8
 845 #define QIB_6120_SerdesStat_BeaconDetD_RMASK 0x1
 846 #define QIB_6120_SerdesStat_RxDetA_LSB 0x7
 847 #define QIB_6120_SerdesStat_RxDetA_RMASK 0x1
 848 #define QIB_6120_SerdesStat_RxDetB_LSB 0x6
 849 #define QIB_6120_SerdesStat_RxDetB_RMASK 0x1
 850 #define QIB_6120_SerdesStat_RxDetC_LSB 0x5
 851 #define QIB_6120_SerdesStat_RxDetC_RMASK 0x1
 852 #define QIB_6120_SerdesStat_RxDetD_LSB 0x4
 853 #define QIB_6120_SerdesStat_RxDetD_RMASK 0x1
 854 #define QIB_6120_SerdesStat_TxIdleDetA_LSB 0x3
 855 #define QIB_6120_SerdesStat_TxIdleDetA_RMASK 0x1
 856 #define QIB_6120_SerdesStat_TxIdleDetB_LSB 0x2
 857 #define QIB_6120_SerdesStat_TxIdleDetB_RMASK 0x1
 858 #define QIB_6120_SerdesStat_TxIdleDetC_LSB 0x1
 859 #define QIB_6120_SerdesStat_TxIdleDetC_RMASK 0x1
 860 #define QIB_6120_SerdesStat_TxIdleDetD_LSB 0x0
 861 #define QIB_6120_SerdesStat_TxIdleDetD_RMASK 0x1
 862 
 863 #define QIB_6120_XGXSCfg_OFFS 0x3D8
 864 #define QIB_6120_XGXSCfg_ArmLaunchErrorDisable_LSB 0x3F
 865 #define QIB_6120_XGXSCfg_ArmLaunchErrorDisable_RMASK 0x1
 866 #define QIB_6120_XGXSCfg_Reserved_LSB 0x17
 867 #define QIB_6120_XGXSCfg_Reserved_RMASK 0xFFFFFFFFFF
 868 #define QIB_6120_XGXSCfg_polarity_inv_LSB 0x13
 869 #define QIB_6120_XGXSCfg_polarity_inv_RMASK 0xF
 870 #define QIB_6120_XGXSCfg_link_sync_mask_LSB 0x9
 871 #define QIB_6120_XGXSCfg_link_sync_mask_RMASK 0x3FF
 872 #define QIB_6120_XGXSCfg_port_addr_LSB 0x4
 873 #define QIB_6120_XGXSCfg_port_addr_RMASK 0x1F
 874 #define QIB_6120_XGXSCfg_mdd_30_LSB 0x3
 875 #define QIB_6120_XGXSCfg_mdd_30_RMASK 0x1
 876 #define QIB_6120_XGXSCfg_xcv_resetn_LSB 0x2
 877 #define QIB_6120_XGXSCfg_xcv_resetn_RMASK 0x1
 878 #define QIB_6120_XGXSCfg_Reserved1_LSB 0x1
 879 #define QIB_6120_XGXSCfg_Reserved1_RMASK 0x1
 880 #define QIB_6120_XGXSCfg_tx_rx_resetn_LSB 0x0
 881 #define QIB_6120_XGXSCfg_tx_rx_resetn_RMASK 0x1
 882 
 883 #define QIB_6120_LBIntCnt_OFFS 0x12000
 884 
 885 #define QIB_6120_LBFlowStallCnt_OFFS 0x12008
 886 
 887 #define QIB_6120_TxUnsupVLErrCnt_OFFS 0x12018
 888 
 889 #define QIB_6120_TxDataPktCnt_OFFS 0x12020
 890 
 891 #define QIB_6120_TxFlowPktCnt_OFFS 0x12028
 892 
 893 #define QIB_6120_TxDwordCnt_OFFS 0x12030
 894 
 895 #define QIB_6120_TxLenErrCnt_OFFS 0x12038
 896 
 897 #define QIB_6120_TxMaxMinLenErrCnt_OFFS 0x12040
 898 
 899 #define QIB_6120_TxUnderrunCnt_OFFS 0x12048
 900 
 901 #define QIB_6120_TxFlowStallCnt_OFFS 0x12050
 902 
 903 #define QIB_6120_TxDroppedPktCnt_OFFS 0x12058
 904 
 905 #define QIB_6120_RxDroppedPktCnt_OFFS 0x12060
 906 
 907 #define QIB_6120_RxDataPktCnt_OFFS 0x12068
 908 
 909 #define QIB_6120_RxFlowPktCnt_OFFS 0x12070
 910 
 911 #define QIB_6120_RxDwordCnt_OFFS 0x12078
 912 
 913 #define QIB_6120_RxLenErrCnt_OFFS 0x12080
 914 
 915 #define QIB_6120_RxMaxMinLenErrCnt_OFFS 0x12088
 916 
 917 #define QIB_6120_RxICRCErrCnt_OFFS 0x12090
 918 
 919 #define QIB_6120_RxVCRCErrCnt_OFFS 0x12098
 920 
 921 #define QIB_6120_RxFlowCtrlErrCnt_OFFS 0x120A0
 922 
 923 #define QIB_6120_RxBadFormatCnt_OFFS 0x120A8
 924 
 925 #define QIB_6120_RxLinkProblemCnt_OFFS 0x120B0
 926 
 927 #define QIB_6120_RxEBPCnt_OFFS 0x120B8
 928 
 929 #define QIB_6120_RxLPCRCErrCnt_OFFS 0x120C0
 930 
 931 #define QIB_6120_RxBufOvflCnt_OFFS 0x120C8
 932 
 933 #define QIB_6120_RxTIDFullErrCnt_OFFS 0x120D0
 934 
 935 #define QIB_6120_RxTIDValidErrCnt_OFFS 0x120D8
 936 
 937 #define QIB_6120_RxPKeyMismatchCnt_OFFS 0x120E0
 938 
 939 #define QIB_6120_RxP0HdrEgrOvflCnt_OFFS 0x120E8
 940 
 941 #define QIB_6120_IBStatusChangeCnt_OFFS 0x12140
 942 
 943 #define QIB_6120_IBLinkErrRecoveryCnt_OFFS 0x12148
 944 
 945 #define QIB_6120_IBLinkDownedCnt_OFFS 0x12150
 946 
 947 #define QIB_6120_IBSymbolErrCnt_OFFS 0x12158
 948 
 949 #define QIB_6120_PcieRetryBufDiagQwordCnt_OFFS 0x12170
 950 
 951 #define QIB_6120_RcvEgrArray0_OFFS 0x14000
 952 
 953 #define QIB_6120_RcvTIDArray0_OFFS 0x54000
 954 
 955 #define QIB_6120_PIOLaunchFIFO_OFFS 0x64000
 956 
 957 #define QIB_6120_SendPIOpbcCache_OFFS 0x64800
 958 
 959 #define QIB_6120_RcvBuf1_OFFS 0x72000
 960 
 961 #define QIB_6120_RcvBuf2_OFFS 0x75000
 962 
 963 #define QIB_6120_RcvFlags_OFFS 0x77000
 964 
 965 #define QIB_6120_RcvLookupBuf1_OFFS 0x79000
 966 
 967 #define QIB_6120_RcvDMABuf_OFFS 0x7B000
 968 
 969 #define QIB_6120_MiscRXEIntMem_OFFS 0x7C000
 970 
 971 #define QIB_6120_PCIERcvBuf_OFFS 0x80000
 972 
 973 #define QIB_6120_PCIERetryBuf_OFFS 0x82000
 974 
 975 #define QIB_6120_PCIERcvBufRdToWrAddr_OFFS 0x84000
 976 
 977 #define QIB_6120_PIOBuf0_MA_OFFS 0x100000
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