1 /*
2 * Copyright (c) 2012 Intel Corporation. All rights reserved.
3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/delay.h>
36 #include <linux/pci.h>
37 #include <linux/vmalloc.h>
38
39 #include "qib.h"
40
41 /*
42 * QLogic_IB "Two Wire Serial Interface" driver.
43 * Originally written for a not-quite-i2c serial eeprom, which is
44 * still used on some supported boards. Later boards have added a
45 * variety of other uses, most board-specific, so the bit-boffing
46 * part has been split off to this file, while the other parts
47 * have been moved to chip-specific files.
48 *
49 * We have also dropped all pretense of fully generic (e.g. pretend
50 * we don't know whether '1' is the higher voltage) interface, as
51 * the restrictions of the generic i2c interface (e.g. no access from
52 * driver itself) make it unsuitable for this use.
53 */
54
55 #define READ_CMD 1
56 #define WRITE_CMD 0
57
58 /**
59 * i2c_wait_for_writes - wait for a write
60 * @dd: the qlogic_ib device
61 *
62 * We use this instead of udelay directly, so we can make sure
63 * that previous register writes have been flushed all the way
64 * to the chip. Since we are delaying anyway, the cost doesn't
65 * hurt, and makes the bit twiddling more regular
66 */
67 static void i2c_wait_for_writes(struct qib_devdata *dd)
68 {
69 /*
70 * implicit read of EXTStatus is as good as explicit
71 * read of scratch, if all we want to do is flush
72 * writes.
73 */
74 dd->f_gpio_mod(dd, 0, 0, 0);
75 rmb(); /* inlined, so prevent compiler reordering */
76 }
77
78 /*
79 * QSFP modules are allowed to hold SCL low for 500uSec. Allow twice that
80 * for "almost compliant" modules
81 */
82 #define SCL_WAIT_USEC 1000
83
84 /* BUF_WAIT is time bus must be free between STOP or ACK and to next START.
85 * Should be 20, but some chips need more.
86 */
87 #define TWSI_BUF_WAIT_USEC 60
88
89 static void scl_out(struct qib_devdata *dd, u8 bit)
90 {
91 u32 mask;
92
93 udelay(1);
94
95 mask = 1UL << dd->gpio_scl_num;
96
97 /* SCL is meant to be bare-drain, so never set "OUT", just DIR */
98 dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);
99
100 /*
101 * Allow for slow slaves by simple
102 * delay for falling edge, sampling on rise.
103 */
104 if (!bit)
105 udelay(2);
106 else {
107 int rise_usec;
108
109 for (rise_usec = SCL_WAIT_USEC; rise_usec > 0; rise_usec -= 2) {
110 if (mask & dd->f_gpio_mod(dd, 0, 0, 0))
111 break;
112 udelay(2);
113 }
114 if (rise_usec <= 0)
115 qib_dev_err(dd, "SCL interface stuck low > %d uSec\n",
116 SCL_WAIT_USEC);
117 }
118 i2c_wait_for_writes(dd);
119 }
120
121 static void sda_out(struct qib_devdata *dd, u8 bit)
122 {
123 u32 mask;
124
125 mask = 1UL << dd->gpio_sda_num;
126
127 /* SDA is meant to be bare-drain, so never set "OUT", just DIR */
128 dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);
129
130 i2c_wait_for_writes(dd);
131 udelay(2);
132 }
133
134 static u8 sda_in(struct qib_devdata *dd, int wait)
135 {
136 int bnum;
137 u32 read_val, mask;
138
139 bnum = dd->gpio_sda_num;
140 mask = (1UL << bnum);
141 /* SDA is meant to be bare-drain, so never set "OUT", just DIR */
142 dd->f_gpio_mod(dd, 0, 0, mask);
143 read_val = dd->f_gpio_mod(dd, 0, 0, 0);
144 if (wait)
145 i2c_wait_for_writes(dd);
146 return (read_val & mask) >> bnum;
147 }
148
149 /**
150 * i2c_ackrcv - see if ack following write is true
151 * @dd: the qlogic_ib device
152 */
153 static int i2c_ackrcv(struct qib_devdata *dd)
154 {
155 u8 ack_received;
156
157 /* AT ENTRY SCL = LOW */
158 /* change direction, ignore data */
159 ack_received = sda_in(dd, 1);
160 scl_out(dd, 1);
161 ack_received = sda_in(dd, 1) == 0;
162 scl_out(dd, 0);
163 return ack_received;
164 }
165
166 static void stop_cmd(struct qib_devdata *dd);
167
168 /**
169 * rd_byte - read a byte, sending STOP on last, else ACK
170 * @dd: the qlogic_ib device
171 *
172 * Returns byte shifted out of device
173 */
174 static int rd_byte(struct qib_devdata *dd, int last)
175 {
176 int bit_cntr, data;
177
178 data = 0;
179
180 for (bit_cntr = 7; bit_cntr >= 0; --bit_cntr) {
181 data <<= 1;
182 scl_out(dd, 1);
183 data |= sda_in(dd, 0);
184 scl_out(dd, 0);
185 }
186 if (last) {
187 scl_out(dd, 1);
188 stop_cmd(dd);
189 } else {
190 sda_out(dd, 0);
191 scl_out(dd, 1);
192 scl_out(dd, 0);
193 sda_out(dd, 1);
194 }
195 return data;
196 }
197
198 /**
199 * wr_byte - write a byte, one bit at a time
200 * @dd: the qlogic_ib device
201 * @data: the byte to write
202 *
203 * Returns 0 if we got the following ack, otherwise 1
204 */
205 static int wr_byte(struct qib_devdata *dd, u8 data)
206 {
207 int bit_cntr;
208 u8 bit;
209
210 for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) {
211 bit = (data >> bit_cntr) & 1;
212 sda_out(dd, bit);
213 scl_out(dd, 1);
214 scl_out(dd, 0);
215 }
216 return (!i2c_ackrcv(dd)) ? 1 : 0;
217 }
218
219 /*
220 * issue TWSI start sequence:
221 * (both clock/data high, clock high, data low while clock is high)
222 */
223 static void start_seq(struct qib_devdata *dd)
224 {
225 sda_out(dd, 1);
226 scl_out(dd, 1);
227 sda_out(dd, 0);
228 udelay(1);
229 scl_out(dd, 0);
230 }
231
232 /**
233 * stop_seq - transmit the stop sequence
234 * @dd: the qlogic_ib device
235 *
236 * (both clock/data low, clock high, data high while clock is high)
237 */
238 static void stop_seq(struct qib_devdata *dd)
239 {
240 scl_out(dd, 0);
241 sda_out(dd, 0);
242 scl_out(dd, 1);
243 sda_out(dd, 1);
244 }
245
246 /**
247 * stop_cmd - transmit the stop condition
248 * @dd: the qlogic_ib device
249 *
250 * (both clock/data low, clock high, data high while clock is high)
251 */
252 static void stop_cmd(struct qib_devdata *dd)
253 {
254 stop_seq(dd);
255 udelay(TWSI_BUF_WAIT_USEC);
256 }
257
258 /**
259 * qib_twsi_reset - reset I2C communication
260 * @dd: the qlogic_ib device
261 */
262
263 int qib_twsi_reset(struct qib_devdata *dd)
264 {
265 int clock_cycles_left = 9;
266 int was_high = 0;
267 u32 pins, mask;
268
269 /* Both SCL and SDA should be high. If not, there
270 * is something wrong.
271 */
272 mask = (1UL << dd->gpio_scl_num) | (1UL << dd->gpio_sda_num);
273
274 /*
275 * Force pins to desired innocuous state.
276 * This is the default power-on state with out=0 and dir=0,
277 * So tri-stated and should be floating high (barring HW problems)
278 */
279 dd->f_gpio_mod(dd, 0, 0, mask);
280
281 /*
282 * Clock nine times to get all listeners into a sane state.
283 * If SDA does not go high at any point, we are wedged.
284 * One vendor recommends then issuing START followed by STOP.
285 * we cannot use our "normal" functions to do that, because
286 * if SCL drops between them, another vendor's part will
287 * wedge, dropping SDA and keeping it low forever, at the end of
288 * the next transaction (even if it was not the device addressed).
289 * So our START and STOP take place with SCL held high.
290 */
291 while (clock_cycles_left--) {
292 scl_out(dd, 0);
293 scl_out(dd, 1);
294 /* Note if SDA is high, but keep clocking to sync slave */
295 was_high |= sda_in(dd, 0);
296 }
297
298 if (was_high) {
299 /*
300 * We saw a high, which we hope means the slave is sync'd.
301 * Issue START, STOP, pause for T_BUF.
302 */
303
304 pins = dd->f_gpio_mod(dd, 0, 0, 0);
305 if ((pins & mask) != mask)
306 qib_dev_err(dd, "GPIO pins not at rest: %d\n",
307 pins & mask);
308 /* Drop SDA to issue START */
309 udelay(1); /* Guarantee .6 uSec setup */
310 sda_out(dd, 0);
311 udelay(1); /* Guarantee .6 uSec hold */
312 /* At this point, SCL is high, SDA low. Raise SDA for STOP */
313 sda_out(dd, 1);
314 udelay(TWSI_BUF_WAIT_USEC);
315 }
316
317 return !was_high;
318 }
319
320 #define QIB_TWSI_START 0x100
321 #define QIB_TWSI_STOP 0x200
322
323 /* Write byte to TWSI, optionally prefixed with START or suffixed with
324 * STOP.
325 * returns 0 if OK (ACK received), else != 0
326 */
327 static int qib_twsi_wr(struct qib_devdata *dd, int data, int flags)
328 {
329 int ret = 1;
330
331 if (flags & QIB_TWSI_START)
332 start_seq(dd);
333
334 ret = wr_byte(dd, data); /* Leaves SCL low (from i2c_ackrcv()) */
335
336 if (flags & QIB_TWSI_STOP)
337 stop_cmd(dd);
338 return ret;
339 }
340
341 /* Added functionality for IBA7220-based cards */
342 #define QIB_TEMP_DEV 0x98
343
344 /*
345 * qib_twsi_blk_rd
346 * Formerly called qib_eeprom_internal_read, and only used for eeprom,
347 * but now the general interface for data transfer from twsi devices.
348 * One vestige of its former role is that it recognizes a device
349 * QIB_TWSI_NO_DEV and does the correct operation for the legacy part,
350 * which responded to all TWSI device codes, interpreting them as
351 * address within device. On all other devices found on board handled by
352 * this driver, the device is followed by a one-byte "address" which selects
353 * the "register" or "offset" within the device from which data should
354 * be read.
355 */
356 int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr,
357 void *buffer, int len)
358 {
359 int ret;
360 u8 *bp = buffer;
361
362 ret = 1;
363
364 if (dev == QIB_TWSI_NO_DEV) {
365 /* legacy not-really-I2C */
366 addr = (addr << 1) | READ_CMD;
367 ret = qib_twsi_wr(dd, addr, QIB_TWSI_START);
368 } else {
369 /* Actual I2C */
370 ret = qib_twsi_wr(dd, dev | WRITE_CMD, QIB_TWSI_START);
371 if (ret) {
372 stop_cmd(dd);
373 ret = 1;
374 goto bail;
375 }
376 /*
377 * SFF spec claims we do _not_ stop after the addr
378 * but simply issue a start with the "read" dev-addr.
379 * Since we are implicitely waiting for ACK here,
380 * we need t_buf (nominally 20uSec) before that start,
381 * and cannot rely on the delay built in to the STOP
382 */
383 ret = qib_twsi_wr(dd, addr, 0);
384 udelay(TWSI_BUF_WAIT_USEC);
385
386 if (ret) {
387 qib_dev_err(dd,
388 "Failed to write interface read addr %02X\n",
389 addr);
390 ret = 1;
391 goto bail;
392 }
393 ret = qib_twsi_wr(dd, dev | READ_CMD, QIB_TWSI_START);
394 }
395 if (ret) {
396 stop_cmd(dd);
397 ret = 1;
398 goto bail;
399 }
400
401 /*
402 * block devices keeps clocking data out as long as we ack,
403 * automatically incrementing the address. Some have "pages"
404 * whose boundaries will not be crossed, but the handling
405 * of these is left to the caller, who is in a better
406 * position to know.
407 */
408 while (len-- > 0) {
409 /*
410 * Get and store data, sending ACK if length remaining,
411 * else STOP
412 */
413 *bp++ = rd_byte(dd, !len);
414 }
415
416 ret = 0;
417
418 bail:
419 return ret;
420 }
421
422 /*
423 * qib_twsi_blk_wr
424 * Formerly called qib_eeprom_internal_write, and only used for eeprom,
425 * but now the general interface for data transfer to twsi devices.
426 * One vestige of its former role is that it recognizes a device
427 * QIB_TWSI_NO_DEV and does the correct operation for the legacy part,
428 * which responded to all TWSI device codes, interpreting them as
429 * address within device. On all other devices found on board handled by
430 * this driver, the device is followed by a one-byte "address" which selects
431 * the "register" or "offset" within the device to which data should
432 * be written.
433 */
434 int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
435 const void *buffer, int len)
436 {
437 int sub_len;
438 const u8 *bp = buffer;
439 int max_wait_time, i;
440 int ret = 1;
441
442 while (len > 0) {
443 if (dev == QIB_TWSI_NO_DEV) {
444 if (qib_twsi_wr(dd, (addr << 1) | WRITE_CMD,
445 QIB_TWSI_START)) {
446 goto failed_write;
447 }
448 } else {
449 /* Real I2C */
450 if (qib_twsi_wr(dd, dev | WRITE_CMD, QIB_TWSI_START))
451 goto failed_write;
452 ret = qib_twsi_wr(dd, addr, 0);
453 if (ret) {
454 qib_dev_err(dd,
455 "Failed to write interface write addr %02X\n",
456 addr);
457 goto failed_write;
458 }
459 }
460
461 sub_len = min(len, 4);
462 addr += sub_len;
463 len -= sub_len;
464
465 for (i = 0; i < sub_len; i++)
466 if (qib_twsi_wr(dd, *bp++, 0))
467 goto failed_write;
468
469 stop_cmd(dd);
470
471 /*
472 * Wait for write complete by waiting for a successful
473 * read (the chip replies with a zero after the write
474 * cmd completes, and before it writes to the eeprom.
475 * The startcmd for the read will fail the ack until
476 * the writes have completed. We do this inline to avoid
477 * the debug prints that are in the real read routine
478 * if the startcmd fails.
479 * We also use the proper device address, so it doesn't matter
480 * whether we have real eeprom_dev. Legacy likes any address.
481 */
482 max_wait_time = 100;
483 while (qib_twsi_wr(dd, dev | READ_CMD, QIB_TWSI_START)) {
484 stop_cmd(dd);
485 if (!--max_wait_time)
486 goto failed_write;
487 }
488 /* now read (and ignore) the resulting byte */
489 rd_byte(dd, 1);
490 }
491
492 ret = 0;
493 goto bail;
494
495 failed_write:
496 stop_cmd(dd);
497 ret = 1;
498
499 bail:
500 return ret;
501 }