drivers/infiniband/hw/qib/qib

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This source file includes following definitions.
qib_read_ureg32
qib_write_ureg
qib_read_kreg32
qib_read_kreg64
qib_write_kreg
qib_write_kreg_ctxt
write_6120_creg
read_6120_creg
read_6120_creg32
qib_6120_txe_recover
qib_6120_set_intr_state
qib_6120_clear_freeze
qib_handle_6120_hwerrors
qib_decode_6120_err
qib_disarm_6120_senderrbufs
chk_6120_linkrecovery
handle_6120_errors
qib_6120_init_hwerrors
qib_set_6120_armlaunch
qib_set_ib_6120_lstate
qib_6120_bringup_serdes
qib_6120_quiet_serdes
qib_6120_setup_setextled
qib_6120_setup_cleanup
qib_wantpiobuf_6120_intr
unlikely_6120_intr
qib_6120intr
qib_setup_6120_interrupt
pe_boardname
qib_6120_setup_reset
qib_6120_put_tid
qib_6120_put_tid_2
qib_6120_clear_tids
qib_6120_tidtemplate
qib_unordered_wc
qib_6120_get_base_info
qib_6120_get_msgheader
qib_6120_config_ctxts
qib_update_6120_usrhead
qib_6120_hdrqempty
alloc_dummy_hdrq
rcvctrl_6120_mod
sendctrl_6120_mod
qib_portcntr_6120
init_6120_cntrnames
qib_read_6120cntrs
qib_read_6120portcntrs
qib_chk_6120_errormask
qib_get_6120_faststats
qib_6120_nointr_fallback
qib_6120_xgxs_reset
qib_6120_get_ib_cfg
qib_6120_set_ib_cfg
qib_6120_set_loopback
pma_6120_timer
qib_set_cntr_6120_sample
qib_6120_iblink_state
qib_6120_phys_portstate
qib_6120_ib_updown
gpio_6120_mod
get_6120_chip_params
set_6120_baseaddrs
qib_late_6120_initreg
init_6120_variables
get_6120_link_buf
qib_6120_getsendbuf
init_sdma_6120_regs
qib_sdma_6120_gethead
qib_sdma_6120_busy
qib_sdma_update_6120_tail
qib_6120_sdma_sendctrl
qib_sdma_set_6120_desc_cnt
qib_6120_setpbc_control
qib_6120_initvl15_bufs
qib_6120_init_ctxt
qib_6120_txchk_change
writescratch
qib_6120_tempsense_rd
qib_6120_notify_dca
qib_6120_eeprom_wen
qib_init_iba6120_funcs
   1 /*
   2  * Copyright (c) 2013 - 2017 Intel Corporation. All rights reserved.
   3  * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
   4  * All rights reserved.
   5  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35 /*
  36  * This file contains all of the code that is specific to the
  37  * QLogic_IB 6120 PCIe chip.
  38  */
  39 
  40 #include <linux/interrupt.h>
  41 #include <linux/pci.h>
  42 #include <linux/delay.h>
  43 #include <rdma/ib_verbs.h>
  44 
  45 #include "qib.h"
  46 #include "qib_6120_regs.h"
  47 
  48 static void qib_6120_setup_setextled(struct qib_pportdata *, u32);
  49 static void sendctrl_6120_mod(struct qib_pportdata *ppd, u32 op);
  50 static u8 qib_6120_phys_portstate(u64);
  51 static u32 qib_6120_iblink_state(u64);
  52 
  53 /*
  54  * This file contains all the chip-specific register information and
  55  * access functions for the Intel Intel_IB PCI-Express chip.
  56  *
  57  */
  58 
  59 /* KREG_IDX uses machine-generated #defines */
  60 #define KREG_IDX(regname) (QIB_6120_##regname##_OFFS / sizeof(u64))
  61 
  62 /* Use defines to tie machine-generated names to lower-case names */
  63 #define kr_extctrl KREG_IDX(EXTCtrl)
  64 #define kr_extstatus KREG_IDX(EXTStatus)
  65 #define kr_gpio_clear KREG_IDX(GPIOClear)
  66 #define kr_gpio_mask KREG_IDX(GPIOMask)
  67 #define kr_gpio_out KREG_IDX(GPIOOut)
  68 #define kr_gpio_status KREG_IDX(GPIOStatus)
  69 #define kr_rcvctrl KREG_IDX(RcvCtrl)
  70 #define kr_sendctrl KREG_IDX(SendCtrl)
  71 #define kr_partitionkey KREG_IDX(RcvPartitionKey)
  72 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
  73 #define kr_ibcstatus KREG_IDX(IBCStatus)
  74 #define kr_ibcctrl KREG_IDX(IBCCtrl)
  75 #define kr_sendbuffererror KREG_IDX(SendBufErr0)
  76 #define kr_rcvbthqp KREG_IDX(RcvBTHQP)
  77 #define kr_counterregbase KREG_IDX(CntrRegBase)
  78 #define kr_palign KREG_IDX(PageAlign)
  79 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
  80 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
  81 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
  82 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
  83 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
  84 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
  85 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
  86 #define kr_scratch KREG_IDX(Scratch)
  87 #define kr_sendctrl KREG_IDX(SendCtrl)
  88 #define kr_sendpioavailaddr KREG_IDX(SendPIOAvailAddr)
  89 #define kr_sendpiobufbase KREG_IDX(SendPIOBufBase)
  90 #define kr_sendpiobufcnt KREG_IDX(SendPIOBufCnt)
  91 #define kr_sendpiosize KREG_IDX(SendPIOSize)
  92 #define kr_sendregbase KREG_IDX(SendRegBase)
  93 #define kr_userregbase KREG_IDX(UserRegBase)
  94 #define kr_control KREG_IDX(Control)
  95 #define kr_intclear KREG_IDX(IntClear)
  96 #define kr_intmask KREG_IDX(IntMask)
  97 #define kr_intstatus KREG_IDX(IntStatus)
  98 #define kr_errclear KREG_IDX(ErrClear)
  99 #define kr_errmask KREG_IDX(ErrMask)
 100 #define kr_errstatus KREG_IDX(ErrStatus)
 101 #define kr_hwerrclear KREG_IDX(HwErrClear)
 102 #define kr_hwerrmask KREG_IDX(HwErrMask)
 103 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
 104 #define kr_revision KREG_IDX(Revision)
 105 #define kr_portcnt KREG_IDX(PortCnt)
 106 #define kr_serdes_cfg0 KREG_IDX(SerdesCfg0)
 107 #define kr_serdes_cfg1 (kr_serdes_cfg0 + 1)
 108 #define kr_serdes_stat KREG_IDX(SerdesStat)
 109 #define kr_xgxs_cfg KREG_IDX(XGXSCfg)
 110 
 111 /* These must only be written via qib_write_kreg_ctxt() */
 112 #define kr_rcvhdraddr KREG_IDX(RcvHdrAddr0)
 113 #define kr_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
 114 
 115 #define CREG_IDX(regname) ((QIB_6120_##regname##_OFFS - \
 116                         QIB_6120_LBIntCnt_OFFS) / sizeof(u64))
 117 
 118 #define cr_badformat CREG_IDX(RxBadFormatCnt)
 119 #define cr_erricrc CREG_IDX(RxICRCErrCnt)
 120 #define cr_errlink CREG_IDX(RxLinkProblemCnt)
 121 #define cr_errlpcrc CREG_IDX(RxLPCRCErrCnt)
 122 #define cr_errpkey CREG_IDX(RxPKeyMismatchCnt)
 123 #define cr_rcvflowctrl_err CREG_IDX(RxFlowCtrlErrCnt)
 124 #define cr_err_rlen CREG_IDX(RxLenErrCnt)
 125 #define cr_errslen CREG_IDX(TxLenErrCnt)
 126 #define cr_errtidfull CREG_IDX(RxTIDFullErrCnt)
 127 #define cr_errtidvalid CREG_IDX(RxTIDValidErrCnt)
 128 #define cr_errvcrc CREG_IDX(RxVCRCErrCnt)
 129 #define cr_ibstatuschange CREG_IDX(IBStatusChangeCnt)
 130 #define cr_lbint CREG_IDX(LBIntCnt)
 131 #define cr_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
 132 #define cr_invalidslen CREG_IDX(TxMaxMinLenErrCnt)
 133 #define cr_lbflowstall CREG_IDX(LBFlowStallCnt)
 134 #define cr_pktrcv CREG_IDX(RxDataPktCnt)
 135 #define cr_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
 136 #define cr_pktsend CREG_IDX(TxDataPktCnt)
 137 #define cr_pktsendflow CREG_IDX(TxFlowPktCnt)
 138 #define cr_portovfl CREG_IDX(RxP0HdrEgrOvflCnt)
 139 #define cr_rcvebp CREG_IDX(RxEBPCnt)
 140 #define cr_rcvovfl CREG_IDX(RxBufOvflCnt)
 141 #define cr_senddropped CREG_IDX(TxDroppedPktCnt)
 142 #define cr_sendstall CREG_IDX(TxFlowStallCnt)
 143 #define cr_sendunderrun CREG_IDX(TxUnderrunCnt)
 144 #define cr_wordrcv CREG_IDX(RxDwordCnt)
 145 #define cr_wordsend CREG_IDX(TxDwordCnt)
 146 #define cr_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
 147 #define cr_rxdroppkt CREG_IDX(RxDroppedPktCnt)
 148 #define cr_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
 149 #define cr_iblinkdown CREG_IDX(IBLinkDownedCnt)
 150 #define cr_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
 151 
 152 #define SYM_RMASK(regname, fldname) ((u64)              \
 153         QIB_6120_##regname##_##fldname##_RMASK)
 154 #define SYM_MASK(regname, fldname) ((u64)               \
 155         QIB_6120_##regname##_##fldname##_RMASK <<       \
 156          QIB_6120_##regname##_##fldname##_LSB)
 157 #define SYM_LSB(regname, fldname) (QIB_6120_##regname##_##fldname##_LSB)
 158 
 159 #define SYM_FIELD(value, regname, fldname) ((u64) \
 160         (((value) >> SYM_LSB(regname, fldname)) & \
 161          SYM_RMASK(regname, fldname)))
 162 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
 163 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
 164 
 165 /* link training states, from IBC */
 166 #define IB_6120_LT_STATE_DISABLED        0x00
 167 #define IB_6120_LT_STATE_LINKUP          0x01
 168 #define IB_6120_LT_STATE_POLLACTIVE      0x02
 169 #define IB_6120_LT_STATE_POLLQUIET       0x03
 170 #define IB_6120_LT_STATE_SLEEPDELAY      0x04
 171 #define IB_6120_LT_STATE_SLEEPQUIET      0x05
 172 #define IB_6120_LT_STATE_CFGDEBOUNCE     0x08
 173 #define IB_6120_LT_STATE_CFGRCVFCFG      0x09
 174 #define IB_6120_LT_STATE_CFGWAITRMT      0x0a
 175 #define IB_6120_LT_STATE_CFGIDLE 0x0b
 176 #define IB_6120_LT_STATE_RECOVERRETRAIN  0x0c
 177 #define IB_6120_LT_STATE_RECOVERWAITRMT  0x0e
 178 #define IB_6120_LT_STATE_RECOVERIDLE     0x0f
 179 
 180 /* link state machine states from IBC */
 181 #define IB_6120_L_STATE_DOWN             0x0
 182 #define IB_6120_L_STATE_INIT             0x1
 183 #define IB_6120_L_STATE_ARM              0x2
 184 #define IB_6120_L_STATE_ACTIVE           0x3
 185 #define IB_6120_L_STATE_ACT_DEFER        0x4
 186 
 187 static const u8 qib_6120_physportstate[0x20] = {
 188         [IB_6120_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
 189         [IB_6120_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
 190         [IB_6120_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
 191         [IB_6120_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
 192         [IB_6120_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
 193         [IB_6120_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
 194         [IB_6120_LT_STATE_CFGDEBOUNCE] =
 195                 IB_PHYSPORTSTATE_CFG_TRAIN,
 196         [IB_6120_LT_STATE_CFGRCVFCFG] =
 197                 IB_PHYSPORTSTATE_CFG_TRAIN,
 198         [IB_6120_LT_STATE_CFGWAITRMT] =
 199                 IB_PHYSPORTSTATE_CFG_TRAIN,
 200         [IB_6120_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_TRAIN,
 201         [IB_6120_LT_STATE_RECOVERRETRAIN] =
 202                 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
 203         [IB_6120_LT_STATE_RECOVERWAITRMT] =
 204                 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
 205         [IB_6120_LT_STATE_RECOVERIDLE] =
 206                 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
 207         [0x10] = IB_PHYSPORTSTATE_CFG_TRAIN,
 208         [0x11] = IB_PHYSPORTSTATE_CFG_TRAIN,
 209         [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN,
 210         [0x13] = IB_PHYSPORTSTATE_CFG_TRAIN,
 211         [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
 212         [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
 213         [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
 214         [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
 215 };
 216 
 217 
 218 struct qib_chip_specific {
 219         u64 __iomem *cregbase;
 220         u64 *cntrs;
 221         u64 *portcntrs;
 222         void *dummy_hdrq;   /* used after ctxt close */
 223         dma_addr_t dummy_hdrq_phys;
 224         spinlock_t kernel_tid_lock; /* no back to back kernel TID writes */
 225         spinlock_t user_tid_lock; /* no back to back user TID writes */
 226         spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
 227         spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
 228         u64 hwerrmask;
 229         u64 errormask;
 230         u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
 231         u64 gpio_mask; /* shadow the gpio mask register */
 232         u64 extctrl; /* shadow the gpio output enable, etc... */
 233         /*
 234          * these 5 fields are used to establish deltas for IB symbol
 235          * errors and linkrecovery errors.  They can be reported on
 236          * some chips during link negotiation prior to INIT, and with
 237          * DDR when faking DDR negotiations with non-IBTA switches.
 238          * The chip counters are adjusted at driver unload if there is
 239          * a non-zero delta.
 240          */
 241         u64 ibdeltainprog;
 242         u64 ibsymdelta;
 243         u64 ibsymsnap;
 244         u64 iblnkerrdelta;
 245         u64 iblnkerrsnap;
 246         u64 ibcctrl; /* shadow for kr_ibcctrl */
 247         u32 lastlinkrecov; /* link recovery issue */
 248         u32 cntrnamelen;
 249         u32 portcntrnamelen;
 250         u32 ncntrs;
 251         u32 nportcntrs;
 252         /* used with gpio interrupts to implement IB counters */
 253         u32 rxfc_unsupvl_errs;
 254         u32 overrun_thresh_errs;
 255         /*
 256          * these count only cases where _successive_ LocalLinkIntegrity
 257          * errors were seen in the receive headers of IB standard packets
 258          */
 259         u32 lli_errs;
 260         u32 lli_counter;
 261         u64 lli_thresh;
 262         u64 sword; /* total dwords sent (sample result) */
 263         u64 rword; /* total dwords received (sample result) */
 264         u64 spkts; /* total packets sent (sample result) */
 265         u64 rpkts; /* total packets received (sample result) */
 266         u64 xmit_wait; /* # of ticks no data sent (sample result) */
 267         struct timer_list pma_timer;
 268         struct qib_pportdata *ppd;
 269         char emsgbuf[128];
 270         char bitsmsgbuf[64];
 271         u8 pma_sample_status;
 272 };
 273 
 274 /* ibcctrl bits */
 275 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
 276 /* cycle through TS1/TS2 till OK */
 277 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
 278 /* wait for TS1, then go on */
 279 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
 280 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
 281 
 282 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1           /* move to 0x11 */
 283 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2          /* move to 0x21 */
 284 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
 285 #define QLOGIC_IB_IBCC_LINKCMD_SHIFT 18
 286 
 287 /*
 288  * We could have a single register get/put routine, that takes a group type,
 289  * but this is somewhat clearer and cleaner.  It also gives us some error
 290  * checking.  64 bit register reads should always work, but are inefficient
 291  * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
 292  * so we use kreg32 wherever possible.  User register and counter register
 293  * reads are always 32 bit reads, so only one form of those routines.
 294  */
 295 
 296 /**
 297  * qib_read_ureg32 - read 32-bit virtualized per-context register
 298  * @dd: device
 299  * @regno: register number
 300  * @ctxt: context number
 301  *
 302  * Return the contents of a register that is virtualized to be per context.
 303  * Returns -1 on errors (not distinguishable from valid contents at
 304  * runtime; we may add a separate error variable at some point).
 305  */
 306 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
 307                                   enum qib_ureg regno, int ctxt)
 308 {
 309         if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
 310                 return 0;
 311 
 312         if (dd->userbase)
 313                 return readl(regno + (u64 __iomem *)
 314                              ((char __iomem *)dd->userbase +
 315                               dd->ureg_align * ctxt));
 316         else
 317                 return readl(regno + (u64 __iomem *)
 318                              (dd->uregbase +
 319                               (char __iomem *)dd->kregbase +
 320                               dd->ureg_align * ctxt));
 321 }
 322 
 323 /**
 324  * qib_write_ureg - write 32-bit virtualized per-context register
 325  * @dd: device
 326  * @regno: register number
 327  * @value: value
 328  * @ctxt: context
 329  *
 330  * Write the contents of a register that is virtualized to be per context.
 331  */
 332 static inline void qib_write_ureg(const struct qib_devdata *dd,
 333                                   enum qib_ureg regno, u64 value, int ctxt)
 334 {
 335         u64 __iomem *ubase;
 336 
 337         if (dd->userbase)
 338                 ubase = (u64 __iomem *)
 339                         ((char __iomem *) dd->userbase +
 340                          dd->ureg_align * ctxt);
 341         else
 342                 ubase = (u64 __iomem *)
 343                         (dd->uregbase +
 344                          (char __iomem *) dd->kregbase +
 345                          dd->ureg_align * ctxt);
 346 
 347         if (dd->kregbase && (dd->flags & QIB_PRESENT))
 348                 writeq(value, &ubase[regno]);
 349 }
 350 
 351 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
 352                                   const u16 regno)
 353 {
 354         if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
 355                 return -1;
 356         return readl((u32 __iomem *)&dd->kregbase[regno]);
 357 }
 358 
 359 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
 360                                   const u16 regno)
 361 {
 362         if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
 363                 return -1;
 364 
 365         return readq(&dd->kregbase[regno]);
 366 }
 367 
 368 static inline void qib_write_kreg(const struct qib_devdata *dd,
 369                                   const u16 regno, u64 value)
 370 {
 371         if (dd->kregbase && (dd->flags & QIB_PRESENT))
 372                 writeq(value, &dd->kregbase[regno]);
 373 }
 374 
 375 /**
 376  * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
 377  * @dd: the qlogic_ib device
 378  * @regno: the register number to write
 379  * @ctxt: the context containing the register
 380  * @value: the value to write
 381  */
 382 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
 383                                        const u16 regno, unsigned ctxt,
 384                                        u64 value)
 385 {
 386         qib_write_kreg(dd, regno + ctxt, value);
 387 }
 388 
 389 static inline void write_6120_creg(const struct qib_devdata *dd,
 390                                    u16 regno, u64 value)
 391 {
 392         if (dd->cspec->cregbase && (dd->flags & QIB_PRESENT))
 393                 writeq(value, &dd->cspec->cregbase[regno]);
 394 }
 395 
 396 static inline u64 read_6120_creg(const struct qib_devdata *dd, u16 regno)
 397 {
 398         if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
 399                 return 0;
 400         return readq(&dd->cspec->cregbase[regno]);
 401 }
 402 
 403 static inline u32 read_6120_creg32(const struct qib_devdata *dd, u16 regno)
 404 {
 405         if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
 406                 return 0;
 407         return readl(&dd->cspec->cregbase[regno]);
 408 }
 409 
 410 /* kr_control bits */
 411 #define QLOGIC_IB_C_RESET 1U
 412 
 413 /* kr_intstatus, kr_intclear, kr_intmask bits */
 414 #define QLOGIC_IB_I_RCVURG_MASK ((1U << 5) - 1)
 415 #define QLOGIC_IB_I_RCVURG_SHIFT 0
 416 #define QLOGIC_IB_I_RCVAVAIL_MASK ((1U << 5) - 1)
 417 #define QLOGIC_IB_I_RCVAVAIL_SHIFT 12
 418 
 419 #define QLOGIC_IB_C_FREEZEMODE 0x00000002
 420 #define QLOGIC_IB_C_LINKENABLE 0x00000004
 421 #define QLOGIC_IB_I_ERROR               0x0000000080000000ULL
 422 #define QLOGIC_IB_I_SPIOSENT            0x0000000040000000ULL
 423 #define QLOGIC_IB_I_SPIOBUFAVAIL        0x0000000020000000ULL
 424 #define QLOGIC_IB_I_GPIO                0x0000000010000000ULL
 425 #define QLOGIC_IB_I_BITSEXTANT \
 426                 ((QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT) | \
 427                 (QLOGIC_IB_I_RCVAVAIL_MASK << \
 428                  QLOGIC_IB_I_RCVAVAIL_SHIFT) | \
 429                 QLOGIC_IB_I_ERROR | QLOGIC_IB_I_SPIOSENT | \
 430                 QLOGIC_IB_I_SPIOBUFAVAIL | QLOGIC_IB_I_GPIO)
 431 
 432 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 433 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK  0x000000000000003fULL
 434 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT 0
 435 #define QLOGIC_IB_HWE_PCIEPOISONEDTLP      0x0000000010000000ULL
 436 #define QLOGIC_IB_HWE_PCIECPLTIMEOUT       0x0000000020000000ULL
 437 #define QLOGIC_IB_HWE_PCIEBUSPARITYXTLH    0x0000000040000000ULL
 438 #define QLOGIC_IB_HWE_PCIEBUSPARITYXADM    0x0000000080000000ULL
 439 #define QLOGIC_IB_HWE_PCIEBUSPARITYRADM    0x0000000100000000ULL
 440 #define QLOGIC_IB_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 441 #define QLOGIC_IB_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 442 #define QLOGIC_IB_HWE_PCIE1PLLFAILED       0x0400000000000000ULL
 443 #define QLOGIC_IB_HWE_PCIE0PLLFAILED       0x0800000000000000ULL
 444 #define QLOGIC_IB_HWE_SERDESPLLFAILED      0x1000000000000000ULL
 445 
 446 
 447 /* kr_extstatus bits */
 448 #define QLOGIC_IB_EXTS_FREQSEL 0x2
 449 #define QLOGIC_IB_EXTS_SERDESSEL 0x4
 450 #define QLOGIC_IB_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 451 #define QLOGIC_IB_EXTS_MEMBIST_FOUND       0x0000000000008000
 452 
 453 /* kr_xgxsconfig bits */
 454 #define QLOGIC_IB_XGXS_RESET          0x5ULL
 455 
 456 #define _QIB_GPIO_SDA_NUM 1
 457 #define _QIB_GPIO_SCL_NUM 0
 458 
 459 /* Bits in GPIO for the added IB link interrupts */
 460 #define GPIO_RXUVL_BIT 3
 461 #define GPIO_OVRUN_BIT 4
 462 #define GPIO_LLI_BIT 5
 463 #define GPIO_ERRINTR_MASK 0x38
 464 
 465 
 466 #define QLOGIC_IB_RT_BUFSIZE_MASK 0xe0000000ULL
 467 #define QLOGIC_IB_RT_BUFSIZE_SHIFTVAL(tid) \
 468         ((((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) >> 29) + 11 - 1)
 469 #define QLOGIC_IB_RT_BUFSIZE(tid) (1 << QLOGIC_IB_RT_BUFSIZE_SHIFTVAL(tid))
 470 #define QLOGIC_IB_RT_IS_VALID(tid) \
 471         (((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) && \
 472          ((((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) != QLOGIC_IB_RT_BUFSIZE_MASK)))
 473 #define QLOGIC_IB_RT_ADDR_MASK 0x1FFFFFFFULL /* 29 bits valid */
 474 #define QLOGIC_IB_RT_ADDR_SHIFT 10
 475 
 476 #define QLOGIC_IB_R_INTRAVAIL_SHIFT 16
 477 #define QLOGIC_IB_R_TAILUPD_SHIFT 31
 478 #define IBA6120_R_PKEY_DIS_SHIFT 30
 479 
 480 #define PBC_6120_VL15_SEND_CTRL (1ULL << 31) /* pbc; VL15; link_buf only */
 481 
 482 #define IBCBUSFRSPCPARITYERR HWE_MASK(IBCBusFromSPCParityErr)
 483 #define IBCBUSTOSPCPARITYERR HWE_MASK(IBCBusToSPCParityErr)
 484 
 485 #define SYM_MASK_BIT(regname, fldname, bit) ((u64) \
 486         ((1ULL << (SYM_LSB(regname, fldname) + (bit)))))
 487 
 488 #define TXEMEMPARITYERR_PIOBUF \
 489         SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 0)
 490 #define TXEMEMPARITYERR_PIOPBC \
 491         SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 1)
 492 #define TXEMEMPARITYERR_PIOLAUNCHFIFO \
 493         SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 2)
 494 
 495 #define RXEMEMPARITYERR_RCVBUF \
 496         SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 0)
 497 #define RXEMEMPARITYERR_LOOKUPQ \
 498         SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 1)
 499 #define RXEMEMPARITYERR_EXPTID \
 500         SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 2)
 501 #define RXEMEMPARITYERR_EAGERTID \
 502         SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 3)
 503 #define RXEMEMPARITYERR_FLAGBUF \
 504         SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 4)
 505 #define RXEMEMPARITYERR_DATAINFO \
 506         SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 5)
 507 #define RXEMEMPARITYERR_HDRINFO \
 508         SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 6)
 509 
 510 /* 6120 specific hardware errors... */
 511 static const struct qib_hwerror_msgs qib_6120_hwerror_msgs[] = {
 512         /* generic hardware errors */
 513         QLOGIC_IB_HWE_MSG(IBCBUSFRSPCPARITYERR, "QIB2IB Parity"),
 514         QLOGIC_IB_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2QIB Parity"),
 515 
 516         QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOBUF,
 517                           "TXE PIOBUF Memory Parity"),
 518         QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOPBC,
 519                           "TXE PIOPBC Memory Parity"),
 520         QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOLAUNCHFIFO,
 521                           "TXE PIOLAUNCHFIFO Memory Parity"),
 522 
 523         QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_RCVBUF,
 524                           "RXE RCVBUF Memory Parity"),
 525         QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_LOOKUPQ,
 526                           "RXE LOOKUPQ Memory Parity"),
 527         QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EAGERTID,
 528                           "RXE EAGERTID Memory Parity"),
 529         QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EXPTID,
 530                           "RXE EXPTID Memory Parity"),
 531         QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_FLAGBUF,
 532                           "RXE FLAGBUF Memory Parity"),
 533         QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_DATAINFO,
 534                           "RXE DATAINFO Memory Parity"),
 535         QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_HDRINFO,
 536                           "RXE HDRINFO Memory Parity"),
 537 
 538         /* chip-specific hardware errors */
 539         QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEPOISONEDTLP,
 540                           "PCIe Poisoned TLP"),
 541         QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLTIMEOUT,
 542                           "PCIe completion timeout"),
 543         /*
 544          * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
 545          * parity or memory parity error failures, because most likely we
 546          * won't be able to talk to the core of the chip.  Nonetheless, we
 547          * might see them, if they are in parts of the PCIe core that aren't
 548          * essential.
 549          */
 550         QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE1PLLFAILED,
 551                           "PCIePLL1"),
 552         QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE0PLLFAILED,
 553                           "PCIePLL0"),
 554         QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXTLH,
 555                           "PCIe XTLH core parity"),
 556         QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXADM,
 557                           "PCIe ADM TX core parity"),
 558         QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYRADM,
 559                           "PCIe ADM RX core parity"),
 560         QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SERDESPLLFAILED,
 561                           "SerDes PLL"),
 562 };
 563 
 564 #define TXE_PIO_PARITY (TXEMEMPARITYERR_PIOBUF | TXEMEMPARITYERR_PIOPBC)
 565 #define _QIB_PLL_FAIL (QLOGIC_IB_HWE_COREPLL_FBSLIP |   \
 566                 QLOGIC_IB_HWE_COREPLL_RFSLIP)
 567 
 568         /* variables for sanity checking interrupt and errors */
 569 #define IB_HWE_BITSEXTANT \
 570         (HWE_MASK(RXEMemParityErr) |                                    \
 571          HWE_MASK(TXEMemParityErr) |                                    \
 572          (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK <<                        \
 573           QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) |                       \
 574          QLOGIC_IB_HWE_PCIE1PLLFAILED |                                 \
 575          QLOGIC_IB_HWE_PCIE0PLLFAILED |                                 \
 576          QLOGIC_IB_HWE_PCIEPOISONEDTLP |                                \
 577          QLOGIC_IB_HWE_PCIECPLTIMEOUT |                                 \
 578          QLOGIC_IB_HWE_PCIEBUSPARITYXTLH |                              \
 579          QLOGIC_IB_HWE_PCIEBUSPARITYXADM |                              \
 580          QLOGIC_IB_HWE_PCIEBUSPARITYRADM |                              \
 581          HWE_MASK(PowerOnBISTFailed) |                                  \
 582          QLOGIC_IB_HWE_COREPLL_FBSLIP |                                 \
 583          QLOGIC_IB_HWE_COREPLL_RFSLIP |                                 \
 584          QLOGIC_IB_HWE_SERDESPLLFAILED |                                \
 585          HWE_MASK(IBCBusToSPCParityErr) |                               \
 586          HWE_MASK(IBCBusFromSPCParityErr))
 587 
 588 #define IB_E_BITSEXTANT \
 589         (ERR_MASK(RcvFormatErr) | ERR_MASK(RcvVCRCErr) |                \
 590          ERR_MASK(RcvICRCErr) | ERR_MASK(RcvMinPktLenErr) |             \
 591          ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvLongPktLenErr) |       \
 592          ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvUnexpectedCharErr) | \
 593          ERR_MASK(RcvUnsupportedVLErr) | ERR_MASK(RcvEBPErr) |          \
 594          ERR_MASK(RcvIBFlowErr) | ERR_MASK(RcvBadVersionErr) |          \
 595          ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) |            \
 596          ERR_MASK(RcvBadTidErr) | ERR_MASK(RcvHdrLenErr) |              \
 597          ERR_MASK(RcvHdrErr) | ERR_MASK(RcvIBLostLinkErr) |             \
 598          ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendMaxPktLenErr) |      \
 599          ERR_MASK(SendUnderRunErr) | ERR_MASK(SendPktLenErr) |          \
 600          ERR_MASK(SendDroppedSmpPktErr) |                               \
 601          ERR_MASK(SendDroppedDataPktErr) |                              \
 602          ERR_MASK(SendPioArmLaunchErr) |                                \
 603          ERR_MASK(SendUnexpectedPktNumErr) |                            \
 604          ERR_MASK(SendUnsupportedVLErr) | ERR_MASK(IBStatusChanged) |   \
 605          ERR_MASK(InvalidAddrErr) | ERR_MASK(ResetNegated) |            \
 606          ERR_MASK(HardwareErr))
 607 
 608 #define QLOGIC_IB_E_PKTERRS ( \
 609                 ERR_MASK(SendPktLenErr) |                               \
 610                 ERR_MASK(SendDroppedDataPktErr) |                       \
 611                 ERR_MASK(RcvVCRCErr) |                                  \
 612                 ERR_MASK(RcvICRCErr) |                                  \
 613                 ERR_MASK(RcvShortPktLenErr) |                           \
 614                 ERR_MASK(RcvEBPErr))
 615 
 616 /* These are all rcv-related errors which we want to count for stats */
 617 #define E_SUM_PKTERRS                                           \
 618         (ERR_MASK(RcvHdrLenErr) | ERR_MASK(RcvBadTidErr) |              \
 619          ERR_MASK(RcvBadVersionErr) | ERR_MASK(RcvHdrErr) |             \
 620          ERR_MASK(RcvLongPktLenErr) | ERR_MASK(RcvShortPktLenErr) |     \
 621          ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvMinPktLenErr) |        \
 622          ERR_MASK(RcvFormatErr) | ERR_MASK(RcvUnsupportedVLErr) |       \
 623          ERR_MASK(RcvUnexpectedCharErr) | ERR_MASK(RcvEBPErr))
 624 
 625 /* These are all send-related errors which we want to count for stats */
 626 #define E_SUM_ERRS                                                      \
 627         (ERR_MASK(SendPioArmLaunchErr) |                                \
 628          ERR_MASK(SendUnexpectedPktNumErr) |                            \
 629          ERR_MASK(SendDroppedDataPktErr) |                              \
 630          ERR_MASK(SendDroppedSmpPktErr) |                               \
 631          ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnsupportedVLErr) |  \
 632          ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) |         \
 633          ERR_MASK(InvalidAddrErr))
 634 
 635 /*
 636  * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore
 637  * errors not related to freeze and cancelling buffers.  Can't ignore
 638  * armlaunch because could get more while still cleaning up, and need
 639  * to cancel those as they happen.
 640  */
 641 #define E_SPKT_ERRS_IGNORE \
 642         (ERR_MASK(SendDroppedDataPktErr) |                              \
 643          ERR_MASK(SendDroppedSmpPktErr) |                               \
 644          ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendMinPktLenErr) |      \
 645          ERR_MASK(SendPktLenErr))
 646 
 647 /*
 648  * these are errors that can occur when the link changes state while
 649  * a packet is being sent or received.  This doesn't cover things
 650  * like EBP or VCRC that can be the result of a sending having the
 651  * link change state, so we receive a "known bad" packet.
 652  */
 653 #define E_SUM_LINK_PKTERRS              \
 654         (ERR_MASK(SendDroppedDataPktErr) |                              \
 655          ERR_MASK(SendDroppedSmpPktErr) |                               \
 656          ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) |         \
 657          ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvMinPktLenErr) |      \
 658          ERR_MASK(RcvUnexpectedCharErr))
 659 
 660 static void qib_6120_put_tid_2(struct qib_devdata *, u64 __iomem *,
 661                                u32, unsigned long);
 662 
 663 /*
 664  * On platforms using this chip, and not having ordered WC stores, we
 665  * can get TXE parity errors due to speculative reads to the PIO buffers,
 666  * and this, due to a chip issue can result in (many) false parity error
 667  * reports.  So it's a debug print on those, and an info print on systems
 668  * where the speculative reads don't occur.
 669  */
 670 static void qib_6120_txe_recover(struct qib_devdata *dd)
 671 {
 672         if (!qib_unordered_wc())
 673                 qib_devinfo(dd->pcidev,
 674                             "Recovering from TXE PIO parity error\n");
 675 }
 676 
 677 /* enable/disable chip from delivering interrupts */
 678 static void qib_6120_set_intr_state(struct qib_devdata *dd, u32 enable)
 679 {
 680         if (enable) {
 681                 if (dd->flags & QIB_BADINTR)
 682                         return;
 683                 qib_write_kreg(dd, kr_intmask, ~0ULL);
 684                 /* force re-interrupt of any pending interrupts. */
 685                 qib_write_kreg(dd, kr_intclear, 0ULL);
 686         } else
 687                 qib_write_kreg(dd, kr_intmask, 0ULL);
 688 }
 689 
 690 /*
 691  * Try to cleanup as much as possible for anything that might have gone
 692  * wrong while in freeze mode, such as pio buffers being written by user
 693  * processes (causing armlaunch), send errors due to going into freeze mode,
 694  * etc., and try to avoid causing extra interrupts while doing so.
 695  * Forcibly update the in-memory pioavail register copies after cleanup
 696  * because the chip won't do it while in freeze mode (the register values
 697  * themselves are kept correct).
 698  * Make sure that we don't lose any important interrupts by using the chip
 699  * feature that says that writing 0 to a bit in *clear that is set in
 700  * *status will cause an interrupt to be generated again (if allowed by
 701  * the *mask value).
 702  * This is in chip-specific code because of all of the register accesses,
 703  * even though the details are similar on most chips
 704  */
 705 static void qib_6120_clear_freeze(struct qib_devdata *dd)
 706 {
 707         /* disable error interrupts, to avoid confusion */
 708         qib_write_kreg(dd, kr_errmask, 0ULL);
 709 
 710         /* also disable interrupts; errormask is sometimes overwritten */
 711         qib_6120_set_intr_state(dd, 0);
 712 
 713         qib_cancel_sends(dd->pport);
 714 
 715         /* clear the freeze, and be sure chip saw it */
 716         qib_write_kreg(dd, kr_control, dd->control);
 717         qib_read_kreg32(dd, kr_scratch);
 718 
 719         /* force in-memory update now we are out of freeze */
 720         qib_force_pio_avail_update(dd);
 721 
 722         /*
 723          * force new interrupt if any hwerr, error or interrupt bits are
 724          * still set, and clear "safe" send packet errors related to freeze
 725          * and cancelling sends.  Re-enable error interrupts before possible
 726          * force of re-interrupt on pending interrupts.
 727          */
 728         qib_write_kreg(dd, kr_hwerrclear, 0ULL);
 729         qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
 730         qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
 731         qib_6120_set_intr_state(dd, 1);
 732 }
 733 
 734 /**
 735  * qib_handle_6120_hwerrors - display hardware errors.
 736  * @dd: the qlogic_ib device
 737  * @msg: the output buffer
 738  * @msgl: the size of the output buffer
 739  *
 740  * Use same msg buffer as regular errors to avoid excessive stack
 741  * use.  Most hardware errors are catastrophic, but for right now,
 742  * we'll print them and continue.  Reuse the same message buffer as
 743  * handle_6120_errors() to avoid excessive stack usage.
 744  */
 745 static void qib_handle_6120_hwerrors(struct qib_devdata *dd, char *msg,
 746                                      size_t msgl)
 747 {
 748         u64 hwerrs;
 749         u32 bits, ctrl;
 750         int isfatal = 0;
 751         char *bitsmsg;
 752 
 753         hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
 754         if (!hwerrs)
 755                 return;
 756         if (hwerrs == ~0ULL) {
 757                 qib_dev_err(dd,
 758                         "Read of hardware error status failed (all bits set); ignoring\n");
 759                 return;
 760         }
 761         qib_stats.sps_hwerrs++;
 762 
 763         /* Always clear the error status register, except MEMBISTFAIL,
 764          * regardless of whether we continue or stop using the chip.
 765          * We want that set so we know it failed, even across driver reload.
 766          * We'll still ignore it in the hwerrmask.  We do this partly for
 767          * diagnostics, but also for support */
 768         qib_write_kreg(dd, kr_hwerrclear,
 769                        hwerrs & ~HWE_MASK(PowerOnBISTFailed));
 770 
 771         hwerrs &= dd->cspec->hwerrmask;
 772 
 773         /*
 774          * Make sure we get this much out, unless told to be quiet,
 775          * or it's occurred within the last 5 seconds.
 776          */
 777         if (hwerrs & ~(TXE_PIO_PARITY | RXEMEMPARITYERR_EAGERTID))
 778                 qib_devinfo(dd->pcidev,
 779                         "Hardware error: hwerr=0x%llx (cleared)\n",
 780                         (unsigned long long) hwerrs);
 781 
 782         if (hwerrs & ~IB_HWE_BITSEXTANT)
 783                 qib_dev_err(dd,
 784                         "hwerror interrupt with unknown errors %llx set\n",
 785                         (unsigned long long)(hwerrs & ~IB_HWE_BITSEXTANT));
 786 
 787         ctrl = qib_read_kreg32(dd, kr_control);
 788         if ((ctrl & QLOGIC_IB_C_FREEZEMODE) && !dd->diag_client) {
 789                 /*
 790                  * Parity errors in send memory are recoverable,
 791                  * just cancel the send (if indicated in * sendbuffererror),
 792                  * count the occurrence, unfreeze (if no other handled
 793                  * hardware error bits are set), and continue. They can
 794                  * occur if a processor speculative read is done to the PIO
 795                  * buffer while we are sending a packet, for example.
 796                  */
 797                 if (hwerrs & TXE_PIO_PARITY) {
 798                         qib_6120_txe_recover(dd);
 799                         hwerrs &= ~TXE_PIO_PARITY;
 800                 }
 801 
 802                 if (!hwerrs) {
 803                         static u32 freeze_cnt;
 804 
 805                         freeze_cnt++;
 806                         qib_6120_clear_freeze(dd);
 807                 } else
 808                         isfatal = 1;
 809         }
 810 
 811         *msg = '\0';
 812 
 813         if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
 814                 isfatal = 1;
 815                 strlcat(msg,
 816                         "[Memory BIST test failed, InfiniPath hardware unusable]",
 817                         msgl);
 818                 /* ignore from now on, so disable until driver reloaded */
 819                 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
 820                 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
 821         }
 822 
 823         qib_format_hwerrors(hwerrs, qib_6120_hwerror_msgs,
 824                             ARRAY_SIZE(qib_6120_hwerror_msgs), msg, msgl);
 825 
 826         bitsmsg = dd->cspec->bitsmsgbuf;
 827         if (hwerrs & (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK <<
 828                       QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT)) {
 829                 bits = (u32) ((hwerrs >>
 830                                QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) &
 831                               QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK);
 832                 snprintf(bitsmsg, sizeof(dd->cspec->bitsmsgbuf),
 833                          "[PCIe Mem Parity Errs %x] ", bits);
 834                 strlcat(msg, bitsmsg, msgl);
 835         }
 836 
 837         if (hwerrs & _QIB_PLL_FAIL) {
 838                 isfatal = 1;
 839                 snprintf(bitsmsg, sizeof(dd->cspec->bitsmsgbuf),
 840                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 841                          (unsigned long long) hwerrs & _QIB_PLL_FAIL);
 842                 strlcat(msg, bitsmsg, msgl);
 843                 /* ignore from now on, so disable until driver reloaded */
 844                 dd->cspec->hwerrmask &= ~(hwerrs & _QIB_PLL_FAIL);
 845                 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
 846         }
 847 
 848         if (hwerrs & QLOGIC_IB_HWE_SERDESPLLFAILED) {
 849                 /*
 850                  * If it occurs, it is left masked since the external
 851                  * interface is unused
 852                  */
 853                 dd->cspec->hwerrmask &= ~QLOGIC_IB_HWE_SERDESPLLFAILED;
 854                 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
 855         }
 856 
 857         if (hwerrs)
 858                 /*
 859                  * if any set that we aren't ignoring; only
 860                  * make the complaint once, in case it's stuck
 861                  * or recurring, and we get here multiple
 862                  * times.
 863                  */
 864                 qib_dev_err(dd, "%s hardware error\n", msg);
 865         else
 866                 *msg = 0; /* recovered from all of them */
 867 
 868         if (isfatal && !dd->diag_client) {
 869                 qib_dev_err(dd,
 870                         "Fatal Hardware Error, no longer usable, SN %.16s\n",
 871                         dd->serial);
 872                 /*
 873                  * for /sys status file and user programs to print; if no
 874                  * trailing brace is copied, we'll know it was truncated.
 875                  */
 876                 if (dd->freezemsg)
 877                         snprintf(dd->freezemsg, dd->freezelen,
 878                                  "{%s}", msg);
 879                 qib_disable_after_error(dd);
 880         }
 881 }
 882 
 883 /*
 884  * Decode the error status into strings, deciding whether to always
 885  * print * it or not depending on "normal packet errors" vs everything
 886  * else.   Return 1 if "real" errors, otherwise 0 if only packet
 887  * errors, so caller can decide what to print with the string.
 888  */
 889 static int qib_decode_6120_err(struct qib_devdata *dd, char *buf, size_t blen,
 890                                u64 err)
 891 {
 892         int iserr = 1;
 893 
 894         *buf = '\0';
 895         if (err & QLOGIC_IB_E_PKTERRS) {
 896                 if (!(err & ~QLOGIC_IB_E_PKTERRS))
 897                         iserr = 0;
 898                 if ((err & ERR_MASK(RcvICRCErr)) &&
 899                     !(err&(ERR_MASK(RcvVCRCErr)|ERR_MASK(RcvEBPErr))))
 900                         strlcat(buf, "CRC ", blen);
 901                 if (!iserr)
 902                         goto done;
 903         }
 904         if (err & ERR_MASK(RcvHdrLenErr))
 905                 strlcat(buf, "rhdrlen ", blen);
 906         if (err & ERR_MASK(RcvBadTidErr))
 907                 strlcat(buf, "rbadtid ", blen);
 908         if (err & ERR_MASK(RcvBadVersionErr))
 909                 strlcat(buf, "rbadversion ", blen);
 910         if (err & ERR_MASK(RcvHdrErr))
 911                 strlcat(buf, "rhdr ", blen);
 912         if (err & ERR_MASK(RcvLongPktLenErr))
 913                 strlcat(buf, "rlongpktlen ", blen);
 914         if (err & ERR_MASK(RcvMaxPktLenErr))
 915                 strlcat(buf, "rmaxpktlen ", blen);
 916         if (err & ERR_MASK(RcvMinPktLenErr))
 917                 strlcat(buf, "rminpktlen ", blen);
 918         if (err & ERR_MASK(SendMinPktLenErr))
 919                 strlcat(buf, "sminpktlen ", blen);
 920         if (err & ERR_MASK(RcvFormatErr))
 921                 strlcat(buf, "rformaterr ", blen);
 922         if (err & ERR_MASK(RcvUnsupportedVLErr))
 923                 strlcat(buf, "runsupvl ", blen);
 924         if (err & ERR_MASK(RcvUnexpectedCharErr))
 925                 strlcat(buf, "runexpchar ", blen);
 926         if (err & ERR_MASK(RcvIBFlowErr))
 927                 strlcat(buf, "ribflow ", blen);
 928         if (err & ERR_MASK(SendUnderRunErr))
 929                 strlcat(buf, "sunderrun ", blen);
 930         if (err & ERR_MASK(SendPioArmLaunchErr))
 931                 strlcat(buf, "spioarmlaunch ", blen);
 932         if (err & ERR_MASK(SendUnexpectedPktNumErr))
 933                 strlcat(buf, "sunexperrpktnum ", blen);
 934         if (err & ERR_MASK(SendDroppedSmpPktErr))
 935                 strlcat(buf, "sdroppedsmppkt ", blen);
 936         if (err & ERR_MASK(SendMaxPktLenErr))
 937                 strlcat(buf, "smaxpktlen ", blen);
 938         if (err & ERR_MASK(SendUnsupportedVLErr))
 939                 strlcat(buf, "sunsupVL ", blen);
 940         if (err & ERR_MASK(InvalidAddrErr))
 941                 strlcat(buf, "invalidaddr ", blen);
 942         if (err & ERR_MASK(RcvEgrFullErr))
 943                 strlcat(buf, "rcvegrfull ", blen);
 944         if (err & ERR_MASK(RcvHdrFullErr))
 945                 strlcat(buf, "rcvhdrfull ", blen);
 946         if (err & ERR_MASK(IBStatusChanged))
 947                 strlcat(buf, "ibcstatuschg ", blen);
 948         if (err & ERR_MASK(RcvIBLostLinkErr))
 949                 strlcat(buf, "riblostlink ", blen);
 950         if (err & ERR_MASK(HardwareErr))
 951                 strlcat(buf, "hardware ", blen);
 952         if (err & ERR_MASK(ResetNegated))
 953                 strlcat(buf, "reset ", blen);
 954 done:
 955         return iserr;
 956 }
 957 
 958 /*
 959  * Called when we might have an error that is specific to a particular
 960  * PIO buffer, and may need to cancel that buffer, so it can be re-used.
 961  */
 962 static void qib_disarm_6120_senderrbufs(struct qib_pportdata *ppd)
 963 {
 964         unsigned long sbuf[2];
 965         struct qib_devdata *dd = ppd->dd;
 966 
 967         /*
 968          * It's possible that sendbuffererror could have bits set; might
 969          * have already done this as a result of hardware error handling.
 970          */
 971         sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
 972         sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
 973 
 974         if (sbuf[0] || sbuf[1])
 975                 qib_disarm_piobufs_set(dd, sbuf,
 976                                        dd->piobcnt2k + dd->piobcnt4k);
 977 }
 978 
 979 static int chk_6120_linkrecovery(struct qib_devdata *dd, u64 ibcs)
 980 {
 981         int ret = 1;
 982         u32 ibstate = qib_6120_iblink_state(ibcs);
 983         u32 linkrecov = read_6120_creg32(dd, cr_iblinkerrrecov);
 984 
 985         if (linkrecov != dd->cspec->lastlinkrecov) {
 986                 /* and no more until active again */
 987                 dd->cspec->lastlinkrecov = 0;
 988                 qib_set_linkstate(dd->pport, QIB_IB_LINKDOWN);
 989                 ret = 0;
 990         }
 991         if (ibstate == IB_PORT_ACTIVE)
 992                 dd->cspec->lastlinkrecov =
 993                         read_6120_creg32(dd, cr_iblinkerrrecov);
 994         return ret;
 995 }
 996 
 997 static void handle_6120_errors(struct qib_devdata *dd, u64 errs)
 998 {
 999         char *msg;
1000         u64 ignore_this_time = 0;
1001         u64 iserr = 0;
1002         struct qib_pportdata *ppd = dd->pport;
1003         u64 mask;
1004 
1005         /* don't report errors that are masked */
1006         errs &= dd->cspec->errormask;
1007         msg = dd->cspec->emsgbuf;
1008 
1009         /* do these first, they are most important */
1010         if (errs & ERR_MASK(HardwareErr))
1011                 qib_handle_6120_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf));
1012 
1013         if (errs & ~IB_E_BITSEXTANT)
1014                 qib_dev_err(dd,
1015                         "error interrupt with unknown errors %llx set\n",
1016                         (unsigned long long) (errs & ~IB_E_BITSEXTANT));
1017 
1018         if (errs & E_SUM_ERRS) {
1019                 qib_disarm_6120_senderrbufs(ppd);
1020                 if ((errs & E_SUM_LINK_PKTERRS) &&
1021                     !(ppd->lflags & QIBL_LINKACTIVE)) {
1022                         /*
1023                          * This can happen when trying to bring the link
1024                          * up, but the IB link changes state at the "wrong"
1025                          * time. The IB logic then complains that the packet
1026                          * isn't valid.  We don't want to confuse people, so
1027                          * we just don't print them, except at debug
1028                          */
1029                         ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1030                 }
1031         } else if ((errs & E_SUM_LINK_PKTERRS) &&
1032                    !(ppd->lflags & QIBL_LINKACTIVE)) {
1033                 /*
1034                  * This can happen when SMA is trying to bring the link
1035                  * up, but the IB link changes state at the "wrong" time.
1036                  * The IB logic then complains that the packet isn't
1037                  * valid.  We don't want to confuse people, so we just
1038                  * don't print them, except at debug
1039                  */
1040                 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1041         }
1042 
1043         qib_write_kreg(dd, kr_errclear, errs);
1044 
1045         errs &= ~ignore_this_time;
1046         if (!errs)
1047                 goto done;
1048 
1049         /*
1050          * The ones we mask off are handled specially below
1051          * or above.
1052          */
1053         mask = ERR_MASK(IBStatusChanged) | ERR_MASK(RcvEgrFullErr) |
1054                 ERR_MASK(RcvHdrFullErr) | ERR_MASK(HardwareErr);
1055         qib_decode_6120_err(dd, msg, sizeof(dd->cspec->emsgbuf), errs & ~mask);
1056 
1057         if (errs & E_SUM_PKTERRS)
1058                 qib_stats.sps_rcverrs++;
1059         if (errs & E_SUM_ERRS)
1060                 qib_stats.sps_txerrs++;
1061 
1062         iserr = errs & ~(E_SUM_PKTERRS | QLOGIC_IB_E_PKTERRS);
1063 
1064         if (errs & ERR_MASK(IBStatusChanged)) {
1065                 u64 ibcs = qib_read_kreg64(dd, kr_ibcstatus);
1066                 u32 ibstate = qib_6120_iblink_state(ibcs);
1067                 int handle = 1;
1068 
1069                 if (ibstate != IB_PORT_INIT && dd->cspec->lastlinkrecov)
1070                         handle = chk_6120_linkrecovery(dd, ibcs);
1071                 /*
1072                  * Since going into a recovery state causes the link state
1073                  * to go down and since recovery is transitory, it is better
1074                  * if we "miss" ever seeing the link training state go into
1075                  * recovery (i.e., ignore this transition for link state
1076                  * special handling purposes) without updating lastibcstat.
1077                  */
1078                 if (handle && qib_6120_phys_portstate(ibcs) ==
1079                                             IB_PHYSPORTSTATE_LINK_ERR_RECOVER)
1080                         handle = 0;
1081                 if (handle)
1082                         qib_handle_e_ibstatuschanged(ppd, ibcs);
1083         }
1084 
1085         if (errs & ERR_MASK(ResetNegated)) {
1086                 qib_dev_err(dd,
1087                         "Got reset, requires re-init (unload and reload driver)\n");
1088                 dd->flags &= ~QIB_INITTED;  /* needs re-init */
1089                 /* mark as having had error */
1090                 *dd->devstatusp |= QIB_STATUS_HWERROR;
1091                 *dd->pport->statusp &= ~QIB_STATUS_IB_CONF;
1092         }
1093 
1094         if (*msg && iserr)
1095                 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1096 
1097         if (ppd->state_wanted & ppd->lflags)
1098                 wake_up_interruptible(&ppd->state_wait);
1099 
1100         /*
1101          * If there were hdrq or egrfull errors, wake up any processes
1102          * waiting in poll.  We used to try to check which contexts had
1103          * the overflow, but given the cost of that and the chip reads
1104          * to support it, it's better to just wake everybody up if we
1105          * get an overflow; waiters can poll again if it's not them.
1106          */
1107         if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1108                 qib_handle_urcv(dd, ~0U);
1109                 if (errs & ERR_MASK(RcvEgrFullErr))
1110                         qib_stats.sps_buffull++;
1111                 else
1112                         qib_stats.sps_hdrfull++;
1113         }
1114 done:
1115         return;
1116 }
1117 
1118 /**
1119  * qib_6120_init_hwerrors - enable hardware errors
1120  * @dd: the qlogic_ib device
1121  *
1122  * now that we have finished initializing everything that might reasonably
1123  * cause a hardware error, and cleared those errors bits as they occur,
1124  * we can enable hardware errors in the mask (potentially enabling
1125  * freeze mode), and enable hardware errors as errors (along with
1126  * everything else) in errormask
1127  */
1128 static void qib_6120_init_hwerrors(struct qib_devdata *dd)
1129 {
1130         u64 val;
1131         u64 extsval;
1132 
1133         extsval = qib_read_kreg64(dd, kr_extstatus);
1134 
1135         if (!(extsval & QLOGIC_IB_EXTS_MEMBIST_ENDTEST))
1136                 qib_dev_err(dd, "MemBIST did not complete!\n");
1137 
1138         /* init so all hwerrors interrupt, and enter freeze, ajdust below */
1139         val = ~0ULL;
1140         if (dd->minrev < 2) {
1141                 /*
1142                  * Avoid problem with internal interface bus parity
1143                  * checking. Fixed in Rev2.
1144                  */
1145                 val &= ~QLOGIC_IB_HWE_PCIEBUSPARITYRADM;
1146         }
1147         /* avoid some intel cpu's speculative read freeze mode issue */
1148         val &= ~TXEMEMPARITYERR_PIOBUF;
1149 
1150         dd->cspec->hwerrmask = val;
1151 
1152         qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
1153         qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1154 
1155         /* clear all */
1156         qib_write_kreg(dd, kr_errclear, ~0ULL);
1157         /* enable errors that are masked, at least this first time. */
1158         qib_write_kreg(dd, kr_errmask, ~0ULL);
1159         dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
1160         /* clear any interrupts up to this point (ints still not enabled) */
1161         qib_write_kreg(dd, kr_intclear, ~0ULL);
1162 
1163         qib_write_kreg(dd, kr_rcvbthqp,
1164                        dd->qpn_mask << (QIB_6120_RcvBTHQP_BTHQP_Mask_LSB - 1) |
1165                        QIB_KD_QP);
1166 }
1167 
1168 /*
1169  * Disable and enable the armlaunch error.  Used for PIO bandwidth testing
1170  * on chips that are count-based, rather than trigger-based.  There is no
1171  * reference counting, but that's also fine, given the intended use.
1172  * Only chip-specific because it's all register accesses
1173  */
1174 static void qib_set_6120_armlaunch(struct qib_devdata *dd, u32 enable)
1175 {
1176         if (enable) {
1177                 qib_write_kreg(dd, kr_errclear,
1178                                ERR_MASK(SendPioArmLaunchErr));
1179                 dd->cspec->errormask |= ERR_MASK(SendPioArmLaunchErr);
1180         } else
1181                 dd->cspec->errormask &= ~ERR_MASK(SendPioArmLaunchErr);
1182         qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1183 }
1184 
1185 /*
1186  * Formerly took parameter <which> in pre-shifted,
1187  * pre-merged form with LinkCmd and LinkInitCmd
1188  * together, and assuming the zero was NOP.
1189  */
1190 static void qib_set_ib_6120_lstate(struct qib_pportdata *ppd, u16 linkcmd,
1191                                    u16 linitcmd)
1192 {
1193         u64 mod_wd;
1194         struct qib_devdata *dd = ppd->dd;
1195         unsigned long flags;
1196 
1197         if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
1198                 /*
1199                  * If we are told to disable, note that so link-recovery
1200                  * code does not attempt to bring us back up.
1201                  */
1202                 spin_lock_irqsave(&ppd->lflags_lock, flags);
1203                 ppd->lflags |= QIBL_IB_LINK_DISABLED;
1204                 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1205         } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
1206                 /*
1207                  * Any other linkinitcmd will lead to LINKDOWN and then
1208                  * to INIT (if all is well), so clear flag to let
1209                  * link-recovery code attempt to bring us back up.
1210                  */
1211                 spin_lock_irqsave(&ppd->lflags_lock, flags);
1212                 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
1213                 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1214         }
1215 
1216         mod_wd = (linkcmd << QLOGIC_IB_IBCC_LINKCMD_SHIFT) |
1217                 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1218 
1219         qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl | mod_wd);
1220         /* write to chip to prevent back-to-back writes of control reg */
1221         qib_write_kreg(dd, kr_scratch, 0);
1222 }
1223 
1224 /**
1225  * qib_6120_bringup_serdes - bring up the serdes
1226  * @dd: the qlogic_ib device
1227  */
1228 static int qib_6120_bringup_serdes(struct qib_pportdata *ppd)
1229 {
1230         struct qib_devdata *dd = ppd->dd;
1231         u64 val, config1, prev_val, hwstat, ibc;
1232 
1233         /* Put IBC in reset, sends disabled */
1234         dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1235         qib_write_kreg(dd, kr_control, 0ULL);
1236 
1237         dd->cspec->ibdeltainprog = 1;
1238         dd->cspec->ibsymsnap = read_6120_creg32(dd, cr_ibsymbolerr);
1239         dd->cspec->iblnkerrsnap = read_6120_creg32(dd, cr_iblinkerrrecov);
1240 
1241         /* flowcontrolwatermark is in units of KBytes */
1242         ibc = 0x5ULL << SYM_LSB(IBCCtrl, FlowCtrlWaterMark);
1243         /*
1244          * How often flowctrl sent.  More or less in usecs; balance against
1245          * watermark value, so that in theory senders always get a flow
1246          * control update in time to not let the IB link go idle.
1247          */
1248         ibc |= 0x3ULL << SYM_LSB(IBCCtrl, FlowCtrlPeriod);
1249         /* max error tolerance */
1250         dd->cspec->lli_thresh = 0xf;
1251         ibc |= (u64) dd->cspec->lli_thresh << SYM_LSB(IBCCtrl, PhyerrThreshold);
1252         /* use "real" buffer space for */
1253         ibc |= 4ULL << SYM_LSB(IBCCtrl, CreditScale);
1254         /* IB credit flow control. */
1255         ibc |= 0xfULL << SYM_LSB(IBCCtrl, OverrunThreshold);
1256         /*
1257          * set initial max size pkt IBC will send, including ICRC; it's the
1258          * PIO buffer size in dwords, less 1; also see qib_set_mtu()
1259          */
1260         ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << SYM_LSB(IBCCtrl, MaxPktLen);
1261         dd->cspec->ibcctrl = ibc; /* without linkcmd or linkinitcmd! */
1262 
1263         /* initially come up waiting for TS1, without sending anything. */
1264         val = dd->cspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
1265                 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1266         qib_write_kreg(dd, kr_ibcctrl, val);
1267 
1268         val = qib_read_kreg64(dd, kr_serdes_cfg0);
1269         config1 = qib_read_kreg64(dd, kr_serdes_cfg1);
1270 
1271         /*
1272          * Force reset on, also set rxdetect enable.  Must do before reading
1273          * serdesstatus at least for simulation, or some of the bits in
1274          * serdes status will come back as undefined and cause simulation
1275          * failures
1276          */
1277         val |= SYM_MASK(SerdesCfg0, ResetPLL) |
1278                 SYM_MASK(SerdesCfg0, RxDetEnX) |
1279                 (SYM_MASK(SerdesCfg0, L1PwrDnA) |
1280                  SYM_MASK(SerdesCfg0, L1PwrDnB) |
1281                  SYM_MASK(SerdesCfg0, L1PwrDnC) |
1282                  SYM_MASK(SerdesCfg0, L1PwrDnD));
1283         qib_write_kreg(dd, kr_serdes_cfg0, val);
1284         /* be sure chip saw it */
1285         qib_read_kreg64(dd, kr_scratch);
1286         udelay(5);              /* need pll reset set at least for a bit */
1287         /*
1288          * after PLL is reset, set the per-lane Resets and TxIdle and
1289          * clear the PLL reset and rxdetect (to get falling edge).
1290          * Leave L1PWR bits set (permanently)
1291          */
1292         val &= ~(SYM_MASK(SerdesCfg0, RxDetEnX) |
1293                  SYM_MASK(SerdesCfg0, ResetPLL) |
1294                  (SYM_MASK(SerdesCfg0, L1PwrDnA) |
1295                   SYM_MASK(SerdesCfg0, L1PwrDnB) |
1296                   SYM_MASK(SerdesCfg0, L1PwrDnC) |
1297                   SYM_MASK(SerdesCfg0, L1PwrDnD)));
1298         val |= (SYM_MASK(SerdesCfg0, ResetA) |
1299                 SYM_MASK(SerdesCfg0, ResetB) |
1300                 SYM_MASK(SerdesCfg0, ResetC) |
1301                 SYM_MASK(SerdesCfg0, ResetD)) |
1302                 SYM_MASK(SerdesCfg0, TxIdeEnX);
1303         qib_write_kreg(dd, kr_serdes_cfg0, val);
1304         /* be sure chip saw it */
1305         (void) qib_read_kreg64(dd, kr_scratch);
1306         /* need PLL reset clear for at least 11 usec before lane
1307          * resets cleared; give it a few more to be sure */
1308         udelay(15);
1309         val &= ~((SYM_MASK(SerdesCfg0, ResetA) |
1310                   SYM_MASK(SerdesCfg0, ResetB) |
1311                   SYM_MASK(SerdesCfg0, ResetC) |
1312                   SYM_MASK(SerdesCfg0, ResetD)) |
1313                  SYM_MASK(SerdesCfg0, TxIdeEnX));
1314 
1315         qib_write_kreg(dd, kr_serdes_cfg0, val);
1316         /* be sure chip saw it */
1317         (void) qib_read_kreg64(dd, kr_scratch);
1318 
1319         val = qib_read_kreg64(dd, kr_xgxs_cfg);
1320         prev_val = val;
1321         if (val & QLOGIC_IB_XGXS_RESET)
1322                 val &= ~QLOGIC_IB_XGXS_RESET;
1323         if (SYM_FIELD(val, XGXSCfg, polarity_inv) != ppd->rx_pol_inv) {
1324                 /* need to compensate for Tx inversion in partner */
1325                 val &= ~SYM_MASK(XGXSCfg, polarity_inv);
1326                 val |= (u64)ppd->rx_pol_inv << SYM_LSB(XGXSCfg, polarity_inv);
1327         }
1328         if (val != prev_val)
1329                 qib_write_kreg(dd, kr_xgxs_cfg, val);
1330 
1331         val = qib_read_kreg64(dd, kr_serdes_cfg0);
1332 
1333         /* clear current and de-emphasis bits */
1334         config1 &= ~0x0ffffffff00ULL;
1335         /* set current to 20ma */
1336         config1 |= 0x00000000000ULL;
1337         /* set de-emphasis to -5.68dB */
1338         config1 |= 0x0cccc000000ULL;
1339         qib_write_kreg(dd, kr_serdes_cfg1, config1);
1340 
1341         /* base and port guid same for single port */
1342         ppd->guid = dd->base_guid;
1343 
1344         /*
1345          * the process of setting and un-resetting the serdes normally
1346          * causes a serdes PLL error, so check for that and clear it
1347          * here.  Also clearr hwerr bit in errstatus, but not others.
1348          */
1349         hwstat = qib_read_kreg64(dd, kr_hwerrstatus);
1350         if (hwstat) {
1351                 /* should just have PLL, clear all set, in an case */
1352                 qib_write_kreg(dd, kr_hwerrclear, hwstat);
1353                 qib_write_kreg(dd, kr_errclear, ERR_MASK(HardwareErr));
1354         }
1355 
1356         dd->control |= QLOGIC_IB_C_LINKENABLE;
1357         dd->control &= ~QLOGIC_IB_C_FREEZEMODE;
1358         qib_write_kreg(dd, kr_control, dd->control);
1359 
1360         return 0;
1361 }
1362 
1363 /**
1364  * qib_6120_quiet_serdes - set serdes to txidle
1365  * @ppd: physical port of the qlogic_ib device
1366  * Called when driver is being unloaded
1367  */
1368 static void qib_6120_quiet_serdes(struct qib_pportdata *ppd)
1369 {
1370         struct qib_devdata *dd = ppd->dd;
1371         u64 val;
1372 
1373         qib_set_ib_6120_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1374 
1375         /* disable IBC */
1376         dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1377         qib_write_kreg(dd, kr_control,
1378                        dd->control | QLOGIC_IB_C_FREEZEMODE);
1379 
1380         if (dd->cspec->ibsymdelta || dd->cspec->iblnkerrdelta ||
1381             dd->cspec->ibdeltainprog) {
1382                 u64 diagc;
1383 
1384                 /* enable counter writes */
1385                 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
1386                 qib_write_kreg(dd, kr_hwdiagctrl,
1387                                diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
1388 
1389                 if (dd->cspec->ibsymdelta || dd->cspec->ibdeltainprog) {
1390                         val = read_6120_creg32(dd, cr_ibsymbolerr);
1391                         if (dd->cspec->ibdeltainprog)
1392                                 val -= val - dd->cspec->ibsymsnap;
1393                         val -= dd->cspec->ibsymdelta;
1394                         write_6120_creg(dd, cr_ibsymbolerr, val);
1395                 }
1396                 if (dd->cspec->iblnkerrdelta || dd->cspec->ibdeltainprog) {
1397                         val = read_6120_creg32(dd, cr_iblinkerrrecov);
1398                         if (dd->cspec->ibdeltainprog)
1399                                 val -= val - dd->cspec->iblnkerrsnap;
1400                         val -= dd->cspec->iblnkerrdelta;
1401                         write_6120_creg(dd, cr_iblinkerrrecov, val);
1402                 }
1403 
1404                 /* and disable counter writes */
1405                 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
1406         }
1407 
1408         val = qib_read_kreg64(dd, kr_serdes_cfg0);
1409         val |= SYM_MASK(SerdesCfg0, TxIdeEnX);
1410         qib_write_kreg(dd, kr_serdes_cfg0, val);
1411 }
1412 
1413 /**
1414  * qib_6120_setup_setextled - set the state of the two external LEDs
1415  * @dd: the qlogic_ib device
1416  * @on: whether the link is up or not
1417  *
1418  * The exact combo of LEDs if on is true is determined by looking
1419  * at the ibcstatus.
1420 
1421  * These LEDs indicate the physical and logical state of IB link.
1422  * For this chip (at least with recommended board pinouts), LED1
1423  * is Yellow (logical state) and LED2 is Green (physical state),
1424  *
1425  * Note:  We try to match the Mellanox HCA LED behavior as best
1426  * we can.  Green indicates physical link state is OK (something is
1427  * plugged in, and we can train).
1428  * Amber indicates the link is logically up (ACTIVE).
1429  * Mellanox further blinks the amber LED to indicate data packet
1430  * activity, but we have no hardware support for that, so it would
1431  * require waking up every 10-20 msecs and checking the counters
1432  * on the chip, and then turning the LED off if appropriate.  That's
1433  * visible overhead, so not something we will do.
1434  *
1435  */
1436 static void qib_6120_setup_setextled(struct qib_pportdata *ppd, u32 on)
1437 {
1438         u64 extctl, val, lst, ltst;
1439         unsigned long flags;
1440         struct qib_devdata *dd = ppd->dd;
1441 
1442         /*
1443          * The diags use the LED to indicate diag info, so we leave
1444          * the external LED alone when the diags are running.
1445          */
1446         if (dd->diag_client)
1447                 return;
1448 
1449         /* Allow override of LED display for, e.g. Locating system in rack */
1450         if (ppd->led_override) {
1451                 ltst = (ppd->led_override & QIB_LED_PHYS) ?
1452                         IB_PHYSPORTSTATE_LINKUP : IB_PHYSPORTSTATE_DISABLED,
1453                 lst = (ppd->led_override & QIB_LED_LOG) ?
1454                         IB_PORT_ACTIVE : IB_PORT_DOWN;
1455         } else if (on) {
1456                 val = qib_read_kreg64(dd, kr_ibcstatus);
1457                 ltst = qib_6120_phys_portstate(val);
1458                 lst = qib_6120_iblink_state(val);
1459         } else {
1460                 ltst = 0;
1461                 lst = 0;
1462         }
1463 
1464         spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
1465         extctl = dd->cspec->extctrl & ~(SYM_MASK(EXTCtrl, LEDPriPortGreenOn) |
1466                                  SYM_MASK(EXTCtrl, LEDPriPortYellowOn));
1467 
1468         if (ltst == IB_PHYSPORTSTATE_LINKUP)
1469                 extctl |= SYM_MASK(EXTCtrl, LEDPriPortYellowOn);
1470         if (lst == IB_PORT_ACTIVE)
1471                 extctl |= SYM_MASK(EXTCtrl, LEDPriPortGreenOn);
1472         dd->cspec->extctrl = extctl;
1473         qib_write_kreg(dd, kr_extctrl, extctl);
1474         spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
1475 }
1476 
1477 /**
1478  * qib_6120_setup_cleanup - clean up any per-chip chip-specific stuff
1479  * @dd: the qlogic_ib device
1480  *
1481  * This is called during driver unload.
1482 */
1483 static void qib_6120_setup_cleanup(struct qib_devdata *dd)
1484 {
1485         qib_free_irq(dd);
1486         kfree(dd->cspec->cntrs);
1487         kfree(dd->cspec->portcntrs);
1488         if (dd->cspec->dummy_hdrq) {
1489                 dma_free_coherent(&dd->pcidev->dev,
1490                                   ALIGN(dd->rcvhdrcnt *
1491                                         dd->rcvhdrentsize *
1492                                         sizeof(u32), PAGE_SIZE),
1493                                   dd->cspec->dummy_hdrq,
1494                                   dd->cspec->dummy_hdrq_phys);
1495                 dd->cspec->dummy_hdrq = NULL;
1496         }
1497 }
1498 
1499 static void qib_wantpiobuf_6120_intr(struct qib_devdata *dd, u32 needint)
1500 {
1501         unsigned long flags;
1502 
1503         spin_lock_irqsave(&dd->sendctrl_lock, flags);
1504         if (needint)
1505                 dd->sendctrl |= SYM_MASK(SendCtrl, PIOIntBufAvail);
1506         else
1507                 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOIntBufAvail);
1508         qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
1509         qib_write_kreg(dd, kr_scratch, 0ULL);
1510         spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
1511 }
1512 
1513 /*
1514  * handle errors and unusual events first, separate function
1515  * to improve cache hits for fast path interrupt handling
1516  */
1517 static noinline void unlikely_6120_intr(struct qib_devdata *dd, u64 istat)
1518 {
1519         if (unlikely(istat & ~QLOGIC_IB_I_BITSEXTANT))
1520                 qib_dev_err(dd, "interrupt with unknown interrupts %Lx set\n",
1521                             istat & ~QLOGIC_IB_I_BITSEXTANT);
1522 
1523         if (istat & QLOGIC_IB_I_ERROR) {
1524                 u64 estat = 0;
1525 
1526                 qib_stats.sps_errints++;
1527                 estat = qib_read_kreg64(dd, kr_errstatus);
1528                 if (!estat)
1529                         qib_devinfo(dd->pcidev,
1530                                 "error interrupt (%Lx), but no error bits set!\n",
1531                                 istat);
1532                 handle_6120_errors(dd, estat);
1533         }
1534 
1535         if (istat & QLOGIC_IB_I_GPIO) {
1536                 u32 gpiostatus;
1537                 u32 to_clear = 0;
1538 
1539                 /*
1540                  * GPIO_3..5 on IBA6120 Rev2 chips indicate
1541                  * errors that we need to count.
1542                  */
1543                 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
1544                 /* First the error-counter case. */
1545                 if (gpiostatus & GPIO_ERRINTR_MASK) {
1546                         /* want to clear the bits we see asserted. */
1547                         to_clear |= (gpiostatus & GPIO_ERRINTR_MASK);
1548 
1549                         /*
1550                          * Count appropriately, clear bits out of our copy,
1551                          * as they have been "handled".
1552                          */
1553                         if (gpiostatus & (1 << GPIO_RXUVL_BIT))
1554                                 dd->cspec->rxfc_unsupvl_errs++;
1555                         if (gpiostatus & (1 << GPIO_OVRUN_BIT))
1556                                 dd->cspec->overrun_thresh_errs++;
1557                         if (gpiostatus & (1 << GPIO_LLI_BIT))
1558                                 dd->cspec->lli_errs++;
1559                         gpiostatus &= ~GPIO_ERRINTR_MASK;
1560                 }
1561                 if (gpiostatus) {
1562                         /*
1563                          * Some unexpected bits remain. If they could have
1564                          * caused the interrupt, complain and clear.
1565                          * To avoid repetition of this condition, also clear
1566                          * the mask. It is almost certainly due to error.
1567                          */
1568                         const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
1569 
1570                         /*
1571                          * Also check that the chip reflects our shadow,
1572                          * and report issues, If they caused the interrupt.
1573                          * we will suppress by refreshing from the shadow.
1574                          */
1575                         if (mask & gpiostatus) {
1576                                 to_clear |= (gpiostatus & mask);
1577                                 dd->cspec->gpio_mask &= ~(gpiostatus & mask);
1578                                 qib_write_kreg(dd, kr_gpio_mask,
1579                                                dd->cspec->gpio_mask);
1580                         }
1581                 }
1582                 if (to_clear)
1583                         qib_write_kreg(dd, kr_gpio_clear, (u64) to_clear);
1584         }
1585 }
1586 
1587 static irqreturn_t qib_6120intr(int irq, void *data)
1588 {
1589         struct qib_devdata *dd = data;
1590         irqreturn_t ret;
1591         u32 istat, ctxtrbits, rmask, crcs = 0;
1592         unsigned i;
1593 
1594         if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
1595                 /*
1596                  * This return value is not great, but we do not want the
1597                  * interrupt core code to remove our interrupt handler
1598                  * because we don't appear to be handling an interrupt
1599                  * during a chip reset.
1600                  */
1601                 ret = IRQ_HANDLED;
1602                 goto bail;
1603         }
1604 
1605         istat = qib_read_kreg32(dd, kr_intstatus);
1606 
1607         if (unlikely(!istat)) {
1608                 ret = IRQ_NONE; /* not our interrupt, or already handled */
1609                 goto bail;
1610         }
1611         if (unlikely(istat == -1)) {
1612                 qib_bad_intrstatus(dd);
1613                 /* don't know if it was our interrupt or not */
1614                 ret = IRQ_NONE;
1615                 goto bail;
1616         }
1617 
1618         this_cpu_inc(*dd->int_counter);
1619 
1620         if (unlikely(istat & (~QLOGIC_IB_I_BITSEXTANT |
1621                               QLOGIC_IB_I_GPIO | QLOGIC_IB_I_ERROR)))
1622                 unlikely_6120_intr(dd, istat);
1623 
1624         /*
1625          * Clear the interrupt bits we found set, relatively early, so we
1626          * "know" know the chip will have seen this by the time we process
1627          * the queue, and will re-interrupt if necessary.  The processor
1628          * itself won't take the interrupt again until we return.
1629          */
1630         qib_write_kreg(dd, kr_intclear, istat);
1631 
1632         /*
1633          * Handle kernel receive queues before checking for pio buffers
1634          * available since receives can overflow; piobuf waiters can afford
1635          * a few extra cycles, since they were waiting anyway.
1636          */
1637         ctxtrbits = istat &
1638                 ((QLOGIC_IB_I_RCVAVAIL_MASK << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1639                  (QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT));
1640         if (ctxtrbits) {
1641                 rmask = (1U << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1642                         (1U << QLOGIC_IB_I_RCVURG_SHIFT);
1643                 for (i = 0; i < dd->first_user_ctxt; i++) {
1644                         if (ctxtrbits & rmask) {
1645                                 ctxtrbits &= ~rmask;
1646                                 crcs += qib_kreceive(dd->rcd[i],
1647                                                      &dd->cspec->lli_counter,
1648                                                      NULL);
1649                         }
1650                         rmask <<= 1;
1651                 }
1652                 if (crcs) {
1653                         u32 cntr = dd->cspec->lli_counter;
1654 
1655                         cntr += crcs;
1656                         if (cntr) {
1657                                 if (cntr > dd->cspec->lli_thresh) {
1658                                         dd->cspec->lli_counter = 0;
1659                                         dd->cspec->lli_errs++;
1660                                 } else
1661                                         dd->cspec->lli_counter += cntr;
1662                         }
1663                 }
1664 
1665 
1666                 if (ctxtrbits) {
1667                         ctxtrbits =
1668                                 (ctxtrbits >> QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1669                                 (ctxtrbits >> QLOGIC_IB_I_RCVURG_SHIFT);
1670                         qib_handle_urcv(dd, ctxtrbits);
1671                 }
1672         }
1673 
1674         if ((istat & QLOGIC_IB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
1675                 qib_ib_piobufavail(dd);
1676 
1677         ret = IRQ_HANDLED;
1678 bail:
1679         return ret;
1680 }
1681 
1682 /*
1683  * Set up our chip-specific interrupt handler
1684  * The interrupt type has already been setup, so
1685  * we just need to do the registration and error checking.
1686  */
1687 static void qib_setup_6120_interrupt(struct qib_devdata *dd)
1688 {
1689         int ret;
1690 
1691         /*
1692          * If the chip supports added error indication via GPIO pins,
1693          * enable interrupts on those bits so the interrupt routine
1694          * can count the events. Also set flag so interrupt routine
1695          * can know they are expected.
1696          */
1697         if (SYM_FIELD(dd->revision, Revision_R,
1698                       ChipRevMinor) > 1) {
1699                 /* Rev2+ reports extra errors via internal GPIO pins */
1700                 dd->cspec->gpio_mask |= GPIO_ERRINTR_MASK;
1701                 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1702         }
1703 
1704         ret = pci_request_irq(dd->pcidev, 0, qib_6120intr, NULL, dd,
1705                               QIB_DRV_NAME);
1706         if (ret)
1707                 qib_dev_err(dd,
1708                             "Couldn't setup interrupt (irq=%d): %d\n",
1709                             pci_irq_vector(dd->pcidev, 0), ret);
1710 }
1711 
1712 /**
1713  * pe_boardname - fill in the board name
1714  * @dd: the qlogic_ib device
1715  *
1716  * info is based on the board revision register
1717  */
1718 static void pe_boardname(struct qib_devdata *dd)
1719 {
1720         u32 boardid;
1721 
1722         boardid = SYM_FIELD(dd->revision, Revision,
1723                             BoardID);
1724 
1725         switch (boardid) {
1726         case 2:
1727                 dd->boardname = "InfiniPath_QLE7140";
1728                 break;
1729         default:
1730                 qib_dev_err(dd, "Unknown 6120 board with ID %u\n", boardid);
1731                 dd->boardname = "Unknown_InfiniPath_6120";
1732                 break;
1733         }
1734 
1735         if (dd->majrev != 4 || !dd->minrev || dd->minrev > 2)
1736                 qib_dev_err(dd,
1737                             "Unsupported InfiniPath hardware revision %u.%u!\n",
1738                             dd->majrev, dd->minrev);
1739 
1740         snprintf(dd->boardversion, sizeof(dd->boardversion),
1741                  "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
1742                  QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
1743                  (unsigned int)SYM_FIELD(dd->revision, Revision_R, Arch),
1744                  dd->majrev, dd->minrev,
1745                  (unsigned int)SYM_FIELD(dd->revision, Revision_R, SW));
1746 }
1747 
1748 /*
1749  * This routine sleeps, so it can only be called from user context, not
1750  * from interrupt context.  If we need interrupt context, we can split
1751  * it into two routines.
1752  */
1753 static int qib_6120_setup_reset(struct qib_devdata *dd)
1754 {
1755         u64 val;
1756         int i;
1757         int ret;
1758         u16 cmdval;
1759         u8 int_line, clinesz;
1760 
1761         qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
1762 
1763         /* Use ERROR so it shows up in logs, etc. */
1764         qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
1765 
1766         /* no interrupts till re-initted */
1767         qib_6120_set_intr_state(dd, 0);
1768 
1769         dd->cspec->ibdeltainprog = 0;
1770         dd->cspec->ibsymdelta = 0;
1771         dd->cspec->iblnkerrdelta = 0;
1772 
1773         /*
1774          * Keep chip from being accessed until we are ready.  Use
1775          * writeq() directly, to allow the write even though QIB_PRESENT
1776          * isn't set.
1777          */
1778         dd->flags &= ~(QIB_INITTED | QIB_PRESENT);
1779         /* so we check interrupts work again */
1780         dd->z_int_counter = qib_int_counter(dd);
1781         val = dd->control | QLOGIC_IB_C_RESET;
1782         writeq(val, &dd->kregbase[kr_control]);
1783         mb(); /* prevent compiler re-ordering around actual reset */
1784 
1785         for (i = 1; i <= 5; i++) {
1786                 /*
1787                  * Allow MBIST, etc. to complete; longer on each retry.
1788                  * We sometimes get machine checks from bus timeout if no
1789                  * response, so for now, make it *really* long.
1790                  */
1791                 msleep(1000 + (1 + i) * 2000);
1792 
1793                 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
1794 
1795                 /*
1796                  * Use readq directly, so we don't need to mark it as PRESENT
1797                  * until we get a successful indication that all is well.
1798                  */
1799                 val = readq(&dd->kregbase[kr_revision]);
1800                 if (val == dd->revision) {
1801                         dd->flags |= QIB_PRESENT; /* it's back */
1802                         ret = qib_reinit_intr(dd);
1803                         goto bail;
1804                 }
1805         }
1806         ret = 0; /* failed */
1807 
1808 bail:
1809         if (ret) {
1810                 if (qib_pcie_params(dd, dd->lbus_width, NULL))
1811                         qib_dev_err(dd,
1812                                 "Reset failed to setup PCIe or interrupts; continuing anyway\n");
1813                 /* clear the reset error, init error/hwerror mask */
1814                 qib_6120_init_hwerrors(dd);
1815                 /* for Rev2 error interrupts; nop for rev 1 */
1816                 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1817                 /* clear the reset error, init error/hwerror mask */
1818                 qib_6120_init_hwerrors(dd);
1819         }
1820         return ret;
1821 }
1822 
1823 /**
1824  * qib_6120_put_tid - write a TID in chip
1825  * @dd: the qlogic_ib device
1826  * @tidptr: pointer to the expected TID (in chip) to update
1827  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0)
1828  * for expected
1829  * @pa: physical address of in memory buffer; tidinvalid if freeing
1830  *
1831  * This exists as a separate routine to allow for special locking etc.
1832  * It's used for both the full cleanup on exit, as well as the normal
1833  * setup and teardown.
1834  */
1835 static void qib_6120_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
1836                              u32 type, unsigned long pa)
1837 {
1838         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1839         unsigned long flags;
1840         int tidx;
1841         spinlock_t *tidlockp; /* select appropriate spinlock */
1842 
1843         if (!dd->kregbase)
1844                 return;
1845 
1846         if (pa != dd->tidinvalid) {
1847                 if (pa & ((1U << 11) - 1)) {
1848                         qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
1849                                     pa);
1850                         return;
1851                 }
1852                 pa >>= 11;
1853                 if (pa & ~QLOGIC_IB_RT_ADDR_MASK) {
1854                         qib_dev_err(dd,
1855                                 "Physical page address 0x%lx larger than supported\n",
1856                                 pa);
1857                         return;
1858                 }
1859 
1860                 if (type == RCVHQ_RCV_TYPE_EAGER)
1861                         pa |= dd->tidtemplate;
1862                 else /* for now, always full 4KB page */
1863                         pa |= 2 << 29;
1864         }
1865 
1866         /*
1867          * Avoid chip issue by writing the scratch register
1868          * before and after the TID, and with an io write barrier.
1869          * We use a spinlock around the writes, so they can't intermix
1870          * with other TID (eager or expected) writes (the chip problem
1871          * is triggered by back to back TID writes). Unfortunately, this
1872          * call can be done from interrupt level for the ctxt 0 eager TIDs,
1873          * so we have to use irqsave locks.
1874          */
1875         /*
1876          * Assumes tidptr always > egrtidbase
1877          * if type == RCVHQ_RCV_TYPE_EAGER.
1878          */
1879         tidx = tidptr - dd->egrtidbase;
1880 
1881         tidlockp = (type == RCVHQ_RCV_TYPE_EAGER && tidx < dd->rcvhdrcnt)
1882                 ? &dd->cspec->kernel_tid_lock : &dd->cspec->user_tid_lock;
1883         spin_lock_irqsave(tidlockp, flags);
1884         qib_write_kreg(dd, kr_scratch, 0xfeeddeaf);
1885         writel(pa, tidp32);
1886         qib_write_kreg(dd, kr_scratch, 0xdeadbeef);
1887         spin_unlock_irqrestore(tidlockp, flags);
1888 }
1889 
1890 /**
1891  * qib_6120_put_tid_2 - write a TID in chip, Revision 2 or higher
1892  * @dd: the qlogic_ib device
1893  * @tidptr: pointer to the expected TID (in chip) to update
1894  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0)
1895  * for expected
1896  * @pa: physical address of in memory buffer; tidinvalid if freeing
1897  *
1898  * This exists as a separate routine to allow for selection of the
1899  * appropriate "flavor". The static calls in cleanup just use the
1900  * revision-agnostic form, as they are not performance critical.
1901  */
1902 static void qib_6120_put_tid_2(struct qib_devdata *dd, u64 __iomem *tidptr,
1903                                u32 type, unsigned long pa)
1904 {
1905         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1906 
1907         if (!dd->kregbase)
1908                 return;
1909 
1910         if (pa != dd->tidinvalid) {
1911                 if (pa & ((1U << 11) - 1)) {
1912                         qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
1913                                     pa);
1914                         return;
1915                 }
1916                 pa >>= 11;
1917                 if (pa & ~QLOGIC_IB_RT_ADDR_MASK) {
1918                         qib_dev_err(dd,
1919                                 "Physical page address 0x%lx larger than supported\n",
1920                                 pa);
1921                         return;
1922                 }
1923 
1924                 if (type == RCVHQ_RCV_TYPE_EAGER)
1925                         pa |= dd->tidtemplate;
1926                 else /* for now, always full 4KB page */
1927                         pa |= 2 << 29;
1928         }
1929         writel(pa, tidp32);
1930 }
1931 
1932 
1933 /**
1934  * qib_6120_clear_tids - clear all TID entries for a context, expected and eager
1935  * @dd: the qlogic_ib device
1936  * @ctxt: the context
1937  *
1938  * clear all TID entries for a context, expected and eager.
1939  * Used from qib_close().  On this chip, TIDs are only 32 bits,
1940  * not 64, but they are still on 64 bit boundaries, so tidbase
1941  * is declared as u64 * for the pointer math, even though we write 32 bits
1942  */
1943 static void qib_6120_clear_tids(struct qib_devdata *dd,
1944                                 struct qib_ctxtdata *rcd)
1945 {
1946         u64 __iomem *tidbase;
1947         unsigned long tidinv;
1948         u32 ctxt;
1949         int i;
1950 
1951         if (!dd->kregbase || !rcd)
1952                 return;
1953 
1954         ctxt = rcd->ctxt;
1955 
1956         tidinv = dd->tidinvalid;
1957         tidbase = (u64 __iomem *)
1958                 ((char __iomem *)(dd->kregbase) +
1959                  dd->rcvtidbase +
1960                  ctxt * dd->rcvtidcnt * sizeof(*tidbase));
1961 
1962         for (i = 0; i < dd->rcvtidcnt; i++)
1963                 /* use func pointer because could be one of two funcs */
1964                 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1965                                   tidinv);
1966 
1967         tidbase = (u64 __iomem *)
1968                 ((char __iomem *)(dd->kregbase) +
1969                  dd->rcvegrbase +
1970                  rcd->rcvegr_tid_base * sizeof(*tidbase));
1971 
1972         for (i = 0; i < rcd->rcvegrcnt; i++)
1973                 /* use func pointer because could be one of two funcs */
1974                 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1975                                   tidinv);
1976 }
1977 
1978 /**
1979  * qib_6120_tidtemplate - setup constants for TID updates
1980  * @dd: the qlogic_ib device
1981  *
1982  * We setup stuff that we use a lot, to avoid calculating each time
1983  */
1984 static void qib_6120_tidtemplate(struct qib_devdata *dd)
1985 {
1986         u32 egrsize = dd->rcvegrbufsize;
1987 
1988         /*
1989          * For now, we always allocate 4KB buffers (at init) so we can
1990          * receive max size packets.  We may want a module parameter to
1991          * specify 2KB or 4KB and/or make be per ctxt instead of per device
1992          * for those who want to reduce memory footprint.  Note that the
1993          * rcvhdrentsize size must be large enough to hold the largest
1994          * IB header (currently 96 bytes) that we expect to handle (plus of
1995          * course the 2 dwords of RHF).
1996          */
1997         if (egrsize == 2048)
1998                 dd->tidtemplate = 1U << 29;
1999         else if (egrsize == 4096)
2000                 dd->tidtemplate = 2U << 29;
2001         dd->tidinvalid = 0;
2002 }
2003 
2004 int __attribute__((weak)) qib_unordered_wc(void)
2005 {
2006         return 0;
2007 }
2008 
2009 /**
2010  * qib_6120_get_base_info - set chip-specific flags for user code
2011  * @rcd: the qlogic_ib ctxt
2012  * @kbase: qib_base_info pointer
2013  *
2014  * We set the PCIE flag because the lower bandwidth on PCIe vs
2015  * HyperTransport can affect some user packet algorithms.
2016  */
2017 static int qib_6120_get_base_info(struct qib_ctxtdata *rcd,
2018                                   struct qib_base_info *kinfo)
2019 {
2020         if (qib_unordered_wc())
2021                 kinfo->spi_runtime_flags |= QIB_RUNTIME_FORCE_WC_ORDER;
2022 
2023         kinfo->spi_runtime_flags |= QIB_RUNTIME_PCIE |
2024                 QIB_RUNTIME_FORCE_PIOAVAIL | QIB_RUNTIME_PIO_REGSWAPPED;
2025         return 0;
2026 }
2027 
2028 
2029 static struct qib_message_header *
2030 qib_6120_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
2031 {
2032         return (struct qib_message_header *)
2033                 &rhf_addr[sizeof(u64) / sizeof(u32)];
2034 }
2035 
2036 static void qib_6120_config_ctxts(struct qib_devdata *dd)
2037 {
2038         dd->ctxtcnt = qib_read_kreg32(dd, kr_portcnt);
2039         if (qib_n_krcv_queues > 1) {
2040                 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports;
2041                 if (dd->first_user_ctxt > dd->ctxtcnt)
2042                         dd->first_user_ctxt = dd->ctxtcnt;
2043                 dd->qpn_mask = dd->first_user_ctxt <= 2 ? 2 : 6;
2044         } else
2045                 dd->first_user_ctxt = dd->num_pports;
2046         dd->n_krcv_queues = dd->first_user_ctxt;
2047 }
2048 
2049 static void qib_update_6120_usrhead(struct qib_ctxtdata *rcd, u64 hd,
2050                                     u32 updegr, u32 egrhd, u32 npkts)
2051 {
2052         if (updegr)
2053                 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
2054         qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
2055 }
2056 
2057 static u32 qib_6120_hdrqempty(struct qib_ctxtdata *rcd)
2058 {
2059         u32 head, tail;
2060 
2061         head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
2062         if (rcd->rcvhdrtail_kvaddr)
2063                 tail = qib_get_rcvhdrtail(rcd);
2064         else
2065                 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
2066         return head == tail;
2067 }
2068 
2069 /*
2070  * Used when we close any ctxt, for DMA already in flight
2071  * at close.  Can't be done until we know hdrq size, so not
2072  * early in chip init.
2073  */
2074 static void alloc_dummy_hdrq(struct qib_devdata *dd)
2075 {
2076         dd->cspec->dummy_hdrq = dma_alloc_coherent(&dd->pcidev->dev,
2077                                         dd->rcd[0]->rcvhdrq_size,
2078                                         &dd->cspec->dummy_hdrq_phys,
2079                                         GFP_ATOMIC | __GFP_COMP);
2080         if (!dd->cspec->dummy_hdrq) {
2081                 qib_devinfo(dd->pcidev, "Couldn't allocate dummy hdrq\n");
2082                 /* fallback to just 0'ing */
2083                 dd->cspec->dummy_hdrq_phys = 0UL;
2084         }
2085 }
2086 
2087 /*
2088  * Modify the RCVCTRL register in chip-specific way. This
2089  * is a function because bit positions and (future) register
2090  * location is chip-specific, but the needed operations are
2091  * generic. <op> is a bit-mask because we often want to
2092  * do multiple modifications.
2093  */
2094 static void rcvctrl_6120_mod(struct qib_pportdata *ppd, unsigned int op,
2095                              int ctxt)
2096 {
2097         struct qib_devdata *dd = ppd->dd;
2098         u64 mask, val;
2099         unsigned long flags;
2100 
2101         spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2102 
2103         if (op & QIB_RCVCTRL_TAILUPD_ENB)
2104                 dd->rcvctrl |= (1ULL << QLOGIC_IB_R_TAILUPD_SHIFT);
2105         if (op & QIB_RCVCTRL_TAILUPD_DIS)
2106                 dd->rcvctrl &= ~(1ULL << QLOGIC_IB_R_TAILUPD_SHIFT);
2107         if (op & QIB_RCVCTRL_PKEY_ENB)
2108                 dd->rcvctrl &= ~(1ULL << IBA6120_R_PKEY_DIS_SHIFT);
2109         if (op & QIB_RCVCTRL_PKEY_DIS)
2110                 dd->rcvctrl |= (1ULL << IBA6120_R_PKEY_DIS_SHIFT);
2111         if (ctxt < 0)
2112                 mask = (1ULL << dd->ctxtcnt) - 1;
2113         else
2114                 mask = (1ULL << ctxt);
2115         if (op & QIB_RCVCTRL_CTXT_ENB) {
2116                 /* always done for specific ctxt */
2117                 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable));
2118                 if (!(dd->flags & QIB_NODMA_RTAIL))
2119                         dd->rcvctrl |= 1ULL << QLOGIC_IB_R_TAILUPD_SHIFT;
2120                 /* Write these registers before the context is enabled. */
2121                 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2122                         dd->rcd[ctxt]->rcvhdrqtailaddr_phys);
2123                 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2124                         dd->rcd[ctxt]->rcvhdrq_phys);
2125 
2126                 if (ctxt == 0 && !dd->cspec->dummy_hdrq)
2127                         alloc_dummy_hdrq(dd);
2128         }
2129         if (op & QIB_RCVCTRL_CTXT_DIS)
2130                 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable));
2131         if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
2132                 dd->rcvctrl |= (mask << QLOGIC_IB_R_INTRAVAIL_SHIFT);
2133         if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
2134                 dd->rcvctrl &= ~(mask << QLOGIC_IB_R_INTRAVAIL_SHIFT);
2135         qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
2136         if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && dd->rhdrhead_intr_off) {
2137                 /* arm rcv interrupt */
2138                 val = qib_read_ureg32(dd, ur_rcvhdrhead, ctxt) |
2139                         dd->rhdrhead_intr_off;
2140                 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2141         }
2142         if (op & QIB_RCVCTRL_CTXT_ENB) {
2143                 /*
2144                  * Init the context registers also; if we were
2145                  * disabled, tail and head should both be zero
2146                  * already from the enable, but since we don't
2147                  * know, we have to do it explicitly.
2148                  */
2149                 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
2150                 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
2151 
2152                 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
2153                 dd->rcd[ctxt]->head = val;
2154                 /* If kctxt, interrupt on next receive. */
2155                 if (ctxt < dd->first_user_ctxt)
2156                         val |= dd->rhdrhead_intr_off;
2157                 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2158         }
2159         if (op & QIB_RCVCTRL_CTXT_DIS) {
2160                 /*
2161                  * Be paranoid, and never write 0's to these, just use an
2162                  * unused page.  Of course,
2163                  * rcvhdraddr points to a large chunk of memory, so this
2164                  * could still trash things, but at least it won't trash
2165                  * page 0, and by disabling the ctxt, it should stop "soon",
2166                  * even if a packet or two is in already in flight after we
2167                  * disabled the ctxt.  Only 6120 has this issue.
2168                  */
2169                 if (ctxt >= 0) {
2170                         qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2171                                             dd->cspec->dummy_hdrq_phys);
2172                         qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2173                                             dd->cspec->dummy_hdrq_phys);
2174                 } else {
2175                         unsigned i;
2176 
2177                         for (i = 0; i < dd->cfgctxts; i++) {
2178                                 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr,
2179                                             i, dd->cspec->dummy_hdrq_phys);
2180                                 qib_write_kreg_ctxt(dd, kr_rcvhdraddr,
2181                                             i, dd->cspec->dummy_hdrq_phys);
2182                         }
2183                 }
2184         }
2185         spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2186 }
2187 
2188 /*
2189  * Modify the SENDCTRL register in chip-specific way. This
2190  * is a function there may be multiple such registers with
2191  * slightly different layouts. Only operations actually used
2192  * are implemented yet.
2193  * Chip requires no back-back sendctrl writes, so write
2194  * scratch register after writing sendctrl
2195  */
2196 static void sendctrl_6120_mod(struct qib_pportdata *ppd, u32 op)
2197 {
2198         struct qib_devdata *dd = ppd->dd;
2199         u64 tmp_dd_sendctrl;
2200         unsigned long flags;
2201 
2202         spin_lock_irqsave(&dd->sendctrl_lock, flags);
2203 
2204         /* First the ones that are "sticky", saved in shadow */
2205         if (op & QIB_SENDCTRL_CLEAR)
2206                 dd->sendctrl = 0;
2207         if (op & QIB_SENDCTRL_SEND_DIS)
2208                 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOEnable);
2209         else if (op & QIB_SENDCTRL_SEND_ENB)
2210                 dd->sendctrl |= SYM_MASK(SendCtrl, PIOEnable);
2211         if (op & QIB_SENDCTRL_AVAIL_DIS)
2212                 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd);
2213         else if (op & QIB_SENDCTRL_AVAIL_ENB)
2214                 dd->sendctrl |= SYM_MASK(SendCtrl, PIOBufAvailUpd);
2215 
2216         if (op & QIB_SENDCTRL_DISARM_ALL) {
2217                 u32 i, last;
2218 
2219                 tmp_dd_sendctrl = dd->sendctrl;
2220                 /*
2221                  * disarm any that are not yet launched, disabling sends
2222                  * and updates until done.
2223                  */
2224                 last = dd->piobcnt2k + dd->piobcnt4k;
2225                 tmp_dd_sendctrl &=
2226                         ~(SYM_MASK(SendCtrl, PIOEnable) |
2227                           SYM_MASK(SendCtrl, PIOBufAvailUpd));
2228                 for (i = 0; i < last; i++) {
2229                         qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl |
2230                                        SYM_MASK(SendCtrl, Disarm) | i);
2231                         qib_write_kreg(dd, kr_scratch, 0);
2232                 }
2233         }
2234 
2235         tmp_dd_sendctrl = dd->sendctrl;
2236 
2237         if (op & QIB_SENDCTRL_FLUSH)
2238                 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Abort);
2239         if (op & QIB_SENDCTRL_DISARM)
2240                 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
2241                         ((op & QIB_6120_SendCtrl_DisarmPIOBuf_RMASK) <<
2242                          SYM_LSB(SendCtrl, DisarmPIOBuf));
2243         if (op & QIB_SENDCTRL_AVAIL_BLIP)
2244                 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd);
2245 
2246         qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
2247         qib_write_kreg(dd, kr_scratch, 0);
2248 
2249         if (op & QIB_SENDCTRL_AVAIL_BLIP) {
2250                 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2251                 qib_write_kreg(dd, kr_scratch, 0);
2252         }
2253 
2254         spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2255 
2256         if (op & QIB_SENDCTRL_FLUSH) {
2257                 u32 v;
2258                 /*
2259                  * ensure writes have hit chip, then do a few
2260                  * more reads, to allow DMA of pioavail registers
2261                  * to occur, so in-memory copy is in sync with
2262                  * the chip.  Not always safe to sleep.
2263                  */
2264                 v = qib_read_kreg32(dd, kr_scratch);
2265                 qib_write_kreg(dd, kr_scratch, v);
2266                 v = qib_read_kreg32(dd, kr_scratch);
2267                 qib_write_kreg(dd, kr_scratch, v);
2268                 qib_read_kreg32(dd, kr_scratch);
2269         }
2270 }
2271 
2272 /**
2273  * qib_portcntr_6120 - read a per-port counter
2274  * @dd: the qlogic_ib device
2275  * @creg: the counter to snapshot
2276  */
2277 static u64 qib_portcntr_6120(struct qib_pportdata *ppd, u32 reg)
2278 {
2279         u64 ret = 0ULL;
2280         struct qib_devdata *dd = ppd->dd;
2281         u16 creg;
2282         /* 0xffff for unimplemented or synthesized counters */
2283         static const u16 xlator[] = {
2284                 [QIBPORTCNTR_PKTSEND] = cr_pktsend,
2285                 [QIBPORTCNTR_WORDSEND] = cr_wordsend,
2286                 [QIBPORTCNTR_PSXMITDATA] = 0xffff,
2287                 [QIBPORTCNTR_PSXMITPKTS] = 0xffff,
2288                 [QIBPORTCNTR_PSXMITWAIT] = 0xffff,
2289                 [QIBPORTCNTR_SENDSTALL] = cr_sendstall,
2290                 [QIBPORTCNTR_PKTRCV] = cr_pktrcv,
2291                 [QIBPORTCNTR_PSRCVDATA] = 0xffff,
2292                 [QIBPORTCNTR_PSRCVPKTS] = 0xffff,
2293                 [QIBPORTCNTR_RCVEBP] = cr_rcvebp,
2294                 [QIBPORTCNTR_RCVOVFL] = cr_rcvovfl,
2295                 [QIBPORTCNTR_WORDRCV] = cr_wordrcv,
2296                 [QIBPORTCNTR_RXDROPPKT] = cr_rxdroppkt,
2297                 [QIBPORTCNTR_RXLOCALPHYERR] = 0xffff,
2298                 [QIBPORTCNTR_RXVLERR] = 0xffff,
2299                 [QIBPORTCNTR_ERRICRC] = cr_erricrc,
2300                 [QIBPORTCNTR_ERRVCRC] = cr_errvcrc,
2301                 [QIBPORTCNTR_ERRLPCRC] = cr_errlpcrc,
2302                 [QIBPORTCNTR_BADFORMAT] = cr_badformat,
2303                 [QIBPORTCNTR_ERR_RLEN] = cr_err_rlen,
2304                 [QIBPORTCNTR_IBSYMBOLERR] = cr_ibsymbolerr,
2305                 [QIBPORTCNTR_INVALIDRLEN] = cr_invalidrlen,
2306                 [QIBPORTCNTR_UNSUPVL] = cr_txunsupvl,
2307                 [QIBPORTCNTR_EXCESSBUFOVFL] = 0xffff,
2308                 [QIBPORTCNTR_ERRLINK] = cr_errlink,
2309                 [QIBPORTCNTR_IBLINKDOWN] = cr_iblinkdown,
2310                 [QIBPORTCNTR_IBLINKERRRECOV] = cr_iblinkerrrecov,
2311                 [QIBPORTCNTR_LLI] = 0xffff,
2312                 [QIBPORTCNTR_PSINTERVAL] = 0xffff,
2313                 [QIBPORTCNTR_PSSTART] = 0xffff,
2314                 [QIBPORTCNTR_PSSTAT] = 0xffff,
2315                 [QIBPORTCNTR_VL15PKTDROP] = 0xffff,
2316                 [QIBPORTCNTR_ERRPKEY] = cr_errpkey,
2317                 [QIBPORTCNTR_KHDROVFL] = 0xffff,
2318         };
2319 
2320         if (reg >= ARRAY_SIZE(xlator)) {
2321                 qib_devinfo(ppd->dd->pcidev,
2322                          "Unimplemented portcounter %u\n", reg);
2323                 goto done;
2324         }
2325         creg = xlator[reg];
2326 
2327         /* handle counters requests not implemented as chip counters */
2328         if (reg == QIBPORTCNTR_LLI)
2329                 ret = dd->cspec->lli_errs;
2330         else if (reg == QIBPORTCNTR_EXCESSBUFOVFL)
2331                 ret = dd->cspec->overrun_thresh_errs;
2332         else if (reg == QIBPORTCNTR_KHDROVFL) {
2333                 int i;
2334 
2335                 /* sum over all kernel contexts */
2336                 for (i = 0; i < dd->first_user_ctxt; i++)
2337                         ret += read_6120_creg32(dd, cr_portovfl + i);
2338         } else if (reg == QIBPORTCNTR_PSSTAT)
2339                 ret = dd->cspec->pma_sample_status;
2340         if (creg == 0xffff)
2341                 goto done;
2342 
2343         /*
2344          * only fast incrementing counters are 64bit; use 32 bit reads to
2345          * avoid two independent reads when on opteron
2346          */
2347         if (creg == cr_wordsend || creg == cr_wordrcv ||
2348             creg == cr_pktsend || creg == cr_pktrcv)
2349                 ret = read_6120_creg(dd, creg);
2350         else
2351                 ret = read_6120_creg32(dd, creg);
2352         if (creg == cr_ibsymbolerr) {
2353                 if (dd->cspec->ibdeltainprog)
2354                         ret -= ret - dd->cspec->ibsymsnap;
2355                 ret -= dd->cspec->ibsymdelta;
2356         } else if (creg == cr_iblinkerrrecov) {
2357                 if (dd->cspec->ibdeltainprog)
2358                         ret -= ret - dd->cspec->iblnkerrsnap;
2359                 ret -= dd->cspec->iblnkerrdelta;
2360         }
2361         if (reg == QIBPORTCNTR_RXDROPPKT) /* add special cased count */
2362                 ret += dd->cspec->rxfc_unsupvl_errs;
2363 
2364 done:
2365         return ret;
2366 }
2367 
2368 /*
2369  * Device counter names (not port-specific), one line per stat,
2370  * single string.  Used by utilities like ipathstats to print the stats
2371  * in a way which works for different versions of drivers, without changing
2372  * the utility.  Names need to be 12 chars or less (w/o newline), for proper
2373  * display by utility.
2374  * Non-error counters are first.
2375  * Start of "error" conters is indicated by a leading "E " on the first
2376  * "error" counter, and doesn't count in label length.
2377  * The EgrOvfl list needs to be last so we truncate them at the configured
2378  * context count for the device.
2379  * cntr6120indices contains the corresponding register indices.
2380  */
2381 static const char cntr6120names[] =
2382         "Interrupts\n"
2383         "HostBusStall\n"
2384         "E RxTIDFull\n"
2385         "RxTIDInvalid\n"
2386         "Ctxt0EgrOvfl\n"
2387         "Ctxt1EgrOvfl\n"
2388         "Ctxt2EgrOvfl\n"
2389         "Ctxt3EgrOvfl\n"
2390         "Ctxt4EgrOvfl\n";
2391 
2392 static const size_t cntr6120indices[] = {
2393         cr_lbint,
2394         cr_lbflowstall,
2395         cr_errtidfull,
2396         cr_errtidvalid,
2397         cr_portovfl + 0,
2398         cr_portovfl + 1,
2399         cr_portovfl + 2,
2400         cr_portovfl + 3,
2401         cr_portovfl + 4,
2402 };
2403 
2404 /*
2405  * same as cntr6120names and cntr6120indices, but for port-specific counters.
2406  * portcntr6120indices is somewhat complicated by some registers needing
2407  * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
2408  */
2409 static const char portcntr6120names[] =
2410         "TxPkt\n"
2411         "TxFlowPkt\n"
2412         "TxWords\n"
2413         "RxPkt\n"
2414         "RxFlowPkt\n"
2415         "RxWords\n"
2416         "TxFlowStall\n"
2417         "E IBStatusChng\n"
2418         "IBLinkDown\n"
2419         "IBLnkRecov\n"
2420         "IBRxLinkErr\n"
2421         "IBSymbolErr\n"
2422         "RxLLIErr\n"
2423         "RxBadFormat\n"
2424         "RxBadLen\n"
2425         "RxBufOvrfl\n"
2426         "RxEBP\n"
2427         "RxFlowCtlErr\n"
2428         "RxICRCerr\n"
2429         "RxLPCRCerr\n"
2430         "RxVCRCerr\n"
2431         "RxInvalLen\n"
2432         "RxInvalPKey\n"
2433         "RxPktDropped\n"
2434         "TxBadLength\n"
2435         "TxDropped\n"
2436         "TxInvalLen\n"
2437         "TxUnderrun\n"
2438         "TxUnsupVL\n"
2439         ;
2440 
2441 #define _PORT_VIRT_FLAG 0x8000 /* "virtual", need adjustments */
2442 static const size_t portcntr6120indices[] = {
2443         QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
2444         cr_pktsendflow,
2445         QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
2446         QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
2447         cr_pktrcvflowctrl,
2448         QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
2449         QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
2450         cr_ibstatuschange,
2451         QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
2452         QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
2453         QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
2454         QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
2455         QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
2456         QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
2457         QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
2458         QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
2459         QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
2460         cr_rcvflowctrl_err,
2461         QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
2462         QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
2463         QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
2464         QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
2465         QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
2466         QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
2467         cr_invalidslen,
2468         cr_senddropped,
2469         cr_errslen,
2470         cr_sendunderrun,
2471         cr_txunsupvl,
2472 };
2473 
2474 /* do all the setup to make the counter reads efficient later */
2475 static void init_6120_cntrnames(struct qib_devdata *dd)
2476 {
2477         int i, j = 0;
2478         char *s;
2479 
2480         for (i = 0, s = (char *)cntr6120names; s && j <= dd->cfgctxts;
2481              i++) {
2482                 /* we always have at least one counter before the egrovfl */
2483                 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
2484                         j = 1;
2485                 s = strchr(s + 1, '\n');
2486                 if (s && j)
2487                         j++;
2488         }
2489         dd->cspec->ncntrs = i;
2490         if (!s)
2491                 /* full list; size is without terminating null */
2492                 dd->cspec->cntrnamelen = sizeof(cntr6120names) - 1;
2493         else
2494                 dd->cspec->cntrnamelen = 1 + s - cntr6120names;
2495         dd->cspec->cntrs = kmalloc_array(dd->cspec->ncntrs, sizeof(u64),
2496                                          GFP_KERNEL);
2497 
2498         for (i = 0, s = (char *)portcntr6120names; s; i++)
2499                 s = strchr(s + 1, '\n');
2500         dd->cspec->nportcntrs = i - 1;
2501         dd->cspec->portcntrnamelen = sizeof(portcntr6120names) - 1;
2502         dd->cspec->portcntrs = kmalloc_array(dd->cspec->nportcntrs,
2503                                              sizeof(u64),
2504                                              GFP_KERNEL);
2505 }
2506 
2507 static u32 qib_read_6120cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
2508                               u64 **cntrp)
2509 {
2510         u32 ret;
2511 
2512         if (namep) {
2513                 ret = dd->cspec->cntrnamelen;
2514                 if (pos >= ret)
2515                         ret = 0; /* final read after getting everything */
2516                 else
2517                         *namep = (char *)cntr6120names;
2518         } else {
2519                 u64 *cntr = dd->cspec->cntrs;
2520                 int i;
2521 
2522                 ret = dd->cspec->ncntrs * sizeof(u64);
2523                 if (!cntr || pos >= ret) {
2524                         /* everything read, or couldn't get memory */
2525                         ret = 0;
2526                         goto done;
2527                 }
2528                 if (pos >= ret) {
2529                         ret = 0; /* final read after getting everything */
2530                         goto done;
2531                 }
2532                 *cntrp = cntr;
2533                 for (i = 0; i < dd->cspec->ncntrs; i++)
2534                         *cntr++ = read_6120_creg32(dd, cntr6120indices[i]);
2535         }
2536 done:
2537         return ret;
2538 }
2539 
2540 static u32 qib_read_6120portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
2541                                   char **namep, u64 **cntrp)
2542 {
2543         u32 ret;
2544 
2545         if (namep) {
2546                 ret = dd->cspec->portcntrnamelen;
2547                 if (pos >= ret)
2548                         ret = 0; /* final read after getting everything */
2549                 else
2550                         *namep = (char *)portcntr6120names;
2551         } else {
2552                 u64 *cntr = dd->cspec->portcntrs;
2553                 struct qib_pportdata *ppd = &dd->pport[port];
2554                 int i;
2555 
2556                 ret = dd->cspec->nportcntrs * sizeof(u64);
2557                 if (!cntr || pos >= ret) {
2558                         /* everything read, or couldn't get memory */
2559                         ret = 0;
2560                         goto done;
2561                 }
2562                 *cntrp = cntr;
2563                 for (i = 0; i < dd->cspec->nportcntrs; i++) {
2564                         if (portcntr6120indices[i] & _PORT_VIRT_FLAG)
2565                                 *cntr++ = qib_portcntr_6120(ppd,
2566                                         portcntr6120indices[i] &
2567                                         ~_PORT_VIRT_FLAG);
2568                         else
2569                                 *cntr++ = read_6120_creg32(dd,
2570                                            portcntr6120indices[i]);
2571                 }
2572         }
2573 done:
2574         return ret;
2575 }
2576 
2577 static void qib_chk_6120_errormask(struct qib_devdata *dd)
2578 {
2579         static u32 fixed;
2580         u32 ctrl;
2581         unsigned long errormask;
2582         unsigned long hwerrs;
2583 
2584         if (!dd->cspec->errormask || !(dd->flags & QIB_INITTED))
2585                 return;
2586 
2587         errormask = qib_read_kreg64(dd, kr_errmask);
2588 
2589         if (errormask == dd->cspec->errormask)
2590                 return;
2591         fixed++;
2592 
2593         hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2594         ctrl = qib_read_kreg32(dd, kr_control);
2595 
2596         qib_write_kreg(dd, kr_errmask,
2597                 dd->cspec->errormask);
2598 
2599         if ((hwerrs & dd->cspec->hwerrmask) ||
2600             (ctrl & QLOGIC_IB_C_FREEZEMODE)) {
2601                 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
2602                 qib_write_kreg(dd, kr_errclear, 0ULL);
2603                 /* force re-interrupt of pending events, just in case */
2604                 qib_write_kreg(dd, kr_intclear, 0ULL);
2605                 qib_devinfo(dd->pcidev,
2606                          "errormask fixed(%u) %lx->%lx, ctrl %x hwerr %lx\n",
2607                          fixed, errormask, (unsigned long)dd->cspec->errormask,
2608                          ctrl, hwerrs);
2609         }
2610 }
2611 
2612 /**
2613  * qib_get_faststats - get word counters from chip before they overflow
2614  * @opaque - contains a pointer to the qlogic_ib device qib_devdata
2615  *
2616  * This needs more work; in particular, decision on whether we really
2617  * need traffic_wds done the way it is
2618  * called from add_timer
2619  */
2620 static void qib_get_6120_faststats(struct timer_list *t)
2621 {
2622         struct qib_devdata *dd = from_timer(dd, t, stats_timer);
2623         struct qib_pportdata *ppd = dd->pport;
2624         unsigned long flags;
2625         u64 traffic_wds;
2626 
2627         /*
2628          * don't access the chip while running diags, or memory diags can
2629          * fail
2630          */
2631         if (!(dd->flags & QIB_INITTED) || dd->diag_client)
2632                 /* but re-arm the timer, for diags case; won't hurt other */
2633                 goto done;
2634 
2635         /*
2636          * We now try to maintain an activity timer, based on traffic
2637          * exceeding a threshold, so we need to check the word-counts
2638          * even if they are 64-bit.
2639          */
2640         traffic_wds = qib_portcntr_6120(ppd, cr_wordsend) +
2641                 qib_portcntr_6120(ppd, cr_wordrcv);
2642         spin_lock_irqsave(&dd->eep_st_lock, flags);
2643         traffic_wds -= dd->traffic_wds;
2644         dd->traffic_wds += traffic_wds;
2645         spin_unlock_irqrestore(&dd->eep_st_lock, flags);
2646 
2647         qib_chk_6120_errormask(dd);
2648 done:
2649         mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
2650 }
2651 
2652 /* no interrupt fallback for these chips */
2653 static int qib_6120_nointr_fallback(struct qib_devdata *dd)
2654 {
2655         return 0;
2656 }
2657 
2658 /*
2659  * reset the XGXS (between serdes and IBC).  Slightly less intrusive
2660  * than resetting the IBC or external link state, and useful in some
2661  * cases to cause some retraining.  To do this right, we reset IBC
2662  * as well.
2663  */
2664 static void qib_6120_xgxs_reset(struct qib_pportdata *ppd)
2665 {
2666         u64 val, prev_val;
2667         struct qib_devdata *dd = ppd->dd;
2668 
2669         prev_val = qib_read_kreg64(dd, kr_xgxs_cfg);
2670         val = prev_val | QLOGIC_IB_XGXS_RESET;
2671         prev_val &= ~QLOGIC_IB_XGXS_RESET; /* be sure */
2672         qib_write_kreg(dd, kr_control,
2673                        dd->control & ~QLOGIC_IB_C_LINKENABLE);
2674         qib_write_kreg(dd, kr_xgxs_cfg, val);
2675         qib_read_kreg32(dd, kr_scratch);
2676         qib_write_kreg(dd, kr_xgxs_cfg, prev_val);
2677         qib_write_kreg(dd, kr_control, dd->control);
2678 }
2679 
2680 static int qib_6120_get_ib_cfg(struct qib_pportdata *ppd, int which)
2681 {
2682         int ret;
2683 
2684         switch (which) {
2685         case QIB_IB_CFG_LWID:
2686                 ret = ppd->link_width_active;
2687                 break;
2688 
2689         case QIB_IB_CFG_SPD:
2690                 ret = ppd->link_speed_active;
2691                 break;
2692 
2693         case QIB_IB_CFG_LWID_ENB:
2694                 ret = ppd->link_width_enabled;
2695                 break;
2696 
2697         case QIB_IB_CFG_SPD_ENB:
2698                 ret = ppd->link_speed_enabled;
2699                 break;
2700 
2701         case QIB_IB_CFG_OP_VLS:
2702                 ret = ppd->vls_operational;
2703                 break;
2704 
2705         case QIB_IB_CFG_VL_HIGH_CAP:
2706                 ret = 0;
2707                 break;
2708 
2709         case QIB_IB_CFG_VL_LOW_CAP:
2710                 ret = 0;
2711                 break;
2712 
2713         case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2714                 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl,
2715                                 OverrunThreshold);
2716                 break;
2717 
2718         case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2719                 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl,
2720                                 PhyerrThreshold);
2721                 break;
2722 
2723         case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2724                 /* will only take effect when the link state changes */
2725                 ret = (ppd->dd->cspec->ibcctrl &
2726                        SYM_MASK(IBCCtrl, LinkDownDefaultState)) ?
2727                         IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
2728                 break;
2729 
2730         case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
2731                 ret = 0; /* no heartbeat on this chip */
2732                 break;
2733 
2734         case QIB_IB_CFG_PMA_TICKS:
2735                 ret = 250; /* 1 usec. */
2736                 break;
2737 
2738         default:
2739                 ret =  -EINVAL;
2740                 break;
2741         }
2742         return ret;
2743 }
2744 
2745 /*
2746  * We assume range checking is already done, if needed.
2747  */
2748 static int qib_6120_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
2749 {
2750         struct qib_devdata *dd = ppd->dd;
2751         int ret = 0;
2752         u64 val64;
2753         u16 lcmd, licmd;
2754 
2755         switch (which) {
2756         case QIB_IB_CFG_LWID_ENB:
2757                 ppd->link_width_enabled = val;
2758                 break;
2759 
2760         case QIB_IB_CFG_SPD_ENB:
2761                 ppd->link_speed_enabled = val;
2762                 break;
2763 
2764         case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2765                 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl,
2766                                   OverrunThreshold);
2767                 if (val64 != val) {
2768                         dd->cspec->ibcctrl &=
2769                                 ~SYM_MASK(IBCCtrl, OverrunThreshold);
2770                         dd->cspec->ibcctrl |= (u64) val <<
2771                                 SYM_LSB(IBCCtrl, OverrunThreshold);
2772                         qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2773                         qib_write_kreg(dd, kr_scratch, 0);
2774                 }
2775                 break;
2776 
2777         case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2778                 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl,
2779                                   PhyerrThreshold);
2780                 if (val64 != val) {
2781                         dd->cspec->ibcctrl &=
2782                                 ~SYM_MASK(IBCCtrl, PhyerrThreshold);
2783                         dd->cspec->ibcctrl |= (u64) val <<
2784                                 SYM_LSB(IBCCtrl, PhyerrThreshold);
2785                         qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2786                         qib_write_kreg(dd, kr_scratch, 0);
2787                 }
2788                 break;
2789 
2790         case QIB_IB_CFG_PKEYS: /* update pkeys */
2791                 val64 = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
2792                         ((u64) ppd->pkeys[2] << 32) |
2793                         ((u64) ppd->pkeys[3] << 48);
2794                 qib_write_kreg(dd, kr_partitionkey, val64);
2795                 break;
2796 
2797         case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2798                 /* will only take effect when the link state changes */
2799                 if (val == IB_LINKINITCMD_POLL)
2800                         dd->cspec->ibcctrl &=
2801                                 ~SYM_MASK(IBCCtrl, LinkDownDefaultState);
2802                 else /* SLEEP */
2803                         dd->cspec->ibcctrl |=
2804                                 SYM_MASK(IBCCtrl, LinkDownDefaultState);
2805                 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2806                 qib_write_kreg(dd, kr_scratch, 0);
2807                 break;
2808 
2809         case QIB_IB_CFG_MTU: /* update the MTU in IBC */
2810                 /*
2811                  * Update our housekeeping variables, and set IBC max
2812                  * size, same as init code; max IBC is max we allow in
2813                  * buffer, less the qword pbc, plus 1 for ICRC, in dwords
2814                  * Set even if it's unchanged, print debug message only
2815                  * on changes.
2816                  */
2817                 val = (ppd->ibmaxlen >> 2) + 1;
2818                 dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, MaxPktLen);
2819                 dd->cspec->ibcctrl |= (u64)val <<
2820                         SYM_LSB(IBCCtrl, MaxPktLen);
2821                 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2822                 qib_write_kreg(dd, kr_scratch, 0);
2823                 break;
2824 
2825         case QIB_IB_CFG_LSTATE: /* set the IB link state */
2826                 switch (val & 0xffff0000) {
2827                 case IB_LINKCMD_DOWN:
2828                         lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
2829                         if (!dd->cspec->ibdeltainprog) {
2830                                 dd->cspec->ibdeltainprog = 1;
2831                                 dd->cspec->ibsymsnap =
2832                                         read_6120_creg32(dd, cr_ibsymbolerr);
2833                                 dd->cspec->iblnkerrsnap =
2834                                         read_6120_creg32(dd, cr_iblinkerrrecov);
2835                         }
2836                         break;
2837 
2838                 case IB_LINKCMD_ARMED:
2839                         lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
2840                         break;
2841 
2842                 case IB_LINKCMD_ACTIVE:
2843                         lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
2844                         break;
2845 
2846                 default:
2847                         ret = -EINVAL;
2848                         qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
2849                         goto bail;
2850                 }
2851                 switch (val & 0xffff) {
2852                 case IB_LINKINITCMD_NOP:
2853                         licmd = 0;
2854                         break;
2855 
2856                 case IB_LINKINITCMD_POLL:
2857                         licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
2858                         break;
2859 
2860                 case IB_LINKINITCMD_SLEEP:
2861                         licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
2862                         break;
2863 
2864                 case IB_LINKINITCMD_DISABLE:
2865                         licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
2866                         break;
2867 
2868                 default:
2869                         ret = -EINVAL;
2870                         qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
2871                                     val & 0xffff);
2872                         goto bail;
2873                 }
2874                 qib_set_ib_6120_lstate(ppd, lcmd, licmd);
2875                 goto bail;
2876 
2877         case QIB_IB_CFG_HRTBT:
2878                 ret = -EINVAL;
2879                 break;
2880 
2881         default:
2882                 ret = -EINVAL;
2883         }
2884 bail:
2885         return ret;
2886 }
2887 
2888 static int qib_6120_set_loopback(struct qib_pportdata *ppd, const char *what)
2889 {
2890         int ret = 0;
2891 
2892         if (!strncmp(what, "ibc", 3)) {
2893                 ppd->dd->cspec->ibcctrl |= SYM_MASK(IBCCtrl, Loopback);
2894                 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
2895                          ppd->dd->unit, ppd->port);
2896         } else if (!strncmp(what, "off", 3)) {
2897                 ppd->dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, Loopback);
2898                 qib_devinfo(ppd->dd->pcidev,
2899                         "Disabling IB%u:%u IBC loopback (normal)\n",
2900                         ppd->dd->unit, ppd->port);
2901         } else
2902                 ret = -EINVAL;
2903         if (!ret) {
2904                 qib_write_kreg(ppd->dd, kr_ibcctrl, ppd->dd->cspec->ibcctrl);
2905                 qib_write_kreg(ppd->dd, kr_scratch, 0);
2906         }
2907         return ret;
2908 }
2909 
2910 static void pma_6120_timer(struct timer_list *t)
2911 {
2912         struct qib_chip_specific *cs = from_timer(cs, t, pma_timer);
2913         struct qib_pportdata *ppd = cs->ppd;
2914         struct qib_ibport *ibp = &ppd->ibport_data;
2915         unsigned long flags;
2916 
2917         spin_lock_irqsave(&ibp->rvp.lock, flags);
2918         if (cs->pma_sample_status == IB_PMA_SAMPLE_STATUS_STARTED) {
2919                 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING;
2920                 qib_snapshot_counters(ppd, &cs->sword, &cs->rword,
2921                                       &cs->spkts, &cs->rpkts, &cs->xmit_wait);
2922                 mod_timer(&cs->pma_timer,
2923                       jiffies + usecs_to_jiffies(ibp->rvp.pma_sample_interval));
2924         } else if (cs->pma_sample_status == IB_PMA_SAMPLE_STATUS_RUNNING) {
2925                 u64 ta, tb, tc, td, te;
2926 
2927                 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE;
2928                 qib_snapshot_counters(ppd, &ta, &tb, &tc, &td, &te);
2929 
2930                 cs->sword = ta - cs->sword;
2931                 cs->rword = tb - cs->rword;
2932                 cs->spkts = tc - cs->spkts;
2933                 cs->rpkts = td - cs->rpkts;
2934                 cs->xmit_wait = te - cs->xmit_wait;
2935         }
2936         spin_unlock_irqrestore(&ibp->rvp.lock, flags);
2937 }
2938 
2939 /*
2940  * Note that the caller has the ibp->rvp.lock held.
2941  */
2942 static void qib_set_cntr_6120_sample(struct qib_pportdata *ppd, u32 intv,
2943                                      u32 start)
2944 {
2945         struct qib_chip_specific *cs = ppd->dd->cspec;
2946 
2947         if (start && intv) {
2948                 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_STARTED;
2949                 mod_timer(&cs->pma_timer, jiffies + usecs_to_jiffies(start));
2950         } else if (intv) {
2951                 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING;
2952                 qib_snapshot_counters(ppd, &cs->sword, &cs->rword,
2953                                       &cs->spkts, &cs->rpkts, &cs->xmit_wait);
2954                 mod_timer(&cs->pma_timer, jiffies + usecs_to_jiffies(intv));
2955         } else {
2956                 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE;
2957                 cs->sword = 0;
2958                 cs->rword = 0;
2959                 cs->spkts = 0;
2960                 cs->rpkts = 0;
2961                 cs->xmit_wait = 0;
2962         }
2963 }
2964 
2965 static u32 qib_6120_iblink_state(u64 ibcs)
2966 {
2967         u32 state = (u32)SYM_FIELD(ibcs, IBCStatus, LinkState);
2968 
2969         switch (state) {
2970         case IB_6120_L_STATE_INIT:
2971                 state = IB_PORT_INIT;
2972                 break;
2973         case IB_6120_L_STATE_ARM:
2974                 state = IB_PORT_ARMED;
2975                 break;
2976         case IB_6120_L_STATE_ACTIVE:
2977                 /* fall through */
2978         case IB_6120_L_STATE_ACT_DEFER:
2979                 state = IB_PORT_ACTIVE;
2980                 break;
2981         default: /* fall through */
2982         case IB_6120_L_STATE_DOWN:
2983                 state = IB_PORT_DOWN;
2984                 break;
2985         }
2986         return state;
2987 }
2988 
2989 /* returns the IBTA port state, rather than the IBC link training state */
2990 static u8 qib_6120_phys_portstate(u64 ibcs)
2991 {
2992         u8 state = (u8)SYM_FIELD(ibcs, IBCStatus, LinkTrainingState);
2993         return qib_6120_physportstate[state];
2994 }
2995 
2996 static int qib_6120_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
2997 {
2998         unsigned long flags;
2999 
3000         spin_lock_irqsave(&ppd->lflags_lock, flags);
3001         ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
3002         spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3003 
3004         if (ibup) {
3005                 if (ppd->dd->cspec->ibdeltainprog) {
3006                         ppd->dd->cspec->ibdeltainprog = 0;
3007                         ppd->dd->cspec->ibsymdelta +=
3008                                 read_6120_creg32(ppd->dd, cr_ibsymbolerr) -
3009                                         ppd->dd->cspec->ibsymsnap;
3010                         ppd->dd->cspec->iblnkerrdelta +=
3011                                 read_6120_creg32(ppd->dd, cr_iblinkerrrecov) -
3012                                         ppd->dd->cspec->iblnkerrsnap;
3013                 }
3014                 qib_hol_init(ppd);
3015         } else {
3016                 ppd->dd->cspec->lli_counter = 0;
3017                 if (!ppd->dd->cspec->ibdeltainprog) {
3018                         ppd->dd->cspec->ibdeltainprog = 1;
3019                         ppd->dd->cspec->ibsymsnap =
3020                                 read_6120_creg32(ppd->dd, cr_ibsymbolerr);
3021                         ppd->dd->cspec->iblnkerrsnap =
3022                                 read_6120_creg32(ppd->dd, cr_iblinkerrrecov);
3023                 }
3024                 qib_hol_down(ppd);
3025         }
3026 
3027         qib_6120_setup_setextled(ppd, ibup);
3028 
3029         return 0;
3030 }
3031 
3032 /* Does read/modify/write to appropriate registers to
3033  * set output and direction bits selected by mask.
3034  * these are in their canonical postions (e.g. lsb of
3035  * dir will end up in D48 of extctrl on existing chips).
3036  * returns contents of GP Inputs.
3037  */
3038 static int gpio_6120_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
3039 {
3040         u64 read_val, new_out;
3041         unsigned long flags;
3042 
3043         if (mask) {
3044                 /* some bits being written, lock access to GPIO */
3045                 dir &= mask;
3046                 out &= mask;
3047                 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
3048                 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
3049                 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
3050                 new_out = (dd->cspec->gpio_out & ~mask) | out;
3051 
3052                 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
3053                 qib_write_kreg(dd, kr_gpio_out, new_out);
3054                 dd->cspec->gpio_out = new_out;
3055                 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
3056         }
3057         /*
3058          * It is unlikely that a read at this time would get valid
3059          * data on a pin whose direction line was set in the same
3060          * call to this function. We include the read here because
3061          * that allows us to potentially combine a change on one pin with
3062          * a read on another, and because the old code did something like
3063          * this.
3064          */
3065         read_val = qib_read_kreg64(dd, kr_extstatus);
3066         return SYM_FIELD(read_val, EXTStatus, GPIOIn);
3067 }
3068 
3069 /*
3070  * Read fundamental info we need to use the chip.  These are
3071  * the registers that describe chip capabilities, and are
3072  * saved in shadow registers.
3073  */
3074 static void get_6120_chip_params(struct qib_devdata *dd)
3075 {
3076         u64 val;
3077         u32 piobufs;
3078         int mtu;
3079 
3080         dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
3081 
3082         dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
3083         dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
3084         dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
3085         dd->palign = qib_read_kreg32(dd, kr_palign);
3086         dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
3087         dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
3088 
3089         dd->rcvhdrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3090 
3091         val = qib_read_kreg64(dd, kr_sendpiosize);
3092         dd->piosize2k = val & ~0U;
3093         dd->piosize4k = val >> 32;
3094 
3095         mtu = ib_mtu_enum_to_int(qib_ibmtu);
3096         if (mtu == -1)
3097                 mtu = QIB_DEFAULT_MTU;
3098         dd->pport->ibmtu = (u32)mtu;
3099 
3100         val = qib_read_kreg64(dd, kr_sendpiobufcnt);
3101         dd->piobcnt2k = val & ~0U;
3102         dd->piobcnt4k = val >> 32;
3103         dd->last_pio = dd->piobcnt4k + dd->piobcnt2k - 1;
3104         /* these may be adjusted in init_chip_wc_pat() */
3105         dd->pio2kbase = (u32 __iomem *)
3106                 (((char __iomem *)dd->kregbase) + dd->pio2k_bufbase);
3107         if (dd->piobcnt4k) {
3108                 dd->pio4kbase = (u32 __iomem *)
3109                         (((char __iomem *) dd->kregbase) +
3110                          (dd->piobufbase >> 32));
3111                 /*
3112                  * 4K buffers take 2 pages; we use roundup just to be
3113                  * paranoid; we calculate it once here, rather than on
3114                  * ever buf allocate
3115                  */
3116                 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
3117         }
3118 
3119         piobufs = dd->piobcnt4k + dd->piobcnt2k;
3120 
3121         dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
3122                 (sizeof(u64) * BITS_PER_BYTE / 2);
3123 }
3124 
3125 /*
3126  * The chip base addresses in cspec and cpspec have to be set
3127  * after possible init_chip_wc_pat(), rather than in
3128  * get_6120_chip_params(), so split out as separate function
3129  */
3130 static void set_6120_baseaddrs(struct qib_devdata *dd)
3131 {
3132         u32 cregbase;
3133 
3134         cregbase = qib_read_kreg32(dd, kr_counterregbase);
3135         dd->cspec->cregbase = (u64 __iomem *)
3136                 ((char __iomem *) dd->kregbase + cregbase);
3137 
3138         dd->egrtidbase = (u64 __iomem *)
3139                 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
3140 }
3141 
3142 /*
3143  * Write the final few registers that depend on some of the
3144  * init setup.  Done late in init, just before bringing up
3145  * the serdes.
3146  */
3147 static int qib_late_6120_initreg(struct qib_devdata *dd)
3148 {
3149         int ret = 0;
3150         u64 val;
3151 
3152         qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
3153         qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
3154         qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
3155         qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
3156         val = qib_read_kreg64(dd, kr_sendpioavailaddr);
3157         if (val != dd->pioavailregs_phys) {
3158                 qib_dev_err(dd,
3159                         "Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n",
3160                         (unsigned long) dd->pioavailregs_phys,
3161                         (unsigned long long) val);
3162                 ret = -EINVAL;
3163         }
3164         return ret;
3165 }
3166 
3167 static int init_6120_variables(struct qib_devdata *dd)
3168 {
3169         int ret = 0;
3170         struct qib_pportdata *ppd;
3171         u32 sbufs;
3172 
3173         ppd = (struct qib_pportdata *)(dd + 1);
3174         dd->pport = ppd;
3175         dd->num_pports = 1;
3176 
3177         dd->cspec = (struct qib_chip_specific *)(ppd + dd->num_pports);
3178         dd->cspec->ppd = ppd;
3179         ppd->cpspec = NULL; /* not used in this chip */
3180 
3181         spin_lock_init(&dd->cspec->kernel_tid_lock);
3182         spin_lock_init(&dd->cspec->user_tid_lock);
3183         spin_lock_init(&dd->cspec->rcvmod_lock);
3184         spin_lock_init(&dd->cspec->gpio_lock);
3185 
3186         /* we haven't yet set QIB_PRESENT, so use read directly */
3187         dd->revision = readq(&dd->kregbase[kr_revision]);
3188 
3189         if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
3190                 qib_dev_err(dd,
3191                         "Revision register read failure, giving up initialization\n");
3192                 ret = -ENODEV;
3193                 goto bail;
3194         }
3195         dd->flags |= QIB_PRESENT;  /* now register routines work */
3196 
3197         dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R,
3198                                     ChipRevMajor);
3199         dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R,
3200                                     ChipRevMinor);
3201 
3202         get_6120_chip_params(dd);
3203         pe_boardname(dd); /* fill in boardname */
3204 
3205         /*
3206          * GPIO bits for TWSI data and clock,
3207          * used for serial EEPROM.
3208          */
3209         dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
3210         dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
3211         dd->twsi_eeprom_dev = QIB_TWSI_NO_DEV;
3212 
3213         if (qib_unordered_wc())
3214                 dd->flags |= QIB_PIO_FLUSH_WC;
3215 
3216         ret = qib_init_pportdata(ppd, dd, 0, 1);
3217         if (ret)
3218                 goto bail;
3219         ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
3220         ppd->link_speed_supported = QIB_IB_SDR;
3221         ppd->link_width_enabled = IB_WIDTH_4X;
3222         ppd->link_speed_enabled = ppd->link_speed_supported;
3223         /* these can't change for this chip, so set once */
3224         ppd->link_width_active = ppd->link_width_enabled;
3225         ppd->link_speed_active = ppd->link_speed_enabled;
3226         ppd->vls_supported = IB_VL_VL0;
3227         ppd->vls_operational = ppd->vls_supported;
3228 
3229         dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE;
3230         dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE;
3231         dd->rhf_offset = 0;
3232 
3233         /* we always allocate at least 2048 bytes for eager buffers */
3234         ret = ib_mtu_enum_to_int(qib_ibmtu);
3235         dd->rcvegrbufsize = ret != -1 ? max(ret, 2048) : QIB_DEFAULT_MTU;
3236         dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
3237 
3238         qib_6120_tidtemplate(dd);
3239 
3240         /*
3241          * We can request a receive interrupt for 1 or
3242          * more packets from current offset.  For now, we set this
3243          * up for a single packet.
3244          */
3245         dd->rhdrhead_intr_off = 1ULL << 32;
3246 
3247         /* setup the stats timer; the add_timer is done at end of init */
3248         timer_setup(&dd->stats_timer, qib_get_6120_faststats, 0);
3249         timer_setup(&dd->cspec->pma_timer, pma_6120_timer, 0);
3250 
3251         dd->ureg_align = qib_read_kreg32(dd, kr_palign);
3252 
3253         dd->piosize2kmax_dwords = dd->piosize2k >> 2;
3254         qib_6120_config_ctxts(dd);
3255         qib_set_ctxtcnt(dd);
3256 
3257         ret = init_chip_wc_pat(dd, 0);
3258         if (ret)
3259                 goto bail;
3260         set_6120_baseaddrs(dd); /* set chip access pointers now */
3261 
3262         ret = 0;
3263         if (qib_mini_init)
3264                 goto bail;
3265 
3266         qib_num_cfg_vls = 1; /* if any 6120's, only one VL */
3267 
3268         ret = qib_create_ctxts(dd);
3269         init_6120_cntrnames(dd);
3270 
3271         /* use all of 4KB buffers for the kernel, otherwise 16 */
3272         sbufs = dd->piobcnt4k ?  dd->piobcnt4k : 16;
3273 
3274         dd->lastctxt_piobuf = dd->piobcnt2k + dd->piobcnt4k - sbufs;
3275         dd->pbufsctxt = dd->lastctxt_piobuf /
3276                 (dd->cfgctxts - dd->first_user_ctxt);
3277 
3278         if (ret)
3279                 goto bail;
3280 bail:
3281         return ret;
3282 }
3283 
3284 /*
3285  * For this chip, we want to use the same buffer every time
3286  * when we are trying to bring the link up (they are always VL15
3287  * packets).  At that link state the packet should always go out immediately
3288  * (or at least be discarded at the tx interface if the link is down).
3289  * If it doesn't, and the buffer isn't available, that means some other
3290  * sender has gotten ahead of us, and is preventing our packet from going
3291  * out.  In that case, we flush all packets, and try again.  If that still
3292  * fails, we fail the request, and hope things work the next time around.
3293  *
3294  * We don't need very complicated heuristics on whether the packet had
3295  * time to go out or not, since even at SDR 1X, it goes out in very short
3296  * time periods, covered by the chip reads done here and as part of the
3297  * flush.
3298  */
3299 static u32 __iomem *get_6120_link_buf(struct qib_pportdata *ppd, u32 *bnum)
3300 {
3301         u32 __iomem *buf;
3302         u32 lbuf = ppd->dd->piobcnt2k + ppd->dd->piobcnt4k - 1;
3303 
3304         /*
3305          * always blip to get avail list updated, since it's almost
3306          * always needed, and is fairly cheap.
3307          */
3308         sendctrl_6120_mod(ppd->dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
3309         qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3310         buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3311         if (buf)
3312                 goto done;
3313 
3314         sendctrl_6120_mod(ppd, QIB_SENDCTRL_DISARM_ALL | QIB_SENDCTRL_FLUSH |
3315                           QIB_SENDCTRL_AVAIL_BLIP);
3316         ppd->dd->upd_pio_shadow  = 1; /* update our idea of what's busy */
3317         qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3318         buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3319 done:
3320         return buf;
3321 }
3322 
3323 static u32 __iomem *qib_6120_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
3324                                         u32 *pbufnum)
3325 {
3326         u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
3327         struct qib_devdata *dd = ppd->dd;
3328         u32 __iomem *buf;
3329 
3330         if (((pbc >> 32) & PBC_6120_VL15_SEND_CTRL) &&
3331                 !(ppd->lflags & (QIBL_IB_AUTONEG_INPROG | QIBL_LINKACTIVE)))
3332                 buf = get_6120_link_buf(ppd, pbufnum);
3333         else {
3334 
3335                 if ((plen + 1) > dd->piosize2kmax_dwords)
3336                         first = dd->piobcnt2k;
3337                 else
3338                         first = 0;
3339                 /* try 4k if all 2k busy, so same last for both sizes */
3340                 last = dd->piobcnt2k + dd->piobcnt4k - 1;
3341                 buf = qib_getsendbuf_range(dd, pbufnum, first, last);
3342         }
3343         return buf;
3344 }
3345 
3346 static int init_sdma_6120_regs(struct qib_pportdata *ppd)
3347 {
3348         return -ENODEV;
3349 }
3350 
3351 static u16 qib_sdma_6120_gethead(struct qib_pportdata *ppd)
3352 {
3353         return 0;
3354 }
3355 
3356 static int qib_sdma_6120_busy(struct qib_pportdata *ppd)
3357 {
3358         return 0;
3359 }
3360 
3361 static void qib_sdma_update_6120_tail(struct qib_pportdata *ppd, u16 tail)
3362 {
3363 }
3364 
3365 static void qib_6120_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
3366 {
3367 }
3368 
3369 static void qib_sdma_set_6120_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
3370 {
3371 }
3372 
3373 /*
3374  * the pbc doesn't need a VL15 indicator, but we need it for link_buf.
3375  * The chip ignores the bit if set.
3376  */
3377 static u32 qib_6120_setpbc_control(struct qib_pportdata *ppd, u32 plen,
3378                                    u8 srate, u8 vl)
3379 {
3380         return vl == 15 ? PBC_6120_VL15_SEND_CTRL : 0;
3381 }
3382 
3383 static void qib_6120_initvl15_bufs(struct qib_devdata *dd)
3384 {
3385 }
3386 
3387 static void qib_6120_init_ctxt(struct qib_ctxtdata *rcd)
3388 {
3389         rcd->rcvegrcnt = rcd->dd->rcvhdrcnt;
3390         rcd->rcvegr_tid_base = rcd->ctxt * rcd->rcvegrcnt;
3391 }
3392 
3393 static void qib_6120_txchk_change(struct qib_devdata *dd, u32 start,
3394         u32 len, u32 avail, struct qib_ctxtdata *rcd)
3395 {
3396 }
3397 
3398 static void writescratch(struct qib_devdata *dd, u32 val)
3399 {
3400         (void) qib_write_kreg(dd, kr_scratch, val);
3401 }
3402 
3403 static int qib_6120_tempsense_rd(struct qib_devdata *dd, int regnum)
3404 {
3405         return -ENXIO;
3406 }
3407 
3408 #ifdef CONFIG_INFINIBAND_QIB_DCA
3409 static int qib_6120_notify_dca(struct qib_devdata *dd, unsigned long event)
3410 {
3411         return 0;
3412 }
3413 #endif
3414 
3415 /* Dummy function, as 6120 boards never disable EEPROM Write */
3416 static int qib_6120_eeprom_wen(struct qib_devdata *dd, int wen)
3417 {
3418         return 1;
3419 }
3420 
3421 /**
3422  * qib_init_iba6120_funcs - set up the chip-specific function pointers
3423  * @pdev: pci_dev of the qlogic_ib device
3424  * @ent: pci_device_id matching this chip
3425  *
3426  * This is global, and is called directly at init to set up the
3427  * chip-specific function pointers for later use.
3428  *
3429  * It also allocates/partially-inits the qib_devdata struct for
3430  * this device.
3431  */
3432 struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *pdev,
3433                                            const struct pci_device_id *ent)
3434 {
3435         struct qib_devdata *dd;
3436         int ret;
3437 
3438         dd = qib_alloc_devdata(pdev, sizeof(struct qib_pportdata) +
3439                                sizeof(struct qib_chip_specific));
3440         if (IS_ERR(dd))
3441                 goto bail;
3442 
3443         dd->f_bringup_serdes    = qib_6120_bringup_serdes;
3444         dd->f_cleanup           = qib_6120_setup_cleanup;
3445         dd->f_clear_tids        = qib_6120_clear_tids;
3446         dd->f_free_irq          = qib_free_irq;
3447         dd->f_get_base_info     = qib_6120_get_base_info;
3448         dd->f_get_msgheader     = qib_6120_get_msgheader;
3449         dd->f_getsendbuf        = qib_6120_getsendbuf;
3450         dd->f_gpio_mod          = gpio_6120_mod;
3451         dd->f_eeprom_wen        = qib_6120_eeprom_wen;
3452         dd->f_hdrqempty         = qib_6120_hdrqempty;
3453         dd->f_ib_updown         = qib_6120_ib_updown;
3454         dd->f_init_ctxt         = qib_6120_init_ctxt;
3455         dd->f_initvl15_bufs     = qib_6120_initvl15_bufs;
3456         dd->f_intr_fallback     = qib_6120_nointr_fallback;
3457         dd->f_late_initreg      = qib_late_6120_initreg;
3458         dd->f_setpbc_control    = qib_6120_setpbc_control;
3459         dd->f_portcntr          = qib_portcntr_6120;
3460         dd->f_put_tid           = (dd->minrev >= 2) ?
3461                                       qib_6120_put_tid_2 :
3462                                       qib_6120_put_tid;
3463         dd->f_quiet_serdes      = qib_6120_quiet_serdes;
3464         dd->f_rcvctrl           = rcvctrl_6120_mod;
3465         dd->f_read_cntrs        = qib_read_6120cntrs;
3466         dd->f_read_portcntrs    = qib_read_6120portcntrs;
3467         dd->f_reset             = qib_6120_setup_reset;
3468         dd->f_init_sdma_regs    = init_sdma_6120_regs;
3469         dd->f_sdma_busy         = qib_sdma_6120_busy;
3470         dd->f_sdma_gethead      = qib_sdma_6120_gethead;
3471         dd->f_sdma_sendctrl     = qib_6120_sdma_sendctrl;
3472         dd->f_sdma_set_desc_cnt = qib_sdma_set_6120_desc_cnt;
3473         dd->f_sdma_update_tail  = qib_sdma_update_6120_tail;
3474         dd->f_sendctrl          = sendctrl_6120_mod;
3475         dd->f_set_armlaunch     = qib_set_6120_armlaunch;
3476         dd->f_set_cntr_sample   = qib_set_cntr_6120_sample;
3477         dd->f_iblink_state      = qib_6120_iblink_state;
3478         dd->f_ibphys_portstate  = qib_6120_phys_portstate;
3479         dd->f_get_ib_cfg        = qib_6120_get_ib_cfg;
3480         dd->f_set_ib_cfg        = qib_6120_set_ib_cfg;
3481         dd->f_set_ib_loopback   = qib_6120_set_loopback;
3482         dd->f_set_intr_state    = qib_6120_set_intr_state;
3483         dd->f_setextled         = qib_6120_setup_setextled;
3484         dd->f_txchk_change      = qib_6120_txchk_change;
3485         dd->f_update_usrhead    = qib_update_6120_usrhead;
3486         dd->f_wantpiobuf_intr   = qib_wantpiobuf_6120_intr;
3487         dd->f_xgxs_reset        = qib_6120_xgxs_reset;
3488         dd->f_writescratch      = writescratch;
3489         dd->f_tempsense_rd      = qib_6120_tempsense_rd;
3490 #ifdef CONFIG_INFINIBAND_QIB_DCA
3491         dd->f_notify_dca = qib_6120_notify_dca;
3492 #endif
3493         /*
3494          * Do remaining pcie setup and save pcie values in dd.
3495          * Any error printing is already done by the init code.
3496          * On return, we have the chip mapped and accessible,
3497          * but chip registers are not set up until start of
3498          * init_6120_variables.
3499          */
3500         ret = qib_pcie_ddinit(dd, pdev, ent);
3501         if (ret < 0)
3502                 goto bail_free;
3503 
3504         /* initialize chip-specific variables */
3505         ret = init_6120_variables(dd);
3506         if (ret)
3507                 goto bail_cleanup;
3508 
3509         if (qib_mini_init)
3510                 goto bail;
3511 
3512         if (qib_pcie_params(dd, 8, NULL))
3513                 qib_dev_err(dd,
3514                         "Failed to setup PCIe or interrupts; continuing anyway\n");
3515         /* clear diagctrl register, in case diags were running and crashed */
3516         qib_write_kreg(dd, kr_hwdiagctrl, 0);
3517 
3518         if (qib_read_kreg64(dd, kr_hwerrstatus) &
3519             QLOGIC_IB_HWE_SERDESPLLFAILED)
3520                 qib_write_kreg(dd, kr_hwerrclear,
3521                                QLOGIC_IB_HWE_SERDESPLLFAILED);
3522 
3523         /* setup interrupt handler (interrupt type handled above) */
3524         qib_setup_6120_interrupt(dd);
3525         /* Note that qpn_mask is set by qib_6120_config_ctxts() first */
3526         qib_6120_init_hwerrors(dd);
3527 
3528         goto bail;
3529 
3530 bail_cleanup:
3531         qib_pcie_ddcleanup(dd);
3532 bail_free:
3533         qib_free_devdata(dd);
3534         dd = ERR_PTR(ret);
3535 bail:
3536         return dd;
3537 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/infiniband/hw/qib/qib_iba6120.c

DEFINITIONS
