drivers/infiniband/hw/cxgb3/cxio

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This source file includes following definitions.
cxio_hal_find_rdev_by_name
cxio_hal_find_rdev_by_t3cdev
cxio_hal_cq_op
cxio_hal_clear_cq_ctx
cxio_hal_clear_qp_ctx
cxio_create_cq
get_qpid
put_qpid
cxio_release_ucontext
cxio_init_ucontext
cxio_create_qp
cxio_destroy_cq
cxio_destroy_qp
insert_recv_cqe
cxio_flush_rq
insert_sq_cqe
cxio_flush_sq
cxio_flush_hw_cq
cqe_completes_wr
cxio_count_scqes
cxio_count_rcqes
cxio_hal_init_ctrl_cq
cxio_hal_init_ctrl_qp
cxio_hal_destroy_ctrl_qp
cxio_hal_ctrl_qp_write_mem
__cxio_tpt_op
cxio_write_pbl
cxio_register_phys_mem
cxio_reregister_phys_mem
cxio_dereg_mem
cxio_allocate_window
cxio_deallocate_window
cxio_allocate_stag
cxio_rdma_init
cxio_register_ev_cb
cxio_unregister_ev_cb
cxio_hal_ev_handler
cxio_rdev_open
cxio_rdev_close
cxio_hal_init
cxio_hal_exit
flush_completed_wrs
create_read_req_cqe
advance_oldest_read
cxio_poll_cq
   1 /*
   2  * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <asm/delay.h>
  33 
  34 #include <linux/mutex.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/sched.h>
  37 #include <linux/spinlock.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #include <net/net_namespace.h>
  42 
  43 #include "cxio_resource.h"
  44 #include "cxio_hal.h"
  45 #include "cxgb3_offload.h"
  46 #include "sge_defs.h"
  47 
  48 static LIST_HEAD(rdev_list);
  49 static cxio_hal_ev_callback_func_t cxio_ev_cb = NULL;
  50 
  51 static struct cxio_rdev *cxio_hal_find_rdev_by_name(char *dev_name)
  52 {
  53         struct cxio_rdev *rdev;
  54 
  55         list_for_each_entry(rdev, &rdev_list, entry)
  56                 if (!strcmp(rdev->dev_name, dev_name))
  57                         return rdev;
  58         return NULL;
  59 }
  60 
  61 static struct cxio_rdev *cxio_hal_find_rdev_by_t3cdev(struct t3cdev *tdev)
  62 {
  63         struct cxio_rdev *rdev;
  64 
  65         list_for_each_entry(rdev, &rdev_list, entry)
  66                 if (rdev->t3cdev_p == tdev)
  67                         return rdev;
  68         return NULL;
  69 }
  70 
  71 int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
  72                    enum t3_cq_opcode op, u32 credit)
  73 {
  74         int ret;
  75         struct t3_cqe *cqe;
  76         u32 rptr;
  77 
  78         struct rdma_cq_op setup;
  79         setup.id = cq->cqid;
  80         setup.credits = (op == CQ_CREDIT_UPDATE) ? credit : 0;
  81         setup.op = op;
  82         ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup);
  83 
  84         if ((ret < 0) || (op == CQ_CREDIT_UPDATE))
  85                 return ret;
  86 
  87         /*
  88          * If the rearm returned an index other than our current index,
  89          * then there might be CQE's in flight (being DMA'd).  We must wait
  90          * here for them to complete or the consumer can miss a notification.
  91          */
  92         if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) {
  93                 int i=0;
  94 
  95                 rptr = cq->rptr;
  96 
  97                 /*
  98                  * Keep the generation correct by bumping rptr until it
  99                  * matches the index returned by the rearm - 1.
 100                  */
 101                 while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret)
 102                         rptr++;
 103 
 104                 /*
 105                  * Now rptr is the index for the (last) cqe that was
 106                  * in-flight at the time the HW rearmed the CQ.  We
 107                  * spin until that CQE is valid.
 108                  */
 109                 cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2);
 110                 while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) {
 111                         udelay(1);
 112                         if (i++ > 1000000) {
 113                                 pr_err("%s: stalled rnic\n", rdev_p->dev_name);
 114                                 return -EIO;
 115                         }
 116                 }
 117 
 118                 return 1;
 119         }
 120 
 121         return 0;
 122 }
 123 
 124 static int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
 125 {
 126         struct rdma_cq_setup setup;
 127         setup.id = cqid;
 128         setup.base_addr = 0;    /* NULL address */
 129         setup.size = 0;         /* disaable the CQ */
 130         setup.credits = 0;
 131         setup.credit_thres = 0;
 132         setup.ovfl_mode = 0;
 133         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 134 }
 135 
 136 static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
 137 {
 138         u64 sge_cmd;
 139         struct t3_modify_qp_wr *wqe;
 140         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
 141         if (!skb) {
 142                 pr_debug("%s alloc_skb failed\n", __func__);
 143                 return -ENOMEM;
 144         }
 145         wqe = skb_put_zero(skb, sizeof(*wqe));
 146         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD,
 147                        T3_COMPLETION_FLAG | T3_NOTIFY_FLAG, 0, qpid, 7,
 148                        T3_SOPEOP);
 149         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
 150         sge_cmd = qpid << 8 | 3;
 151         wqe->sge_cmd = cpu_to_be64(sge_cmd);
 152         skb->priority = CPL_PRIORITY_CONTROL;
 153         return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
 154 }
 155 
 156 int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq, int kernel)
 157 {
 158         struct rdma_cq_setup setup;
 159         int size = (1UL << (cq->size_log2)) * sizeof(struct t3_cqe);
 160 
 161         size += 1; /* one extra page for storing cq-in-err state */
 162         cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
 163         if (!cq->cqid)
 164                 return -ENOMEM;
 165         if (kernel) {
 166                 cq->sw_queue = kzalloc(size, GFP_KERNEL);
 167                 if (!cq->sw_queue)
 168                         return -ENOMEM;
 169         }
 170         cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev), size,
 171                                              &(cq->dma_addr), GFP_KERNEL);
 172         if (!cq->queue) {
 173                 kfree(cq->sw_queue);
 174                 return -ENOMEM;
 175         }
 176         dma_unmap_addr_set(cq, mapping, cq->dma_addr);
 177         setup.id = cq->cqid;
 178         setup.base_addr = (u64) (cq->dma_addr);
 179         setup.size = 1UL << cq->size_log2;
 180         setup.credits = 65535;
 181         setup.credit_thres = 1;
 182         if (rdev_p->t3cdev_p->type != T3A)
 183                 setup.ovfl_mode = 0;
 184         else
 185                 setup.ovfl_mode = 1;
 186         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 187 }
 188 
 189 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 190 {
 191         struct cxio_qpid_list *entry;
 192         u32 qpid;
 193         int i;
 194 
 195         mutex_lock(&uctx->lock);
 196         if (!list_empty(&uctx->qpids)) {
 197                 entry = list_entry(uctx->qpids.next, struct cxio_qpid_list,
 198                                    entry);
 199                 list_del(&entry->entry);
 200                 qpid = entry->qpid;
 201                 kfree(entry);
 202         } else {
 203                 qpid = cxio_hal_get_qpid(rdev_p->rscp);
 204                 if (!qpid)
 205                         goto out;
 206                 for (i = qpid+1; i & rdev_p->qpmask; i++) {
 207                         entry = kmalloc(sizeof(*entry), GFP_KERNEL);
 208                         if (!entry)
 209                                 break;
 210                         entry->qpid = i;
 211                         list_add_tail(&entry->entry, &uctx->qpids);
 212                 }
 213         }
 214 out:
 215         mutex_unlock(&uctx->lock);
 216         pr_debug("%s qpid 0x%x\n", __func__, qpid);
 217         return qpid;
 218 }
 219 
 220 static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
 221                      struct cxio_ucontext *uctx)
 222 {
 223         struct cxio_qpid_list *entry;
 224 
 225         entry = kmalloc(sizeof(*entry), GFP_KERNEL);
 226         if (!entry)
 227                 return;
 228         pr_debug("%s qpid 0x%x\n", __func__, qpid);
 229         entry->qpid = qpid;
 230         mutex_lock(&uctx->lock);
 231         list_add_tail(&entry->entry, &uctx->qpids);
 232         mutex_unlock(&uctx->lock);
 233 }
 234 
 235 void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 236 {
 237         struct list_head *pos, *nxt;
 238         struct cxio_qpid_list *entry;
 239 
 240         mutex_lock(&uctx->lock);
 241         list_for_each_safe(pos, nxt, &uctx->qpids) {
 242                 entry = list_entry(pos, struct cxio_qpid_list, entry);
 243                 list_del_init(&entry->entry);
 244                 if (!(entry->qpid & rdev_p->qpmask))
 245                         cxio_hal_put_qpid(rdev_p->rscp, entry->qpid);
 246                 kfree(entry);
 247         }
 248         mutex_unlock(&uctx->lock);
 249 }
 250 
 251 void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 252 {
 253         INIT_LIST_HEAD(&uctx->qpids);
 254         mutex_init(&uctx->lock);
 255 }
 256 
 257 int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
 258                    struct t3_wq *wq, struct cxio_ucontext *uctx)
 259 {
 260         int depth = 1UL << wq->size_log2;
 261         int rqsize = 1UL << wq->rq_size_log2;
 262 
 263         wq->qpid = get_qpid(rdev_p, uctx);
 264         if (!wq->qpid)
 265                 return -ENOMEM;
 266 
 267         wq->rq = kcalloc(depth, sizeof(struct t3_swrq), GFP_KERNEL);
 268         if (!wq->rq)
 269                 goto err1;
 270 
 271         wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
 272         if (!wq->rq_addr)
 273                 goto err2;
 274 
 275         wq->sq = kcalloc(depth, sizeof(struct t3_swsq), GFP_KERNEL);
 276         if (!wq->sq)
 277                 goto err3;
 278 
 279         wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
 280                                        depth * sizeof(union t3_wr),
 281                                        &(wq->dma_addr), GFP_KERNEL);
 282         if (!wq->queue)
 283                 goto err4;
 284 
 285         dma_unmap_addr_set(wq, mapping, wq->dma_addr);
 286         wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
 287         if (!kernel_domain)
 288                 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
 289                                         (wq->qpid << rdev_p->qpshift);
 290         wq->rdev = rdev_p;
 291         pr_debug("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n",
 292                  __func__, wq->qpid, wq->doorbell, (unsigned long long)wq->udb);
 293         return 0;
 294 err4:
 295         kfree(wq->sq);
 296 err3:
 297         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
 298 err2:
 299         kfree(wq->rq);
 300 err1:
 301         put_qpid(rdev_p, wq->qpid, uctx);
 302         return -ENOMEM;
 303 }
 304 
 305 void cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 306 {
 307         cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
 308         kfree(cq->sw_queue);
 309         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 310                           (1UL << (cq->size_log2))
 311                           * sizeof(struct t3_cqe) + 1, cq->queue,
 312                           dma_unmap_addr(cq, mapping));
 313         cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
 314 }
 315 
 316 int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
 317                     struct cxio_ucontext *uctx)
 318 {
 319         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 320                           (1UL << (wq->size_log2))
 321                           * sizeof(union t3_wr), wq->queue,
 322                           dma_unmap_addr(wq, mapping));
 323         kfree(wq->sq);
 324         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
 325         kfree(wq->rq);
 326         put_qpid(rdev_p, wq->qpid, uctx);
 327         return 0;
 328 }
 329 
 330 static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq)
 331 {
 332         struct t3_cqe cqe;
 333 
 334         pr_debug("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
 335                  wq, cq, cq->sw_rptr, cq->sw_wptr);
 336         memset(&cqe, 0, sizeof(cqe));
 337         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
 338                                  V_CQE_OPCODE(T3_SEND) |
 339                                  V_CQE_TYPE(0) |
 340                                  V_CQE_SWCQE(1) |
 341                                  V_CQE_QPID(wq->qpid) |
 342                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
 343                                                        cq->size_log2)));
 344         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
 345         cq->sw_wptr++;
 346 }
 347 
 348 int cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count)
 349 {
 350         u32 ptr;
 351         int flushed = 0;
 352 
 353         pr_debug("%s wq %p cq %p\n", __func__, wq, cq);
 354 
 355         /* flush RQ */
 356         pr_debug("%s rq_rptr %u rq_wptr %u skip count %u\n", __func__,
 357                  wq->rq_rptr, wq->rq_wptr, count);
 358         ptr = wq->rq_rptr + count;
 359         while (ptr++ != wq->rq_wptr) {
 360                 insert_recv_cqe(wq, cq);
 361                 flushed++;
 362         }
 363         return flushed;
 364 }
 365 
 366 static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq,
 367                           struct t3_swsq *sqp)
 368 {
 369         struct t3_cqe cqe;
 370 
 371         pr_debug("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
 372                  wq, cq, cq->sw_rptr, cq->sw_wptr);
 373         memset(&cqe, 0, sizeof(cqe));
 374         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
 375                                  V_CQE_OPCODE(sqp->opcode) |
 376                                  V_CQE_TYPE(1) |
 377                                  V_CQE_SWCQE(1) |
 378                                  V_CQE_QPID(wq->qpid) |
 379                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
 380                                                        cq->size_log2)));
 381         cqe.u.scqe.wrid_hi = sqp->sq_wptr;
 382 
 383         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
 384         cq->sw_wptr++;
 385 }
 386 
 387 int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count)
 388 {
 389         __u32 ptr = wq->sq_rptr + count;
 390         int flushed = 0;
 391         struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
 392 
 393         while (ptr != wq->sq_wptr) {
 394                 sqp->signaled = 0;
 395                 insert_sq_cqe(wq, cq, sqp);
 396                 ptr++;
 397                 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
 398                 flushed++;
 399         }
 400         return flushed;
 401 }
 402 
 403 /*
 404  * Move all CQEs from the HWCQ into the SWCQ.
 405  */
 406 void cxio_flush_hw_cq(struct t3_cq *cq)
 407 {
 408         struct t3_cqe *cqe, *swcqe;
 409 
 410         pr_debug("%s cq %p cqid 0x%x\n", __func__, cq, cq->cqid);
 411         cqe = cxio_next_hw_cqe(cq);
 412         while (cqe) {
 413                 pr_debug("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
 414                          __func__, cq->rptr, cq->sw_wptr);
 415                 swcqe = cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2);
 416                 *swcqe = *cqe;
 417                 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
 418                 cq->sw_wptr++;
 419                 cq->rptr++;
 420                 cqe = cxio_next_hw_cqe(cq);
 421         }
 422 }
 423 
 424 static int cqe_completes_wr(struct t3_cqe *cqe, struct t3_wq *wq)
 425 {
 426         if (CQE_OPCODE(*cqe) == T3_TERMINATE)
 427                 return 0;
 428 
 429         if ((CQE_OPCODE(*cqe) == T3_RDMA_WRITE) && RQ_TYPE(*cqe))
 430                 return 0;
 431 
 432         if ((CQE_OPCODE(*cqe) == T3_READ_RESP) && SQ_TYPE(*cqe))
 433                 return 0;
 434 
 435         if (CQE_SEND_OPCODE(*cqe) && RQ_TYPE(*cqe) &&
 436             Q_EMPTY(wq->rq_rptr, wq->rq_wptr))
 437                 return 0;
 438 
 439         return 1;
 440 }
 441 
 442 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
 443 {
 444         struct t3_cqe *cqe;
 445         u32 ptr;
 446 
 447         *count = 0;
 448         ptr = cq->sw_rptr;
 449         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
 450                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
 451                 if ((SQ_TYPE(*cqe) ||
 452                      ((CQE_OPCODE(*cqe) == T3_READ_RESP) && wq->oldest_read)) &&
 453                     (CQE_QPID(*cqe) == wq->qpid))
 454                         (*count)++;
 455                 ptr++;
 456         }
 457         pr_debug("%s cq %p count %d\n", __func__, cq, *count);
 458 }
 459 
 460 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
 461 {
 462         struct t3_cqe *cqe;
 463         u32 ptr;
 464 
 465         *count = 0;
 466         pr_debug("%s count zero %d\n", __func__, *count);
 467         ptr = cq->sw_rptr;
 468         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
 469                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
 470                 if (RQ_TYPE(*cqe) && (CQE_OPCODE(*cqe) != T3_READ_RESP) &&
 471                     (CQE_QPID(*cqe) == wq->qpid) && cqe_completes_wr(cqe, wq))
 472                         (*count)++;
 473                 ptr++;
 474         }
 475         pr_debug("%s cq %p count %d\n", __func__, cq, *count);
 476 }
 477 
 478 static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
 479 {
 480         struct rdma_cq_setup setup;
 481         setup.id = 0;
 482         setup.base_addr = 0;    /* NULL address */
 483         setup.size = 1;         /* enable the CQ */
 484         setup.credits = 0;
 485 
 486         /* force SGE to redirect to RspQ and interrupt */
 487         setup.credit_thres = 0;
 488         setup.ovfl_mode = 1;
 489         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 490 }
 491 
 492 static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
 493 {
 494         int err;
 495         u64 sge_cmd, ctx0, ctx1;
 496         u64 base_addr;
 497         struct t3_modify_qp_wr *wqe;
 498         struct sk_buff *skb;
 499 
 500         skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
 501         if (!skb) {
 502                 pr_debug("%s alloc_skb failed\n", __func__);
 503                 return -ENOMEM;
 504         }
 505         err = cxio_hal_init_ctrl_cq(rdev_p);
 506         if (err) {
 507                 pr_debug("%s err %d initializing ctrl_cq\n", __func__, err);
 508                 goto err;
 509         }
 510         rdev_p->ctrl_qp.workq = dma_alloc_coherent(
 511                                         &(rdev_p->rnic_info.pdev->dev),
 512                                         (1 << T3_CTRL_QP_SIZE_LOG2) *
 513                                         sizeof(union t3_wr),
 514                                         &(rdev_p->ctrl_qp.dma_addr),
 515                                         GFP_KERNEL);
 516         if (!rdev_p->ctrl_qp.workq) {
 517                 pr_debug("%s dma_alloc_coherent failed\n", __func__);
 518                 err = -ENOMEM;
 519                 goto err;
 520         }
 521         dma_unmap_addr_set(&rdev_p->ctrl_qp, mapping,
 522                            rdev_p->ctrl_qp.dma_addr);
 523         rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
 524 
 525         mutex_init(&rdev_p->ctrl_qp.lock);
 526         init_waitqueue_head(&rdev_p->ctrl_qp.waitq);
 527 
 528         /* update HW Ctrl QP context */
 529         base_addr = rdev_p->ctrl_qp.dma_addr;
 530         base_addr >>= 12;
 531         ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) |
 532                 V_EC_BASE_LO((u32) base_addr & 0xffff));
 533         ctx0 <<= 32;
 534         ctx0 |= V_EC_CREDITS(FW_WR_NUM);
 535         base_addr >>= 16;
 536         ctx1 = (u32) base_addr;
 537         base_addr >>= 32;
 538         ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) |
 539                         V_EC_TYPE(0) | V_EC_GEN(1) |
 540                         V_EC_UP_TOKEN(T3_CTL_QP_TID) | F_EC_VALID)) << 32;
 541         wqe = skb_put_zero(skb, sizeof(*wqe));
 542         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0,
 543                        T3_CTL_QP_TID, 7, T3_SOPEOP);
 544         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
 545         sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3;
 546         wqe->sge_cmd = cpu_to_be64(sge_cmd);
 547         wqe->ctx1 = cpu_to_be64(ctx1);
 548         wqe->ctx0 = cpu_to_be64(ctx0);
 549         pr_debug("CtrlQP dma_addr %pad workq %p size %d\n",
 550                  &rdev_p->ctrl_qp.dma_addr, rdev_p->ctrl_qp.workq,
 551                  1 << T3_CTRL_QP_SIZE_LOG2);
 552         skb->priority = CPL_PRIORITY_CONTROL;
 553         return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
 554 err:
 555         kfree_skb(skb);
 556         return err;
 557 }
 558 
 559 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
 560 {
 561         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 562                           (1UL << T3_CTRL_QP_SIZE_LOG2)
 563                           * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
 564                           dma_unmap_addr(&rdev_p->ctrl_qp, mapping));
 565         return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
 566 }
 567 
 568 /* write len bytes of data into addr (32B aligned address)
 569  * If data is NULL, clear len byte of memory to zero.
 570  * caller acquires the ctrl_qp lock before the call
 571  */
 572 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
 573                                       u32 len, void *data)
 574 {
 575         u32 i, nr_wqe, copy_len;
 576         u8 *copy_data;
 577         u8 wr_len, utx_len;     /* length in 8 byte flit */
 578         enum t3_wr_flags flag;
 579         __be64 *wqe;
 580         u64 utx_cmd;
 581         addr &= 0x7FFFFFF;
 582         nr_wqe = len % 96 ? len / 96 + 1 : len / 96;    /* 96B max per WQE */
 583         pr_debug("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
 584                  __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
 585                  nr_wqe, data, addr);
 586         utx_len = 3;            /* in 32B unit */
 587         for (i = 0; i < nr_wqe; i++) {
 588                 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
 589                            T3_CTRL_QP_SIZE_LOG2)) {
 590                         pr_debug("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, wait for more space i %d\n",
 591                                  __func__,
 592                                  rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
 593                         if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 594                                              !Q_FULL(rdev_p->ctrl_qp.rptr,
 595                                                      rdev_p->ctrl_qp.wptr,
 596                                                      T3_CTRL_QP_SIZE_LOG2))) {
 597                                 pr_debug("%s ctrl_qp workq interrupted\n",
 598                                          __func__);
 599                                 return -ERESTARTSYS;
 600                         }
 601                         pr_debug("%s ctrl_qp wakeup, continue posting work request i %d\n",
 602                                  __func__, i);
 603                 }
 604                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
 605                                                 (1 << T3_CTRL_QP_SIZE_LOG2)));
 606                 flag = 0;
 607                 if (i == (nr_wqe - 1)) {
 608                         /* last WQE */
 609                         flag = T3_COMPLETION_FLAG;
 610                         if (len % 32)
 611                                 utx_len = len / 32 + 1;
 612                         else
 613                                 utx_len = len / 32;
 614                 }
 615 
 616                 /*
 617                  * Force a CQE to return the credit to the workq in case
 618                  * we posted more than half the max QP size of WRs
 619                  */
 620                 if ((i != 0) &&
 621                     (i % (((1 << T3_CTRL_QP_SIZE_LOG2)) >> 1) == 0)) {
 622                         flag = T3_COMPLETION_FLAG;
 623                         pr_debug("%s force completion at i %d\n", __func__, i);
 624                 }
 625 
 626                 /* build the utx mem command */
 627                 wqe += (sizeof(struct t3_bypass_wr) >> 3);
 628                 utx_cmd = (T3_UTX_MEM_WRITE << 28) | (addr + i * 3);
 629                 utx_cmd <<= 32;
 630                 utx_cmd |= (utx_len << 28) | ((utx_len << 2) + 1);
 631                 *wqe = cpu_to_be64(utx_cmd);
 632                 wqe++;
 633                 copy_data = (u8 *) data + i * 96;
 634                 copy_len = len > 96 ? 96 : len;
 635 
 636                 /* clear memory content if data is NULL */
 637                 if (data)
 638                         memcpy(wqe, copy_data, copy_len);
 639                 else
 640                         memset(wqe, 0, copy_len);
 641                 if (copy_len % 32)
 642                         memset(((u8 *) wqe) + copy_len, 0,
 643                                32 - (copy_len % 32));
 644                 wr_len = ((sizeof(struct t3_bypass_wr)) >> 3) + 1 +
 645                          (utx_len << 2);
 646                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
 647                               (1 << T3_CTRL_QP_SIZE_LOG2)));
 648 
 649                 /* wptr in the WRID[31:0] */
 650                 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
 651 
 652                 /*
 653                  * This must be the last write with a memory barrier
 654                  * for the genbit
 655                  */
 656                 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag,
 657                                Q_GENBIT(rdev_p->ctrl_qp.wptr,
 658                                         T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID,
 659                                wr_len, T3_SOPEOP);
 660                 if (flag == T3_COMPLETION_FLAG)
 661                         ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
 662                 len -= 96;
 663                 rdev_p->ctrl_qp.wptr++;
 664         }
 665         return 0;
 666 }
 667 
 668 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl_size and pbl_addr
 669  * OUT: stag index
 670  * TBD: shared memory region support
 671  */
 672 static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
 673                          u32 *stag, u8 stag_state, u32 pdid,
 674                          enum tpt_mem_type type, enum tpt_mem_perm perm,
 675                          u32 zbva, u64 to, u32 len, u8 page_size,
 676                          u32 pbl_size, u32 pbl_addr)
 677 {
 678         int err;
 679         struct tpt_entry tpt;
 680         u32 stag_idx;
 681         u32 wptr;
 682 
 683         if (cxio_fatal_error(rdev_p))
 684                 return -EIO;
 685 
 686         stag_state = stag_state > 0;
 687         stag_idx = (*stag) >> 8;
 688 
 689         if ((!reset_tpt_entry) && !(*stag != T3_STAG_UNSET)) {
 690                 stag_idx = cxio_hal_get_stag(rdev_p->rscp);
 691                 if (!stag_idx)
 692                         return -ENOMEM;
 693                 *stag = (stag_idx << 8) | ((*stag) & 0xFF);
 694         }
 695         pr_debug("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
 696                  __func__, stag_state, type, pdid, stag_idx);
 697 
 698         mutex_lock(&rdev_p->ctrl_qp.lock);
 699 
 700         /* write TPT entry */
 701         if (reset_tpt_entry)
 702                 memset(&tpt, 0, sizeof(tpt));
 703         else {
 704                 tpt.valid_stag_pdid = cpu_to_be32(F_TPT_VALID |
 705                                 V_TPT_STAG_KEY((*stag) & M_TPT_STAG_KEY) |
 706                                 V_TPT_STAG_STATE(stag_state) |
 707                                 V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
 708                 BUG_ON(page_size >= 28);
 709                 tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
 710                         ((perm & TPT_MW_BIND) ? F_TPT_MW_BIND_ENABLE : 0) |
 711                         V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
 712                         V_TPT_PAGE_SIZE(page_size));
 713                 tpt.rsvd_pbl_addr = cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3));
 714                 tpt.len = cpu_to_be32(len);
 715                 tpt.va_hi = cpu_to_be32((u32) (to >> 32));
 716                 tpt.va_low_or_fbo = cpu_to_be32((u32) (to & 0xFFFFFFFFULL));
 717                 tpt.rsvd_bind_cnt_or_pstag = 0;
 718                 tpt.rsvd_pbl_size = cpu_to_be32(V_TPT_PBL_SIZE(pbl_size >> 2));
 719         }
 720         err = cxio_hal_ctrl_qp_write_mem(rdev_p,
 721                                        stag_idx +
 722                                        (rdev_p->rnic_info.tpt_base >> 5),
 723                                        sizeof(tpt), &tpt);
 724 
 725         /* release the stag index to free pool */
 726         if (reset_tpt_entry)
 727                 cxio_hal_put_stag(rdev_p->rscp, stag_idx);
 728 
 729         wptr = rdev_p->ctrl_qp.wptr;
 730         mutex_unlock(&rdev_p->ctrl_qp.lock);
 731         if (!err)
 732                 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 733                                              SEQ32_GE(rdev_p->ctrl_qp.rptr,
 734                                                       wptr)))
 735                         return -ERESTARTSYS;
 736         return err;
 737 }
 738 
 739 int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
 740                    u32 pbl_addr, u32 pbl_size)
 741 {
 742         u32 wptr;
 743         int err;
 744 
 745         pr_debug("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
 746                  __func__, pbl_addr, rdev_p->rnic_info.pbl_base,
 747                  pbl_size);
 748 
 749         mutex_lock(&rdev_p->ctrl_qp.lock);
 750         err = cxio_hal_ctrl_qp_write_mem(rdev_p, pbl_addr >> 5, pbl_size << 3,
 751                                          pbl);
 752         wptr = rdev_p->ctrl_qp.wptr;
 753         mutex_unlock(&rdev_p->ctrl_qp.lock);
 754         if (err)
 755                 return err;
 756 
 757         if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 758                                      SEQ32_GE(rdev_p->ctrl_qp.rptr,
 759                                               wptr)))
 760                 return -ERESTARTSYS;
 761 
 762         return 0;
 763 }
 764 
 765 int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
 766                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
 767                            u8 page_size, u32 pbl_size, u32 pbl_addr)
 768 {
 769         *stag = T3_STAG_UNSET;
 770         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
 771                              zbva, to, len, page_size, pbl_size, pbl_addr);
 772 }
 773 
 774 int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
 775                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
 776                            u8 page_size, u32 pbl_size, u32 pbl_addr)
 777 {
 778         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
 779                              zbva, to, len, page_size, pbl_size, pbl_addr);
 780 }
 781 
 782 int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
 783                    u32 pbl_addr)
 784 {
 785         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
 786                              pbl_size, pbl_addr);
 787 }
 788 
 789 int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
 790 {
 791         *stag = T3_STAG_UNSET;
 792         return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
 793                              0, 0);
 794 }
 795 
 796 int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
 797 {
 798         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
 799                              0, 0);
 800 }
 801 
 802 int cxio_allocate_stag(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr)
 803 {
 804         *stag = T3_STAG_UNSET;
 805         return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_NON_SHARED_MR,
 806                              0, 0, 0ULL, 0, 0, pbl_size, pbl_addr);
 807 }
 808 
 809 int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
 810 {
 811         struct t3_rdma_init_wr *wqe;
 812         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_ATOMIC);
 813         if (!skb)
 814                 return -ENOMEM;
 815         pr_debug("%s rdev_p %p\n", __func__, rdev_p);
 816         wqe = __skb_put(skb, sizeof(*wqe));
 817         wqe->wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT));
 818         wqe->wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(attr->tid) |
 819                                            V_FW_RIWR_LEN(sizeof(*wqe) >> 3));
 820         wqe->wrid.id1 = 0;
 821         wqe->qpid = cpu_to_be32(attr->qpid);
 822         wqe->pdid = cpu_to_be32(attr->pdid);
 823         wqe->scqid = cpu_to_be32(attr->scqid);
 824         wqe->rcqid = cpu_to_be32(attr->rcqid);
 825         wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
 826         wqe->rq_size = cpu_to_be32(attr->rq_size);
 827         wqe->mpaattrs = attr->mpaattrs;
 828         wqe->qpcaps = attr->qpcaps;
 829         wqe->ulpdu_size = cpu_to_be16(attr->tcp_emss);
 830         wqe->rqe_count = cpu_to_be16(attr->rqe_count);
 831         wqe->flags_rtr_type = cpu_to_be16(attr->flags |
 832                                           V_RTR_TYPE(attr->rtr_type) |
 833                                           V_CHAN(attr->chan));
 834         wqe->ord = cpu_to_be32(attr->ord);
 835         wqe->ird = cpu_to_be32(attr->ird);
 836         wqe->qp_dma_addr = cpu_to_be64(attr->qp_dma_addr);
 837         wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
 838         wqe->irs = cpu_to_be32(attr->irs);
 839         skb->priority = 0;      /* 0=>ToeQ; 1=>CtrlQ */
 840         return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
 841 }
 842 
 843 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
 844 {
 845         cxio_ev_cb = ev_cb;
 846 }
 847 
 848 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
 849 {
 850         cxio_ev_cb = NULL;
 851 }
 852 
 853 static int cxio_hal_ev_handler(struct t3cdev *t3cdev_p, struct sk_buff *skb)
 854 {
 855         static int cnt;
 856         struct cxio_rdev *rdev_p = NULL;
 857         struct respQ_msg_t *rsp_msg = (struct respQ_msg_t *) skb->data;
 858         pr_debug("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x se %0x notify %0x cqbranch %0x creditth %0x\n",
 859                  cnt, __func__, RSPQ_CQID(rsp_msg), RSPQ_CQPTR(rsp_msg),
 860                  RSPQ_GENBIT(rsp_msg), RSPQ_OVERFLOW(rsp_msg), RSPQ_AN(rsp_msg),
 861                  RSPQ_SE(rsp_msg), RSPQ_NOTIFY(rsp_msg), RSPQ_CQBRANCH(rsp_msg),
 862                  RSPQ_CREDIT_THRESH(rsp_msg));
 863         pr_debug("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
 864                  CQE_QPID(rsp_msg->cqe), CQE_GENBIT(rsp_msg->cqe),
 865                  CQE_TYPE(rsp_msg->cqe), CQE_STATUS(rsp_msg->cqe),
 866                  CQE_OPCODE(rsp_msg->cqe), CQE_LEN(rsp_msg->cqe),
 867                  CQE_WRID_HI(rsp_msg->cqe), CQE_WRID_LOW(rsp_msg->cqe));
 868         rdev_p = (struct cxio_rdev *)t3cdev_p->ulp;
 869         if (!rdev_p) {
 870                 pr_debug("%s called by t3cdev %p with null ulp\n", __func__,
 871                          t3cdev_p);
 872                 return 0;
 873         }
 874         if (CQE_QPID(rsp_msg->cqe) == T3_CTRL_QP_ID) {
 875                 rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
 876                 wake_up_interruptible(&rdev_p->ctrl_qp.waitq);
 877                 dev_kfree_skb_irq(skb);
 878         } else if (CQE_QPID(rsp_msg->cqe) == 0xfff8)
 879                 dev_kfree_skb_irq(skb);
 880         else if (cxio_ev_cb)
 881                 (*cxio_ev_cb) (rdev_p, skb);
 882         else
 883                 dev_kfree_skb_irq(skb);
 884         cnt++;
 885         return 0;
 886 }
 887 
 888 /* Caller takes care of locking if needed */
 889 int cxio_rdev_open(struct cxio_rdev *rdev_p)
 890 {
 891         struct net_device *netdev_p = NULL;
 892         int err = 0;
 893         if (strlen(rdev_p->dev_name)) {
 894                 if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) {
 895                         return -EBUSY;
 896                 }
 897                 netdev_p = dev_get_by_name(&init_net, rdev_p->dev_name);
 898                 if (!netdev_p) {
 899                         return -EINVAL;
 900                 }
 901                 dev_put(netdev_p);
 902         } else if (rdev_p->t3cdev_p) {
 903                 if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) {
 904                         return -EBUSY;
 905                 }
 906                 netdev_p = rdev_p->t3cdev_p->lldev;
 907                 strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name,
 908                         T3_MAX_DEV_NAME_LEN);
 909         } else {
 910                 pr_debug("%s t3cdev_p or dev_name must be set\n", __func__);
 911                 return -EINVAL;
 912         }
 913 
 914         list_add_tail(&rdev_p->entry, &rdev_list);
 915 
 916         pr_debug("%s opening rnic dev %s\n", __func__, rdev_p->dev_name);
 917         memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
 918         if (!rdev_p->t3cdev_p)
 919                 rdev_p->t3cdev_p = dev2t3cdev(netdev_p);
 920         rdev_p->t3cdev_p->ulp = (void *) rdev_p;
 921 
 922         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_EMBEDDED_INFO,
 923                                          &(rdev_p->fw_info));
 924         if (err) {
 925                 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
 926                        __func__, rdev_p->t3cdev_p, err);
 927                 goto err1;
 928         }
 929         if (G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers) != CXIO_FW_MAJ) {
 930                 pr_err("fatal firmware version mismatch: need version %u but adapter has version %u\n",
 931                        CXIO_FW_MAJ,
 932                        G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers));
 933                 err = -EINVAL;
 934                 goto err1;
 935         }
 936 
 937         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS,
 938                                          &(rdev_p->rnic_info));
 939         if (err) {
 940                 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
 941                        __func__, rdev_p->t3cdev_p, err);
 942                 goto err1;
 943         }
 944         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS,
 945                                     &(rdev_p->port_info));
 946         if (err) {
 947                 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
 948                        __func__, rdev_p->t3cdev_p, err);
 949                 goto err1;
 950         }
 951 
 952         /*
 953          * qpshift is the number of bits to shift the qpid left in order
 954          * to get the correct address of the doorbell for that qp.
 955          */
 956         cxio_init_ucontext(rdev_p, &rdev_p->uctx);
 957         rdev_p->qpshift = PAGE_SHIFT -
 958                           ilog2(65536 >>
 959                                     ilog2(rdev_p->rnic_info.udbell_len >>
 960                                               PAGE_SHIFT));
 961         rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
 962         rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
 963         pr_debug("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n",
 964                  __func__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base,
 965                  rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p),
 966                  rdev_p->rnic_info.pbl_base,
 967                  rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
 968                  rdev_p->rnic_info.rqt_top);
 969         pr_debug("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu qpnr %d qpmask 0x%x\n",
 970                  rdev_p->rnic_info.udbell_len,
 971                  rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
 972                  rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
 973 
 974         err = cxio_hal_init_ctrl_qp(rdev_p);
 975         if (err) {
 976                 pr_err("%s error %d initializing ctrl_qp\n", __func__, err);
 977                 goto err1;
 978         }
 979         err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
 980                                      0, T3_MAX_NUM_QP, T3_MAX_NUM_CQ,
 981                                      T3_MAX_NUM_PD);
 982         if (err) {
 983                 pr_err("%s error %d initializing hal resources\n",
 984                        __func__, err);
 985                 goto err2;
 986         }
 987         err = cxio_hal_pblpool_create(rdev_p);
 988         if (err) {
 989                 pr_err("%s error %d initializing pbl mem pool\n",
 990                        __func__, err);
 991                 goto err3;
 992         }
 993         err = cxio_hal_rqtpool_create(rdev_p);
 994         if (err) {
 995                 pr_err("%s error %d initializing rqt mem pool\n",
 996                        __func__, err);
 997                 goto err4;
 998         }
 999         return 0;
1000 err4:
1001         cxio_hal_pblpool_destroy(rdev_p);
1002 err3:
1003         cxio_hal_destroy_resource(rdev_p->rscp);
1004 err2:
1005         cxio_hal_destroy_ctrl_qp(rdev_p);
1006 err1:
1007         rdev_p->t3cdev_p->ulp = NULL;
1008         list_del(&rdev_p->entry);
1009         return err;
1010 }
1011 
1012 void cxio_rdev_close(struct cxio_rdev *rdev_p)
1013 {
1014         if (rdev_p) {
1015                 cxio_hal_pblpool_destroy(rdev_p);
1016                 cxio_hal_rqtpool_destroy(rdev_p);
1017                 list_del(&rdev_p->entry);
1018                 cxio_hal_destroy_ctrl_qp(rdev_p);
1019                 cxio_hal_destroy_resource(rdev_p->rscp);
1020                 rdev_p->t3cdev_p->ulp = NULL;
1021         }
1022 }
1023 
1024 int __init cxio_hal_init(void)
1025 {
1026         if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI))
1027                 return -ENOMEM;
1028         t3_register_cpl_handler(CPL_ASYNC_NOTIF, cxio_hal_ev_handler);
1029         return 0;
1030 }
1031 
1032 void __exit cxio_hal_exit(void)
1033 {
1034         struct cxio_rdev *rdev, *tmp;
1035 
1036         t3_register_cpl_handler(CPL_ASYNC_NOTIF, NULL);
1037         list_for_each_entry_safe(rdev, tmp, &rdev_list, entry)
1038                 cxio_rdev_close(rdev);
1039         cxio_hal_destroy_rhdl_resource();
1040 }
1041 
1042 static void flush_completed_wrs(struct t3_wq *wq, struct t3_cq *cq)
1043 {
1044         struct t3_swsq *sqp;
1045         __u32 ptr = wq->sq_rptr;
1046         int count = Q_COUNT(wq->sq_rptr, wq->sq_wptr);
1047 
1048         sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1049         while (count--)
1050                 if (!sqp->signaled) {
1051                         ptr++;
1052                         sqp = wq->sq + Q_PTR2IDX(ptr,  wq->sq_size_log2);
1053                 } else if (sqp->complete) {
1054 
1055                         /*
1056                          * Insert this completed cqe into the swcq.
1057                          */
1058                         pr_debug("%s moving cqe into swcq sq idx %ld cq idx %ld\n",
1059                                  __func__, Q_PTR2IDX(ptr,  wq->sq_size_log2),
1060                                  Q_PTR2IDX(cq->sw_wptr, cq->size_log2));
1061                         sqp->cqe.header |= htonl(V_CQE_SWCQE(1));
1062                         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2))
1063                                 = sqp->cqe;
1064                         cq->sw_wptr++;
1065                         sqp->signaled = 0;
1066                         break;
1067                 } else
1068                         break;
1069 }
1070 
1071 static void create_read_req_cqe(struct t3_wq *wq, struct t3_cqe *hw_cqe,
1072                                 struct t3_cqe *read_cqe)
1073 {
1074         read_cqe->u.scqe.wrid_hi = wq->oldest_read->sq_wptr;
1075         read_cqe->len = wq->oldest_read->read_len;
1076         read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(*hw_cqe)) |
1077                                  V_CQE_SWCQE(SW_CQE(*hw_cqe)) |
1078                                  V_CQE_OPCODE(T3_READ_REQ) |
1079                                  V_CQE_TYPE(1));
1080 }
1081 
1082 /*
1083  * Return a ptr to the next read wr in the SWSQ or NULL.
1084  */
1085 static void advance_oldest_read(struct t3_wq *wq)
1086 {
1087 
1088         u32 rptr = wq->oldest_read - wq->sq + 1;
1089         u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2);
1090 
1091         while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) {
1092                 wq->oldest_read = wq->sq + Q_PTR2IDX(rptr, wq->sq_size_log2);
1093 
1094                 if (wq->oldest_read->opcode == T3_READ_REQ)
1095                         return;
1096                 rptr++;
1097         }
1098         wq->oldest_read = NULL;
1099 }
1100 
1101 /*
1102  * cxio_poll_cq
1103  *
1104  * Caller must:
1105  *     check the validity of the first CQE,
1106  *     supply the wq assicated with the qpid.
1107  *
1108  * credit: cq credit to return to sge.
1109  * cqe_flushed: 1 iff the CQE is flushed.
1110  * cqe: copy of the polled CQE.
1111  *
1112  * return value:
1113  *     0       CQE returned,
1114  *    -1       CQE skipped, try again.
1115  */
1116 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
1117                      u8 *cqe_flushed, u64 *cookie, u32 *credit)
1118 {
1119         int ret = 0;
1120         struct t3_cqe *hw_cqe, read_cqe;
1121 
1122         *cqe_flushed = 0;
1123         *credit = 0;
1124         hw_cqe = cxio_next_cqe(cq);
1125 
1126         pr_debug("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
1127                  __func__, CQE_OOO(*hw_cqe), CQE_QPID(*hw_cqe),
1128                  CQE_GENBIT(*hw_cqe), CQE_TYPE(*hw_cqe), CQE_STATUS(*hw_cqe),
1129                  CQE_OPCODE(*hw_cqe), CQE_LEN(*hw_cqe), CQE_WRID_HI(*hw_cqe),
1130                  CQE_WRID_LOW(*hw_cqe));
1131 
1132         /*
1133          * skip cqe's not affiliated with a QP.
1134          */
1135         if (wq == NULL) {
1136                 ret = -1;
1137                 goto skip_cqe;
1138         }
1139 
1140         /*
1141          * Gotta tweak READ completions:
1142          *      1) the cqe doesn't contain the sq_wptr from the wr.
1143          *      2) opcode not reflected from the wr.
1144          *      3) read_len not reflected from the wr.
1145          *      4) cq_type is RQ_TYPE not SQ_TYPE.
1146          */
1147         if (RQ_TYPE(*hw_cqe) && (CQE_OPCODE(*hw_cqe) == T3_READ_RESP)) {
1148 
1149                 /*
1150                  * If this is an unsolicited read response, then the read
1151                  * was generated by the kernel driver as part of peer-2-peer
1152                  * connection setup.  So ignore the completion.
1153                  */
1154                 if (!wq->oldest_read) {
1155                         if (CQE_STATUS(*hw_cqe))
1156                                 wq->error = 1;
1157                         ret = -1;
1158                         goto skip_cqe;
1159                 }
1160 
1161                 /*
1162                  * Don't write to the HWCQ, so create a new read req CQE
1163                  * in local memory.
1164                  */
1165                 create_read_req_cqe(wq, hw_cqe, &read_cqe);
1166                 hw_cqe = &read_cqe;
1167                 advance_oldest_read(wq);
1168         }
1169 
1170         /*
1171          * T3A: Discard TERMINATE CQEs.
1172          */
1173         if (CQE_OPCODE(*hw_cqe) == T3_TERMINATE) {
1174                 ret = -1;
1175                 wq->error = 1;
1176                 goto skip_cqe;
1177         }
1178 
1179         if (CQE_STATUS(*hw_cqe) || wq->error) {
1180                 *cqe_flushed = wq->error;
1181                 wq->error = 1;
1182 
1183                 /*
1184                  * T3A inserts errors into the CQE.  We cannot return
1185                  * these as work completions.
1186                  */
1187                 /* incoming write failures */
1188                 if ((CQE_OPCODE(*hw_cqe) == T3_RDMA_WRITE)
1189                      && RQ_TYPE(*hw_cqe)) {
1190                         ret = -1;
1191                         goto skip_cqe;
1192                 }
1193                 /* incoming read request failures */
1194                 if ((CQE_OPCODE(*hw_cqe) == T3_READ_RESP) && SQ_TYPE(*hw_cqe)) {
1195                         ret = -1;
1196                         goto skip_cqe;
1197                 }
1198 
1199                 /* incoming SEND with no receive posted failures */
1200                 if (CQE_SEND_OPCODE(*hw_cqe) && RQ_TYPE(*hw_cqe) &&
1201                     Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1202                         ret = -1;
1203                         goto skip_cqe;
1204                 }
1205                 BUG_ON((*cqe_flushed == 0) && !SW_CQE(*hw_cqe));
1206                 goto proc_cqe;
1207         }
1208 
1209         /*
1210          * RECV completion.
1211          */
1212         if (RQ_TYPE(*hw_cqe)) {
1213 
1214                 /*
1215                  * HW only validates 4 bits of MSN.  So we must validate that
1216                  * the MSN in the SEND is the next expected MSN.  If its not,
1217                  * then we complete this with TPT_ERR_MSN and mark the wq in
1218                  * error.
1219                  */
1220 
1221                 if (Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1222                         wq->error = 1;
1223                         ret = -1;
1224                         goto skip_cqe;
1225                 }
1226 
1227                 if (unlikely((CQE_WRID_MSN(*hw_cqe) != (wq->rq_rptr + 1)))) {
1228                         wq->error = 1;
1229                         hw_cqe->header |= htonl(V_CQE_STATUS(TPT_ERR_MSN));
1230                         goto proc_cqe;
1231                 }
1232                 goto proc_cqe;
1233         }
1234 
1235         /*
1236          * If we get here its a send completion.
1237          *
1238          * Handle out of order completion. These get stuffed
1239          * in the SW SQ. Then the SW SQ is walked to move any
1240          * now in-order completions into the SW CQ.  This handles
1241          * 2 cases:
1242          *      1) reaping unsignaled WRs when the first subsequent
1243          *         signaled WR is completed.
1244          *      2) out of order read completions.
1245          */
1246         if (!SW_CQE(*hw_cqe) && (CQE_WRID_SQ_WPTR(*hw_cqe) != wq->sq_rptr)) {
1247                 struct t3_swsq *sqp;
1248 
1249                 pr_debug("%s out of order completion going in swsq at idx %ld\n",
1250                          __func__,
1251                          Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe),
1252                                    wq->sq_size_log2));
1253                 sqp = wq->sq +
1254                       Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2);
1255                 sqp->cqe = *hw_cqe;
1256                 sqp->complete = 1;
1257                 ret = -1;
1258                 goto flush_wq;
1259         }
1260 
1261 proc_cqe:
1262         *cqe = *hw_cqe;
1263 
1264         /*
1265          * Reap the associated WR(s) that are freed up with this
1266          * completion.
1267          */
1268         if (SQ_TYPE(*hw_cqe)) {
1269                 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
1270                 pr_debug("%s completing sq idx %ld\n", __func__,
1271                          Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
1272                 *cookie = wq->sq[Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2)].wr_id;
1273                 wq->sq_rptr++;
1274         } else {
1275                 pr_debug("%s completing rq idx %ld\n", __func__,
1276                          Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1277                 *cookie = wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].wr_id;
1278                 if (wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].pbl_addr)
1279                         cxio_hal_pblpool_free(wq->rdev,
1280                                 wq->rq[Q_PTR2IDX(wq->rq_rptr,
1281                                 wq->rq_size_log2)].pbl_addr, T3_STAG0_PBL_SIZE);
1282                 BUG_ON(Q_EMPTY(wq->rq_rptr, wq->rq_wptr));
1283                 wq->rq_rptr++;
1284         }
1285 
1286 flush_wq:
1287         /*
1288          * Flush any completed cqes that are now in-order.
1289          */
1290         flush_completed_wrs(wq, cq);
1291 
1292 skip_cqe:
1293         if (SW_CQE(*hw_cqe)) {
1294                 pr_debug("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n",
1295                          __func__, cq, cq->cqid, cq->sw_rptr);
1296                 ++cq->sw_rptr;
1297         } else {
1298                 pr_debug("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n",
1299                          __func__, cq, cq->cqid, cq->rptr);
1300                 ++cq->rptr;
1301 
1302                 /*
1303                  * T3A: compute credits.
1304                  */
1305                 if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1)))
1306                     || ((cq->rptr - cq->wptr) >= 128)) {
1307                         *credit = cq->rptr - cq->wptr;
1308                         cq->wptr = cq->rptr;
1309                 }
1310         }
1311         return ret;
1312 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/infiniband/hw/cxgb3/cxio_hal.c

DEFINITIONS
