root/drivers/infiniband/hw/hfi1/chip_registers.h

INCLUDED FROM

   1 #ifndef DEF_CHIP_REG
   2 #define DEF_CHIP_REG
   3 
   4 /*
   5  * Copyright(c) 2015, 2016 Intel Corporation.
   6  *
   7  * This file is provided under a dual BSD/GPLv2 license.  When using or
   8  * redistributing this file, you may do so under either license.
   9  *
  10  * GPL LICENSE SUMMARY
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of version 2 of the GNU General Public License as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * General Public License for more details.
  20  *
  21  * BSD LICENSE
  22  *
  23  * Redistribution and use in source and binary forms, with or without
  24  * modification, are permitted provided that the following conditions
  25  * are met:
  26  *
  27  *  - Redistributions of source code must retain the above copyright
  28  *    notice, this list of conditions and the following disclaimer.
  29  *  - Redistributions in binary form must reproduce the above copyright
  30  *    notice, this list of conditions and the following disclaimer in
  31  *    the documentation and/or other materials provided with the
  32  *    distribution.
  33  *  - Neither the name of Intel Corporation nor the names of its
  34  *    contributors may be used to endorse or promote products derived
  35  *    from this software without specific prior written permission.
  36  *
  37  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  38  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  39  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  40  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  41  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  42  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  43  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  44  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  45  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  46  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48  *
  49  */
  50 
  51 #define CORE            0x000000000000
  52 #define CCE                     (CORE + 0x000000000000)
  53 #define ASIC            (CORE + 0x000000400000)
  54 #define MISC            (CORE + 0x000000500000)
  55 #define DC_TOP_CSRS             (CORE + 0x000000600000)
  56 #define CHIP_DEBUG              (CORE + 0x000000700000)
  57 #define RXE                     (CORE + 0x000001000000)
  58 #define TXE                     (CORE + 0x000001800000)
  59 #define DCC_CSRS                (DC_TOP_CSRS + 0x000000000000)
  60 #define DC_LCB_CSRS             (DC_TOP_CSRS + 0x000000001000)
  61 #define DC_8051_CSRS            (DC_TOP_CSRS + 0x000000002000)
  62 #define PCIE            0
  63 
  64 #define ASIC_NUM_SCRATCH 4
  65 #define CCE_ERR_INT_CNT 0
  66 #define CCE_MISC_INT_CNT 2
  67 #define CCE_NUM_32_BIT_COUNTERS 3
  68 #define CCE_NUM_32_BIT_INT_COUNTERS 6
  69 #define CCE_NUM_INT_CSRS 12
  70 #define CCE_NUM_INT_MAP_CSRS 96
  71 #define CCE_NUM_MSIX_PBAS 4
  72 #define CCE_NUM_MSIX_VECTORS 256
  73 #define CCE_NUM_SCRATCH 4
  74 #define CCE_PCIE_POSTED_CRDT_STALL_CNT 2
  75 #define CCE_PCIE_TRGT_STALL_CNT 0
  76 #define CCE_PIO_WR_STALL_CNT 1
  77 #define CCE_RCV_AVAIL_INT_CNT 3
  78 #define CCE_RCV_URGENT_INT_CNT 4
  79 #define CCE_SDMA_INT_CNT 1
  80 #define CCE_SEND_CREDIT_INT_CNT 5
  81 #define DCC_CFG_LED_CNTRL (DCC_CSRS + 0x000000000040)
  82 #define DCC_CFG_LED_CNTRL_LED_CNTRL_SMASK 0x10ull
  83 #define DCC_CFG_LED_CNTRL_LED_SW_BLINK_RATE_SHIFT 0
  84 #define DCC_CFG_LED_CNTRL_LED_SW_BLINK_RATE_SMASK 0xFull
  85 #define DCC_CFG_PORT_CONFIG (DCC_CSRS + 0x000000000008)
  86 #define DCC_CFG_PORT_CONFIG1 (DCC_CSRS + 0x000000000010)
  87 #define DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK 0xFFFFull
  88 #define DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT 16
  89 #define DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK 0xFFFF0000ull
  90 #define DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK 0xFFFFull
  91 #define DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT 0
  92 #define DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK 0xFFFFull
  93 #define DCC_CFG_PORT_CONFIG_LINK_STATE_MASK 0x7ull
  94 #define DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT 48
  95 #define DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK 0x7000000000000ull
  96 #define DCC_CFG_PORT_CONFIG_MTU_CAP_MASK 0x7ull
  97 #define DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT 32
  98 #define DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK 0x700000000ull
  99 #define DCC_CFG_RESET (DCC_CSRS + 0x000000000000)
 100 #define DCC_CFG_RESET_RESET_LCB          BIT_ULL(0)
 101 #define DCC_CFG_RESET_RESET_TX_FPE       BIT_ULL(1)
 102 #define DCC_CFG_RESET_RESET_RX_FPE       BIT_ULL(2)
 103 #define DCC_CFG_RESET_RESET_8051         BIT_ULL(3)
 104 #define DCC_CFG_RESET_ENABLE_CCLK_BCC    BIT_ULL(4)
 105 #define DCC_CFG_SC_VL_TABLE_15_0 (DCC_CSRS + 0x000000000028)
 106 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY0_SHIFT 0
 107 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY10_SHIFT 40
 108 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY11_SHIFT 44
 109 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY12_SHIFT 48
 110 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY13_SHIFT 52
 111 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY14_SHIFT 56
 112 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY15_SHIFT 60
 113 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY1_SHIFT 4
 114 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY2_SHIFT 8
 115 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY3_SHIFT 12
 116 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY4_SHIFT 16
 117 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY5_SHIFT 20
 118 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY6_SHIFT 24
 119 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY7_SHIFT 28
 120 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY8_SHIFT 32
 121 #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY9_SHIFT 36
 122 #define DCC_CFG_SC_VL_TABLE_31_16 (DCC_CSRS + 0x000000000030)
 123 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY16_SHIFT 0
 124 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY17_SHIFT 4
 125 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY18_SHIFT 8
 126 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY19_SHIFT 12
 127 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY20_SHIFT 16
 128 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY21_SHIFT 20
 129 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY22_SHIFT 24
 130 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY23_SHIFT 28
 131 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY24_SHIFT 32
 132 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY25_SHIFT 36
 133 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY26_SHIFT 40
 134 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY27_SHIFT 44
 135 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY28_SHIFT 48
 136 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY29_SHIFT 52
 137 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY30_SHIFT 56
 138 #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY31_SHIFT 60
 139 #define DCC_ERR_DROPPED_PKT_CNT (DCC_CSRS + 0x000000000120)
 140 #define DCC_ERR_FLG (DCC_CSRS + 0x000000000050)
 141 #define DCC_ERR_FLG_BAD_CRDT_ACK_ERR_SMASK 0x4000ull
 142 #define DCC_ERR_FLG_BAD_CTRL_DIST_ERR_SMASK 0x200000ull
 143 #define DCC_ERR_FLG_BAD_CTRL_FLIT_ERR_SMASK 0x10000ull
 144 #define DCC_ERR_FLG_BAD_DLID_TARGET_ERR_SMASK 0x200ull
 145 #define DCC_ERR_FLG_BAD_HEAD_DIST_ERR_SMASK 0x800000ull
 146 #define DCC_ERR_FLG_BAD_L2_ERR_SMASK 0x2ull
 147 #define DCC_ERR_FLG_BAD_LVER_ERR_SMASK 0x400ull
 148 #define DCC_ERR_FLG_BAD_MID_TAIL_ERR_SMASK 0x8ull
 149 #define DCC_ERR_FLG_BAD_PKT_LENGTH_ERR_SMASK 0x4000000ull
 150 #define DCC_ERR_FLG_BAD_PREEMPTION_ERR_SMASK 0x10ull
 151 #define DCC_ERR_FLG_BAD_SC_ERR_SMASK 0x4ull
 152 #define DCC_ERR_FLG_BAD_TAIL_DIST_ERR_SMASK 0x400000ull
 153 #define DCC_ERR_FLG_BAD_VL_MARKER_ERR_SMASK 0x80ull
 154 #define DCC_ERR_FLG_CLR (DCC_CSRS + 0x000000000060)
 155 #define DCC_ERR_FLG_CSR_ACCESS_BLOCKED_HOST_SMASK 0x8000000000ull
 156 #define DCC_ERR_FLG_CSR_ACCESS_BLOCKED_UC_SMASK 0x10000000000ull
 157 #define DCC_ERR_FLG_CSR_INVAL_ADDR_SMASK 0x400000000000ull
 158 #define DCC_ERR_FLG_CSR_PARITY_ERR_SMASK 0x200000000000ull
 159 #define DCC_ERR_FLG_DLID_ZERO_ERR_SMASK 0x40000000ull
 160 #define DCC_ERR_FLG_EN (DCC_CSRS + 0x000000000058)
 161 #define DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK 0x8000000000ull
 162 #define DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK 0x10000000000ull
 163 #define DCC_ERR_FLG_EVENT_CNTR_PARITY_ERR_SMASK 0x20000ull
 164 #define DCC_ERR_FLG_EVENT_CNTR_ROLLOVER_ERR_SMASK 0x40000ull
 165 #define DCC_ERR_FLG_FMCONFIG_ERR_SMASK 0x40000000000000ull
 166 #define DCC_ERR_FLG_FPE_TX_FIFO_OVFLW_ERR_SMASK 0x2000000000ull
 167 #define DCC_ERR_FLG_FPE_TX_FIFO_UNFLW_ERR_SMASK 0x4000000000ull
 168 #define DCC_ERR_FLG_LATE_EBP_ERR_SMASK 0x1000000000ull
 169 #define DCC_ERR_FLG_LATE_LONG_ERR_SMASK 0x800000000ull
 170 #define DCC_ERR_FLG_LATE_SHORT_ERR_SMASK 0x400000000ull
 171 #define DCC_ERR_FLG_LENGTH_MTU_ERR_SMASK 0x80000000ull
 172 #define DCC_ERR_FLG_LINK_ERR_SMASK 0x80000ull
 173 #define DCC_ERR_FLG_MISC_CNTR_ROLLOVER_ERR_SMASK 0x100000ull
 174 #define DCC_ERR_FLG_NONVL15_STATE_ERR_SMASK 0x1000000ull
 175 #define DCC_ERR_FLG_PERM_NVL15_ERR_SMASK 0x10000000ull
 176 #define DCC_ERR_FLG_PREEMPTION_ERR_SMASK 0x20ull
 177 #define DCC_ERR_FLG_PREEMPTIONVL15_ERR_SMASK 0x40ull
 178 #define DCC_ERR_FLG_RCVPORT_ERR_SMASK 0x80000000000000ull
 179 #define DCC_ERR_FLG_RX_BYTE_SHFT_PARITY_ERR_SMASK 0x1000000000000ull
 180 #define DCC_ERR_FLG_RX_CTRL_PARITY_MBE_ERR_SMASK 0x100000000000ull
 181 #define DCC_ERR_FLG_RX_EARLY_DROP_ERR_SMASK 0x200000000ull
 182 #define DCC_ERR_FLG_SLID_ZERO_ERR_SMASK 0x20000000ull
 183 #define DCC_ERR_FLG_TX_BYTE_SHFT_PARITY_ERR_SMASK 0x800000000000ull
 184 #define DCC_ERR_FLG_TX_CTRL_PARITY_ERR_SMASK 0x20000000000ull
 185 #define DCC_ERR_FLG_TX_CTRL_PARITY_MBE_ERR_SMASK 0x40000000000ull
 186 #define DCC_ERR_FLG_TX_SC_PARITY_ERR_SMASK 0x80000000000ull
 187 #define DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK 0x2000ull
 188 #define DCC_ERR_FLG_UNSUP_PKT_TYPE_SMASK 0x8000ull
 189 #define DCC_ERR_FLG_UNSUP_VL_ERR_SMASK 0x8000000ull
 190 #define DCC_ERR_FLG_VL15_MULTI_ERR_SMASK 0x2000000ull
 191 #define DCC_ERR_FMCONFIG_ERR_CNT (DCC_CSRS + 0x000000000110)
 192 #define DCC_ERR_INFO_FMCONFIG (DCC_CSRS + 0x000000000090)
 193 #define DCC_ERR_INFO_PORTRCV (DCC_CSRS + 0x000000000078)
 194 #define DCC_ERR_INFO_PORTRCV_HDR0 (DCC_CSRS + 0x000000000080)
 195 #define DCC_ERR_INFO_PORTRCV_HDR1 (DCC_CSRS + 0x000000000088)
 196 #define DCC_ERR_INFO_UNCORRECTABLE (DCC_CSRS + 0x000000000098)
 197 #define DCC_ERR_PORTRCV_ERR_CNT (DCC_CSRS + 0x000000000108)
 198 #define DCC_ERR_RCVREMOTE_PHY_ERR_CNT (DCC_CSRS + 0x000000000118)
 199 #define DCC_ERR_UNCORRECTABLE_CNT (DCC_CSRS + 0x000000000100)
 200 #define DCC_PRF_PORT_MARK_FECN_CNT (DCC_CSRS + 0x000000000330)
 201 #define DCC_PRF_PORT_RCV_BECN_CNT (DCC_CSRS + 0x000000000290)
 202 #define DCC_PRF_PORT_RCV_BUBBLE_CNT (DCC_CSRS + 0x0000000002E0)
 203 #define DCC_PRF_PORT_RCV_CORRECTABLE_CNT (DCC_CSRS + 0x000000000140)
 204 #define DCC_PRF_PORT_RCV_DATA_CNT (DCC_CSRS + 0x000000000198)
 205 #define DCC_PRF_PORT_RCV_FECN_CNT (DCC_CSRS + 0x000000000240)
 206 #define DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT (DCC_CSRS + 0x000000000130)
 207 #define DCC_PRF_PORT_RCV_PKTS_CNT (DCC_CSRS + 0x0000000001A8)
 208 #define DCC_PRF_PORT_VL_MARK_FECN_CNT (DCC_CSRS + 0x000000000338)
 209 #define DCC_PRF_PORT_VL_RCV_BECN_CNT (DCC_CSRS + 0x000000000298)
 210 #define DCC_PRF_PORT_VL_RCV_BUBBLE_CNT (DCC_CSRS + 0x0000000002E8)
 211 #define DCC_PRF_PORT_VL_RCV_DATA_CNT (DCC_CSRS + 0x0000000001B0)
 212 #define DCC_PRF_PORT_VL_RCV_FECN_CNT (DCC_CSRS + 0x000000000248)
 213 #define DCC_PRF_PORT_VL_RCV_PKTS_CNT (DCC_CSRS + 0x0000000001F8)
 214 #define DCC_PRF_PORT_XMIT_CORRECTABLE_CNT (DCC_CSRS + 0x000000000138)
 215 #define DCC_PRF_PORT_XMIT_DATA_CNT (DCC_CSRS + 0x000000000190)
 216 #define DCC_PRF_PORT_XMIT_MULTICAST_CNT (DCC_CSRS + 0x000000000128)
 217 #define DCC_PRF_PORT_XMIT_PKTS_CNT (DCC_CSRS + 0x0000000001A0)
 218 #define DCC_PRF_RX_FLOW_CRTL_CNT (DCC_CSRS + 0x000000000180)
 219 #define DCC_PRF_TX_FLOW_CRTL_CNT (DCC_CSRS + 0x000000000188)
 220 #define DC_DC8051_CFG_CSR_ACCESS_SEL (DC_8051_CSRS + 0x000000000110)
 221 #define DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK 0x2ull
 222 #define DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK 0x1ull
 223 #define DC_DC8051_CFG_EXT_DEV_0 (DC_8051_CSRS + 0x000000000118)
 224 #define DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK 0x1ull
 225 #define DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT 8
 226 #define DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT 16
 227 #define DC_DC8051_CFG_EXT_DEV_1 (DC_8051_CSRS + 0x000000000120)
 228 #define DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK 0xFFFFull
 229 #define DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT 16
 230 #define DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK 0xFFFF0000ull
 231 #define DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK 0x1ull
 232 #define DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK 0xFFull
 233 #define DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT 8
 234 #define DC_DC8051_CFG_HOST_CMD_0 (DC_8051_CSRS + 0x000000000028)
 235 #define DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK 0xFFFFFFFFFFFFull
 236 #define DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT 16
 237 #define DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK 0x1ull
 238 #define DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK 0xFFull
 239 #define DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT 8
 240 #define DC_DC8051_CFG_HOST_CMD_1 (DC_8051_CSRS + 0x000000000030)
 241 #define DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK 0x1ull
 242 #define DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK 0xFFull
 243 #define DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT 8
 244 #define DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK 0xFFFFFFFFFFFFull
 245 #define DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT 16
 246 #define DC_DC8051_CFG_LOCAL_GUID (DC_8051_CSRS + 0x000000000038)
 247 #define DC_DC8051_CFG_MODE (DC_8051_CSRS + 0x000000000070)
 248 #define DC_DC8051_CFG_RAM_ACCESS_CTRL (DC_8051_CSRS + 0x000000000008)
 249 #define DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK 0x7FFFull
 250 #define DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT 0
 251 #define DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK 0x1000000ull
 252 #define DC_DC8051_CFG_RAM_ACCESS_CTRL_READ_ENA_SMASK 0x10000ull
 253 #define DC_DC8051_CFG_RAM_ACCESS_SETUP (DC_8051_CSRS + 0x000000000000)
 254 #define DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK 0x100ull
 255 #define DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK 0x1ull
 256 #define DC_DC8051_CFG_RAM_ACCESS_STATUS (DC_8051_CSRS + 0x000000000018)
 257 #define DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK 0x10000ull
 258 #define DC_DC8051_CFG_RAM_ACCESS_WR_DATA (DC_8051_CSRS + 0x000000000010)
 259 #define DC_DC8051_CFG_RAM_ACCESS_RD_DATA (DC_8051_CSRS + 0x000000000020)
 260 #define DC_DC8051_CFG_RST (DC_8051_CSRS + 0x000000000068)
 261 #define DC_DC8051_CFG_RST_CRAM_SMASK 0x2ull
 262 #define DC_DC8051_CFG_RST_DRAM_SMASK 0x4ull
 263 #define DC_DC8051_CFG_RST_IRAM_SMASK 0x8ull
 264 #define DC_DC8051_CFG_RST_M8051W_SMASK 0x1ull
 265 #define DC_DC8051_CFG_RST_SFR_SMASK 0x10ull
 266 #define DC_DC8051_DBG_ERR_INFO_SET_BY_8051 (DC_8051_CSRS + 0x0000000000D8)
 267 #define DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK 0xFFFFFFFFull
 268 #define DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT 16
 269 #define DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK 0xFFFFull
 270 #define DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT 0
 271 #define DC_DC8051_ERR_CLR (DC_8051_CSRS + 0x0000000000E8)
 272 #define DC_DC8051_ERR_EN (DC_8051_CSRS + 0x0000000000F0)
 273 #define DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK 0x2ull
 274 #define DC_DC8051_ERR_FLG (DC_8051_CSRS + 0x0000000000E0)
 275 #define DC_DC8051_ERR_FLG_CRAM_MBE_SMASK 0x4ull
 276 #define DC_DC8051_ERR_FLG_CRAM_SBE_SMASK 0x8ull
 277 #define DC_DC8051_ERR_FLG_DRAM_MBE_SMASK 0x10ull
 278 #define DC_DC8051_ERR_FLG_DRAM_SBE_SMASK 0x20ull
 279 #define DC_DC8051_ERR_FLG_INVALID_CSR_ADDR_SMASK 0x400ull
 280 #define DC_DC8051_ERR_FLG_IRAM_MBE_SMASK 0x40ull
 281 #define DC_DC8051_ERR_FLG_IRAM_SBE_SMASK 0x80ull
 282 #define DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK 0x2ull
 283 #define DC_DC8051_ERR_FLG_SET_BY_8051_SMASK 0x1ull
 284 #define DC_DC8051_ERR_FLG_UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES_SMASK 0x100ull
 285 #define DC_DC8051_STS_CUR_STATE (DC_8051_CSRS + 0x000000000060)
 286 #define DC_DC8051_STS_CUR_STATE_FIRMWARE_MASK 0xFFull
 287 #define DC_DC8051_STS_CUR_STATE_FIRMWARE_SHIFT 16
 288 #define DC_DC8051_STS_CUR_STATE_PORT_MASK 0xFFull
 289 #define DC_DC8051_STS_CUR_STATE_PORT_SHIFT 0
 290 #define DC_DC8051_STS_LOCAL_FM_SECURITY (DC_8051_CSRS + 0x000000000050)
 291 #define DC_DC8051_STS_LOCAL_FM_SECURITY_DISABLED_MASK 0x1ull
 292 #define DC_DC8051_STS_REMOTE_FM_SECURITY (DC_8051_CSRS + 0x000000000058)
 293 #define DC_DC8051_STS_REMOTE_GUID (DC_8051_CSRS + 0x000000000040)
 294 #define DC_DC8051_STS_REMOTE_NODE_TYPE (DC_8051_CSRS + 0x000000000048)
 295 #define DC_DC8051_STS_REMOTE_NODE_TYPE_VAL_MASK 0x3ull
 296 #define DC_DC8051_STS_REMOTE_PORT_NO (DC_8051_CSRS + 0x000000000130)
 297 #define DC_DC8051_STS_REMOTE_PORT_NO_VAL_SMASK 0xFFull
 298 #define DC_LCB_CFG_ALLOW_LINK_UP (DC_LCB_CSRS + 0x000000000128)
 299 #define DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT 0
 300 #define DC_LCB_CFG_CRC_MODE (DC_LCB_CSRS + 0x000000000058)
 301 #define DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT 0
 302 #define DC_LCB_CFG_IGNORE_LOST_RCLK (DC_LCB_CSRS + 0x000000000020)
 303 #define DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK 0x1ull
 304 #define DC_LCB_CFG_LANE_WIDTH (DC_LCB_CSRS + 0x000000000100)
 305 #define DC_LCB_CFG_LINK_KILL_EN (DC_LCB_CSRS + 0x000000000120)
 306 #define DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK 0x100000ull
 307 #define DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK 0x400000ull
 308 #define DC_LCB_CFG_LN_DCLK (DC_LCB_CSRS + 0x000000000060)
 309 #define DC_LCB_CFG_LOOPBACK (DC_LCB_CSRS + 0x0000000000F8)
 310 #define DC_LCB_CFG_LOOPBACK_VAL_SHIFT 0
 311 #define DC_LCB_CFG_RUN (DC_LCB_CSRS + 0x000000000000)
 312 #define DC_LCB_CFG_RUN_EN_SHIFT 0
 313 #define DC_LCB_CFG_RX_FIFOS_RADR (DC_LCB_CSRS + 0x000000000018)
 314 #define DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 8
 315 #define DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 4
 316 #define DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT 0
 317 #define DC_LCB_CFG_TX_FIFOS_RADR (DC_LCB_CSRS + 0x000000000010)
 318 #define DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT 0
 319 #define DC_LCB_CFG_TX_FIFOS_RESET (DC_LCB_CSRS + 0x000000000008)
 320 #define DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT 0
 321 #define DC_LCB_CFG_REINIT_AS_SLAVE (DC_LCB_CSRS + 0x000000000030)
 322 #define DC_LCB_CFG_CNT_FOR_SKIP_STALL (DC_LCB_CSRS + 0x000000000040)
 323 #define DC_LCB_CFG_CLK_CNTR (DC_LCB_CSRS + 0x000000000110)
 324 #define DC_LCB_ERR_CLR (DC_LCB_CSRS + 0x000000000308)
 325 #define DC_LCB_ERR_EN (DC_LCB_CSRS + 0x000000000310)
 326 #define DC_LCB_ERR_FLG (DC_LCB_CSRS + 0x000000000300)
 327 #define DC_LCB_ERR_FLG_REDUNDANT_FLIT_PARITY_ERR_SMASK 0x20000000ull
 328 #define DC_LCB_ERR_FLG_NEG_EDGE_LINK_TRANSFER_ACTIVE_SMASK 0x10000000ull
 329 #define DC_LCB_ERR_FLG_HOLD_REINIT_SMASK 0x8000000ull
 330 #define DC_LCB_ERR_FLG_RST_FOR_INCOMPLT_RND_TRIP_SMASK 0x4000000ull
 331 #define DC_LCB_ERR_FLG_RST_FOR_LINK_TIMEOUT_SMASK 0x2000000ull
 332 #define DC_LCB_ERR_FLG_CREDIT_RETURN_FLIT_MBE_SMASK 0x1000000ull
 333 #define DC_LCB_ERR_FLG_REPLAY_BUF_SBE_SMASK 0x800000ull
 334 #define DC_LCB_ERR_FLG_REPLAY_BUF_MBE_SMASK 0x400000ull
 335 #define DC_LCB_ERR_FLG_FLIT_INPUT_BUF_SBE_SMASK 0x200000ull
 336 #define DC_LCB_ERR_FLG_FLIT_INPUT_BUF_MBE_SMASK 0x100000ull
 337 #define DC_LCB_ERR_FLG_VL_ACK_INPUT_WRONG_CRC_MODE_SMASK 0x80000ull
 338 #define DC_LCB_ERR_FLG_VL_ACK_INPUT_PARITY_ERR_SMASK 0x40000ull
 339 #define DC_LCB_ERR_FLG_VL_ACK_INPUT_BUF_OFLW_SMASK 0x20000ull
 340 #define DC_LCB_ERR_FLG_FLIT_INPUT_BUF_OFLW_SMASK 0x10000ull
 341 #define DC_LCB_ERR_FLG_ILLEGAL_FLIT_ENCODING_SMASK 0x8000ull
 342 #define DC_LCB_ERR_FLG_ILLEGAL_NULL_LTP_SMASK 0x4000ull
 343 #define DC_LCB_ERR_FLG_UNEXPECTED_ROUND_TRIP_MARKER_SMASK 0x2000ull
 344 #define DC_LCB_ERR_FLG_UNEXPECTED_REPLAY_MARKER_SMASK 0x1000ull
 345 #define DC_LCB_ERR_FLG_RCLK_STOPPED_SMASK 0x800ull
 346 #define DC_LCB_ERR_FLG_CRC_ERR_CNT_HIT_LIMIT_SMASK 0x400ull
 347 #define DC_LCB_ERR_FLG_REINIT_FOR_LN_DEGRADE_SMASK 0x200ull
 348 #define DC_LCB_ERR_FLG_REINIT_FROM_PEER_SMASK 0x100ull
 349 #define DC_LCB_ERR_FLG_SEQ_CRC_ERR_SMASK 0x80ull
 350 #define DC_LCB_ERR_FLG_RX_LESS_THAN_FOUR_LNS_SMASK 0x40ull
 351 #define DC_LCB_ERR_FLG_TX_LESS_THAN_FOUR_LNS_SMASK 0x20ull
 352 #define DC_LCB_ERR_FLG_LOST_REINIT_STALL_OR_TOS_SMASK 0x10ull
 353 #define DC_LCB_ERR_FLG_ALL_LNS_FAILED_REINIT_TEST_SMASK 0x8ull
 354 #define DC_LCB_ERR_FLG_RST_FOR_FAILED_DESKEW_SMASK 0x4ull
 355 #define DC_LCB_ERR_FLG_INVALID_CSR_ADDR_SMASK 0x2ull
 356 #define DC_LCB_ERR_FLG_CSR_PARITY_ERR_SMASK 0x1ull
 357 #define DC_LCB_ERR_INFO_CRC_ERR_LN0 (DC_LCB_CSRS + 0x000000000328)
 358 #define DC_LCB_ERR_INFO_CRC_ERR_LN1 (DC_LCB_CSRS + 0x000000000330)
 359 #define DC_LCB_ERR_INFO_CRC_ERR_LN2 (DC_LCB_CSRS + 0x000000000338)
 360 #define DC_LCB_ERR_INFO_CRC_ERR_LN3 (DC_LCB_CSRS + 0x000000000340)
 361 #define DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN (DC_LCB_CSRS + 0x000000000348)
 362 #define DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT (DC_LCB_CSRS + 0x000000000368)
 363 #define DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT (DC_LCB_CSRS + 0x000000000370)
 364 #define DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT (DC_LCB_CSRS + 0x000000000378)
 365 #define DC_LCB_ERR_INFO_MISC_FLG_CNT (DC_LCB_CSRS + 0x000000000390)
 366 #define DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT (DC_LCB_CSRS + 0x000000000380)
 367 #define DC_LCB_ERR_INFO_RX_REPLAY_CNT (DC_LCB_CSRS + 0x000000000358)
 368 #define DC_LCB_ERR_INFO_SBE_CNT (DC_LCB_CSRS + 0x000000000388)
 369 #define DC_LCB_ERR_INFO_SEQ_CRC_CNT (DC_LCB_CSRS + 0x000000000360)
 370 #define DC_LCB_ERR_INFO_TOTAL_CRC_ERR (DC_LCB_CSRS + 0x000000000320)
 371 #define DC_LCB_ERR_INFO_TX_REPLAY_CNT (DC_LCB_CSRS + 0x000000000350)
 372 #define DC_LCB_PG_DBG_FLIT_CRDTS_CNT (DC_LCB_CSRS + 0x000000000580)
 373 #define DC_LCB_PG_STS_PAUSE_COMPLETE_CNT (DC_LCB_CSRS + 0x0000000005F8)
 374 #define DC_LCB_PG_STS_TX_MBE_CNT (DC_LCB_CSRS + 0x000000000608)
 375 #define DC_LCB_PG_STS_TX_SBE_CNT (DC_LCB_CSRS + 0x000000000600)
 376 #define DC_LCB_PRF_ACCEPTED_LTP_CNT (DC_LCB_CSRS + 0x000000000408)
 377 #define DC_LCB_PRF_CLK_CNTR (DC_LCB_CSRS + 0x000000000420)
 378 #define DC_LCB_PRF_GOOD_LTP_CNT (DC_LCB_CSRS + 0x000000000400)
 379 #define DC_LCB_PRF_RX_FLIT_CNT (DC_LCB_CSRS + 0x000000000410)
 380 #define DC_LCB_PRF_TX_FLIT_CNT (DC_LCB_CSRS + 0x000000000418)
 381 #define DC_LCB_STS_LINK_TRANSFER_ACTIVE (DC_LCB_CSRS + 0x000000000468)
 382 #define DC_LCB_STS_ROUND_TRIP_LTP_CNT (DC_LCB_CSRS + 0x0000000004B0)
 383 #define RCV_LENGTH_ERR_CNT 0
 384 #define RCV_SHORT_ERR_CNT 2
 385 #define RCV_ICRC_ERR_CNT 6
 386 #define RCV_EBP_CNT 9
 387 #define RCV_BUF_OVFL_CNT 10
 388 #define RCV_CONTEXT_EGR_STALL 22
 389 #define RCV_DATA_PKT_CNT 0
 390 #define RCV_DWORD_CNT 1
 391 #define RCV_TID_FLOW_GEN_MISMATCH_CNT 20
 392 #define RCV_TID_FLOW_SEQ_MISMATCH_CNT 23
 393 #define RCV_TID_FULL_ERR_CNT 18
 394 #define RCV_TID_VALID_ERR_CNT 19
 395 #define RXE_NUM_32_BIT_COUNTERS 24
 396 #define RXE_NUM_64_BIT_COUNTERS 2
 397 #define RXE_NUM_RSM_INSTANCES 4
 398 #define RXE_NUM_TID_FLOWS 32
 399 #define RXE_PER_CONTEXT_OFFSET 0x0300000
 400 #define SEND_DATA_PKT_CNT 0
 401 #define SEND_DATA_PKT_VL0_CNT 12
 402 #define SEND_DATA_VL0_CNT 3
 403 #define SEND_DROPPED_PKT_CNT 5
 404 #define SEND_DWORD_CNT 1
 405 #define SEND_FLOW_STALL_CNT 4
 406 #define SEND_HEADERS_ERR_CNT 6
 407 #define SEND_LEN_ERR_CNT 1
 408 #define SEND_MAX_MIN_LEN_ERR_CNT 2
 409 #define SEND_UNDERRUN_CNT 3
 410 #define SEND_UNSUP_VL_ERR_CNT 0
 411 #define SEND_WAIT_CNT 2
 412 #define SEND_WAIT_VL0_CNT 21
 413 #define TXE_PIO_SEND_OFFSET 0x0800000
 414 #define ASIC_CFG_DRV_STR (ASIC + 0x000000000048)
 415 #define ASIC_CFG_MUTEX (ASIC + 0x000000000040)
 416 #define ASIC_CFG_SBUS_EXECUTE (ASIC + 0x000000000008)
 417 #define ASIC_CFG_SBUS_EXECUTE_EXECUTE_SMASK 0x1ull
 418 #define ASIC_CFG_SBUS_EXECUTE_FAST_MODE_SMASK 0x2ull
 419 #define ASIC_CFG_SBUS_REQUEST (ASIC + 0x000000000000)
 420 #define ASIC_CFG_SBUS_REQUEST_COMMAND_SHIFT 16
 421 #define ASIC_CFG_SBUS_REQUEST_DATA_ADDR_SHIFT 8
 422 #define ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT 32
 423 #define ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT 0
 424 #define ASIC_CFG_SCRATCH (ASIC + 0x000000000020)
 425 #define ASIC_CFG_SCRATCH_1 (ASIC_CFG_SCRATCH + 0x08)
 426 #define ASIC_CFG_SCRATCH_2 (ASIC_CFG_SCRATCH + 0x10)
 427 #define ASIC_CFG_SCRATCH_3 (ASIC_CFG_SCRATCH + 0x18)
 428 #define ASIC_CFG_THERM_POLL_EN (ASIC + 0x000000000050)
 429 #define ASIC_EEP_ADDR_CMD (ASIC + 0x000000000308)
 430 #define ASIC_EEP_ADDR_CMD_EP_ADDR_MASK 0xFFFFFFull
 431 #define ASIC_EEP_CTL_STAT (ASIC + 0x000000000300)
 432 #define ASIC_EEP_CTL_STAT_EP_RESET_SMASK 0x4ull
 433 #define ASIC_EEP_CTL_STAT_RATE_SPI_SHIFT 8
 434 #define ASIC_EEP_CTL_STAT_RESETCSR 0x0000000083818000ull
 435 #define ASIC_EEP_DATA (ASIC + 0x000000000310)
 436 #define ASIC_GPIO_CLEAR (ASIC + 0x000000000230)
 437 #define ASIC_GPIO_FORCE (ASIC + 0x000000000238)
 438 #define ASIC_GPIO_IN (ASIC + 0x000000000200)
 439 #define ASIC_GPIO_INVERT (ASIC + 0x000000000210)
 440 #define ASIC_GPIO_MASK (ASIC + 0x000000000220)
 441 #define ASIC_GPIO_OE (ASIC + 0x000000000208)
 442 #define ASIC_GPIO_OUT (ASIC + 0x000000000218)
 443 #define ASIC_PCIE_SD_HOST_CMD (ASIC + 0x000000000100)
 444 #define ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT 0
 445 #define ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK 0x400ull
 446 #define ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT 2
 447 #define ASIC_PCIE_SD_HOST_CMD_TIMER_MASK 0xFFFFFull
 448 #define ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT 12
 449 #define ASIC_PCIE_SD_HOST_STATUS (ASIC + 0x000000000108)
 450 #define ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK 0x7ull
 451 #define ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT 2
 452 #define ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK 0x3ull
 453 #define ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT 0
 454 #define ASIC_PCIE_SD_INTRPT_DATA_CODE (ASIC + 0x000000000110)
 455 #define ASIC_PCIE_SD_INTRPT_ENABLE (ASIC + 0x000000000118)
 456 #define ASIC_PCIE_SD_INTRPT_LIST (ASIC + 0x000000000180)
 457 #define ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT 16
 458 #define ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT 0
 459 #define ASIC_PCIE_SD_INTRPT_STATUS (ASIC + 0x000000000128)
 460 #define ASIC_QSFP1_CLEAR (ASIC + 0x000000000270)
 461 #define ASIC_QSFP1_FORCE (ASIC + 0x000000000278)
 462 #define ASIC_QSFP1_IN (ASIC + 0x000000000240)
 463 #define ASIC_QSFP1_INVERT (ASIC + 0x000000000250)
 464 #define ASIC_QSFP1_MASK (ASIC + 0x000000000260)
 465 #define ASIC_QSFP1_OE (ASIC + 0x000000000248)
 466 #define ASIC_QSFP1_OUT (ASIC + 0x000000000258)
 467 #define ASIC_QSFP1_STATUS (ASIC + 0x000000000268)
 468 #define ASIC_QSFP2_CLEAR (ASIC + 0x0000000002B0)
 469 #define ASIC_QSFP2_FORCE (ASIC + 0x0000000002B8)
 470 #define ASIC_QSFP2_IN (ASIC + 0x000000000280)
 471 #define ASIC_QSFP2_INVERT (ASIC + 0x000000000290)
 472 #define ASIC_QSFP2_MASK (ASIC + 0x0000000002A0)
 473 #define ASIC_QSFP2_OE (ASIC + 0x000000000288)
 474 #define ASIC_QSFP2_OUT (ASIC + 0x000000000298)
 475 #define ASIC_QSFP2_STATUS (ASIC + 0x0000000002A8)
 476 #define ASIC_STS_SBUS_COUNTERS (ASIC + 0x000000000018)
 477 #define ASIC_STS_SBUS_COUNTERS_EXECUTE_CNT_MASK 0xFFFFull
 478 #define ASIC_STS_SBUS_COUNTERS_EXECUTE_CNT_SHIFT 0
 479 #define ASIC_STS_SBUS_COUNTERS_RCV_DATA_VALID_CNT_MASK 0xFFFFull
 480 #define ASIC_STS_SBUS_COUNTERS_RCV_DATA_VALID_CNT_SHIFT 16
 481 #define ASIC_STS_SBUS_RESULT (ASIC + 0x000000000010)
 482 #define ASIC_STS_SBUS_RESULT_DONE_SMASK 0x1ull
 483 #define ASIC_STS_SBUS_RESULT_RCV_DATA_VALID_SMASK 0x2ull
 484 #define ASIC_STS_SBUS_RESULT_RESULT_CODE_SHIFT 2
 485 #define ASIC_STS_SBUS_RESULT_RESULT_CODE_MASK 0x7ull
 486 #define ASIC_STS_SBUS_RESULT_DATA_OUT_SHIFT 32
 487 #define ASIC_STS_SBUS_RESULT_DATA_OUT_MASK 0xFFFFFFFFull
 488 #define ASIC_STS_THERM (ASIC + 0x000000000058)
 489 #define ASIC_STS_THERM_CRIT_TEMP_MASK 0x7FFull
 490 #define ASIC_STS_THERM_CRIT_TEMP_SHIFT 18
 491 #define ASIC_STS_THERM_CURR_TEMP_MASK 0x7FFull
 492 #define ASIC_STS_THERM_CURR_TEMP_SHIFT 2
 493 #define ASIC_STS_THERM_HI_TEMP_MASK 0x7FFull
 494 #define ASIC_STS_THERM_HI_TEMP_SHIFT 50
 495 #define ASIC_STS_THERM_LO_TEMP_MASK 0x7FFull
 496 #define ASIC_STS_THERM_LO_TEMP_SHIFT 34
 497 #define ASIC_STS_THERM_LOW_SHIFT 13
 498 #define CCE_COUNTER_ARRAY32 (CCE + 0x000000000060)
 499 #define CCE_CTRL (CCE + 0x000000000010)
 500 #define CCE_CTRL_RXE_RESUME_SMASK 0x800ull
 501 #define CCE_CTRL_SPC_FREEZE_SMASK 0x100ull
 502 #define CCE_CTRL_SPC_UNFREEZE_SMASK 0x200ull
 503 #define CCE_CTRL_TXE_RESUME_SMASK 0x2000ull
 504 #define CCE_DC_CTRL (CCE + 0x0000000000B8)
 505 #define CCE_DC_CTRL_DC_RESET_SMASK 0x1ull
 506 #define CCE_DC_CTRL_RESETCSR 0x0000000000000001ull
 507 #define CCE_ERR_CLEAR (CCE + 0x000000000050)
 508 #define CCE_ERR_MASK (CCE + 0x000000000048)
 509 #define CCE_ERR_STATUS (CCE + 0x000000000040)
 510 #define CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK 0x40ull
 511 #define CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK 0x1000ull
 512 #define CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK \
 513                 0x200ull
 514 #define CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK \
 515                 0x800ull
 516 #define CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK \
 517                 0x400ull
 518 #define CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK 0x100ull
 519 #define CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK 0x80ull
 520 #define CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK 0x1ull
 521 #define CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK 0x2ull
 522 #define CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK 0x4ull
 523 #define CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK 0x4000000000ull
 524 #define CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK 0x8000000000ull
 525 #define CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK 0x10000000000ull
 526 #define CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK 0x1000000000ull
 527 #define CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK 0x2000000000ull
 528 #define CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK 0x400000000ull
 529 #define CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK 0x20ull
 530 #define CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK 0x800000000ull
 531 #define CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK 0x100000000ull
 532 #define CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK 0x200000000ull
 533 #define CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK 0x10ull
 534 #define CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK 0x8ull
 535 #define CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK 0x40000000ull
 536 #define CCE_ERR_STATUS_LA_TRIGGERED_SMASK 0x80000000ull
 537 #define CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK 0x40000ull
 538 #define CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK 0x4000000ull
 539 #define CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK 0x20000ull
 540 #define CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK 0x2000000ull
 541 #define CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK 0x100000ull
 542 #define CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK 0x80000ull
 543 #define CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK 0x10000ull
 544 #define CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK 0x1000000ull
 545 #define CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK 0x8000ull
 546 #define CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK 0x800000ull
 547 #define CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK 0x20000000ull
 548 #define CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK 0x2000ull
 549 #define CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK 0x200000ull
 550 #define CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK 0x4000ull
 551 #define CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK 0x400000ull
 552 #define CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK 0x10000000ull
 553 #define CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK 0x8000000ull
 554 #define CCE_INT_CLEAR (CCE + 0x000000110A00)
 555 #define CCE_INT_COUNTER_ARRAY32 (CCE + 0x000000110D00)
 556 #define CCE_INT_FORCE (CCE + 0x000000110B00)
 557 #define CCE_INT_MAP (CCE + 0x000000110500)
 558 #define CCE_INT_MASK (CCE + 0x000000110900)
 559 #define CCE_INT_STATUS (CCE + 0x000000110800)
 560 #define CCE_MSIX_INT_GRANTED (CCE + 0x000000110200)
 561 #define CCE_MSIX_TABLE_LOWER (CCE + 0x000000100000)
 562 #define CCE_MSIX_TABLE_UPPER (CCE + 0x000000100008)
 563 #define CCE_MSIX_TABLE_UPPER_RESETCSR 0x0000000100000000ull
 564 #define CCE_MSIX_VEC_CLR_WITHOUT_INT (CCE + 0x000000110400)
 565 #define CCE_PCIE_CTRL (CCE + 0x0000000000C0)
 566 #define CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK 0x3ull
 567 #define CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT 0
 568 #define CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK 0xFull
 569 #define CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT 2
 570 #define CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT 8
 571 #define CCE_PCIE_CTRL_XMT_MARGIN_SHIFT 9
 572 #define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK 0x1ull
 573 #define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT 12
 574 #define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK 0x7ull
 575 #define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT 13
 576 #define CCE_REVISION (CCE + 0x000000000000)
 577 #define CCE_REVISION2 (CCE + 0x000000000008)
 578 #define CCE_REVISION2_HFI_ID_MASK 0x1ull
 579 #define CCE_REVISION2_HFI_ID_SHIFT 0
 580 #define CCE_REVISION2_IMPL_CODE_SHIFT 8
 581 #define CCE_REVISION2_IMPL_REVISION_SHIFT 16
 582 #define CCE_REVISION_BOARD_ID_LOWER_NIBBLE_MASK 0xFull
 583 #define CCE_REVISION_BOARD_ID_LOWER_NIBBLE_SHIFT 32
 584 #define CCE_REVISION_CHIP_REV_MAJOR_MASK 0xFFull
 585 #define CCE_REVISION_CHIP_REV_MAJOR_SHIFT 8
 586 #define CCE_REVISION_CHIP_REV_MINOR_MASK 0xFFull
 587 #define CCE_REVISION_CHIP_REV_MINOR_SHIFT 0
 588 #define CCE_REVISION_SW_MASK 0xFFull
 589 #define CCE_REVISION_SW_SHIFT 24
 590 #define CCE_SCRATCH (CCE + 0x000000000020)
 591 #define CCE_STATUS (CCE + 0x000000000018)
 592 #define CCE_STATUS_RXE_FROZE_SMASK 0x2ull
 593 #define CCE_STATUS_RXE_PAUSED_SMASK 0x20ull
 594 #define CCE_STATUS_SDMA_FROZE_SMASK 0x1ull
 595 #define CCE_STATUS_SDMA_PAUSED_SMASK 0x10ull
 596 #define CCE_STATUS_TXE_FROZE_SMASK 0x4ull
 597 #define CCE_STATUS_TXE_PAUSED_SMASK 0x40ull
 598 #define CCE_STATUS_TXE_PIO_FROZE_SMASK 0x8ull
 599 #define CCE_STATUS_TXE_PIO_PAUSED_SMASK 0x80ull
 600 #define MISC_CFG_FW_CTRL (MISC + 0x000000001000)
 601 #define MISC_CFG_FW_CTRL_FW_8051_LOADED_SMASK 0x2ull
 602 #define MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT 2
 603 #define MISC_CFG_FW_CTRL_RSA_STATUS_SMASK 0xCull
 604 #define MISC_CFG_RSA_CMD (MISC + 0x000000000A08)
 605 #define MISC_CFG_RSA_MODULUS (MISC + 0x000000000400)
 606 #define MISC_CFG_RSA_MU (MISC + 0x000000000A10)
 607 #define MISC_CFG_RSA_R2 (MISC + 0x000000000000)
 608 #define MISC_CFG_RSA_SIGNATURE (MISC + 0x000000000200)
 609 #define MISC_CFG_SHA_PRELOAD (MISC + 0x000000000A00)
 610 #define MISC_ERR_CLEAR (MISC + 0x000000002010)
 611 #define MISC_ERR_MASK (MISC + 0x000000002008)
 612 #define MISC_ERR_STATUS (MISC + 0x000000002000)
 613 #define MISC_ERR_STATUS_MISC_PLL_LOCK_FAIL_ERR_SMASK 0x1000ull
 614 #define MISC_ERR_STATUS_MISC_MBIST_FAIL_ERR_SMASK 0x800ull
 615 #define MISC_ERR_STATUS_MISC_INVALID_EEP_CMD_ERR_SMASK 0x400ull
 616 #define MISC_ERR_STATUS_MISC_EFUSE_DONE_PARITY_ERR_SMASK 0x200ull
 617 #define MISC_ERR_STATUS_MISC_EFUSE_WRITE_ERR_SMASK 0x100ull
 618 #define MISC_ERR_STATUS_MISC_EFUSE_READ_BAD_ADDR_ERR_SMASK 0x80ull
 619 #define MISC_ERR_STATUS_MISC_EFUSE_CSR_PARITY_ERR_SMASK 0x40ull
 620 #define MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK 0x20ull
 621 #define MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK 0x10ull
 622 #define MISC_ERR_STATUS_MISC_SBUS_WRITE_FAILED_ERR_SMASK 0x8ull
 623 #define MISC_ERR_STATUS_MISC_CSR_WRITE_BAD_ADDR_ERR_SMASK 0x4ull
 624 #define MISC_ERR_STATUS_MISC_CSR_READ_BAD_ADDR_ERR_SMASK 0x2ull
 625 #define MISC_ERR_STATUS_MISC_CSR_PARITY_ERR_SMASK 0x1ull
 626 #define PCI_CFG_MSIX0 (PCIE + 0x0000000000B0)
 627 #define PCI_CFG_REG1 (PCIE + 0x000000000004)
 628 #define PCI_CFG_REG11 (PCIE + 0x00000000002C)
 629 #define PCIE_CFG_SPCIE1 (PCIE + 0x00000000014C)
 630 #define PCIE_CFG_SPCIE2 (PCIE + 0x000000000150)
 631 #define PCIE_CFG_TPH2 (PCIE + 0x000000000180)
 632 #define RCV_ARRAY (RXE + 0x000000200000)
 633 #define RCV_ARRAY_CNT (RXE + 0x000000000018)
 634 #define RCV_ARRAY_RT_ADDR_MASK 0xFFFFFFFFFull
 635 #define RCV_ARRAY_RT_ADDR_SHIFT 0
 636 #define RCV_ARRAY_RT_BUF_SIZE_SHIFT 36
 637 #define RCV_ARRAY_RT_WRITE_ENABLE_SMASK 0x8000000000000000ull
 638 #define RCV_AVAIL_TIME_OUT (RXE + 0x000000100050)
 639 #define RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK 0xFFull
 640 #define RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT 0
 641 #define RCV_BTH_QP (RXE + 0x000000000028)
 642 #define RCV_BTH_QP_KDETH_QP_MASK 0xFFull
 643 #define RCV_BTH_QP_KDETH_QP_SHIFT 16
 644 #define RCV_BYPASS (RXE + 0x000000000038)
 645 #define RCV_BYPASS_HDR_SIZE_SHIFT 16
 646 #define RCV_BYPASS_HDR_SIZE_MASK 0x1Full
 647 #define RCV_BYPASS_HDR_SIZE_SMASK 0x1F0000ull
 648 #define RCV_BYPASS_BYPASS_CONTEXT_SHIFT 0
 649 #define RCV_BYPASS_BYPASS_CONTEXT_MASK 0xFFull
 650 #define RCV_BYPASS_BYPASS_CONTEXT_SMASK 0xFFull
 651 #define RCV_CONTEXTS (RXE + 0x000000000010)
 652 #define RCV_COUNTER_ARRAY32 (RXE + 0x000000000400)
 653 #define RCV_COUNTER_ARRAY64 (RXE + 0x000000000500)
 654 #define RCV_CTRL (RXE + 0x000000000000)
 655 #define RCV_CTRL_RCV_BYPASS_ENABLE_SMASK 0x10ull
 656 #define RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK 0x40ull
 657 #define RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK 0x4ull
 658 #define RCV_CTRL_RCV_PORT_ENABLE_SMASK 0x1ull
 659 #define RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK 0x2ull
 660 #define RCV_CTRL_RCV_RSM_ENABLE_SMASK 0x20ull
 661 #define RCV_CTRL_RX_RBUF_INIT_SMASK 0x200ull
 662 #define RCV_CTXT_CTRL (RXE + 0x000000100000)
 663 #define RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK 0x4ull
 664 #define RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK 0x8ull
 665 #define RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK 0x7ull
 666 #define RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT 8
 667 #define RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK 0x700ull
 668 #define RCV_CTXT_CTRL_ENABLE_SMASK 0x1ull
 669 #define RCV_CTXT_CTRL_INTR_AVAIL_SMASK 0x20ull
 670 #define RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK 0x2ull
 671 #define RCV_CTXT_CTRL_TAIL_UPD_SMASK 0x40ull
 672 #define RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK 0x10ull
 673 #define RCV_CTXT_STATUS (RXE + 0x000000100008)
 674 #define RCV_EGR_CTRL (RXE + 0x000000100010)
 675 #define RCV_EGR_CTRL_EGR_BASE_INDEX_MASK 0x1FFFull
 676 #define RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT 0
 677 #define RCV_EGR_CTRL_EGR_CNT_MASK 0x1FFull
 678 #define RCV_EGR_CTRL_EGR_CNT_SHIFT 32
 679 #define RCV_EGR_INDEX_HEAD (RXE + 0x000000300018)
 680 #define RCV_EGR_INDEX_HEAD_HEAD_MASK 0x7FFull
 681 #define RCV_EGR_INDEX_HEAD_HEAD_SHIFT 0
 682 #define RCV_ERR_CLEAR (RXE + 0x000000000070)
 683 #define RCV_ERR_INFO (RXE + 0x000000000050)
 684 #define RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SC_SMASK 0x1Full
 685 #define RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK 0x20ull
 686 #define RCV_ERR_MASK (RXE + 0x000000000068)
 687 #define RCV_ERR_STATUS (RXE + 0x000000000060)
 688 #define RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK 0x8000000000000000ull
 689 #define RCV_ERR_STATUS_RX_CSR_READ_BAD_ADDR_ERR_SMASK 0x2000000000000000ull
 690 #define RCV_ERR_STATUS_RX_CSR_WRITE_BAD_ADDR_ERR_SMASK \
 691                 0x4000000000000000ull
 692 #define RCV_ERR_STATUS_RX_DC_INTF_PARITY_ERR_SMASK 0x2ull
 693 #define RCV_ERR_STATUS_RX_DC_SOP_EOP_PARITY_ERR_SMASK 0x200ull
 694 #define RCV_ERR_STATUS_RX_DMA_CSR_COR_ERR_SMASK 0x1ull
 695 #define RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK 0x200000000000000ull
 696 #define RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK 0x1000000000000000ull
 697 #define RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_COR_ERR_SMASK \
 698                 0x40000000000000ull
 699 #define RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
 700                 0x20000000000000ull
 701 #define RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
 702                 0x800000000000000ull
 703 #define RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
 704                 0x400000000000000ull
 705 #define RCV_ERR_STATUS_RX_DMA_FLAG_COR_ERR_SMASK 0x800ull
 706 #define RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK 0x400ull
 707 #define RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_COR_ERR_SMASK 0x10000000000000ull
 708 #define RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK 0x8000000000000ull
 709 #define RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK 0x200000000000ull
 710 #define RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK 0x400000000000ull
 711 #define RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK 0x100000000000ull
 712 #define RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
 713                 0x10000000000ull
 714 #define RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK 0x8000000000ull
 715 #define RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
 716                 0x20000000000ull
 717 #define RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_COR_ERR_SMASK 0x80000000000ull
 718 #define RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK 0x40000000000ull
 719 #define RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK 0x40000000ull
 720 #define RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_COR_ERR_SMASK 0x100000ull
 721 #define RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK 0x80000ull
 722 #define RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK 0x400000ull
 723 #define RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK 0x10000000ull
 724 #define RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK 0x2000000ull
 725 #define RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
 726                 0x200000ull
 727 #define RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK 0x800000ull
 728 #define RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
 729                 0x8000000ull
 730 #define RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK 0x4000000ull
 731 #define RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK 0x1000000ull
 732 #define RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK 0x20000000ull
 733 #define RCV_ERR_STATUS_RX_RBUF_DATA_COR_ERR_SMASK 0x100000000000000ull
 734 #define RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK 0x80000000000000ull
 735 #define RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK 0x1000000000000ull
 736 #define RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK 0x800000000000ull
 737 #define RCV_ERR_STATUS_RX_RBUF_DESC_PART2_COR_ERR_SMASK 0x4000000000000ull
 738 #define RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK 0x2000000000000ull
 739 #define RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK 0x100000000ull
 740 #define RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK 0x800000000ull
 741 #define RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
 742                 0x1000000000ull
 743 #define RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK 0x200000000ull
 744 #define RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK 0x400000000ull
 745 #define RCV_ERR_STATUS_RX_RBUF_FREE_LIST_COR_ERR_SMASK 0x4000ull
 746 #define RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK 0x2000ull
 747 #define RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK 0x80000000ull
 748 #define RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_COR_ERR_SMASK 0x40000ull
 749 #define RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK 0x10000ull
 750 #define RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK 0x8000ull
 751 #define RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK 0x20000ull
 752 #define RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_COR_ERR_SMASK 0x4000000000ull
 753 #define RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK 0x2000000000ull
 754 #define RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK 0x100ull
 755 #define RCV_ERR_STATUS_RX_RCV_DATA_COR_ERR_SMASK 0x20ull
 756 #define RCV_ERR_STATUS_RX_RCV_DATA_UNC_ERR_SMASK 0x10ull
 757 #define RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK 0x1000ull
 758 #define RCV_ERR_STATUS_RX_RCV_HDR_COR_ERR_SMASK 0x8ull
 759 #define RCV_ERR_STATUS_RX_RCV_HDR_UNC_ERR_SMASK 0x4ull
 760 #define RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_COR_ERR_SMASK 0x80ull
 761 #define RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK 0x40ull
 762 #define RCV_HDR_ADDR (RXE + 0x000000100028)
 763 #define RCV_HDR_CNT (RXE + 0x000000100030)
 764 #define RCV_HDR_CNT_CNT_MASK 0x1FFull
 765 #define RCV_HDR_CNT_CNT_SHIFT 0
 766 #define RCV_HDR_ENT_SIZE (RXE + 0x000000100038)
 767 #define RCV_HDR_ENT_SIZE_ENT_SIZE_MASK 0x7ull
 768 #define RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT 0
 769 #define RCV_HDR_HEAD (RXE + 0x000000300008)
 770 #define RCV_HDR_HEAD_COUNTER_MASK 0xFFull
 771 #define RCV_HDR_HEAD_COUNTER_SHIFT 32
 772 #define RCV_HDR_HEAD_HEAD_MASK 0x7FFFFull
 773 #define RCV_HDR_HEAD_HEAD_SHIFT 0
 774 #define RCV_HDR_HEAD_HEAD_SMASK 0x7FFFFull
 775 #define RCV_HDR_OVFL_CNT (RXE + 0x000000100058)
 776 #define RCV_HDR_SIZE (RXE + 0x000000100040)
 777 #define RCV_HDR_SIZE_HDR_SIZE_MASK 0x1Full
 778 #define RCV_HDR_SIZE_HDR_SIZE_SHIFT 0
 779 #define RCV_HDR_TAIL (RXE + 0x000000300000)
 780 #define RCV_HDR_TAIL_ADDR (RXE + 0x000000100048)
 781 #define RCV_KEY_CTRL (RXE + 0x000000100020)
 782 #define RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK 0x200000000ull
 783 #define RCV_KEY_CTRL_JOB_KEY_VALUE_MASK 0xFFFFull
 784 #define RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT 0
 785 #define RCV_MULTICAST (RXE + 0x000000000030)
 786 #define RCV_PARTITION_KEY (RXE + 0x000000000200)
 787 #define RCV_PARTITION_KEY_PARTITION_KEY_A_MASK 0xFFFFull
 788 #define RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT 16
 789 #define RCV_QP_MAP_TABLE (RXE + 0x000000000100)
 790 #define RCV_RSM_CFG (RXE + 0x000000000600)
 791 #define RCV_RSM_CFG_ENABLE_OR_CHAIN_RSM0_MASK 0x1ull
 792 #define RCV_RSM_CFG_ENABLE_OR_CHAIN_RSM0_SHIFT 0
 793 #define RCV_RSM_CFG_PACKET_TYPE_SHIFT 60
 794 #define RCV_RSM_CFG_OFFSET_SHIFT 32
 795 #define RCV_RSM_MAP_TABLE (RXE + 0x000000000900)
 796 #define RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK 0xFFull
 797 #define RCV_RSM_MATCH (RXE + 0x000000000800)
 798 #define RCV_RSM_MATCH_MASK1_SHIFT 0
 799 #define RCV_RSM_MATCH_MASK2_SHIFT 16
 800 #define RCV_RSM_MATCH_VALUE1_SHIFT 8
 801 #define RCV_RSM_MATCH_VALUE2_SHIFT 24
 802 #define RCV_RSM_SELECT (RXE + 0x000000000700)
 803 #define RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT 0
 804 #define RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT 16
 805 #define RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT 32
 806 #define RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT 44
 807 #define RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT 48
 808 #define RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT 60
 809 #define RCV_STATUS (RXE + 0x000000000008)
 810 #define RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK 0x1ull
 811 #define RCV_STATUS_RX_RBUF_INIT_DONE_SMASK 0x200ull
 812 #define RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK 0x40ull
 813 #define RCV_TID_CTRL (RXE + 0x000000100018)
 814 #define RCV_TID_CTRL_TID_BASE_INDEX_MASK 0x1FFFull
 815 #define RCV_TID_CTRL_TID_BASE_INDEX_SHIFT 0
 816 #define RCV_TID_CTRL_TID_PAIR_CNT_MASK 0x1FFull
 817 #define RCV_TID_CTRL_TID_PAIR_CNT_SHIFT 32
 818 #define RCV_TID_FLOW_TABLE (RXE + 0x000000300800)
 819 #define RCV_VL15 (RXE + 0x000000000048)
 820 #define SEND_BTH_QP (TXE + 0x0000000000A0)
 821 #define SEND_BTH_QP_KDETH_QP_MASK 0xFFull
 822 #define SEND_BTH_QP_KDETH_QP_SHIFT 16
 823 #define SEND_CM_CREDIT_USED_STATUS (TXE + 0x000000000510)
 824 #define SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK \
 825                 0x1000000000000ull
 826 #define SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK \
 827                 0x8000000000000000ull
 828 #define SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK \
 829                 0x2000000000000ull
 830 #define SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK \
 831                 0x4000000000000ull
 832 #define SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK \
 833                 0x8000000000000ull
 834 #define SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK \
 835                 0x10000000000000ull
 836 #define SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK \
 837                 0x20000000000000ull
 838 #define SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK \
 839                 0x40000000000000ull
 840 #define SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK \
 841                 0x80000000000000ull
 842 #define SEND_CM_CREDIT_VL (TXE + 0x000000000600)
 843 #define SEND_CM_CREDIT_VL15 (TXE + 0x000000000678)
 844 #define SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT 0
 845 #define SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK 0xFFFFull
 846 #define SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT 0
 847 #define SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK 0xFFFFull
 848 #define SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK 0xFFFFull
 849 #define SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT 16
 850 #define SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK 0xFFFF0000ull
 851 #define SEND_CM_CTRL (TXE + 0x000000000500)
 852 #define SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK 0x8ull
 853 #define SEND_CM_CTRL_RESETCSR 0x0000000000000020ull
 854 #define SEND_CM_GLOBAL_CREDIT (TXE + 0x000000000508)
 855 #define SEND_CM_GLOBAL_CREDIT_AU_MASK 0x7ull
 856 #define SEND_CM_GLOBAL_CREDIT_AU_SHIFT 16
 857 #define SEND_CM_GLOBAL_CREDIT_AU_SMASK 0x70000ull
 858 #define SEND_CM_GLOBAL_CREDIT_RESETCSR 0x0000094000030000ull
 859 #define SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK 0xFFFFull
 860 #define SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT 0
 861 #define SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK 0xFFFFull
 862 #define SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK 0xFFFFull
 863 #define SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT 32
 864 #define SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK 0xFFFF00000000ull
 865 #define SEND_CM_LOCAL_AU_TABLE0_TO3 (TXE + 0x000000000520)
 866 #define SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT 0
 867 #define SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT 16
 868 #define SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT 32
 869 #define SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT 48
 870 #define SEND_CM_LOCAL_AU_TABLE4_TO7 (TXE + 0x000000000528)
 871 #define SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT 0
 872 #define SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT 16
 873 #define SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT 32
 874 #define SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT 48
 875 #define SEND_CM_REMOTE_AU_TABLE0_TO3 (TXE + 0x000000000530)
 876 #define SEND_CM_REMOTE_AU_TABLE4_TO7 (TXE + 0x000000000538)
 877 #define SEND_CM_TIMER_CTRL (TXE + 0x000000000518)
 878 #define SEND_CONTEXTS (TXE + 0x000000000010)
 879 #define SEND_CONTEXT_SET_CTRL (TXE + 0x000000000200)
 880 #define SEND_COUNTER_ARRAY32 (TXE + 0x000000000300)
 881 #define SEND_COUNTER_ARRAY64 (TXE + 0x000000000400)
 882 #define SEND_CTRL (TXE + 0x000000000000)
 883 #define SEND_CTRL_CM_RESET_SMASK 0x4ull
 884 #define SEND_CTRL_SEND_ENABLE_SMASK 0x1ull
 885 #define SEND_CTRL_UNSUPPORTED_VL_SHIFT 3
 886 #define SEND_CTRL_UNSUPPORTED_VL_MASK 0xFFull
 887 #define SEND_CTRL_UNSUPPORTED_VL_SMASK (SEND_CTRL_UNSUPPORTED_VL_MASK \
 888                 << SEND_CTRL_UNSUPPORTED_VL_SHIFT)
 889 #define SEND_CTRL_VL_ARBITER_ENABLE_SMASK 0x2ull
 890 #define SEND_CTXT_CHECK_ENABLE (TXE + 0x000000100080)
 891 #define SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 0x80ull
 892 #define SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK 0x1ull
 893 #define SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK 0x4ull
 894 #define SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK 0x20ull
 895 #define SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK 0x8ull
 896 #define SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK 0x10ull
 897 #define SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 0x40ull
 898 #define SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK 0x2ull
 899 #define SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 0x20000ull
 900 #define SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK \
 901                 0x200000ull
 902 #define SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK 0x800ull
 903 #define SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK 0x400ull
 904 #define SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK 0x1000ull
 905 #define SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK 0x2000ull
 906 #define SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK \
 907                 0x100000ull
 908 #define SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK 0x10000ull
 909 #define SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 0x200ull
 910 #define SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK 0x100ull
 911 #define SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK \
 912                 0x80000ull
 913 #define SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK \
 914                 0x40000ull
 915 #define SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK \
 916                 0x8000ull
 917 #define SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK \
 918                 0x4000ull
 919 #define SEND_CTXT_CHECK_JOB_KEY (TXE + 0x000000100090)
 920 #define SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK 0x100000000ull
 921 #define SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK 0xFFFF0000ull
 922 #define SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK 0xFFFFull
 923 #define SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT 0
 924 #define SEND_CTXT_CHECK_OPCODE (TXE + 0x0000001000A8)
 925 #define SEND_CTXT_CHECK_OPCODE_MASK_SHIFT 8
 926 #define SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT 0
 927 #define SEND_CTXT_CHECK_PARTITION_KEY (TXE + 0x000000100098)
 928 #define SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK 0xFFFFull
 929 #define SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT 0
 930 #define SEND_CTXT_CHECK_SLID (TXE + 0x0000001000A0)
 931 #define SEND_CTXT_CHECK_SLID_MASK_MASK 0xFFFFull
 932 #define SEND_CTXT_CHECK_SLID_MASK_SHIFT 16
 933 #define SEND_CTXT_CHECK_SLID_VALUE_MASK 0xFFFFull
 934 #define SEND_CTXT_CHECK_SLID_VALUE_SHIFT 0
 935 #define SEND_CTXT_CHECK_VL (TXE + 0x000000100088)
 936 #define SEND_CTXT_CREDIT_CTRL (TXE + 0x000000100010)
 937 #define SEND_CTXT_CREDIT_CTRL_CREDIT_INTR_SMASK 0x20000ull
 938 #define SEND_CTXT_CREDIT_CTRL_EARLY_RETURN_SMASK 0x10000ull
 939 #define SEND_CTXT_CREDIT_CTRL_THRESHOLD_MASK 0x7FFull
 940 #define SEND_CTXT_CREDIT_CTRL_THRESHOLD_SHIFT 0
 941 #define SEND_CTXT_CREDIT_CTRL_THRESHOLD_SMASK 0x7FFull
 942 #define SEND_CTXT_CREDIT_STATUS (TXE + 0x000000100018)
 943 #define SEND_CTXT_CREDIT_STATUS_CURRENT_FREE_COUNTER_MASK 0x7FFull
 944 #define SEND_CTXT_CREDIT_STATUS_CURRENT_FREE_COUNTER_SHIFT 32
 945 #define SEND_CTXT_CREDIT_STATUS_LAST_RETURNED_COUNTER_SMASK 0x7FFull
 946 #define SEND_CTXT_CREDIT_FORCE (TXE + 0x000000100028)
 947 #define SEND_CTXT_CREDIT_FORCE_FORCE_RETURN_SMASK 0x1ull
 948 #define SEND_CTXT_CREDIT_RETURN_ADDR (TXE + 0x000000100020)
 949 #define SEND_CTXT_CREDIT_RETURN_ADDR_ADDRESS_SMASK 0xFFFFFFFFFFC0ull
 950 #define SEND_CTXT_CTRL (TXE + 0x000000100000)
 951 #define SEND_CTXT_CTRL_CTXT_BASE_MASK 0x3FFFull
 952 #define SEND_CTXT_CTRL_CTXT_BASE_SHIFT 32
 953 #define SEND_CTXT_CTRL_CTXT_DEPTH_MASK 0x7FFull
 954 #define SEND_CTXT_CTRL_CTXT_DEPTH_SHIFT 48
 955 #define SEND_CTXT_CTRL_CTXT_ENABLE_SMASK 0x1ull
 956 #define SEND_CTXT_ERR_CLEAR (TXE + 0x000000100050)
 957 #define SEND_CTXT_ERR_MASK (TXE + 0x000000100048)
 958 #define SEND_CTXT_ERR_STATUS (TXE + 0x000000100040)
 959 #define SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK 0x2ull
 960 #define SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK 0x1ull
 961 #define SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK 0x4ull
 962 #define SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK 0x10ull
 963 #define SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK 0x8ull
 964 #define SEND_CTXT_STATUS (TXE + 0x000000100008)
 965 #define SEND_CTXT_STATUS_CTXT_HALTED_SMASK 0x1ull
 966 #define SEND_DMA_BASE_ADDR (TXE + 0x000000200010)
 967 #define SEND_DMA_CHECK_ENABLE (TXE + 0x000000200080)
 968 #define SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 0x80ull
 969 #define SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK 0x1ull
 970 #define SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK 0x4ull
 971 #define SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK 0x20ull
 972 #define SEND_DMA_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK 0x8ull
 973 #define SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK 0x10ull
 974 #define SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 0x40ull
 975 #define SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK 0x2ull
 976 #define SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 0x20000ull
 977 #define SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK 0x200000ull
 978 #define SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK \
 979                 0x100000ull
 980 #define SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 0x200ull
 981 #define SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK 0x100ull
 982 #define SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK \
 983                 0x80000ull
 984 #define SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK 0x40000ull
 985 #define SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK \
 986                 0x8000ull
 987 #define SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK 0x4000ull
 988 #define SEND_DMA_CHECK_JOB_KEY (TXE + 0x000000200090)
 989 #define SEND_DMA_CHECK_OPCODE (TXE + 0x0000002000A8)
 990 #define SEND_DMA_CHECK_PARTITION_KEY (TXE + 0x000000200098)
 991 #define SEND_DMA_CHECK_SLID (TXE + 0x0000002000A0)
 992 #define SEND_DMA_CHECK_SLID_MASK_MASK 0xFFFFull
 993 #define SEND_DMA_CHECK_SLID_MASK_SHIFT 16
 994 #define SEND_DMA_CHECK_SLID_VALUE_MASK 0xFFFFull
 995 #define SEND_DMA_CHECK_SLID_VALUE_SHIFT 0
 996 #define SEND_DMA_CHECK_VL (TXE + 0x000000200088)
 997 #define SEND_DMA_CTRL (TXE + 0x000000200000)
 998 #define SEND_DMA_CTRL_SDMA_CLEANUP_SMASK 0x4ull
 999 #define SEND_DMA_CTRL_SDMA_ENABLE_SMASK 0x1ull
1000 #define SEND_DMA_CTRL_SDMA_HALT_SMASK 0x2ull
1001 #define SEND_DMA_CTRL_SDMA_INT_ENABLE_SMASK 0x8ull
1002 #define SEND_DMA_DESC_CNT (TXE + 0x000000200050)
1003 #define SEND_DMA_DESC_CNT_CNT_MASK 0xFFFFull
1004 #define SEND_DMA_DESC_CNT_CNT_SHIFT 0
1005 #define SEND_DMA_ENG_ERR_CLEAR (TXE + 0x000000200070)
1006 #define SEND_DMA_ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK 0x1ull
1007 #define SEND_DMA_ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SHIFT 18
1008 #define SEND_DMA_ENG_ERR_MASK (TXE + 0x000000200068)
1009 #define SEND_DMA_ENG_ERR_STATUS (TXE + 0x000000200060)
1010 #define SEND_DMA_ENG_ERR_STATUS_SDMA_ASSEMBLY_UNC_ERR_SMASK 0x8000ull
1011 #define SEND_DMA_ENG_ERR_STATUS_SDMA_DESC_TABLE_UNC_ERR_SMASK 0x4000ull
1012 #define SEND_DMA_ENG_ERR_STATUS_SDMA_FIRST_DESC_ERR_SMASK 0x10ull
1013 #define SEND_DMA_ENG_ERR_STATUS_SDMA_GEN_MISMATCH_ERR_SMASK 0x2ull
1014 #define SEND_DMA_ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK 0x40ull
1015 #define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_ADDRESS_ERR_SMASK 0x800ull
1016 #define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_LENGTH_ERR_SMASK 0x1000ull
1017 #define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK \
1018                 0x40000ull
1019 #define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_SELECT_ERR_SMASK 0x400ull
1020 #define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_STORAGE_UNC_ERR_SMASK \
1021                 0x20000ull
1022 #define SEND_DMA_ENG_ERR_STATUS_SDMA_LENGTH_MISMATCH_ERR_SMASK 0x80ull
1023 #define SEND_DMA_ENG_ERR_STATUS_SDMA_MEM_READ_ERR_SMASK 0x20ull
1024 #define SEND_DMA_ENG_ERR_STATUS_SDMA_PACKET_DESC_OVERFLOW_ERR_SMASK \
1025                 0x100ull
1026 #define SEND_DMA_ENG_ERR_STATUS_SDMA_PACKET_TRACKING_UNC_ERR_SMASK \
1027                 0x10000ull
1028 #define SEND_DMA_ENG_ERR_STATUS_SDMA_TAIL_OUT_OF_BOUNDS_ERR_SMASK 0x8ull
1029 #define SEND_DMA_ENG_ERR_STATUS_SDMA_TIMEOUT_ERR_SMASK 0x2000ull
1030 #define SEND_DMA_ENG_ERR_STATUS_SDMA_TOO_LONG_ERR_SMASK 0x4ull
1031 #define SEND_DMA_ENG_ERR_STATUS_SDMA_WRONG_DW_ERR_SMASK 0x1ull
1032 #define SEND_DMA_ENGINES (TXE + 0x000000000018)
1033 #define SEND_DMA_ERR_CLEAR (TXE + 0x000000000070)
1034 #define SEND_DMA_ERR_MASK (TXE + 0x000000000068)
1035 #define SEND_DMA_ERR_STATUS (TXE + 0x000000000060)
1036 #define SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK 0x2ull
1037 #define SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK 0x8ull
1038 #define SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK 0x4ull
1039 #define SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK 0x1ull
1040 #define SEND_DMA_HEAD (TXE + 0x000000200028)
1041 #define SEND_DMA_HEAD_ADDR (TXE + 0x000000200030)
1042 #define SEND_DMA_LEN_GEN (TXE + 0x000000200018)
1043 #define SEND_DMA_LEN_GEN_GENERATION_SHIFT 16
1044 #define SEND_DMA_LEN_GEN_LENGTH_SHIFT 6
1045 #define SEND_DMA_MEMORY (TXE + 0x0000002000B0)
1046 #define SEND_DMA_MEMORY_SDMA_MEMORY_CNT_SHIFT 16
1047 #define SEND_DMA_MEMORY_SDMA_MEMORY_INDEX_SHIFT 0
1048 #define SEND_DMA_MEM_SIZE (TXE + 0x000000000028)
1049 #define SEND_DMA_PRIORITY_THLD (TXE + 0x000000200038)
1050 #define SEND_DMA_RELOAD_CNT (TXE + 0x000000200048)
1051 #define SEND_DMA_STATUS (TXE + 0x000000200008)
1052 #define SEND_DMA_STATUS_ENG_CLEANED_UP_SMASK 0x200000000000000ull
1053 #define SEND_DMA_STATUS_ENG_HALTED_SMASK 0x100000000000000ull
1054 #define SEND_DMA_TAIL (TXE + 0x000000200020)
1055 #define SEND_EGRESS_CTXT_STATUS (TXE + 0x000000000800)
1056 #define SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_HALT_STATUS_SMASK 0x10000ull
1057 #define SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SHIFT 0
1058 #define SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SMASK \
1059                 0x3FFFull
1060 #define SEND_EGRESS_ERR_CLEAR (TXE + 0x000000000090)
1061 #define SEND_EGRESS_ERR_INFO (TXE + 0x000000000F00)
1062 #define SEND_EGRESS_ERR_INFO_BAD_PKT_LEN_ERR_SMASK 0x20000ull
1063 #define SEND_EGRESS_ERR_INFO_BYPASS_ERR_SMASK 0x800ull
1064 #define SEND_EGRESS_ERR_INFO_GRH_ERR_SMASK 0x400ull
1065 #define SEND_EGRESS_ERR_INFO_JOB_KEY_ERR_SMASK 0x4ull
1066 #define SEND_EGRESS_ERR_INFO_KDETH_PACKETS_ERR_SMASK 0x1000ull
1067 #define SEND_EGRESS_ERR_INFO_NON_KDETH_PACKETS_ERR_SMASK 0x2000ull
1068 #define SEND_EGRESS_ERR_INFO_OPCODE_ERR_SMASK 0x20ull
1069 #define SEND_EGRESS_ERR_INFO_PARTITION_KEY_ERR_SMASK 0x8ull
1070 #define SEND_EGRESS_ERR_INFO_PBC_STATIC_RATE_CONTROL_ERR_SMASK 0x100000ull
1071 #define SEND_EGRESS_ERR_INFO_PBC_TEST_ERR_SMASK 0x10000ull
1072 #define SEND_EGRESS_ERR_INFO_RAW_ERR_SMASK 0x100ull
1073 #define SEND_EGRESS_ERR_INFO_RAW_IPV6_ERR_SMASK 0x200ull
1074 #define SEND_EGRESS_ERR_INFO_SLID_ERR_SMASK 0x10ull
1075 #define SEND_EGRESS_ERR_INFO_TOO_LONG_BYPASS_PACKETS_ERR_SMASK 0x80000ull
1076 #define SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK 0x40000ull
1077 #define SEND_EGRESS_ERR_INFO_TOO_SMALL_BYPASS_PACKETS_ERR_SMASK 0x8000ull
1078 #define SEND_EGRESS_ERR_INFO_TOO_SMALL_IB_PACKETS_ERR_SMASK 0x4000ull
1079 #define SEND_EGRESS_ERR_INFO_VL_ERR_SMASK 0x2ull
1080 #define SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK 0x40ull
1081 #define SEND_EGRESS_ERR_MASK (TXE + 0x000000000088)
1082 #define SEND_EGRESS_ERR_SOURCE (TXE + 0x000000000F08)
1083 #define SEND_EGRESS_ERR_STATUS (TXE + 0x000000000080)
1084 #define SEND_EGRESS_ERR_STATUS_TX_CONFIG_PARITY_ERR_SMASK 0x8000ull
1085 #define SEND_EGRESS_ERR_STATUS_TX_CREDIT_OVERRUN_ERR_SMASK \
1086                 0x200000000000000ull
1087 #define SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_PARITY_ERR_SMASK \
1088                 0x20000000000ull
1089 #define SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK \
1090                 0x800000000000ull
1091 #define SEND_EGRESS_ERR_STATUS_TX_EGRESS_FIFO_COR_ERR_SMASK \
1092                 0x2000000000000000ull
1093 #define SEND_EGRESS_ERR_STATUS_TX_EGRESS_FIFO_UNC_ERR_SMASK \
1094                 0x200000000000ull
1095 #define SEND_EGRESS_ERR_STATUS_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR_SMASK \
1096                 0x8ull
1097 #define SEND_EGRESS_ERR_STATUS_TX_HCRC_INSERTION_ERR_SMASK \
1098                 0x400000000000ull
1099 #define SEND_EGRESS_ERR_STATUS_TX_ILLEGAL_VL_ERR_SMASK 0x1000ull
1100 #define SEND_EGRESS_ERR_STATUS_TX_INCORRECT_LINK_STATE_ERR_SMASK 0x20ull
1101 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_CSR_PARITY_ERR_SMASK 0x2000ull
1102 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO0_COR_ERR_SMASK \
1103                 0x1000000000000ull
1104 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR_SMASK \
1105                 0x100000000ull
1106 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO1_COR_ERR_SMASK \
1107                 0x2000000000000ull
1108 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR_SMASK \
1109                 0x200000000ull
1110 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO2_COR_ERR_SMASK \
1111                 0x4000000000000ull
1112 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR_SMASK \
1113                 0x400000000ull
1114 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO3_COR_ERR_SMASK \
1115                 0x8000000000000ull
1116 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR_SMASK \
1117                 0x800000000ull
1118 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO4_COR_ERR_SMASK \
1119                 0x10000000000000ull
1120 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR_SMASK \
1121                 0x1000000000ull
1122 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO5_COR_ERR_SMASK \
1123                 0x20000000000000ull
1124 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR_SMASK \
1125                 0x2000000000ull
1126 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO6_COR_ERR_SMASK \
1127                 0x40000000000000ull
1128 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR_SMASK \
1129                 0x4000000000ull
1130 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO7_COR_ERR_SMASK \
1131                 0x80000000000000ull
1132 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR_SMASK \
1133                 0x8000000000ull
1134 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO8_COR_ERR_SMASK \
1135                 0x100000000000000ull
1136 #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR_SMASK \
1137                 0x10000000000ull
1138 #define SEND_EGRESS_ERR_STATUS_TX_LINKDOWN_ERR_SMASK 0x10ull
1139 #define SEND_EGRESS_ERR_STATUS_TX_PIO_LAUNCH_INTF_PARITY_ERR_SMASK 0x80ull
1140 #define SEND_EGRESS_ERR_STATUS_TX_PKT_INTEGRITY_MEM_COR_ERR_SMASK 0x1ull
1141 #define SEND_EGRESS_ERR_STATUS_TX_PKT_INTEGRITY_MEM_UNC_ERR_SMASK 0x2ull
1142 #define SEND_EGRESS_ERR_STATUS_TX_READ_PIO_MEMORY_COR_ERR_SMASK \
1143                 0x1000000000000000ull
1144 #define SEND_EGRESS_ERR_STATUS_TX_READ_PIO_MEMORY_CSR_UNC_ERR_SMASK \
1145                 0x8000000000000000ull
1146 #define SEND_EGRESS_ERR_STATUS_TX_READ_PIO_MEMORY_UNC_ERR_SMASK \
1147                 0x100000000000ull
1148 #define SEND_EGRESS_ERR_STATUS_TX_READ_SDMA_MEMORY_COR_ERR_SMASK \
1149                 0x800000000000000ull
1150 #define SEND_EGRESS_ERR_STATUS_TX_READ_SDMA_MEMORY_CSR_UNC_ERR_SMASK \
1151                 0x4000000000000000ull
1152 #define SEND_EGRESS_ERR_STATUS_TX_READ_SDMA_MEMORY_UNC_ERR_SMASK \
1153                 0x80000000000ull
1154 #define SEND_EGRESS_ERR_STATUS_TX_SB_HDR_COR_ERR_SMASK 0x400000000000000ull
1155 #define SEND_EGRESS_ERR_STATUS_TX_SB_HDR_UNC_ERR_SMASK 0x40000000000ull
1156 #define SEND_EGRESS_ERR_STATUS_TX_SBRD_CTL_CSR_PARITY_ERR_SMASK 0x4000ull
1157 #define SEND_EGRESS_ERR_STATUS_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR_SMASK \
1158                 0x800ull
1159 #define SEND_EGRESS_ERR_STATUS_TX_SDMA0_DISALLOWED_PACKET_ERR_SMASK \
1160                 0x10000ull
1161 #define SEND_EGRESS_ERR_STATUS_TX_SDMA10_DISALLOWED_PACKET_ERR_SMASK \
1162                 0x4000000ull
1163 #define SEND_EGRESS_ERR_STATUS_TX_SDMA11_DISALLOWED_PACKET_ERR_SMASK \
1164                 0x8000000ull
1165 #define SEND_EGRESS_ERR_STATUS_TX_SDMA12_DISALLOWED_PACKET_ERR_SMASK \
1166                 0x10000000ull
1167 #define SEND_EGRESS_ERR_STATUS_TX_SDMA13_DISALLOWED_PACKET_ERR_SMASK \
1168                 0x20000000ull
1169 #define SEND_EGRESS_ERR_STATUS_TX_SDMA14_DISALLOWED_PACKET_ERR_SMASK \
1170                 0x40000000ull
1171 #define SEND_EGRESS_ERR_STATUS_TX_SDMA15_DISALLOWED_PACKET_ERR_SMASK \
1172                 0x80000000ull
1173 #define SEND_EGRESS_ERR_STATUS_TX_SDMA1_DISALLOWED_PACKET_ERR_SMASK \
1174                 0x20000ull
1175 #define SEND_EGRESS_ERR_STATUS_TX_SDMA2_DISALLOWED_PACKET_ERR_SMASK \
1176                 0x40000ull
1177 #define SEND_EGRESS_ERR_STATUS_TX_SDMA3_DISALLOWED_PACKET_ERR_SMASK \
1178                 0x80000ull
1179 #define SEND_EGRESS_ERR_STATUS_TX_SDMA4_DISALLOWED_PACKET_ERR_SMASK \
1180                 0x100000ull
1181 #define SEND_EGRESS_ERR_STATUS_TX_SDMA5_DISALLOWED_PACKET_ERR_SMASK \
1182                 0x200000ull
1183 #define SEND_EGRESS_ERR_STATUS_TX_SDMA6_DISALLOWED_PACKET_ERR_SMASK \
1184                 0x400000ull
1185 #define SEND_EGRESS_ERR_STATUS_TX_SDMA7_DISALLOWED_PACKET_ERR_SMASK \
1186                 0x800000ull
1187 #define SEND_EGRESS_ERR_STATUS_TX_SDMA8_DISALLOWED_PACKET_ERR_SMASK \
1188                 0x1000000ull
1189 #define SEND_EGRESS_ERR_STATUS_TX_SDMA9_DISALLOWED_PACKET_ERR_SMASK \
1190                 0x2000000ull
1191 #define SEND_EGRESS_ERR_STATUS_TX_SDMA_LAUNCH_INTF_PARITY_ERR_SMASK \
1192                 0x100ull
1193 #define SEND_EGRESS_SEND_DMA_STATUS (TXE + 0x000000000E00)
1194 #define SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT 0
1195 #define SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \
1196                 0x3FFFull
1197 #define SEND_ERR_CLEAR (TXE + 0x0000000000F0)
1198 #define SEND_ERR_MASK (TXE + 0x0000000000E8)
1199 #define SEND_ERR_STATUS (TXE + 0x0000000000E0)
1200 #define SEND_ERR_STATUS_SEND_CSR_PARITY_ERR_SMASK 0x1ull
1201 #define SEND_ERR_STATUS_SEND_CSR_READ_BAD_ADDR_ERR_SMASK 0x2ull
1202 #define SEND_ERR_STATUS_SEND_CSR_WRITE_BAD_ADDR_ERR_SMASK 0x4ull
1203 #define SEND_HIGH_PRIORITY_LIMIT (TXE + 0x000000000030)
1204 #define SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK 0x3FFFull
1205 #define SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT 0
1206 #define SEND_HIGH_PRIORITY_LIST (TXE + 0x000000000180)
1207 #define SEND_LEN_CHECK0 (TXE + 0x0000000000D0)
1208 #define SEND_LEN_CHECK0_LEN_VL0_MASK 0xFFFull
1209 #define SEND_LEN_CHECK0_LEN_VL1_SHIFT 12
1210 #define SEND_LEN_CHECK1 (TXE + 0x0000000000D8)
1211 #define SEND_LEN_CHECK1_LEN_VL15_MASK 0xFFFull
1212 #define SEND_LEN_CHECK1_LEN_VL15_SHIFT 48
1213 #define SEND_LEN_CHECK1_LEN_VL4_MASK 0xFFFull
1214 #define SEND_LEN_CHECK1_LEN_VL5_SHIFT 12
1215 #define SEND_LOW_PRIORITY_LIST (TXE + 0x000000000100)
1216 #define SEND_LOW_PRIORITY_LIST_VL_MASK 0x7ull
1217 #define SEND_LOW_PRIORITY_LIST_VL_SHIFT 16
1218 #define SEND_LOW_PRIORITY_LIST_WEIGHT_MASK 0xFFull
1219 #define SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT 0
1220 #define SEND_PIO_ERR_CLEAR (TXE + 0x000000000050)
1221 #define SEND_PIO_ERR_CLEAR_PIO_INIT_SM_IN_ERR_SMASK 0x20000ull
1222 #define SEND_PIO_ERR_MASK (TXE + 0x000000000048)
1223 #define SEND_PIO_ERR_STATUS (TXE + 0x000000000040)
1224 #define SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
1225                 0x1000000ull
1226 #define SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK 0x8000ull
1227 #define SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK 0x4ull
1228 #define SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
1229                 0x100000000ull
1230 #define SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK 0x100000ull
1231 #define SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK 0x80000ull
1232 #define SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK 0x20000ull
1233 #define SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
1234                 0x200000000ull
1235 #define SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK 0x20ull
1236 #define SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
1237                 0x400000000ull
1238 #define SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK 0x40ull
1239 #define SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK \
1240                 0x800000000ull
1241 #define SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK 0x200ull
1242 #define SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK 0x40000ull
1243 #define SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK 0x10000000ull
1244 #define SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK 0x10000ull
1245 #define SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK 0x20000000ull
1246 #define SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK 0x8ull
1247 #define SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK 0x10ull
1248 #define SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK 0x80ull
1249 #define SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
1250                 0x100ull
1251 #define SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK 0x400ull
1252 #define SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK 0x400000ull
1253 #define SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK 0x8000000ull
1254 #define SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK 0x4000000ull
1255 #define SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK 0x2000000ull
1256 #define SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK 0x2000ull
1257 #define SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK 0x800ull
1258 #define SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK 0x4000ull
1259 #define SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK 0x1000ull
1260 #define SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK 0x2ull
1261 #define SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK 0x1ull
1262 #define SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK 0x200000ull
1263 #define SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK 0x800000ull
1264 #define SEND_PIO_INIT_CTXT (TXE + 0x000000000038)
1265 #define SEND_PIO_INIT_CTXT_PIO_ALL_CTXT_INIT_SMASK 0x1ull
1266 #define SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_MASK 0xFFull
1267 #define SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_SHIFT 8
1268 #define SEND_PIO_INIT_CTXT_PIO_INIT_ERR_SMASK 0x8ull
1269 #define SEND_PIO_INIT_CTXT_PIO_INIT_IN_PROGRESS_SMASK 0x4ull
1270 #define SEND_PIO_INIT_CTXT_PIO_SINGLE_CTXT_INIT_SMASK 0x2ull
1271 #define SEND_PIO_MEM_SIZE (TXE + 0x000000000020)
1272 #define SEND_SC2VLT0 (TXE + 0x0000000000B0)
1273 #define SEND_SC2VLT0_SC0_SHIFT 0
1274 #define SEND_SC2VLT0_SC1_SHIFT 8
1275 #define SEND_SC2VLT0_SC2_SHIFT 16
1276 #define SEND_SC2VLT0_SC3_SHIFT 24
1277 #define SEND_SC2VLT0_SC4_SHIFT 32
1278 #define SEND_SC2VLT0_SC5_SHIFT 40
1279 #define SEND_SC2VLT0_SC6_SHIFT 48
1280 #define SEND_SC2VLT0_SC7_SHIFT 56
1281 #define SEND_SC2VLT1 (TXE + 0x0000000000B8)
1282 #define SEND_SC2VLT1_SC10_SHIFT 16
1283 #define SEND_SC2VLT1_SC11_SHIFT 24
1284 #define SEND_SC2VLT1_SC12_SHIFT 32
1285 #define SEND_SC2VLT1_SC13_SHIFT 40
1286 #define SEND_SC2VLT1_SC14_SHIFT 48
1287 #define SEND_SC2VLT1_SC15_SHIFT 56
1288 #define SEND_SC2VLT1_SC8_SHIFT 0
1289 #define SEND_SC2VLT1_SC9_SHIFT 8
1290 #define SEND_SC2VLT2 (TXE + 0x0000000000C0)
1291 #define SEND_SC2VLT2_SC16_SHIFT 0
1292 #define SEND_SC2VLT2_SC17_SHIFT 8
1293 #define SEND_SC2VLT2_SC18_SHIFT 16
1294 #define SEND_SC2VLT2_SC19_SHIFT 24
1295 #define SEND_SC2VLT2_SC20_SHIFT 32
1296 #define SEND_SC2VLT2_SC21_SHIFT 40
1297 #define SEND_SC2VLT2_SC22_SHIFT 48
1298 #define SEND_SC2VLT2_SC23_SHIFT 56
1299 #define SEND_SC2VLT3 (TXE + 0x0000000000C8)
1300 #define SEND_SC2VLT3_SC24_SHIFT 0
1301 #define SEND_SC2VLT3_SC25_SHIFT 8
1302 #define SEND_SC2VLT3_SC26_SHIFT 16
1303 #define SEND_SC2VLT3_SC27_SHIFT 24
1304 #define SEND_SC2VLT3_SC28_SHIFT 32
1305 #define SEND_SC2VLT3_SC29_SHIFT 40
1306 #define SEND_SC2VLT3_SC30_SHIFT 48
1307 #define SEND_SC2VLT3_SC31_SHIFT 56
1308 #define SEND_STATIC_RATE_CONTROL (TXE + 0x0000000000A8)
1309 #define SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT 0
1310 #define SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK 0xFFFFull
1311 #define PCIE_CFG_REG_PL2 (PCIE + 0x000000000708)
1312 #define PCIE_CFG_REG_PL3 (PCIE + 0x00000000070C)
1313 #define PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT 27
1314 #define PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK 0x38000000
1315 #define PCIE_CFG_REG_PL102 (PCIE + 0x000000000898)
1316 #define PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT 12
1317 #define PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT 6
1318 #define PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT 0
1319 #define PCIE_CFG_REG_PL103 (PCIE + 0x00000000089C)
1320 #define PCIE_CFG_REG_PL105 (PCIE + 0x0000000008A4)
1321 #define PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK 0x1ull
1322 #define PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT 24
1323 #define PCIE_CFG_REG_PL100 (PCIE + 0x000000000890)
1324 #define PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK 0x400ull
1325 #define PCIE_CFG_REG_PL101 (PCIE + 0x000000000894)
1326 #define PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT 6
1327 #define PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT 0
1328 #define PCIE_CFG_REG_PL106 (PCIE + 0x0000000008A8)
1329 #define PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT 8
1330 #define PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK 0x20ull
1331 #define PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK 0x10ull
1332 #define CCE_INT_BLOCKED (CCE + 0x000000110C00)
1333 #define SEND_DMA_IDLE_CNT (TXE + 0x000000200040)
1334 #define SEND_DMA_DESC_FETCHED_CNT (TXE + 0x000000200058)
1335 #define CCE_MSIX_PBA_OFFSET 0X0110000
1336 
1337 #endif          /* DEF_CHIP_REG */