1 #ifndef _PIO_H
2 #define _PIO_H
3 /*
4 * Copyright(c) 2015-2017 Intel Corporation.
5 *
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
8 *
9 * GPL LICENSE SUMMARY
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * BSD LICENSE
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 *
26 * - Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
28 * - Redistributions in binary form must reproduce the above copyright
29 * notice, this list of conditions and the following disclaimer in
30 * the documentation and/or other materials provided with the
31 * distribution.
32 * - Neither the name of Intel Corporation nor the names of its
33 * contributors may be used to endorse or promote products derived
34 * from this software without specific prior written permission.
35 *
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 *
48 */
49
50 /* send context types */
51 #define SC_KERNEL 0
52 #define SC_VL15 1
53 #define SC_ACK 2
54 #define SC_USER 3 /* must be the last one: it may take all left */
55 #define SC_MAX 4 /* count of send context types */
56
57 /* invalid send context index */
58 #define INVALID_SCI 0xff
59
60 /* PIO buffer release callback function */
61 typedef void (*pio_release_cb)(void *arg, int code);
62
63 /* PIO release codes - in bits, as there could more than one that apply */
64 #define PRC_OK 0 /* no known error */
65 #define PRC_STATUS_ERR 0x01 /* credit return due to status error */
66 #define PRC_PBC 0x02 /* credit return due to PBC */
67 #define PRC_THRESHOLD 0x04 /* credit return due to threshold */
68 #define PRC_FILL_ERR 0x08 /* credit return due fill error */
69 #define PRC_FORCE 0x10 /* credit return due credit force */
70 #define PRC_SC_DISABLE 0x20 /* clean-up after a context disable */
71
72 /* byte helper */
73 union mix {
74 u64 val64;
75 u32 val32[2];
76 u8 val8[8];
77 };
78
79 /* an allocated PIO buffer */
80 struct pio_buf {
81 struct send_context *sc;/* back pointer to owning send context */
82 pio_release_cb cb; /* called when the buffer is released */
83 void *arg; /* argument for cb */
84 void __iomem *start; /* buffer start address */
85 void __iomem *end; /* context end address */
86 unsigned long sent_at; /* buffer is sent when <= free */
87 union mix carry; /* pending unwritten bytes */
88 u16 qw_written; /* QW written so far */
89 u8 carry_bytes; /* number of valid bytes in carry */
90 };
91
92 /* cache line aligned pio buffer array */
93 union pio_shadow_ring {
94 struct pio_buf pbuf;
95 } ____cacheline_aligned;
96
97 /* per-NUMA send context */
98 struct send_context {
99 /* read-only after init */
100 struct hfi1_devdata *dd; /* device */
101 union pio_shadow_ring *sr; /* shadow ring */
102 void __iomem *base_addr; /* start of PIO memory */
103 u32 __percpu *buffers_allocated;/* count of buffers allocated */
104 u32 size; /* context size, in bytes */
105
106 int node; /* context home node */
107 u32 sr_size; /* size of the shadow ring */
108 u16 flags; /* flags */
109 u8 type; /* context type */
110 u8 sw_index; /* software index number */
111 u8 hw_context; /* hardware context number */
112 u8 group; /* credit return group */
113
114 /* allocator fields */
115 spinlock_t alloc_lock ____cacheline_aligned_in_smp;
116 u32 sr_head; /* shadow ring head */
117 unsigned long fill; /* official alloc count */
118 unsigned long alloc_free; /* copy of free (less cache thrash) */
119 u32 fill_wrap; /* tracks fill within ring */
120 u32 credits; /* number of blocks in context */
121 /* adding a new field here would make it part of this cacheline */
122
123 /* releaser fields */
124 spinlock_t release_lock ____cacheline_aligned_in_smp;
125 u32 sr_tail; /* shadow ring tail */
126 unsigned long free; /* official free count */
127 volatile __le64 *hw_free; /* HW free counter */
128 /* list for PIO waiters */
129 struct list_head piowait ____cacheline_aligned_in_smp;
130 seqlock_t waitlock;
131
132 spinlock_t credit_ctrl_lock ____cacheline_aligned_in_smp;
133 u32 credit_intr_count; /* count of credit intr users */
134 u64 credit_ctrl; /* cache for credit control */
135 wait_queue_head_t halt_wait; /* wait until kernel sees interrupt */
136 struct work_struct halt_work; /* halted context work queue entry */
137 };
138
139 /* send context flags */
140 #define SCF_ENABLED 0x01
141 #define SCF_IN_FREE 0x02
142 #define SCF_HALTED 0x04
143 #define SCF_FROZEN 0x08
144 #define SCF_LINK_DOWN 0x10
145
146 struct send_context_info {
147 struct send_context *sc; /* allocated working context */
148 u16 allocated; /* has this been allocated? */
149 u16 type; /* context type */
150 u16 base; /* base in PIO array */
151 u16 credits; /* size in PIO array */
152 };
153
154 /* DMA credit return, index is always (context & 0x7) */
155 struct credit_return {
156 volatile __le64 cr[8];
157 };
158
159 /* NUMA indexed credit return array */
160 struct credit_return_base {
161 struct credit_return *va;
162 dma_addr_t dma;
163 };
164
165 /* send context configuration sizes (one per type) */
166 struct sc_config_sizes {
167 short int size;
168 short int count;
169 };
170
171 /*
172 * The diagram below details the relationship of the mapping structures
173 *
174 * Since the mapping now allows for non-uniform send contexts per vl, the
175 * number of send contexts for a vl is either the vl_scontexts[vl] or
176 * a computation based on num_kernel_send_contexts/num_vls:
177 *
178 * For example:
179 * nactual = vl_scontexts ? vl_scontexts[vl] : num_kernel_send_contexts/num_vls
180 *
181 * n = roundup to next highest power of 2 using nactual
182 *
183 * In the case where there are num_kernel_send_contexts/num_vls doesn't divide
184 * evenly, the extras are added from the last vl downward.
185 *
186 * For the case where n > nactual, the send contexts are assigned
187 * in a round robin fashion wrapping back to the first send context
188 * for a particular vl.
189 *
190 * dd->pio_map
191 * | pio_map_elem[0]
192 * | +--------------------+
193 * v | mask |
194 * pio_vl_map |--------------------|
195 * +--------------------------+ | ksc[0] -> sc 1 |
196 * | list (RCU) | |--------------------|
197 * |--------------------------| ->| ksc[1] -> sc 2 |
198 * | mask | --/ |--------------------|
199 * |--------------------------| -/ | * |
200 * | actual_vls (max 8) | -/ |--------------------|
201 * |--------------------------| --/ | ksc[n-1] -> sc n |
202 * | vls (max 8) | -/ +--------------------+
203 * |--------------------------| --/
204 * | map[0] |-/
205 * |--------------------------| +--------------------+
206 * | map[1] |--- | mask |
207 * |--------------------------| \---- |--------------------|
208 * | * | \-- | ksc[0] -> sc 1+n |
209 * | * | \---- |--------------------|
210 * | * | \->| ksc[1] -> sc 2+n |
211 * |--------------------------| |--------------------|
212 * | map[vls - 1] |- | * |
213 * +--------------------------+ \- |--------------------|
214 * \- | ksc[m-1] -> sc m+n |
215 * \ +--------------------+
216 * \-
217 * \
218 * \- +----------------------+
219 * \- | mask |
220 * \ |----------------------|
221 * \- | ksc[0] -> sc 1+m+n |
222 * \- |----------------------|
223 * >| ksc[1] -> sc 2+m+n |
224 * |----------------------|
225 * | * |
226 * |----------------------|
227 * | ksc[o-1] -> sc o+m+n |
228 * +----------------------+
229 *
230 */
231
232 /* Initial number of send contexts per VL */
233 #define INIT_SC_PER_VL 2
234
235 /*
236 * struct pio_map_elem - mapping for a vl
237 * @mask - selector mask
238 * @ksc - array of kernel send contexts for this vl
239 *
240 * The mask is used to "mod" the selector to
241 * produce index into the trailing array of
242 * kscs
243 */
244 struct pio_map_elem {
245 u32 mask;
246 struct send_context *ksc[0];
247 };
248
249 /*
250 * struct pio_vl_map - mapping for a vl
251 * @list - rcu head for free callback
252 * @mask - vl mask to "mod" the vl to produce an index to map array
253 * @actual_vls - number of vls
254 * @vls - numbers of vls rounded to next power of 2
255 * @map - array of pio_map_elem entries
256 *
257 * This is the parent mapping structure. The trailing members of the
258 * struct point to pio_map_elem entries, which in turn point to an
259 * array of kscs for that vl.
260 */
261 struct pio_vl_map {
262 struct rcu_head list;
263 u32 mask;
264 u8 actual_vls;
265 u8 vls;
266 struct pio_map_elem *map[0];
267 };
268
269 int pio_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls,
270 u8 *vl_scontexts);
271 void free_pio_map(struct hfi1_devdata *dd);
272 struct send_context *pio_select_send_context_vl(struct hfi1_devdata *dd,
273 u32 selector, u8 vl);
274 struct send_context *pio_select_send_context_sc(struct hfi1_devdata *dd,
275 u32 selector, u8 sc5);
276
277 /* send context functions */
278 int init_credit_return(struct hfi1_devdata *dd);
279 void free_credit_return(struct hfi1_devdata *dd);
280 int init_sc_pools_and_sizes(struct hfi1_devdata *dd);
281 int init_send_contexts(struct hfi1_devdata *dd);
282 int init_credit_return(struct hfi1_devdata *dd);
283 int init_pervl_scs(struct hfi1_devdata *dd);
284 struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
285 uint hdrqentsize, int numa);
286 void sc_free(struct send_context *sc);
287 int sc_enable(struct send_context *sc);
288 void sc_disable(struct send_context *sc);
289 int sc_restart(struct send_context *sc);
290 void sc_return_credits(struct send_context *sc);
291 void sc_flush(struct send_context *sc);
292 void sc_drop(struct send_context *sc);
293 void sc_stop(struct send_context *sc, int bit);
294 struct pio_buf *sc_buffer_alloc(struct send_context *sc, u32 dw_len,
295 pio_release_cb cb, void *arg);
296 void sc_release_update(struct send_context *sc);
297 void sc_return_credits(struct send_context *sc);
298 void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context);
299 void sc_add_credit_return_intr(struct send_context *sc);
300 void sc_del_credit_return_intr(struct send_context *sc);
301 void sc_set_cr_threshold(struct send_context *sc, u32 new_threshold);
302 u32 sc_percent_to_threshold(struct send_context *sc, u32 percent);
303 u32 sc_mtu_to_threshold(struct send_context *sc, u32 mtu, u32 hdrqentsize);
304 void hfi1_sc_wantpiobuf_intr(struct send_context *sc, u32 needint);
305 void sc_wait(struct hfi1_devdata *dd);
306 void set_pio_integrity(struct send_context *sc);
307
308 /* support functions */
309 void pio_reset_all(struct hfi1_devdata *dd);
310 void pio_freeze(struct hfi1_devdata *dd);
311 void pio_kernel_unfreeze(struct hfi1_devdata *dd);
312 void pio_kernel_linkup(struct hfi1_devdata *dd);
313
314 /* global PIO send control operations */
315 #define PSC_GLOBAL_ENABLE 0
316 #define PSC_GLOBAL_DISABLE 1
317 #define PSC_GLOBAL_VLARB_ENABLE 2
318 #define PSC_GLOBAL_VLARB_DISABLE 3
319 #define PSC_CM_RESET 4
320 #define PSC_DATA_VL_ENABLE 5
321 #define PSC_DATA_VL_DISABLE 6
322
323 void __cm_reset(struct hfi1_devdata *dd, u64 sendctrl);
324 void pio_send_control(struct hfi1_devdata *dd, int op);
325
326 /* PIO copy routines */
327 void pio_copy(struct hfi1_devdata *dd, struct pio_buf *pbuf, u64 pbc,
328 const void *from, size_t count);
329 void seg_pio_copy_start(struct pio_buf *pbuf, u64 pbc,
330 const void *from, size_t nbytes);
331 void seg_pio_copy_mid(struct pio_buf *pbuf, const void *from, size_t nbytes);
332 void seg_pio_copy_end(struct pio_buf *pbuf);
333
334 void seqfile_dump_sci(struct seq_file *s, u32 i,
335 struct send_context_info *sci);
336
337 #endif /* _PIO_H */