root/drivers/infiniband/hw/hfi1/chip.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. read_kctxt_csr
  2. write_kctxt_csr
  3. get_kctxt_csr_addr
  4. read_uctxt_csr
  5. write_uctxt_csr
  6. chip_rcv_contexts
  7. chip_send_contexts
  8. chip_sdma_engines
  9. chip_pio_mem_size
  10. chip_sdma_mem_size
  11. chip_rcv_array_count
  12. is_lcb_offset
  13. vl_from_idx
  14. idx_from_vl
   1 #ifndef _CHIP_H
   2 #define _CHIP_H
   3 /*
   4  * Copyright(c) 2015 - 2018 Intel Corporation.
   5  *
   6  * This file is provided under a dual BSD/GPLv2 license.  When using or
   7  * redistributing this file, you may do so under either license.
   8  *
   9  * GPL LICENSE SUMMARY
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * BSD LICENSE
  21  *
  22  * Redistribution and use in source and binary forms, with or without
  23  * modification, are permitted provided that the following conditions
  24  * are met:
  25  *
  26  *  - Redistributions of source code must retain the above copyright
  27  *    notice, this list of conditions and the following disclaimer.
  28  *  - Redistributions in binary form must reproduce the above copyright
  29  *    notice, this list of conditions and the following disclaimer in
  30  *    the documentation and/or other materials provided with the
  31  *    distribution.
  32  *  - Neither the name of Intel Corporation nor the names of its
  33  *    contributors may be used to endorse or promote products derived
  34  *    from this software without specific prior written permission.
  35  *
  36  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  37  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  38  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  39  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  40  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  41  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  42  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  43  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  44  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  45  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  46  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  47  *
  48  */
  49 
  50 /*
  51  * This file contains all of the defines that is specific to the HFI chip
  52  */
  53 
  54 /* sizes */
  55 #define BITS_PER_REGISTER (BITS_PER_BYTE * sizeof(u64))
  56 #define NUM_INTERRUPT_SOURCES 768
  57 #define RXE_NUM_CONTEXTS 160
  58 #define RXE_PER_CONTEXT_SIZE 0x1000     /* 4k */
  59 #define RXE_NUM_TID_FLOWS 32
  60 #define RXE_NUM_DATA_VL 8
  61 #define TXE_NUM_CONTEXTS 160
  62 #define TXE_NUM_SDMA_ENGINES 16
  63 #define NUM_CONTEXTS_PER_SET 8
  64 #define VL_ARB_HIGH_PRIO_TABLE_SIZE 16
  65 #define VL_ARB_LOW_PRIO_TABLE_SIZE 16
  66 #define VL_ARB_TABLE_SIZE 16
  67 #define TXE_NUM_32_BIT_COUNTER 7
  68 #define TXE_NUM_64_BIT_COUNTER 30
  69 #define TXE_NUM_DATA_VL 8
  70 #define TXE_PIO_SIZE (32 * 0x100000)    /* 32 MB */
  71 #define PIO_BLOCK_SIZE 64                       /* bytes */
  72 #define SDMA_BLOCK_SIZE 64                      /* bytes */
  73 #define RCV_BUF_BLOCK_SIZE 64               /* bytes */
  74 #define PIO_CMASK 0x7ff /* counter mask for free and fill counters */
  75 #define MAX_EAGER_ENTRIES    2048       /* max receive eager entries */
  76 #define MAX_TID_PAIR_ENTRIES 1024       /* max receive expected pairs */
  77 /*
  78  * Virtual? Allocation Unit, defined as AU = 8*2^vAU, 64 bytes, AU is fixed
  79  * at 64 bytes for all generation one devices
  80  */
  81 #define CM_VAU 3
  82 /* HFI link credit count, AKA receive buffer depth (RBUF_DEPTH) */
  83 #define CM_GLOBAL_CREDITS 0x880
  84 /* Number of PKey entries in the HW */
  85 #define MAX_PKEY_VALUES 16
  86 
  87 #include "chip_registers.h"
  88 
  89 #define RXE_PER_CONTEXT_USER   (RXE + RXE_PER_CONTEXT_OFFSET)
  90 #define TXE_PIO_SEND (TXE + TXE_PIO_SEND_OFFSET)
  91 
  92 /* PBC flags */
  93 #define PBC_INTR                BIT_ULL(31)
  94 #define PBC_DC_INFO_SHIFT       (30)
  95 #define PBC_DC_INFO             BIT_ULL(PBC_DC_INFO_SHIFT)
  96 #define PBC_TEST_EBP            BIT_ULL(29)
  97 #define PBC_PACKET_BYPASS       BIT_ULL(28)
  98 #define PBC_CREDIT_RETURN       BIT_ULL(25)
  99 #define PBC_INSERT_BYPASS_ICRC  BIT_ULL(24)
 100 #define PBC_TEST_BAD_ICRC       BIT_ULL(23)
 101 #define PBC_FECN                BIT_ULL(22)
 102 
 103 /* PbcInsertHcrc field settings */
 104 #define PBC_IHCRC_LKDETH 0x0    /* insert @ local KDETH offset */
 105 #define PBC_IHCRC_GKDETH 0x1    /* insert @ global KDETH offset */
 106 #define PBC_IHCRC_NONE   0x2    /* no HCRC inserted */
 107 
 108 /* PBC fields */
 109 #define PBC_STATIC_RATE_CONTROL_COUNT_SHIFT 32
 110 #define PBC_STATIC_RATE_CONTROL_COUNT_MASK 0xffffull
 111 #define PBC_STATIC_RATE_CONTROL_COUNT_SMASK \
 112         (PBC_STATIC_RATE_CONTROL_COUNT_MASK << \
 113         PBC_STATIC_RATE_CONTROL_COUNT_SHIFT)
 114 
 115 #define PBC_INSERT_HCRC_SHIFT 26
 116 #define PBC_INSERT_HCRC_MASK 0x3ull
 117 #define PBC_INSERT_HCRC_SMASK \
 118         (PBC_INSERT_HCRC_MASK << PBC_INSERT_HCRC_SHIFT)
 119 
 120 #define PBC_VL_SHIFT 12
 121 #define PBC_VL_MASK 0xfull
 122 #define PBC_VL_SMASK (PBC_VL_MASK << PBC_VL_SHIFT)
 123 
 124 #define PBC_LENGTH_DWS_SHIFT 0
 125 #define PBC_LENGTH_DWS_MASK 0xfffull
 126 #define PBC_LENGTH_DWS_SMASK \
 127         (PBC_LENGTH_DWS_MASK << PBC_LENGTH_DWS_SHIFT)
 128 
 129 /* Credit Return Fields */
 130 #define CR_COUNTER_SHIFT 0
 131 #define CR_COUNTER_MASK 0x7ffull
 132 #define CR_COUNTER_SMASK (CR_COUNTER_MASK << CR_COUNTER_SHIFT)
 133 
 134 #define CR_STATUS_SHIFT 11
 135 #define CR_STATUS_MASK 0x1ull
 136 #define CR_STATUS_SMASK (CR_STATUS_MASK << CR_STATUS_SHIFT)
 137 
 138 #define CR_CREDIT_RETURN_DUE_TO_PBC_SHIFT 12
 139 #define CR_CREDIT_RETURN_DUE_TO_PBC_MASK 0x1ull
 140 #define CR_CREDIT_RETURN_DUE_TO_PBC_SMASK \
 141         (CR_CREDIT_RETURN_DUE_TO_PBC_MASK << \
 142         CR_CREDIT_RETURN_DUE_TO_PBC_SHIFT)
 143 
 144 #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SHIFT 13
 145 #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_MASK 0x1ull
 146 #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SMASK \
 147         (CR_CREDIT_RETURN_DUE_TO_THRESHOLD_MASK << \
 148         CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SHIFT)
 149 
 150 #define CR_CREDIT_RETURN_DUE_TO_ERR_SHIFT 14
 151 #define CR_CREDIT_RETURN_DUE_TO_ERR_MASK 0x1ull
 152 #define CR_CREDIT_RETURN_DUE_TO_ERR_SMASK \
 153         (CR_CREDIT_RETURN_DUE_TO_ERR_MASK << \
 154         CR_CREDIT_RETURN_DUE_TO_ERR_SHIFT)
 155 
 156 #define CR_CREDIT_RETURN_DUE_TO_FORCE_SHIFT 15
 157 #define CR_CREDIT_RETURN_DUE_TO_FORCE_MASK 0x1ull
 158 #define CR_CREDIT_RETURN_DUE_TO_FORCE_SMASK \
 159         (CR_CREDIT_RETURN_DUE_TO_FORCE_MASK << \
 160         CR_CREDIT_RETURN_DUE_TO_FORCE_SHIFT)
 161 
 162 /* Specific IRQ sources */
 163 #define CCE_ERR_INT               0
 164 #define RXE_ERR_INT               1
 165 #define MISC_ERR_INT              2
 166 #define PIO_ERR_INT               4
 167 #define SDMA_ERR_INT              5
 168 #define EGRESS_ERR_INT            6
 169 #define TXE_ERR_INT               7
 170 #define PBC_INT                 240
 171 #define GPIO_ASSERT_INT         241
 172 #define QSFP1_INT               242
 173 #define QSFP2_INT               243
 174 #define TCRIT_INT               244
 175 
 176 /* interrupt source ranges */
 177 #define IS_FIRST_SOURCE         CCE_ERR_INT
 178 #define IS_GENERAL_ERR_START              0
 179 #define IS_SDMAENG_ERR_START             16
 180 #define IS_SENDCTXT_ERR_START            32
 181 #define IS_SDMA_START                   192
 182 #define IS_SDMA_PROGRESS_START          208
 183 #define IS_SDMA_IDLE_START              224
 184 #define IS_VARIOUS_START                240
 185 #define IS_DC_START                     248
 186 #define IS_RCVAVAIL_START               256
 187 #define IS_RCVURGENT_START              416
 188 #define IS_SENDCREDIT_START             576
 189 #define IS_RESERVED_START               736
 190 #define IS_LAST_SOURCE                  767
 191 
 192 /* derived interrupt source values */
 193 #define IS_GENERAL_ERR_END              7
 194 #define IS_SDMAENG_ERR_END              31
 195 #define IS_SENDCTXT_ERR_END             191
 196 #define IS_SDMA_END                     207
 197 #define IS_SDMA_PROGRESS_END            223
 198 #define IS_SDMA_IDLE_END                239
 199 #define IS_VARIOUS_END                  244
 200 #define IS_DC_END                       255
 201 #define IS_RCVAVAIL_END                 415
 202 #define IS_RCVURGENT_END                575
 203 #define IS_SENDCREDIT_END               735
 204 #define IS_RESERVED_END                 IS_LAST_SOURCE
 205 
 206 /* DCC_CFG_PORT_CONFIG logical link states */
 207 #define LSTATE_DOWN    0x1
 208 #define LSTATE_INIT    0x2
 209 #define LSTATE_ARMED   0x3
 210 #define LSTATE_ACTIVE  0x4
 211 
 212 /* DCC_CFG_RESET reset states */
 213 #define LCB_RX_FPE_TX_FPE_INTO_RESET   (DCC_CFG_RESET_RESET_LCB    | \
 214                                         DCC_CFG_RESET_RESET_TX_FPE | \
 215                                         DCC_CFG_RESET_RESET_RX_FPE | \
 216                                         DCC_CFG_RESET_ENABLE_CCLK_BCC)
 217                                         /* 0x17 */
 218 
 219 #define LCB_RX_FPE_TX_FPE_OUT_OF_RESET  DCC_CFG_RESET_ENABLE_CCLK_BCC /* 0x10 */
 220 
 221 /* DC8051_STS_CUR_STATE port values (physical link states) */
 222 #define PLS_DISABLED                       0x30
 223 #define PLS_OFFLINE                                0x90
 224 #define PLS_OFFLINE_QUIET                          0x90
 225 #define PLS_OFFLINE_PLANNED_DOWN_INFORM    0x91
 226 #define PLS_OFFLINE_READY_TO_QUIET_LT      0x92
 227 #define PLS_OFFLINE_REPORT_FAILURE                 0x93
 228 #define PLS_OFFLINE_READY_TO_QUIET_BCC     0x94
 229 #define PLS_OFFLINE_QUIET_DURATION         0x95
 230 #define PLS_POLLING                                0x20
 231 #define PLS_POLLING_QUIET                          0x20
 232 #define PLS_POLLING_ACTIVE                         0x21
 233 #define PLS_CONFIGPHY                      0x40
 234 #define PLS_CONFIGPHY_DEBOUCE              0x40
 235 #define PLS_CONFIGPHY_ESTCOMM              0x41
 236 #define PLS_CONFIGPHY_ESTCOMM_TXRX_HUNT    0x42
 237 #define PLS_CONFIGPHY_ESTCOMM_LOCAL_COMPLETE   0x43
 238 #define PLS_CONFIGPHY_OPTEQ                        0x44
 239 #define PLS_CONFIGPHY_OPTEQ_OPTIMIZING     0x44
 240 #define PLS_CONFIGPHY_OPTEQ_LOCAL_COMPLETE         0x45
 241 #define PLS_CONFIGPHY_VERIFYCAP            0x46
 242 #define PLS_CONFIGPHY_VERIFYCAP_EXCHANGE           0x46
 243 #define PLS_CONFIGPHY_VERIFYCAP_LOCAL_COMPLETE 0x47
 244 #define PLS_CONFIGLT                       0x48
 245 #define PLS_CONFIGLT_CONFIGURE             0x48
 246 #define PLS_CONFIGLT_LINK_TRANSFER_ACTIVE          0x49
 247 #define PLS_LINKUP                                 0x50
 248 #define PLS_PHYTEST                                0xB0
 249 #define PLS_INTERNAL_SERDES_LOOPBACK       0xe1
 250 #define PLS_QUICK_LINKUP                           0xe2
 251 
 252 /* DC_DC8051_CFG_HOST_CMD_0.REQ_TYPE - 8051 host commands */
 253 #define HCMD_LOAD_CONFIG_DATA  0x01
 254 #define HCMD_READ_CONFIG_DATA  0x02
 255 #define HCMD_CHANGE_PHY_STATE  0x03
 256 #define HCMD_SEND_LCB_IDLE_MSG 0x04
 257 #define HCMD_MISC                  0x05
 258 #define HCMD_READ_LCB_IDLE_MSG 0x06
 259 #define HCMD_READ_LCB_CSR      0x07
 260 #define HCMD_WRITE_LCB_CSR     0x08
 261 #define HCMD_INTERFACE_TEST        0xff
 262 
 263 /* DC_DC8051_CFG_HOST_CMD_1.RETURN_CODE - 8051 host command return */
 264 #define HCMD_SUCCESS 2
 265 
 266 /* DC_DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR - error flags */
 267 #define SPICO_ROM_FAILED                BIT(0)
 268 #define UNKNOWN_FRAME                   BIT(1)
 269 #define TARGET_BER_NOT_MET              BIT(2)
 270 #define FAILED_SERDES_INTERNAL_LOOPBACK BIT(3)
 271 #define FAILED_SERDES_INIT              BIT(4)
 272 #define FAILED_LNI_POLLING              BIT(5)
 273 #define FAILED_LNI_DEBOUNCE             BIT(6)
 274 #define FAILED_LNI_ESTBCOMM             BIT(7)
 275 #define FAILED_LNI_OPTEQ                BIT(8)
 276 #define FAILED_LNI_VERIFY_CAP1          BIT(9)
 277 #define FAILED_LNI_VERIFY_CAP2          BIT(10)
 278 #define FAILED_LNI_CONFIGLT             BIT(11)
 279 #define HOST_HANDSHAKE_TIMEOUT          BIT(12)
 280 #define EXTERNAL_DEVICE_REQ_TIMEOUT     BIT(13)
 281 
 282 #define FAILED_LNI (FAILED_LNI_POLLING | FAILED_LNI_DEBOUNCE \
 283                         | FAILED_LNI_ESTBCOMM | FAILED_LNI_OPTEQ \
 284                         | FAILED_LNI_VERIFY_CAP1 \
 285                         | FAILED_LNI_VERIFY_CAP2 \
 286                         | FAILED_LNI_CONFIGLT | HOST_HANDSHAKE_TIMEOUT \
 287                         | EXTERNAL_DEVICE_REQ_TIMEOUT)
 288 
 289 /* DC_DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG - host message flags */
 290 #define HOST_REQ_DONE           BIT(0)
 291 #define BC_PWR_MGM_MSG          BIT(1)
 292 #define BC_SMA_MSG              BIT(2)
 293 #define BC_BCC_UNKNOWN_MSG      BIT(3)
 294 #define BC_IDLE_UNKNOWN_MSG     BIT(4)
 295 #define EXT_DEVICE_CFG_REQ      BIT(5)
 296 #define VERIFY_CAP_FRAME        BIT(6)
 297 #define LINKUP_ACHIEVED         BIT(7)
 298 #define LINK_GOING_DOWN         BIT(8)
 299 #define LINK_WIDTH_DOWNGRADED   BIT(9)
 300 
 301 /* DC_DC8051_CFG_EXT_DEV_1.REQ_TYPE - 8051 host requests */
 302 #define HREQ_LOAD_CONFIG        0x01
 303 #define HREQ_SAVE_CONFIG        0x02
 304 #define HREQ_READ_CONFIG        0x03
 305 #define HREQ_SET_TX_EQ_ABS      0x04
 306 #define HREQ_SET_TX_EQ_REL      0x05
 307 #define HREQ_ENABLE             0x06
 308 #define HREQ_LCB_RESET          0x07
 309 #define HREQ_CONFIG_DONE        0xfe
 310 #define HREQ_INTERFACE_TEST     0xff
 311 
 312 /* DC_DC8051_CFG_EXT_DEV_0.RETURN_CODE - 8051 host request return codes */
 313 #define HREQ_INVALID            0x01
 314 #define HREQ_SUCCESS            0x02
 315 #define HREQ_NOT_SUPPORTED              0x03
 316 #define HREQ_FEATURE_NOT_SUPPORTED      0x04 /* request specific feature */
 317 #define HREQ_REQUEST_REJECTED   0xfe
 318 #define HREQ_EXECUTION_ONGOING  0xff
 319 
 320 /* MISC host command functions */
 321 #define HCMD_MISC_REQUEST_LCB_ACCESS 0x1
 322 #define HCMD_MISC_GRANT_LCB_ACCESS   0x2
 323 
 324 /* idle flit message types */
 325 #define IDLE_PHYSICAL_LINK_MGMT 0x1
 326 #define IDLE_CRU                    0x2
 327 #define IDLE_SMA                    0x3
 328 #define IDLE_POWER_MGMT     0x4
 329 
 330 /* idle flit message send fields (both send and read) */
 331 #define IDLE_PAYLOAD_MASK 0xffffffffffull /* 40 bits */
 332 #define IDLE_PAYLOAD_SHIFT 8
 333 #define IDLE_MSG_TYPE_MASK 0xf
 334 #define IDLE_MSG_TYPE_SHIFT 0
 335 
 336 /* idle flit message read fields */
 337 #define READ_IDLE_MSG_TYPE_MASK 0xf
 338 #define READ_IDLE_MSG_TYPE_SHIFT 0
 339 
 340 /* SMA idle flit payload commands */
 341 #define SMA_IDLE_ARM    1
 342 #define SMA_IDLE_ACTIVE 2
 343 
 344 /* DC_DC8051_CFG_MODE.GENERAL bits */
 345 #define DISABLE_SELF_GUID_CHECK 0x2
 346 
 347 /* Bad L2 frame error code */
 348 #define BAD_L2_ERR      0x6
 349 
 350 /*
 351  * Eager buffer minimum and maximum sizes supported by the hardware.
 352  * All power-of-two sizes in between are supported as well.
 353  * MAX_EAGER_BUFFER_TOTAL is the maximum size of memory
 354  * allocatable for Eager buffer to a single context. All others
 355  * are limits for the RcvArray entries.
 356  */
 357 #define MIN_EAGER_BUFFER       (4 * 1024)
 358 #define MAX_EAGER_BUFFER       (256 * 1024)
 359 #define MAX_EAGER_BUFFER_TOTAL (64 * (1 << 20)) /* max per ctxt 64MB */
 360 #define MAX_EXPECTED_BUFFER    (2048 * 1024)
 361 
 362 /*
 363  * Receive expected base and count and eager base and count increment -
 364  * the CSR fields hold multiples of this value.
 365  */
 366 #define RCV_SHIFT 3
 367 #define RCV_INCREMENT BIT(RCV_SHIFT)
 368 
 369 /*
 370  * Receive header queue entry increment - the CSR holds multiples of
 371  * this value.
 372  */
 373 #define HDRQ_SIZE_SHIFT 5
 374 #define HDRQ_INCREMENT BIT(HDRQ_SIZE_SHIFT)
 375 
 376 /*
 377  * Freeze handling flags
 378  */
 379 #define FREEZE_ABORT     0x01   /* do not do recovery */
 380 #define FREEZE_SELF          0x02       /* initiate the freeze */
 381 #define FREEZE_LINK_DOWN 0x04   /* link is down */
 382 
 383 /*
 384  * Chip implementation codes.
 385  */
 386 #define ICODE_RTL_SILICON               0x00
 387 #define ICODE_RTL_VCS_SIMULATION        0x01
 388 #define ICODE_FPGA_EMULATION    0x02
 389 #define ICODE_FUNCTIONAL_SIMULATOR      0x03
 390 
 391 /*
 392  * 8051 data memory size.
 393  */
 394 #define DC8051_DATA_MEM_SIZE 0x1000
 395 
 396 /*
 397  * 8051 firmware registers
 398  */
 399 #define NUM_GENERAL_FIELDS 0x17
 400 #define NUM_LANE_FIELDS    0x8
 401 
 402 /* 8051 general register Field IDs */
 403 #define LINK_OPTIMIZATION_SETTINGS   0x00
 404 #define LINK_TUNING_PARAMETERS       0x02
 405 #define DC_HOST_COMM_SETTINGS        0x03
 406 #define TX_SETTINGS                  0x06
 407 #define VERIFY_CAP_LOCAL_PHY         0x07
 408 #define VERIFY_CAP_LOCAL_FABRIC      0x08
 409 #define VERIFY_CAP_LOCAL_LINK_MODE   0x09
 410 #define LOCAL_DEVICE_ID              0x0a
 411 #define RESERVED_REGISTERS           0x0b
 412 #define LOCAL_LNI_INFO               0x0c
 413 #define REMOTE_LNI_INFO              0x0d
 414 #define MISC_STATUS                  0x0e
 415 #define VERIFY_CAP_REMOTE_PHY        0x0f
 416 #define VERIFY_CAP_REMOTE_FABRIC     0x10
 417 #define VERIFY_CAP_REMOTE_LINK_WIDTH 0x11
 418 #define LAST_LOCAL_STATE_COMPLETE    0x12
 419 #define LAST_REMOTE_STATE_COMPLETE   0x13
 420 #define LINK_QUALITY_INFO            0x14
 421 #define REMOTE_DEVICE_ID             0x15
 422 #define LINK_DOWN_REASON             0x16 /* first byte of offset 0x16 */
 423 #define VERSION_PATCH                0x16 /* last byte of offset 0x16 */
 424 
 425 /* 8051 lane specific register field IDs */
 426 #define TX_EQ_SETTINGS          0x00
 427 #define CHANNEL_LOSS_SETTINGS   0x05
 428 
 429 /* Lane ID for general configuration registers */
 430 #define GENERAL_CONFIG 4
 431 
 432 /* LINK_TUNING_PARAMETERS fields */
 433 #define TUNING_METHOD_SHIFT 24
 434 
 435 /* LINK_OPTIMIZATION_SETTINGS fields */
 436 #define ENABLE_EXT_DEV_CONFIG_SHIFT 24
 437 
 438 /* LOAD_DATA 8051 command shifts and fields */
 439 #define LOAD_DATA_FIELD_ID_SHIFT 40
 440 #define LOAD_DATA_FIELD_ID_MASK 0xfull
 441 #define LOAD_DATA_LANE_ID_SHIFT 32
 442 #define LOAD_DATA_LANE_ID_MASK 0xfull
 443 #define LOAD_DATA_DATA_SHIFT   0x0
 444 #define LOAD_DATA_DATA_MASK   0xffffffffull
 445 
 446 /* READ_DATA 8051 command shifts and fields */
 447 #define READ_DATA_FIELD_ID_SHIFT 40
 448 #define READ_DATA_FIELD_ID_MASK 0xffull
 449 #define READ_DATA_LANE_ID_SHIFT 32
 450 #define READ_DATA_LANE_ID_MASK 0xffull
 451 #define READ_DATA_DATA_SHIFT   0x0
 452 #define READ_DATA_DATA_MASK   0xffffffffull
 453 
 454 /* TX settings fields */
 455 #define ENABLE_LANE_TX_SHIFT            0
 456 #define ENABLE_LANE_TX_MASK             0xff
 457 #define TX_POLARITY_INVERSION_SHIFT     8
 458 #define TX_POLARITY_INVERSION_MASK      0xff
 459 #define RX_POLARITY_INVERSION_SHIFT     16
 460 #define RX_POLARITY_INVERSION_MASK      0xff
 461 #define MAX_RATE_SHIFT                  24
 462 #define MAX_RATE_MASK                   0xff
 463 
 464 /* verify capability PHY fields */
 465 #define CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT  0x4
 466 #define CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK   0x1
 467 #define POWER_MANAGEMENT_SHIFT                  0x0
 468 #define POWER_MANAGEMENT_MASK                   0xf
 469 
 470 /* 8051 lane register Field IDs */
 471 #define SPICO_FW_VERSION 0x7    /* SPICO firmware version */
 472 
 473 /* SPICO firmware version fields */
 474 #define SPICO_ROM_VERSION_SHIFT 0
 475 #define SPICO_ROM_VERSION_MASK 0xffff
 476 #define SPICO_ROM_PROD_ID_SHIFT 16
 477 #define SPICO_ROM_PROD_ID_MASK 0xffff
 478 
 479 /* verify capability fabric fields */
 480 #define VAU_SHIFT       0
 481 #define VAU_MASK        0x0007
 482 #define Z_SHIFT         3
 483 #define Z_MASK          0x0001
 484 #define VCU_SHIFT       4
 485 #define VCU_MASK        0x0007
 486 #define VL15BUF_SHIFT   8
 487 #define VL15BUF_MASK    0x0fff
 488 #define CRC_SIZES_SHIFT 20
 489 #define CRC_SIZES_MASK  0x7
 490 
 491 /* verify capability local link width fields */
 492 #define LINK_WIDTH_SHIFT 0              /* also for remote link width */
 493 #define LINK_WIDTH_MASK 0xffff          /* also for remote link width */
 494 #define LOCAL_FLAG_BITS_SHIFT 16
 495 #define LOCAL_FLAG_BITS_MASK 0xff
 496 #define MISC_CONFIG_BITS_SHIFT 24
 497 #define MISC_CONFIG_BITS_MASK 0xff
 498 
 499 /* verify capability remote link width fields */
 500 #define REMOTE_TX_RATE_SHIFT 16
 501 #define REMOTE_TX_RATE_MASK 0xff
 502 
 503 /* LOCAL_DEVICE_ID fields */
 504 #define LOCAL_DEVICE_REV_SHIFT 0
 505 #define LOCAL_DEVICE_REV_MASK 0xff
 506 #define LOCAL_DEVICE_ID_SHIFT 8
 507 #define LOCAL_DEVICE_ID_MASK 0xffff
 508 
 509 /* REMOTE_DEVICE_ID fields */
 510 #define REMOTE_DEVICE_REV_SHIFT 0
 511 #define REMOTE_DEVICE_REV_MASK 0xff
 512 #define REMOTE_DEVICE_ID_SHIFT 8
 513 #define REMOTE_DEVICE_ID_MASK 0xffff
 514 
 515 /* local LNI link width fields */
 516 #define ENABLE_LANE_RX_SHIFT 16
 517 #define ENABLE_LANE_RX_MASK  0xff
 518 
 519 /* mask, shift for reading 'mgmt_enabled' value from REMOTE_LNI_INFO field */
 520 #define MGMT_ALLOWED_SHIFT 23
 521 #define MGMT_ALLOWED_MASK 0x1
 522 
 523 /* mask, shift for 'link_quality' within LINK_QUALITY_INFO field */
 524 #define LINK_QUALITY_SHIFT 24
 525 #define LINK_QUALITY_MASK  0x7
 526 
 527 /*
 528  * mask, shift for reading 'planned_down_remote_reason_code'
 529  * from LINK_QUALITY_INFO field
 530  */
 531 #define DOWN_REMOTE_REASON_SHIFT 16
 532 #define DOWN_REMOTE_REASON_MASK  0xff
 533 
 534 #define HOST_INTERFACE_VERSION 1
 535 #define HOST_INTERFACE_VERSION_SHIFT 16
 536 #define HOST_INTERFACE_VERSION_MASK  0xff
 537 
 538 /* verify capability PHY power management bits */
 539 #define PWRM_BER_CONTROL        0x1
 540 #define PWRM_BANDWIDTH_CONTROL  0x2
 541 
 542 /* 8051 link down reasons */
 543 #define LDR_LINK_TRANSFER_ACTIVE_LOW   0xa
 544 #define LDR_RECEIVED_LINKDOWN_IDLE_MSG 0xb
 545 #define LDR_RECEIVED_HOST_OFFLINE_REQ  0xc
 546 
 547 /* verify capability fabric CRC size bits */
 548 enum {
 549         CAP_CRC_14B = (1 << 0), /* 14b CRC */
 550         CAP_CRC_48B = (1 << 1), /* 48b CRC */
 551         CAP_CRC_12B_16B_PER_LANE = (1 << 2) /* 12b-16b per lane CRC */
 552 };
 553 
 554 #define SUPPORTED_CRCS (CAP_CRC_14B | CAP_CRC_48B)
 555 
 556 /* misc status version fields */
 557 #define STS_FM_VERSION_MINOR_SHIFT 16
 558 #define STS_FM_VERSION_MINOR_MASK  0xff
 559 #define STS_FM_VERSION_MAJOR_SHIFT 24
 560 #define STS_FM_VERSION_MAJOR_MASK  0xff
 561 #define STS_FM_VERSION_PATCH_SHIFT 24
 562 #define STS_FM_VERSION_PATCH_MASK  0xff
 563 
 564 /* LCB_CFG_CRC_MODE TX_VAL and RX_VAL CRC mode values */
 565 #define LCB_CRC_16B                     0x0     /* 16b CRC */
 566 #define LCB_CRC_14B                     0x1     /* 14b CRC */
 567 #define LCB_CRC_48B                     0x2     /* 48b CRC */
 568 #define LCB_CRC_12B_16B_PER_LANE        0x3     /* 12b-16b per lane CRC */
 569 
 570 /*
 571  * the following enum is (almost) a copy/paste of the definition
 572  * in the OPA spec, section 20.2.2.6.8 (PortInfo)
 573  */
 574 enum {
 575         PORT_LTP_CRC_MODE_NONE = 0,
 576         PORT_LTP_CRC_MODE_14 = 1, /* 14-bit LTP CRC mode (optional) */
 577         PORT_LTP_CRC_MODE_16 = 2, /* 16-bit LTP CRC mode */
 578         PORT_LTP_CRC_MODE_48 = 4,
 579                 /* 48-bit overlapping LTP CRC mode (optional) */
 580         PORT_LTP_CRC_MODE_PER_LANE = 8
 581                 /* 12 to 16 bit per lane LTP CRC mode (optional) */
 582 };
 583 
 584 /* timeouts */
 585 #define LINK_RESTART_DELAY 1000         /* link restart delay, in ms */
 586 #define TIMEOUT_8051_START 5000         /* 8051 start timeout, in ms */
 587 #define DC8051_COMMAND_TIMEOUT 1000     /* DC8051 command timeout, in ms */
 588 #define FREEZE_STATUS_TIMEOUT 20        /* wait for freeze indicators, in ms */
 589 #define VL_STATUS_CLEAR_TIMEOUT 5000    /* per-VL status clear, in ms */
 590 #define CCE_STATUS_TIMEOUT 10           /* time to clear CCE Status, in ms */
 591 
 592 /* cclock tick time, in picoseconds per tick: 1/speed * 10^12  */
 593 #define ASIC_CCLOCK_PS  1242    /* 805 MHz */
 594 #define FPGA_CCLOCK_PS 30300    /*  33 MHz */
 595 
 596 /*
 597  * Mask of enabled MISC errors.  Do not enable the two RSA engine errors -
 598  * see firmware.c:run_rsa() for details.
 599  */
 600 #define DRIVER_MISC_MASK \
 601         (~(MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK \
 602                 | MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK))
 603 
 604 /* valid values for the loopback module parameter */
 605 #define LOOPBACK_NONE   0       /* no loopback - default */
 606 #define LOOPBACK_SERDES 1
 607 #define LOOPBACK_LCB    2
 608 #define LOOPBACK_CABLE  3       /* external cable */
 609 
 610 /* set up bits in MISC_CONFIG_BITS */
 611 #define LOOPBACK_SERDES_CONFIG_BIT_MASK_SHIFT 0
 612 #define EXT_CFG_LCB_RESET_SUPPORTED_SHIFT     3
 613 
 614 /* read and write hardware registers */
 615 u64 read_csr(const struct hfi1_devdata *dd, u32 offset);
 616 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value);
 617 
 618 /*
 619  * The *_kctxt_* flavor of the CSR read/write functions are for
 620  * per-context or per-SDMA CSRs that are not mappable to user-space.
 621  * Their spacing is not a PAGE_SIZE multiple.
 622  */
 623 static inline u64 read_kctxt_csr(const struct hfi1_devdata *dd, int ctxt,
 624                                  u32 offset0)
 625 {
 626         /* kernel per-context CSRs are separated by 0x100 */
 627         return read_csr(dd, offset0 + (0x100 * ctxt));
 628 }
 629 
 630 static inline void write_kctxt_csr(struct hfi1_devdata *dd, int ctxt,
 631                                    u32 offset0, u64 value)
 632 {
 633         /* kernel per-context CSRs are separated by 0x100 */
 634         write_csr(dd, offset0 + (0x100 * ctxt), value);
 635 }
 636 
 637 int read_lcb_csr(struct hfi1_devdata *dd, u32 offset, u64 *data);
 638 int write_lcb_csr(struct hfi1_devdata *dd, u32 offset, u64 data);
 639 
 640 void __iomem *get_csr_addr(
 641         const struct hfi1_devdata *dd,
 642         u32 offset);
 643 
 644 static inline void __iomem *get_kctxt_csr_addr(
 645         const struct hfi1_devdata *dd,
 646         int ctxt,
 647         u32 offset0)
 648 {
 649         return get_csr_addr(dd, offset0 + (0x100 * ctxt));
 650 }
 651 
 652 /*
 653  * The *_uctxt_* flavor of the CSR read/write functions are for
 654  * per-context CSRs that are mappable to user space. All these CSRs
 655  * are spaced by a PAGE_SIZE multiple in order to be mappable to
 656  * different processes without exposing other contexts' CSRs
 657  */
 658 static inline u64 read_uctxt_csr(const struct hfi1_devdata *dd, int ctxt,
 659                                  u32 offset0)
 660 {
 661         /* user per-context CSRs are separated by 0x1000 */
 662         return read_csr(dd, offset0 + (0x1000 * ctxt));
 663 }
 664 
 665 static inline void write_uctxt_csr(struct hfi1_devdata *dd, int ctxt,
 666                                    u32 offset0, u64 value)
 667 {
 668         /* user per-context CSRs are separated by 0x1000 */
 669         write_csr(dd, offset0 + (0x1000 * ctxt), value);
 670 }
 671 
 672 static inline u32 chip_rcv_contexts(struct hfi1_devdata *dd)
 673 {
 674         return read_csr(dd, RCV_CONTEXTS);
 675 }
 676 
 677 static inline u32 chip_send_contexts(struct hfi1_devdata *dd)
 678 {
 679         return read_csr(dd, SEND_CONTEXTS);
 680 }
 681 
 682 static inline u32 chip_sdma_engines(struct hfi1_devdata *dd)
 683 {
 684         return read_csr(dd, SEND_DMA_ENGINES);
 685 }
 686 
 687 static inline u32 chip_pio_mem_size(struct hfi1_devdata *dd)
 688 {
 689         return read_csr(dd, SEND_PIO_MEM_SIZE);
 690 }
 691 
 692 static inline u32 chip_sdma_mem_size(struct hfi1_devdata *dd)
 693 {
 694         return read_csr(dd, SEND_DMA_MEM_SIZE);
 695 }
 696 
 697 static inline u32 chip_rcv_array_count(struct hfi1_devdata *dd)
 698 {
 699         return read_csr(dd, RCV_ARRAY_CNT);
 700 }
 701 
 702 u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,
 703                u32 dw_len);
 704 
 705 /* firmware.c */
 706 #define SBUS_MASTER_BROADCAST 0xfd
 707 #define NUM_PCIE_SERDES 16      /* number of PCIe serdes on the SBus */
 708 extern const u8 pcie_serdes_broadcast[];
 709 extern const u8 pcie_pcs_addrs[2][NUM_PCIE_SERDES];
 710 
 711 /* SBus commands */
 712 #define RESET_SBUS_RECEIVER 0x20
 713 #define WRITE_SBUS_RECEIVER 0x21
 714 #define READ_SBUS_RECEIVER  0x22
 715 void sbus_request(struct hfi1_devdata *dd,
 716                   u8 receiver_addr, u8 data_addr, u8 command, u32 data_in);
 717 int sbus_request_slow(struct hfi1_devdata *dd,
 718                       u8 receiver_addr, u8 data_addr, u8 command, u32 data_in);
 719 void set_sbus_fast_mode(struct hfi1_devdata *dd);
 720 void clear_sbus_fast_mode(struct hfi1_devdata *dd);
 721 int hfi1_firmware_init(struct hfi1_devdata *dd);
 722 int load_pcie_firmware(struct hfi1_devdata *dd);
 723 int load_firmware(struct hfi1_devdata *dd);
 724 void dispose_firmware(void);
 725 int acquire_hw_mutex(struct hfi1_devdata *dd);
 726 void release_hw_mutex(struct hfi1_devdata *dd);
 727 
 728 /*
 729  * Bitmask of dynamic access for ASIC block chip resources.  Each HFI has its
 730  * own range of bits for the resource so it can clear its own bits on
 731  * starting and exiting.  If either HFI has the resource bit set, the
 732  * resource is in use.  The separate bit ranges are:
 733  *      HFI0 bits  7:0
 734  *      HFI1 bits 15:8
 735  */
 736 #define CR_SBUS  0x01   /* SBUS, THERM, and PCIE registers */
 737 #define CR_EPROM 0x02   /* EEP, GPIO registers */
 738 #define CR_I2C1  0x04   /* QSFP1_OE register */
 739 #define CR_I2C2  0x08   /* QSFP2_OE register */
 740 #define CR_DYN_SHIFT 8  /* dynamic flag shift */
 741 #define CR_DYN_MASK  ((1ull << CR_DYN_SHIFT) - 1)
 742 
 743 /*
 744  * Bitmask of static ASIC states these are outside of the dynamic ASIC
 745  * block chip resources above.  These are to be set once and never cleared.
 746  * Must be holding the SBus dynamic flag when setting.
 747  */
 748 #define CR_THERM_INIT   0x010000
 749 
 750 int acquire_chip_resource(struct hfi1_devdata *dd, u32 resource, u32 mswait);
 751 void release_chip_resource(struct hfi1_devdata *dd, u32 resource);
 752 bool check_chip_resource(struct hfi1_devdata *dd, u32 resource,
 753                          const char *func);
 754 void init_chip_resources(struct hfi1_devdata *dd);
 755 void finish_chip_resources(struct hfi1_devdata *dd);
 756 
 757 /* ms wait time for access to an SBus resoure */
 758 #define SBUS_TIMEOUT 4000 /* long enough for a FW download and SBR */
 759 
 760 /* ms wait time for a qsfp (i2c) chain to become available */
 761 #define QSFP_WAIT 20000 /* long enough for FW update to the F4 uc */
 762 
 763 void fabric_serdes_reset(struct hfi1_devdata *dd);
 764 int read_8051_data(struct hfi1_devdata *dd, u32 addr, u32 len, u64 *result);
 765 
 766 /* chip.c */
 767 void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor,
 768                       u8 *ver_patch);
 769 int write_host_interface_version(struct hfi1_devdata *dd, u8 version);
 770 void read_guid(struct hfi1_devdata *dd);
 771 int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout);
 772 void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
 773                           u8 neigh_reason, u8 rem_reason);
 774 int set_link_state(struct hfi1_pportdata *, u32 state);
 775 int port_ltp_to_cap(int port_ltp);
 776 void handle_verify_cap(struct work_struct *work);
 777 void handle_freeze(struct work_struct *work);
 778 void handle_link_up(struct work_struct *work);
 779 void handle_link_down(struct work_struct *work);
 780 void handle_link_downgrade(struct work_struct *work);
 781 void handle_link_bounce(struct work_struct *work);
 782 void handle_start_link(struct work_struct *work);
 783 void handle_sma_message(struct work_struct *work);
 784 int reset_qsfp(struct hfi1_pportdata *ppd);
 785 void qsfp_event(struct work_struct *work);
 786 void start_freeze_handling(struct hfi1_pportdata *ppd, int flags);
 787 int send_idle_sma(struct hfi1_devdata *dd, u64 message);
 788 int load_8051_config(struct hfi1_devdata *, u8, u8, u32);
 789 int read_8051_config(struct hfi1_devdata *, u8, u8, u32 *);
 790 int start_link(struct hfi1_pportdata *ppd);
 791 int bringup_serdes(struct hfi1_pportdata *ppd);
 792 void set_intr_state(struct hfi1_devdata *dd, u32 enable);
 793 bool apply_link_downgrade_policy(struct hfi1_pportdata *ppd,
 794                                  bool refresh_widths);
 795 void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
 796                     u32 intr_adjust, u32 npkts);
 797 int stop_drain_data_vls(struct hfi1_devdata *dd);
 798 int open_fill_data_vls(struct hfi1_devdata *dd);
 799 u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns);
 800 u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclock);
 801 void get_linkup_link_widths(struct hfi1_pportdata *ppd);
 802 void read_ltp_rtt(struct hfi1_devdata *dd);
 803 void clear_linkup_counters(struct hfi1_devdata *dd);
 804 u32 hdrqempty(struct hfi1_ctxtdata *rcd);
 805 int is_ax(struct hfi1_devdata *dd);
 806 int is_bx(struct hfi1_devdata *dd);
 807 bool is_urg_masked(struct hfi1_ctxtdata *rcd);
 808 u32 read_physical_state(struct hfi1_devdata *dd);
 809 u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate);
 810 const char *opa_lstate_name(u32 lstate);
 811 const char *opa_pstate_name(u32 pstate);
 812 u32 driver_pstate(struct hfi1_pportdata *ppd);
 813 u32 driver_lstate(struct hfi1_pportdata *ppd);
 814 
 815 int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok);
 816 int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok);
 817 #define LCB_START DC_LCB_CSRS
 818 #define LCB_END   DC_8051_CSRS /* next block is 8051 */
 819 static inline int is_lcb_offset(u32 offset)
 820 {
 821         return (offset >= LCB_START && offset < LCB_END);
 822 }
 823 
 824 extern uint num_vls;
 825 
 826 extern uint disable_integrity;
 827 u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl);
 828 u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data);
 829 u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl);
 830 u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data);
 831 u32 read_logical_state(struct hfi1_devdata *dd);
 832 void force_recv_intr(struct hfi1_ctxtdata *rcd);
 833 
 834 /* Per VL indexes */
 835 enum {
 836         C_VL_0 = 0,
 837         C_VL_1,
 838         C_VL_2,
 839         C_VL_3,
 840         C_VL_4,
 841         C_VL_5,
 842         C_VL_6,
 843         C_VL_7,
 844         C_VL_15,
 845         C_VL_COUNT
 846 };
 847 
 848 static inline int vl_from_idx(int idx)
 849 {
 850         return (idx == C_VL_15 ? 15 : idx);
 851 }
 852 
 853 static inline int idx_from_vl(int vl)
 854 {
 855         return (vl == 15 ? C_VL_15 : vl);
 856 }
 857 
 858 /* Per device counter indexes */
 859 enum {
 860         C_RCV_OVF = 0,
 861         C_RX_LEN_ERR,
 862         C_RX_SHORT_ERR,
 863         C_RX_ICRC_ERR,
 864         C_RX_EBP,
 865         C_RX_TID_FULL,
 866         C_RX_TID_INVALID,
 867         C_RX_TID_FLGMS,
 868         C_RX_CTX_EGRS,
 869         C_RCV_TID_FLSMS,
 870         C_CCE_PCI_CR_ST,
 871         C_CCE_PCI_TR_ST,
 872         C_CCE_PIO_WR_ST,
 873         C_CCE_ERR_INT,
 874         C_CCE_SDMA_INT,
 875         C_CCE_MISC_INT,
 876         C_CCE_RCV_AV_INT,
 877         C_CCE_RCV_URG_INT,
 878         C_CCE_SEND_CR_INT,
 879         C_DC_UNC_ERR,
 880         C_DC_RCV_ERR,
 881         C_DC_FM_CFG_ERR,
 882         C_DC_RMT_PHY_ERR,
 883         C_DC_DROPPED_PKT,
 884         C_DC_MC_XMIT_PKTS,
 885         C_DC_MC_RCV_PKTS,
 886         C_DC_XMIT_CERR,
 887         C_DC_RCV_CERR,
 888         C_DC_RCV_FCC,
 889         C_DC_XMIT_FCC,
 890         C_DC_XMIT_FLITS,
 891         C_DC_RCV_FLITS,
 892         C_DC_XMIT_PKTS,
 893         C_DC_RCV_PKTS,
 894         C_DC_RX_FLIT_VL,
 895         C_DC_RX_PKT_VL,
 896         C_DC_RCV_FCN,
 897         C_DC_RCV_FCN_VL,
 898         C_DC_RCV_BCN,
 899         C_DC_RCV_BCN_VL,
 900         C_DC_RCV_BBL,
 901         C_DC_RCV_BBL_VL,
 902         C_DC_MARK_FECN,
 903         C_DC_MARK_FECN_VL,
 904         C_DC_TOTAL_CRC,
 905         C_DC_CRC_LN0,
 906         C_DC_CRC_LN1,
 907         C_DC_CRC_LN2,
 908         C_DC_CRC_LN3,
 909         C_DC_CRC_MULT_LN,
 910         C_DC_TX_REPLAY,
 911         C_DC_RX_REPLAY,
 912         C_DC_SEQ_CRC_CNT,
 913         C_DC_ESC0_ONLY_CNT,
 914         C_DC_ESC0_PLUS1_CNT,
 915         C_DC_ESC0_PLUS2_CNT,
 916         C_DC_REINIT_FROM_PEER_CNT,
 917         C_DC_SBE_CNT,
 918         C_DC_MISC_FLG_CNT,
 919         C_DC_PRF_GOOD_LTP_CNT,
 920         C_DC_PRF_ACCEPTED_LTP_CNT,
 921         C_DC_PRF_RX_FLIT_CNT,
 922         C_DC_PRF_TX_FLIT_CNT,
 923         C_DC_PRF_CLK_CNTR,
 924         C_DC_PG_DBG_FLIT_CRDTS_CNT,
 925         C_DC_PG_STS_PAUSE_COMPLETE_CNT,
 926         C_DC_PG_STS_TX_SBE_CNT,
 927         C_DC_PG_STS_TX_MBE_CNT,
 928         C_SW_CPU_INTR,
 929         C_SW_CPU_RCV_LIM,
 930         C_SW_CTX0_SEQ_DROP,
 931         C_SW_VTX_WAIT,
 932         C_SW_PIO_WAIT,
 933         C_SW_PIO_DRAIN,
 934         C_SW_KMEM_WAIT,
 935         C_SW_TID_WAIT,
 936         C_SW_SEND_SCHED,
 937         C_SDMA_DESC_FETCHED_CNT,
 938         C_SDMA_INT_CNT,
 939         C_SDMA_ERR_CNT,
 940         C_SDMA_IDLE_INT_CNT,
 941         C_SDMA_PROGRESS_INT_CNT,
 942 /* MISC_ERR_STATUS */
 943         C_MISC_PLL_LOCK_FAIL_ERR,
 944         C_MISC_MBIST_FAIL_ERR,
 945         C_MISC_INVALID_EEP_CMD_ERR,
 946         C_MISC_EFUSE_DONE_PARITY_ERR,
 947         C_MISC_EFUSE_WRITE_ERR,
 948         C_MISC_EFUSE_READ_BAD_ADDR_ERR,
 949         C_MISC_EFUSE_CSR_PARITY_ERR,
 950         C_MISC_FW_AUTH_FAILED_ERR,
 951         C_MISC_KEY_MISMATCH_ERR,
 952         C_MISC_SBUS_WRITE_FAILED_ERR,
 953         C_MISC_CSR_WRITE_BAD_ADDR_ERR,
 954         C_MISC_CSR_READ_BAD_ADDR_ERR,
 955         C_MISC_CSR_PARITY_ERR,
 956 /* CceErrStatus */
 957         /*
 958         * A special counter that is the aggregate count
 959         * of all the cce_err_status errors.  The remainder
 960         * are actual bits in the CceErrStatus register.
 961         */
 962         C_CCE_ERR_STATUS_AGGREGATED_CNT,
 963         C_CCE_MSIX_CSR_PARITY_ERR,
 964         C_CCE_INT_MAP_UNC_ERR,
 965         C_CCE_INT_MAP_COR_ERR,
 966         C_CCE_MSIX_TABLE_UNC_ERR,
 967         C_CCE_MSIX_TABLE_COR_ERR,
 968         C_CCE_RXDMA_CONV_FIFO_PARITY_ERR,
 969         C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR,
 970         C_CCE_SEG_WRITE_BAD_ADDR_ERR,
 971         C_CCE_SEG_READ_BAD_ADDR_ERR,
 972         C_LA_TRIGGERED,
 973         C_CCE_TRGT_CPL_TIMEOUT_ERR,
 974         C_PCIC_RECEIVE_PARITY_ERR,
 975         C_PCIC_TRANSMIT_BACK_PARITY_ERR,
 976         C_PCIC_TRANSMIT_FRONT_PARITY_ERR,
 977         C_PCIC_CPL_DAT_Q_UNC_ERR,
 978         C_PCIC_CPL_HD_Q_UNC_ERR,
 979         C_PCIC_POST_DAT_Q_UNC_ERR,
 980         C_PCIC_POST_HD_Q_UNC_ERR,
 981         C_PCIC_RETRY_SOT_MEM_UNC_ERR,
 982         C_PCIC_RETRY_MEM_UNC_ERR,
 983         C_PCIC_N_POST_DAT_Q_PARITY_ERR,
 984         C_PCIC_N_POST_H_Q_PARITY_ERR,
 985         C_PCIC_CPL_DAT_Q_COR_ERR,
 986         C_PCIC_CPL_HD_Q_COR_ERR,
 987         C_PCIC_POST_DAT_Q_COR_ERR,
 988         C_PCIC_POST_HD_Q_COR_ERR,
 989         C_PCIC_RETRY_SOT_MEM_COR_ERR,
 990         C_PCIC_RETRY_MEM_COR_ERR,
 991         C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR,
 992         C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR,
 993         C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR,
 994         C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR,
 995         C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR,
 996         C_CCE_CSR_CFG_BUS_PARITY_ERR,
 997         C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR,
 998         C_CCE_RSPD_DATA_PARITY_ERR,
 999         C_CCE_TRGT_ACCESS_ERR,
1000         C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR,
1001         C_CCE_CSR_WRITE_BAD_ADDR_ERR,
1002         C_CCE_CSR_READ_BAD_ADDR_ERR,
1003         C_CCE_CSR_PARITY_ERR,
1004 /* RcvErrStatus */
1005         C_RX_CSR_PARITY_ERR,
1006         C_RX_CSR_WRITE_BAD_ADDR_ERR,
1007         C_RX_CSR_READ_BAD_ADDR_ERR,
1008         C_RX_DMA_CSR_UNC_ERR,
1009         C_RX_DMA_DQ_FSM_ENCODING_ERR,
1010         C_RX_DMA_EQ_FSM_ENCODING_ERR,
1011         C_RX_DMA_CSR_PARITY_ERR,
1012         C_RX_RBUF_DATA_COR_ERR,
1013         C_RX_RBUF_DATA_UNC_ERR,
1014         C_RX_DMA_DATA_FIFO_RD_COR_ERR,
1015         C_RX_DMA_DATA_FIFO_RD_UNC_ERR,
1016         C_RX_DMA_HDR_FIFO_RD_COR_ERR,
1017         C_RX_DMA_HDR_FIFO_RD_UNC_ERR,
1018         C_RX_RBUF_DESC_PART2_COR_ERR,
1019         C_RX_RBUF_DESC_PART2_UNC_ERR,
1020         C_RX_RBUF_DESC_PART1_COR_ERR,
1021         C_RX_RBUF_DESC_PART1_UNC_ERR,
1022         C_RX_HQ_INTR_FSM_ERR,
1023         C_RX_HQ_INTR_CSR_PARITY_ERR,
1024         C_RX_LOOKUP_CSR_PARITY_ERR,
1025         C_RX_LOOKUP_RCV_ARRAY_COR_ERR,
1026         C_RX_LOOKUP_RCV_ARRAY_UNC_ERR,
1027         C_RX_LOOKUP_DES_PART2_PARITY_ERR,
1028         C_RX_LOOKUP_DES_PART1_UNC_COR_ERR,
1029         C_RX_LOOKUP_DES_PART1_UNC_ERR,
1030         C_RX_RBUF_NEXT_FREE_BUF_COR_ERR,
1031         C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR,
1032         C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR,
1033         C_RX_RBUF_FL_INITDONE_PARITY_ERR,
1034         C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR,
1035         C_RX_RBUF_FL_RD_ADDR_PARITY_ERR,
1036         C_RX_RBUF_EMPTY_ERR,
1037         C_RX_RBUF_FULL_ERR,
1038         C_RX_RBUF_BAD_LOOKUP_ERR,
1039         C_RX_RBUF_CTX_ID_PARITY_ERR,
1040         C_RX_RBUF_CSR_QEOPDW_PARITY_ERR,
1041         C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR,
1042         C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR,
1043         C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR,
1044         C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR,
1045         C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR,
1046         C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR,
1047         C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR,
1048         C_RX_RBUF_BLOCK_LIST_READ_COR_ERR,
1049         C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR,
1050         C_RX_RBUF_LOOKUP_DES_COR_ERR,
1051         C_RX_RBUF_LOOKUP_DES_UNC_ERR,
1052         C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR,
1053         C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR,
1054         C_RX_RBUF_FREE_LIST_COR_ERR,
1055         C_RX_RBUF_FREE_LIST_UNC_ERR,
1056         C_RX_RCV_FSM_ENCODING_ERR,
1057         C_RX_DMA_FLAG_COR_ERR,
1058         C_RX_DMA_FLAG_UNC_ERR,
1059         C_RX_DC_SOP_EOP_PARITY_ERR,
1060         C_RX_RCV_CSR_PARITY_ERR,
1061         C_RX_RCV_QP_MAP_TABLE_COR_ERR,
1062         C_RX_RCV_QP_MAP_TABLE_UNC_ERR,
1063         C_RX_RCV_DATA_COR_ERR,
1064         C_RX_RCV_DATA_UNC_ERR,
1065         C_RX_RCV_HDR_COR_ERR,
1066         C_RX_RCV_HDR_UNC_ERR,
1067         C_RX_DC_INTF_PARITY_ERR,
1068         C_RX_DMA_CSR_COR_ERR,
1069 /* SendPioErrStatus */
1070         C_PIO_PEC_SOP_HEAD_PARITY_ERR,
1071         C_PIO_PCC_SOP_HEAD_PARITY_ERR,
1072         C_PIO_LAST_RETURNED_CNT_PARITY_ERR,
1073         C_PIO_CURRENT_FREE_CNT_PARITY_ERR,
1074         C_PIO_RSVD_31_ERR,
1075         C_PIO_RSVD_30_ERR,
1076         C_PIO_PPMC_SOP_LEN_ERR,
1077         C_PIO_PPMC_BQC_MEM_PARITY_ERR,
1078         C_PIO_VL_FIFO_PARITY_ERR,
1079         C_PIO_VLF_SOP_PARITY_ERR,
1080         C_PIO_VLF_V1_LEN_PARITY_ERR,
1081         C_PIO_BLOCK_QW_COUNT_PARITY_ERR,
1082         C_PIO_WRITE_QW_VALID_PARITY_ERR,
1083         C_PIO_STATE_MACHINE_ERR,
1084         C_PIO_WRITE_DATA_PARITY_ERR,
1085         C_PIO_HOST_ADDR_MEM_COR_ERR,
1086         C_PIO_HOST_ADDR_MEM_UNC_ERR,
1087         C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR,
1088         C_PIO_INIT_SM_IN_ERR,
1089         C_PIO_PPMC_PBL_FIFO_ERR,
1090         C_PIO_CREDIT_RET_FIFO_PARITY_ERR,
1091         C_PIO_V1_LEN_MEM_BANK1_COR_ERR,
1092         C_PIO_V1_LEN_MEM_BANK0_COR_ERR,
1093         C_PIO_V1_LEN_MEM_BANK1_UNC_ERR,
1094         C_PIO_V1_LEN_MEM_BANK0_UNC_ERR,
1095         C_PIO_SM_PKT_RESET_PARITY_ERR,
1096         C_PIO_PKT_EVICT_FIFO_PARITY_ERR,
1097         C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR,
1098         C_PIO_SBRDCTL_CRREL_PARITY_ERR,
1099         C_PIO_PEC_FIFO_PARITY_ERR,
1100         C_PIO_PCC_FIFO_PARITY_ERR,
1101         C_PIO_SB_MEM_FIFO1_ERR,
1102         C_PIO_SB_MEM_FIFO0_ERR,
1103         C_PIO_CSR_PARITY_ERR,
1104         C_PIO_WRITE_ADDR_PARITY_ERR,
1105         C_PIO_WRITE_BAD_CTXT_ERR,
1106 /* SendDmaErrStatus */
1107         C_SDMA_PCIE_REQ_TRACKING_COR_ERR,
1108         C_SDMA_PCIE_REQ_TRACKING_UNC_ERR,
1109         C_SDMA_CSR_PARITY_ERR,
1110         C_SDMA_RPY_TAG_ERR,
1111 /* SendEgressErrStatus */
1112         C_TX_READ_PIO_MEMORY_CSR_UNC_ERR,
1113         C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR,
1114         C_TX_EGRESS_FIFO_COR_ERR,
1115         C_TX_READ_PIO_MEMORY_COR_ERR,
1116         C_TX_READ_SDMA_MEMORY_COR_ERR,
1117         C_TX_SB_HDR_COR_ERR,
1118         C_TX_CREDIT_OVERRUN_ERR,
1119         C_TX_LAUNCH_FIFO8_COR_ERR,
1120         C_TX_LAUNCH_FIFO7_COR_ERR,
1121         C_TX_LAUNCH_FIFO6_COR_ERR,
1122         C_TX_LAUNCH_FIFO5_COR_ERR,
1123         C_TX_LAUNCH_FIFO4_COR_ERR,
1124         C_TX_LAUNCH_FIFO3_COR_ERR,
1125         C_TX_LAUNCH_FIFO2_COR_ERR,
1126         C_TX_LAUNCH_FIFO1_COR_ERR,
1127         C_TX_LAUNCH_FIFO0_COR_ERR,
1128         C_TX_CREDIT_RETURN_VL_ERR,
1129         C_TX_HCRC_INSERTION_ERR,
1130         C_TX_EGRESS_FIFI_UNC_ERR,
1131         C_TX_READ_PIO_MEMORY_UNC_ERR,
1132         C_TX_READ_SDMA_MEMORY_UNC_ERR,
1133         C_TX_SB_HDR_UNC_ERR,
1134         C_TX_CREDIT_RETURN_PARITY_ERR,
1135         C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR,
1136         C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR,
1137         C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR,
1138         C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR,
1139         C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR,
1140         C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR,
1141         C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR,
1142         C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR,
1143         C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR,
1144         C_TX_SDMA15_DISALLOWED_PACKET_ERR,
1145         C_TX_SDMA14_DISALLOWED_PACKET_ERR,
1146         C_TX_SDMA13_DISALLOWED_PACKET_ERR,
1147         C_TX_SDMA12_DISALLOWED_PACKET_ERR,
1148         C_TX_SDMA11_DISALLOWED_PACKET_ERR,
1149         C_TX_SDMA10_DISALLOWED_PACKET_ERR,
1150         C_TX_SDMA9_DISALLOWED_PACKET_ERR,
1151         C_TX_SDMA8_DISALLOWED_PACKET_ERR,
1152         C_TX_SDMA7_DISALLOWED_PACKET_ERR,
1153         C_TX_SDMA6_DISALLOWED_PACKET_ERR,
1154         C_TX_SDMA5_DISALLOWED_PACKET_ERR,
1155         C_TX_SDMA4_DISALLOWED_PACKET_ERR,
1156         C_TX_SDMA3_DISALLOWED_PACKET_ERR,
1157         C_TX_SDMA2_DISALLOWED_PACKET_ERR,
1158         C_TX_SDMA1_DISALLOWED_PACKET_ERR,
1159         C_TX_SDMA0_DISALLOWED_PACKET_ERR,
1160         C_TX_CONFIG_PARITY_ERR,
1161         C_TX_SBRD_CTL_CSR_PARITY_ERR,
1162         C_TX_LAUNCH_CSR_PARITY_ERR,
1163         C_TX_ILLEGAL_CL_ERR,
1164         C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR,
1165         C_TX_RESERVED_10,
1166         C_TX_RESERVED_9,
1167         C_TX_SDMA_LAUNCH_INTF_PARITY_ERR,
1168         C_TX_PIO_LAUNCH_INTF_PARITY_ERR,
1169         C_TX_RESERVED_6,
1170         C_TX_INCORRECT_LINK_STATE_ERR,
1171         C_TX_LINK_DOWN_ERR,
1172         C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR,
1173         C_TX_RESERVED_2,
1174         C_TX_PKT_INTEGRITY_MEM_UNC_ERR,
1175         C_TX_PKT_INTEGRITY_MEM_COR_ERR,
1176 /* SendErrStatus */
1177         C_SEND_CSR_WRITE_BAD_ADDR_ERR,
1178         C_SEND_CSR_READ_BAD_ADD_ERR,
1179         C_SEND_CSR_PARITY_ERR,
1180 /* SendCtxtErrStatus */
1181         C_PIO_WRITE_OUT_OF_BOUNDS_ERR,
1182         C_PIO_WRITE_OVERFLOW_ERR,
1183         C_PIO_WRITE_CROSSES_BOUNDARY_ERR,
1184         C_PIO_DISALLOWED_PACKET_ERR,
1185         C_PIO_INCONSISTENT_SOP_ERR,
1186 /*SendDmaEngErrStatus */
1187         C_SDMA_HEADER_REQUEST_FIFO_COR_ERR,
1188         C_SDMA_HEADER_STORAGE_COR_ERR,
1189         C_SDMA_PACKET_TRACKING_COR_ERR,
1190         C_SDMA_ASSEMBLY_COR_ERR,
1191         C_SDMA_DESC_TABLE_COR_ERR,
1192         C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR,
1193         C_SDMA_HEADER_STORAGE_UNC_ERR,
1194         C_SDMA_PACKET_TRACKING_UNC_ERR,
1195         C_SDMA_ASSEMBLY_UNC_ERR,
1196         C_SDMA_DESC_TABLE_UNC_ERR,
1197         C_SDMA_TIMEOUT_ERR,
1198         C_SDMA_HEADER_LENGTH_ERR,
1199         C_SDMA_HEADER_ADDRESS_ERR,
1200         C_SDMA_HEADER_SELECT_ERR,
1201         C_SMDA_RESERVED_9,
1202         C_SDMA_PACKET_DESC_OVERFLOW_ERR,
1203         C_SDMA_LENGTH_MISMATCH_ERR,
1204         C_SDMA_HALT_ERR,
1205         C_SDMA_MEM_READ_ERR,
1206         C_SDMA_FIRST_DESC_ERR,
1207         C_SDMA_TAIL_OUT_OF_BOUNDS_ERR,
1208         C_SDMA_TOO_LONG_ERR,
1209         C_SDMA_GEN_MISMATCH_ERR,
1210         C_SDMA_WRONG_DW_ERR,
1211         DEV_CNTR_LAST  /* Must be kept last */
1212 };
1213 
1214 /* Per port counter indexes */
1215 enum {
1216         C_TX_UNSUP_VL = 0,
1217         C_TX_INVAL_LEN,
1218         C_TX_MM_LEN_ERR,
1219         C_TX_UNDERRUN,
1220         C_TX_FLOW_STALL,
1221         C_TX_DROPPED,
1222         C_TX_HDR_ERR,
1223         C_TX_PKT,
1224         C_TX_WORDS,
1225         C_TX_WAIT,
1226         C_TX_FLIT_VL,
1227         C_TX_PKT_VL,
1228         C_TX_WAIT_VL,
1229         C_RX_PKT,
1230         C_RX_WORDS,
1231         C_SW_LINK_DOWN,
1232         C_SW_LINK_UP,
1233         C_SW_UNKNOWN_FRAME,
1234         C_SW_XMIT_DSCD,
1235         C_SW_XMIT_DSCD_VL,
1236         C_SW_XMIT_CSTR_ERR,
1237         C_SW_RCV_CSTR_ERR,
1238         C_SW_IBP_LOOP_PKTS,
1239         C_SW_IBP_RC_RESENDS,
1240         C_SW_IBP_RNR_NAKS,
1241         C_SW_IBP_OTHER_NAKS,
1242         C_SW_IBP_RC_TIMEOUTS,
1243         C_SW_IBP_PKT_DROPS,
1244         C_SW_IBP_DMA_WAIT,
1245         C_SW_IBP_RC_SEQNAK,
1246         C_SW_IBP_RC_DUPREQ,
1247         C_SW_IBP_RDMA_SEQ,
1248         C_SW_IBP_UNALIGNED,
1249         C_SW_IBP_SEQ_NAK,
1250         C_SW_IBP_RC_CRWAITS,
1251         C_SW_CPU_RC_ACKS,
1252         C_SW_CPU_RC_QACKS,
1253         C_SW_CPU_RC_DELAYED_COMP,
1254         C_RCV_HDR_OVF_0,
1255         C_RCV_HDR_OVF_1,
1256         C_RCV_HDR_OVF_2,
1257         C_RCV_HDR_OVF_3,
1258         C_RCV_HDR_OVF_4,
1259         C_RCV_HDR_OVF_5,
1260         C_RCV_HDR_OVF_6,
1261         C_RCV_HDR_OVF_7,
1262         C_RCV_HDR_OVF_8,
1263         C_RCV_HDR_OVF_9,
1264         C_RCV_HDR_OVF_10,
1265         C_RCV_HDR_OVF_11,
1266         C_RCV_HDR_OVF_12,
1267         C_RCV_HDR_OVF_13,
1268         C_RCV_HDR_OVF_14,
1269         C_RCV_HDR_OVF_15,
1270         C_RCV_HDR_OVF_16,
1271         C_RCV_HDR_OVF_17,
1272         C_RCV_HDR_OVF_18,
1273         C_RCV_HDR_OVF_19,
1274         C_RCV_HDR_OVF_20,
1275         C_RCV_HDR_OVF_21,
1276         C_RCV_HDR_OVF_22,
1277         C_RCV_HDR_OVF_23,
1278         C_RCV_HDR_OVF_24,
1279         C_RCV_HDR_OVF_25,
1280         C_RCV_HDR_OVF_26,
1281         C_RCV_HDR_OVF_27,
1282         C_RCV_HDR_OVF_28,
1283         C_RCV_HDR_OVF_29,
1284         C_RCV_HDR_OVF_30,
1285         C_RCV_HDR_OVF_31,
1286         C_RCV_HDR_OVF_32,
1287         C_RCV_HDR_OVF_33,
1288         C_RCV_HDR_OVF_34,
1289         C_RCV_HDR_OVF_35,
1290         C_RCV_HDR_OVF_36,
1291         C_RCV_HDR_OVF_37,
1292         C_RCV_HDR_OVF_38,
1293         C_RCV_HDR_OVF_39,
1294         C_RCV_HDR_OVF_40,
1295         C_RCV_HDR_OVF_41,
1296         C_RCV_HDR_OVF_42,
1297         C_RCV_HDR_OVF_43,
1298         C_RCV_HDR_OVF_44,
1299         C_RCV_HDR_OVF_45,
1300         C_RCV_HDR_OVF_46,
1301         C_RCV_HDR_OVF_47,
1302         C_RCV_HDR_OVF_48,
1303         C_RCV_HDR_OVF_49,
1304         C_RCV_HDR_OVF_50,
1305         C_RCV_HDR_OVF_51,
1306         C_RCV_HDR_OVF_52,
1307         C_RCV_HDR_OVF_53,
1308         C_RCV_HDR_OVF_54,
1309         C_RCV_HDR_OVF_55,
1310         C_RCV_HDR_OVF_56,
1311         C_RCV_HDR_OVF_57,
1312         C_RCV_HDR_OVF_58,
1313         C_RCV_HDR_OVF_59,
1314         C_RCV_HDR_OVF_60,
1315         C_RCV_HDR_OVF_61,
1316         C_RCV_HDR_OVF_62,
1317         C_RCV_HDR_OVF_63,
1318         C_RCV_HDR_OVF_64,
1319         C_RCV_HDR_OVF_65,
1320         C_RCV_HDR_OVF_66,
1321         C_RCV_HDR_OVF_67,
1322         C_RCV_HDR_OVF_68,
1323         C_RCV_HDR_OVF_69,
1324         C_RCV_HDR_OVF_70,
1325         C_RCV_HDR_OVF_71,
1326         C_RCV_HDR_OVF_72,
1327         C_RCV_HDR_OVF_73,
1328         C_RCV_HDR_OVF_74,
1329         C_RCV_HDR_OVF_75,
1330         C_RCV_HDR_OVF_76,
1331         C_RCV_HDR_OVF_77,
1332         C_RCV_HDR_OVF_78,
1333         C_RCV_HDR_OVF_79,
1334         C_RCV_HDR_OVF_80,
1335         C_RCV_HDR_OVF_81,
1336         C_RCV_HDR_OVF_82,
1337         C_RCV_HDR_OVF_83,
1338         C_RCV_HDR_OVF_84,
1339         C_RCV_HDR_OVF_85,
1340         C_RCV_HDR_OVF_86,
1341         C_RCV_HDR_OVF_87,
1342         C_RCV_HDR_OVF_88,
1343         C_RCV_HDR_OVF_89,
1344         C_RCV_HDR_OVF_90,
1345         C_RCV_HDR_OVF_91,
1346         C_RCV_HDR_OVF_92,
1347         C_RCV_HDR_OVF_93,
1348         C_RCV_HDR_OVF_94,
1349         C_RCV_HDR_OVF_95,
1350         C_RCV_HDR_OVF_96,
1351         C_RCV_HDR_OVF_97,
1352         C_RCV_HDR_OVF_98,
1353         C_RCV_HDR_OVF_99,
1354         C_RCV_HDR_OVF_100,
1355         C_RCV_HDR_OVF_101,
1356         C_RCV_HDR_OVF_102,
1357         C_RCV_HDR_OVF_103,
1358         C_RCV_HDR_OVF_104,
1359         C_RCV_HDR_OVF_105,
1360         C_RCV_HDR_OVF_106,
1361         C_RCV_HDR_OVF_107,
1362         C_RCV_HDR_OVF_108,
1363         C_RCV_HDR_OVF_109,
1364         C_RCV_HDR_OVF_110,
1365         C_RCV_HDR_OVF_111,
1366         C_RCV_HDR_OVF_112,
1367         C_RCV_HDR_OVF_113,
1368         C_RCV_HDR_OVF_114,
1369         C_RCV_HDR_OVF_115,
1370         C_RCV_HDR_OVF_116,
1371         C_RCV_HDR_OVF_117,
1372         C_RCV_HDR_OVF_118,
1373         C_RCV_HDR_OVF_119,
1374         C_RCV_HDR_OVF_120,
1375         C_RCV_HDR_OVF_121,
1376         C_RCV_HDR_OVF_122,
1377         C_RCV_HDR_OVF_123,
1378         C_RCV_HDR_OVF_124,
1379         C_RCV_HDR_OVF_125,
1380         C_RCV_HDR_OVF_126,
1381         C_RCV_HDR_OVF_127,
1382         C_RCV_HDR_OVF_128,
1383         C_RCV_HDR_OVF_129,
1384         C_RCV_HDR_OVF_130,
1385         C_RCV_HDR_OVF_131,
1386         C_RCV_HDR_OVF_132,
1387         C_RCV_HDR_OVF_133,
1388         C_RCV_HDR_OVF_134,
1389         C_RCV_HDR_OVF_135,
1390         C_RCV_HDR_OVF_136,
1391         C_RCV_HDR_OVF_137,
1392         C_RCV_HDR_OVF_138,
1393         C_RCV_HDR_OVF_139,
1394         C_RCV_HDR_OVF_140,
1395         C_RCV_HDR_OVF_141,
1396         C_RCV_HDR_OVF_142,
1397         C_RCV_HDR_OVF_143,
1398         C_RCV_HDR_OVF_144,
1399         C_RCV_HDR_OVF_145,
1400         C_RCV_HDR_OVF_146,
1401         C_RCV_HDR_OVF_147,
1402         C_RCV_HDR_OVF_148,
1403         C_RCV_HDR_OVF_149,
1404         C_RCV_HDR_OVF_150,
1405         C_RCV_HDR_OVF_151,
1406         C_RCV_HDR_OVF_152,
1407         C_RCV_HDR_OVF_153,
1408         C_RCV_HDR_OVF_154,
1409         C_RCV_HDR_OVF_155,
1410         C_RCV_HDR_OVF_156,
1411         C_RCV_HDR_OVF_157,
1412         C_RCV_HDR_OVF_158,
1413         C_RCV_HDR_OVF_159,
1414         PORT_CNTR_LAST /* Must be kept last */
1415 };
1416 
1417 u64 get_all_cpu_total(u64 __percpu *cntr);
1418 void hfi1_start_cleanup(struct hfi1_devdata *dd);
1419 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd);
1420 void hfi1_init_ctxt(struct send_context *sc);
1421 void hfi1_put_tid(struct hfi1_devdata *dd, u32 index,
1422                   u32 type, unsigned long pa, u16 order);
1423 void hfi1_quiet_serdes(struct hfi1_pportdata *ppd);
1424 void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op,
1425                   struct hfi1_ctxtdata *rcd);
1426 u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp);
1427 u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp);
1428 int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which);
1429 int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val);
1430 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd,
1431                        u16 jkey);
1432 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt);
1433 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt,
1434                        u16 pkey);
1435 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt);
1436 void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality);
1437 void hfi1_init_vnic_rsm(struct hfi1_devdata *dd);
1438 void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd);
1439 
1440 irqreturn_t general_interrupt(int irq, void *data);
1441 irqreturn_t sdma_interrupt(int irq, void *data);
1442 irqreturn_t receive_context_interrupt(int irq, void *data);
1443 irqreturn_t receive_context_thread(int irq, void *data);
1444 
1445 int set_intr_bits(struct hfi1_devdata *dd, u16 first, u16 last, bool set);
1446 void init_qsfp_int(struct hfi1_devdata *dd);
1447 void clear_all_interrupts(struct hfi1_devdata *dd);
1448 void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr);
1449 void remap_sdma_interrupts(struct hfi1_devdata *dd, int engine, int msix_intr);
1450 void reset_interrupts(struct hfi1_devdata *dd);
1451 u8 hfi1_get_qp_map(struct hfi1_devdata *dd, u8 idx);
1452 
1453 /*
1454  * Interrupt source table.
1455  *
1456  * Each entry is an interrupt source "type".  It is ordered by increasing
1457  * number.
1458  */
1459 struct is_table {
1460         int start;       /* interrupt source type start */
1461         int end;         /* interrupt source type end */
1462         /* routine that returns the name of the interrupt source */
1463         char *(*is_name)(char *name, size_t size, unsigned int source);
1464         /* routine to call when receiving an interrupt */
1465         void (*is_int)(struct hfi1_devdata *dd, unsigned int source);
1466 };
1467 
1468 #endif /* _CHIP_H */
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