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33 #ifndef _HNS_ROCE_HW_V1_H
34 #define _HNS_ROCE_HW_V1_H
35
36 #define CQ_STATE_VALID 2
37
38 #define HNS_ROCE_V1_MAX_PD_NUM 0x8000
39 #define HNS_ROCE_V1_MAX_CQ_NUM 0x10000
40 #define HNS_ROCE_V1_MAX_CQE_NUM 0x8000
41
42 #define HNS_ROCE_V1_MAX_QP_NUM 0x40000
43 #define HNS_ROCE_V1_MAX_WQE_NUM 0x4000
44
45 #define HNS_ROCE_V1_MAX_MTPT_NUM 0x80000
46
47 #define HNS_ROCE_V1_MAX_MTT_SEGS 0x100000
48
49 #define HNS_ROCE_V1_MAX_QP_INIT_RDMA 128
50 #define HNS_ROCE_V1_MAX_QP_DEST_RDMA 128
51
52 #define HNS_ROCE_V1_MAX_SQ_DESC_SZ 64
53 #define HNS_ROCE_V1_MAX_RQ_DESC_SZ 64
54 #define HNS_ROCE_V1_SG_NUM 2
55 #define HNS_ROCE_V1_INLINE_SIZE 32
56
57 #define HNS_ROCE_V1_UAR_NUM 256
58 #define HNS_ROCE_V1_PHY_UAR_NUM 8
59
60 #define HNS_ROCE_V1_GID_NUM 16
61 #define HNS_ROCE_V1_RESV_QP 8
62
63 #define HNS_ROCE_V1_MAX_IRQ_NUM 34
64 #define HNS_ROCE_V1_COMP_VEC_NUM 32
65 #define HNS_ROCE_V1_AEQE_VEC_NUM 1
66 #define HNS_ROCE_V1_ABNORMAL_VEC_NUM 1
67
68 #define HNS_ROCE_V1_COMP_EQE_NUM 0x8000
69 #define HNS_ROCE_V1_ASYNC_EQE_NUM 0x400
70
71 #define HNS_ROCE_V1_QPC_ENTRY_SIZE 256
72 #define HNS_ROCE_V1_IRRL_ENTRY_SIZE 8
73 #define HNS_ROCE_V1_CQC_ENTRY_SIZE 64
74 #define HNS_ROCE_V1_MTPT_ENTRY_SIZE 64
75 #define HNS_ROCE_V1_MTT_ENTRY_SIZE 64
76
77 #define HNS_ROCE_V1_CQE_ENTRY_SIZE 32
78 #define HNS_ROCE_V1_PAGE_SIZE_SUPPORT 0xFFFFF000
79
80 #define HNS_ROCE_V1_TABLE_CHUNK_SIZE (1 << 17)
81
82 #define HNS_ROCE_V1_EXT_RAQ_WF 8
83 #define HNS_ROCE_V1_RAQ_ENTRY 64
84 #define HNS_ROCE_V1_RAQ_DEPTH 32768
85 #define HNS_ROCE_V1_RAQ_SIZE (HNS_ROCE_V1_RAQ_ENTRY * HNS_ROCE_V1_RAQ_DEPTH)
86
87 #define HNS_ROCE_V1_SDB_DEPTH 0x400
88 #define HNS_ROCE_V1_ODB_DEPTH 0x400
89
90 #define HNS_ROCE_V1_DB_RSVD 0x80
91
92 #define HNS_ROCE_V1_SDB_ALEPT HNS_ROCE_V1_DB_RSVD
93 #define HNS_ROCE_V1_SDB_ALFUL (HNS_ROCE_V1_SDB_DEPTH - HNS_ROCE_V1_DB_RSVD)
94 #define HNS_ROCE_V1_ODB_ALEPT HNS_ROCE_V1_DB_RSVD
95 #define HNS_ROCE_V1_ODB_ALFUL (HNS_ROCE_V1_ODB_DEPTH - HNS_ROCE_V1_DB_RSVD)
96
97 #define HNS_ROCE_V1_EXT_SDB_DEPTH 0x4000
98 #define HNS_ROCE_V1_EXT_ODB_DEPTH 0x4000
99 #define HNS_ROCE_V1_EXT_SDB_ENTRY 16
100 #define HNS_ROCE_V1_EXT_ODB_ENTRY 16
101 #define HNS_ROCE_V1_EXT_SDB_SIZE \
102 (HNS_ROCE_V1_EXT_SDB_DEPTH * HNS_ROCE_V1_EXT_SDB_ENTRY)
103 #define HNS_ROCE_V1_EXT_ODB_SIZE \
104 (HNS_ROCE_V1_EXT_ODB_DEPTH * HNS_ROCE_V1_EXT_ODB_ENTRY)
105
106 #define HNS_ROCE_V1_EXT_SDB_ALEPT HNS_ROCE_V1_DB_RSVD
107 #define HNS_ROCE_V1_EXT_SDB_ALFUL \
108 (HNS_ROCE_V1_EXT_SDB_DEPTH - HNS_ROCE_V1_DB_RSVD)
109 #define HNS_ROCE_V1_EXT_ODB_ALEPT HNS_ROCE_V1_DB_RSVD
110 #define HNS_ROCE_V1_EXT_ODB_ALFUL \
111 (HNS_ROCE_V1_EXT_ODB_DEPTH - HNS_ROCE_V1_DB_RSVD)
112
113 #define HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS 50000
114 #define HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS 10000
115 #define HNS_ROCE_V1_FREE_MR_WAIT_VALUE 5
116 #define HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE 20
117
118 #define HNS_ROCE_BT_RSV_BUF_SIZE (1 << 17)
119
120 #define HNS_ROCE_V1_TPTR_ENTRY_SIZE 2
121 #define HNS_ROCE_V1_TPTR_BUF_SIZE \
122 (HNS_ROCE_V1_TPTR_ENTRY_SIZE * HNS_ROCE_V1_MAX_CQ_NUM)
123
124 #define HNS_ROCE_ODB_POLL_MODE 0
125
126 #define HNS_ROCE_SDB_NORMAL_MODE 0
127 #define HNS_ROCE_SDB_EXTEND_MODE 1
128
129 #define HNS_ROCE_ODB_EXTEND_MODE 1
130
131 #define KEY_VALID 0x02
132
133 #define HNS_ROCE_CQE_QPN_MASK 0x3ffff
134 #define HNS_ROCE_CQE_STATUS_MASK 0x1f
135 #define HNS_ROCE_CQE_OPCODE_MASK 0xf
136
137 #define HNS_ROCE_CQE_SUCCESS 0x00
138 #define HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR 0x01
139 #define HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR 0x02
140 #define HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR 0x03
141 #define HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR 0x04
142 #define HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR 0x05
143 #define HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR 0x06
144 #define HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR 0x07
145 #define HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR 0x08
146 #define HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR 0x09
147 #define HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR 0x0a
148 #define HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR 0x0b
149 #define HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR 0x0c
150
151 #define QP1C_CFGN_OFFSET 0x28
152 #define PHY_PORT_OFFSET 0x8
153 #define MTPT_IDX_SHIFT 16
154 #define ALL_PORT_VAL_OPEN 0x3f
155 #define POL_TIME_INTERVAL_VAL 0x80
156 #define SLEEP_TIME_INTERVAL 20
157 #define SQ_PSN_SHIFT 8
158 #define QKEY_VAL 0x80010000
159 #define SDB_INV_CNT_OFFSET 8
160
161 #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x10
162 #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x10
163
164 #define HNS_ROCE_INT_MASK_DISABLE 0
165 #define HNS_ROCE_INT_MASK_ENABLE 1
166
167 #define CEQ_REG_OFFSET 0x18
168
169 #define HNS_ROCE_CEQE_CEQE_COMP_OWNER_S 0
170
171 #define HNS_ROCE_V1_CONS_IDX_M GENMASK(15, 0)
172
173 #define HNS_ROCE_CEQE_CEQE_COMP_CQN_S 16
174 #define HNS_ROCE_CEQE_CEQE_COMP_CQN_M GENMASK(31, 16)
175
176 #define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S 16
177 #define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M GENMASK(23, 16)
178
179 #define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S 24
180 #define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M GENMASK(30, 24)
181
182 #define HNS_ROCE_AEQE_U32_4_OWNER_S 31
183
184 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S 0
185 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M GENMASK(23, 0)
186
187 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S 25
188 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M GENMASK(27, 25)
189
190 #define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S 0
191 #define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M GENMASK(15, 0)
192
193 #define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S 0
194 #define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M GENMASK(4, 0)
195
196 struct hns_roce_cq_context {
197 __le32 cqc_byte_4;
198 __le32 cq_bt_l;
199 __le32 cqc_byte_12;
200 __le32 cur_cqe_ba0_l;
201 __le32 cqc_byte_20;
202 __le32 cqe_tptr_addr_l;
203 __le32 cur_cqe_ba1_l;
204 __le32 cqc_byte_32;
205 };
206
207 #define CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S 0
208 #define CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M \
209 (((1UL << 2) - 1) << CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S)
210
211 #define CQ_CONTEXT_CQC_BYTE_4_CQN_S 16
212 #define CQ_CONTEXT_CQC_BYTE_4_CQN_M \
213 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_4_CQN_S)
214
215 #define CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S 0
216 #define CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M \
217 (((1UL << 17) - 1) << CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S)
218
219 #define CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S 20
220 #define CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M \
221 (((1UL << 4) - 1) << CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S)
222
223 #define CQ_CONTEXT_CQC_BYTE_12_CEQN_S 24
224 #define CQ_CONTEXT_CQC_BYTE_12_CEQN_M \
225 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_12_CEQN_S)
226
227 #define CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S 0
228 #define CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M \
229 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S)
230
231 #define CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S 16
232 #define CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M \
233 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S)
234
235 #define CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S 8
236 #define CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M \
237 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S)
238
239 #define CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S 0
240 #define CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M \
241 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S)
242
243 #define CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S 9
244
245 #define CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S 8
246 #define CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S 14
247 #define CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S 15
248
249 #define CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S 16
250 #define CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M \
251 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S)
252
253 struct hns_roce_cqe {
254 __le32 cqe_byte_4;
255 union {
256 __le32 r_key;
257 __le32 immediate_data;
258 };
259 __le32 byte_cnt;
260 __le32 cqe_byte_16;
261 __le32 cqe_byte_20;
262 __le32 s_mac_l;
263 __le32 cqe_byte_28;
264 __le32 reserved;
265 };
266
267 #define CQE_BYTE_4_OWNER_S 7
268 #define CQE_BYTE_4_SQ_RQ_FLAG_S 14
269
270 #define CQE_BYTE_4_STATUS_OF_THE_OPERATION_S 8
271 #define CQE_BYTE_4_STATUS_OF_THE_OPERATION_M \
272 (((1UL << 5) - 1) << CQE_BYTE_4_STATUS_OF_THE_OPERATION_S)
273
274 #define CQE_BYTE_4_WQE_INDEX_S 16
275 #define CQE_BYTE_4_WQE_INDEX_M (((1UL << 14) - 1) << CQE_BYTE_4_WQE_INDEX_S)
276
277 #define CQE_BYTE_4_OPERATION_TYPE_S 0
278 #define CQE_BYTE_4_OPERATION_TYPE_M \
279 (((1UL << 4) - 1) << CQE_BYTE_4_OPERATION_TYPE_S)
280
281 #define CQE_BYTE_4_IMM_INDICATOR_S 15
282
283 #define CQE_BYTE_16_LOCAL_QPN_S 0
284 #define CQE_BYTE_16_LOCAL_QPN_M (((1UL << 24) - 1) << CQE_BYTE_16_LOCAL_QPN_S)
285
286 #define CQE_BYTE_20_PORT_NUM_S 26
287 #define CQE_BYTE_20_PORT_NUM_M (((1UL << 3) - 1) << CQE_BYTE_20_PORT_NUM_S)
288
289 #define CQE_BYTE_20_SL_S 24
290 #define CQE_BYTE_20_SL_M (((1UL << 2) - 1) << CQE_BYTE_20_SL_S)
291
292 #define CQE_BYTE_20_REMOTE_QPN_S 0
293 #define CQE_BYTE_20_REMOTE_QPN_M \
294 (((1UL << 24) - 1) << CQE_BYTE_20_REMOTE_QPN_S)
295
296 #define CQE_BYTE_20_GRH_PRESENT_S 29
297
298 #define CQE_BYTE_28_P_KEY_IDX_S 16
299 #define CQE_BYTE_28_P_KEY_IDX_M (((1UL << 16) - 1) << CQE_BYTE_28_P_KEY_IDX_S)
300
301 #define CQ_DB_REQ_NOT_SOL 0
302 #define CQ_DB_REQ_NOT (1 << 16)
303
304 struct hns_roce_v1_mpt_entry {
305 __le32 mpt_byte_4;
306 __le32 pbl_addr_l;
307 __le32 mpt_byte_12;
308 __le32 virt_addr_l;
309 __le32 virt_addr_h;
310 __le32 length;
311 __le32 mpt_byte_28;
312 __le32 pa0_l;
313 __le32 mpt_byte_36;
314 __le32 mpt_byte_40;
315 __le32 mpt_byte_44;
316 __le32 mpt_byte_48;
317 __le32 pa4_l;
318 __le32 mpt_byte_56;
319 __le32 mpt_byte_60;
320 __le32 mpt_byte_64;
321 };
322
323 #define MPT_BYTE_4_KEY_STATE_S 0
324 #define MPT_BYTE_4_KEY_STATE_M (((1UL << 2) - 1) << MPT_BYTE_4_KEY_STATE_S)
325
326 #define MPT_BYTE_4_KEY_S 8
327 #define MPT_BYTE_4_KEY_M (((1UL << 8) - 1) << MPT_BYTE_4_KEY_S)
328
329 #define MPT_BYTE_4_PAGE_SIZE_S 16
330 #define MPT_BYTE_4_PAGE_SIZE_M (((1UL << 2) - 1) << MPT_BYTE_4_PAGE_SIZE_S)
331
332 #define MPT_BYTE_4_MW_TYPE_S 20
333
334 #define MPT_BYTE_4_MW_BIND_ENABLE_S 21
335
336 #define MPT_BYTE_4_OWN_S 22
337
338 #define MPT_BYTE_4_MEMORY_LOCATION_TYPE_S 24
339 #define MPT_BYTE_4_MEMORY_LOCATION_TYPE_M \
340 (((1UL << 2) - 1) << MPT_BYTE_4_MEMORY_LOCATION_TYPE_S)
341
342 #define MPT_BYTE_4_REMOTE_ATOMIC_S 26
343 #define MPT_BYTE_4_LOCAL_WRITE_S 27
344 #define MPT_BYTE_4_REMOTE_WRITE_S 28
345 #define MPT_BYTE_4_REMOTE_READ_S 29
346 #define MPT_BYTE_4_REMOTE_INVAL_ENABLE_S 30
347 #define MPT_BYTE_4_ADDRESS_TYPE_S 31
348
349 #define MPT_BYTE_12_PBL_ADDR_H_S 0
350 #define MPT_BYTE_12_PBL_ADDR_H_M \
351 (((1UL << 17) - 1) << MPT_BYTE_12_PBL_ADDR_H_S)
352
353 #define MPT_BYTE_12_MW_BIND_COUNTER_S 17
354 #define MPT_BYTE_12_MW_BIND_COUNTER_M \
355 (((1UL << 15) - 1) << MPT_BYTE_12_MW_BIND_COUNTER_S)
356
357 #define MPT_BYTE_28_PD_S 0
358 #define MPT_BYTE_28_PD_M (((1UL << 16) - 1) << MPT_BYTE_28_PD_S)
359
360 #define MPT_BYTE_28_L_KEY_IDX_L_S 16
361 #define MPT_BYTE_28_L_KEY_IDX_L_M \
362 (((1UL << 16) - 1) << MPT_BYTE_28_L_KEY_IDX_L_S)
363
364 #define MPT_BYTE_36_PA0_H_S 0
365 #define MPT_BYTE_36_PA0_H_M (((1UL << 5) - 1) << MPT_BYTE_36_PA0_H_S)
366
367 #define MPT_BYTE_36_PA1_L_S 8
368 #define MPT_BYTE_36_PA1_L_M (((1UL << 24) - 1) << MPT_BYTE_36_PA1_L_S)
369
370 #define MPT_BYTE_40_PA1_H_S 0
371 #define MPT_BYTE_40_PA1_H_M (((1UL << 13) - 1) << MPT_BYTE_40_PA1_H_S)
372
373 #define MPT_BYTE_40_PA2_L_S 16
374 #define MPT_BYTE_40_PA2_L_M (((1UL << 16) - 1) << MPT_BYTE_40_PA2_L_S)
375
376 #define MPT_BYTE_44_PA2_H_S 0
377 #define MPT_BYTE_44_PA2_H_M (((1UL << 21) - 1) << MPT_BYTE_44_PA2_H_S)
378
379 #define MPT_BYTE_44_PA3_L_S 24
380 #define MPT_BYTE_44_PA3_L_M (((1UL << 8) - 1) << MPT_BYTE_44_PA3_L_S)
381
382 #define MPT_BYTE_48_PA3_H_S 0
383 #define MPT_BYTE_48_PA3_H_M (((1UL << 29) - 1) << MPT_BYTE_48_PA3_H_S)
384
385 #define MPT_BYTE_56_PA4_H_S 0
386 #define MPT_BYTE_56_PA4_H_M (((1UL << 5) - 1) << MPT_BYTE_56_PA4_H_S)
387
388 #define MPT_BYTE_56_PA5_L_S 8
389 #define MPT_BYTE_56_PA5_L_M (((1UL << 24) - 1) << MPT_BYTE_56_PA5_L_S)
390
391 #define MPT_BYTE_60_PA5_H_S 0
392 #define MPT_BYTE_60_PA5_H_M (((1UL << 13) - 1) << MPT_BYTE_60_PA5_H_S)
393
394 #define MPT_BYTE_60_PA6_L_S 16
395 #define MPT_BYTE_60_PA6_L_M (((1UL << 16) - 1) << MPT_BYTE_60_PA6_L_S)
396
397 #define MPT_BYTE_64_PA6_H_S 0
398 #define MPT_BYTE_64_PA6_H_M (((1UL << 21) - 1) << MPT_BYTE_64_PA6_H_S)
399
400 #define MPT_BYTE_64_L_KEY_IDX_H_S 24
401 #define MPT_BYTE_64_L_KEY_IDX_H_M \
402 (((1UL << 8) - 1) << MPT_BYTE_64_L_KEY_IDX_H_S)
403
404 struct hns_roce_wqe_ctrl_seg {
405 __le32 sgl_pa_h;
406 __le32 flag;
407 union {
408 __be32 imm_data;
409 __le32 inv_key;
410 };
411 __le32 msg_length;
412 };
413
414 struct hns_roce_wqe_data_seg {
415 __le64 addr;
416 __le32 lkey;
417 __le32 len;
418 };
419
420 struct hns_roce_wqe_raddr_seg {
421 __le32 rkey;
422 __le32 len;
423 __le64 raddr;
424 };
425
426 struct hns_roce_rq_wqe_ctrl {
427 __le32 rwqe_byte_4;
428 __le32 rocee_sgl_ba_l;
429 __le32 rwqe_byte_12;
430 __le32 reserved[5];
431 };
432
433 #define RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S 16
434 #define RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M \
435 (((1UL << 6) - 1) << RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S)
436
437 #define HNS_ROCE_QP_DESTROY_TIMEOUT_MSECS 10000
438
439 #define GID_LEN 16
440
441 struct hns_roce_ud_send_wqe {
442 __le32 dmac_h;
443 __le32 u32_8;
444 __le32 immediate_data;
445
446 __le32 u32_16;
447 union {
448 unsigned char dgid[GID_LEN];
449 struct {
450 __le32 u32_20;
451 __le32 u32_24;
452 __le32 u32_28;
453 __le32 u32_32;
454 };
455 };
456
457 __le32 u32_36;
458 __le32 u32_40;
459
460 __le32 va0_l;
461 __le32 va0_h;
462 __le32 l_key0;
463
464 __le32 va1_l;
465 __le32 va1_h;
466 __le32 l_key1;
467 };
468
469 #define UD_SEND_WQE_U32_4_DMAC_0_S 0
470 #define UD_SEND_WQE_U32_4_DMAC_0_M \
471 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_0_S)
472
473 #define UD_SEND_WQE_U32_4_DMAC_1_S 8
474 #define UD_SEND_WQE_U32_4_DMAC_1_M \
475 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_1_S)
476
477 #define UD_SEND_WQE_U32_4_DMAC_2_S 16
478 #define UD_SEND_WQE_U32_4_DMAC_2_M \
479 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_2_S)
480
481 #define UD_SEND_WQE_U32_4_DMAC_3_S 24
482 #define UD_SEND_WQE_U32_4_DMAC_3_M \
483 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_3_S)
484
485 #define UD_SEND_WQE_U32_8_DMAC_4_S 0
486 #define UD_SEND_WQE_U32_8_DMAC_4_M \
487 (((1UL << 8) - 1) << UD_SEND_WQE_U32_8_DMAC_4_S)
488
489 #define UD_SEND_WQE_U32_8_DMAC_5_S 8
490 #define UD_SEND_WQE_U32_8_DMAC_5_M \
491 (((1UL << 8) - 1) << UD_SEND_WQE_U32_8_DMAC_5_S)
492
493 #define UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S 22
494
495 #define UD_SEND_WQE_U32_8_OPERATION_TYPE_S 16
496 #define UD_SEND_WQE_U32_8_OPERATION_TYPE_M \
497 (((1UL << 4) - 1) << UD_SEND_WQE_U32_8_OPERATION_TYPE_S)
498
499 #define UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S 24
500 #define UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M \
501 (((1UL << 6) - 1) << UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S)
502
503 #define UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S 31
504
505 #define UD_SEND_WQE_U32_16_DEST_QP_S 0
506 #define UD_SEND_WQE_U32_16_DEST_QP_M \
507 (((1UL << 24) - 1) << UD_SEND_WQE_U32_16_DEST_QP_S)
508
509 #define UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S 24
510 #define UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M \
511 (((1UL << 8) - 1) << UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S)
512
513 #define UD_SEND_WQE_U32_36_FLOW_LABEL_S 0
514 #define UD_SEND_WQE_U32_36_FLOW_LABEL_M \
515 (((1UL << 20) - 1) << UD_SEND_WQE_U32_36_FLOW_LABEL_S)
516
517 #define UD_SEND_WQE_U32_36_PRIORITY_S 20
518 #define UD_SEND_WQE_U32_36_PRIORITY_M \
519 (((1UL << 4) - 1) << UD_SEND_WQE_U32_36_PRIORITY_S)
520
521 #define UD_SEND_WQE_U32_36_SGID_INDEX_S 24
522 #define UD_SEND_WQE_U32_36_SGID_INDEX_M \
523 (((1UL << 8) - 1) << UD_SEND_WQE_U32_36_SGID_INDEX_S)
524
525 #define UD_SEND_WQE_U32_40_HOP_LIMIT_S 0
526 #define UD_SEND_WQE_U32_40_HOP_LIMIT_M \
527 (((1UL << 8) - 1) << UD_SEND_WQE_U32_40_HOP_LIMIT_S)
528
529 #define UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S 8
530 #define UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M \
531 (((1UL << 8) - 1) << UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S)
532
533 struct hns_roce_sqp_context {
534 __le32 qp1c_bytes_4;
535 __le32 sq_rq_bt_l;
536 __le32 qp1c_bytes_12;
537 __le32 qp1c_bytes_16;
538 __le32 qp1c_bytes_20;
539 __le32 cur_rq_wqe_ba_l;
540 __le32 qp1c_bytes_28;
541 __le32 qp1c_bytes_32;
542 __le32 cur_sq_wqe_ba_l;
543 __le32 qp1c_bytes_40;
544 };
545
546 #define QP1C_BYTES_4_QP_STATE_S 0
547 #define QP1C_BYTES_4_QP_STATE_M \
548 (((1UL << 3) - 1) << QP1C_BYTES_4_QP_STATE_S)
549
550 #define QP1C_BYTES_4_SQ_WQE_SHIFT_S 8
551 #define QP1C_BYTES_4_SQ_WQE_SHIFT_M \
552 (((1UL << 4) - 1) << QP1C_BYTES_4_SQ_WQE_SHIFT_S)
553
554 #define QP1C_BYTES_4_RQ_WQE_SHIFT_S 12
555 #define QP1C_BYTES_4_RQ_WQE_SHIFT_M \
556 (((1UL << 4) - 1) << QP1C_BYTES_4_RQ_WQE_SHIFT_S)
557
558 #define QP1C_BYTES_4_PD_S 16
559 #define QP1C_BYTES_4_PD_M (((1UL << 16) - 1) << QP1C_BYTES_4_PD_S)
560
561 #define QP1C_BYTES_12_SQ_RQ_BT_H_S 0
562 #define QP1C_BYTES_12_SQ_RQ_BT_H_M \
563 (((1UL << 17) - 1) << QP1C_BYTES_12_SQ_RQ_BT_H_S)
564
565 #define QP1C_BYTES_16_RQ_HEAD_S 0
566 #define QP1C_BYTES_16_RQ_HEAD_M (((1UL << 15) - 1) << QP1C_BYTES_16_RQ_HEAD_S)
567
568 #define QP1C_BYTES_16_PORT_NUM_S 16
569 #define QP1C_BYTES_16_PORT_NUM_M \
570 (((1UL << 3) - 1) << QP1C_BYTES_16_PORT_NUM_S)
571
572 #define QP1C_BYTES_16_SIGNALING_TYPE_S 27
573 #define QP1C_BYTES_16_LOCAL_ENABLE_E2E_CREDIT_S 28
574 #define QP1C_BYTES_16_RQ_BA_FLG_S 29
575 #define QP1C_BYTES_16_SQ_BA_FLG_S 30
576 #define QP1C_BYTES_16_QP1_ERR_S 31
577
578 #define QP1C_BYTES_20_SQ_HEAD_S 0
579 #define QP1C_BYTES_20_SQ_HEAD_M (((1UL << 15) - 1) << QP1C_BYTES_20_SQ_HEAD_S)
580
581 #define QP1C_BYTES_20_PKEY_IDX_S 16
582 #define QP1C_BYTES_20_PKEY_IDX_M \
583 (((1UL << 16) - 1) << QP1C_BYTES_20_PKEY_IDX_S)
584
585 #define QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S 0
586 #define QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M \
587 (((1UL << 5) - 1) << QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S)
588
589 #define QP1C_BYTES_28_RQ_CUR_IDX_S 16
590 #define QP1C_BYTES_28_RQ_CUR_IDX_M \
591 (((1UL << 15) - 1) << QP1C_BYTES_28_RQ_CUR_IDX_S)
592
593 #define QP1C_BYTES_32_TX_CQ_NUM_S 0
594 #define QP1C_BYTES_32_TX_CQ_NUM_M \
595 (((1UL << 16) - 1) << QP1C_BYTES_32_TX_CQ_NUM_S)
596
597 #define QP1C_BYTES_32_RX_CQ_NUM_S 16
598 #define QP1C_BYTES_32_RX_CQ_NUM_M \
599 (((1UL << 16) - 1) << QP1C_BYTES_32_RX_CQ_NUM_S)
600
601 #define QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S 0
602 #define QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M \
603 (((1UL << 5) - 1) << QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S)
604
605 #define QP1C_BYTES_40_SQ_CUR_IDX_S 16
606 #define QP1C_BYTES_40_SQ_CUR_IDX_M \
607 (((1UL << 15) - 1) << QP1C_BYTES_40_SQ_CUR_IDX_S)
608
609 #define HNS_ROCE_WQE_INLINE (1UL<<31)
610 #define HNS_ROCE_WQE_SE (1UL<<30)
611
612 #define HNS_ROCE_WQE_SGE_NUM_BIT 24
613 #define HNS_ROCE_WQE_IMM (1UL<<23)
614 #define HNS_ROCE_WQE_FENCE (1UL<<21)
615 #define HNS_ROCE_WQE_CQ_NOTIFY (1UL<<20)
616
617 #define HNS_ROCE_WQE_OPCODE_SEND (0<<16)
618 #define HNS_ROCE_WQE_OPCODE_RDMA_READ (1<<16)
619 #define HNS_ROCE_WQE_OPCODE_RDMA_WRITE (2<<16)
620 #define HNS_ROCE_WQE_OPCODE_LOCAL_INV (4<<16)
621 #define HNS_ROCE_WQE_OPCODE_UD_SEND (7<<16)
622 #define HNS_ROCE_WQE_OPCODE_MASK (15<<16)
623
624 struct hns_roce_qp_context {
625 __le32 qpc_bytes_4;
626 __le32 qpc_bytes_8;
627 __le32 qpc_bytes_12;
628 __le32 qpc_bytes_16;
629 __le32 sq_rq_bt_l;
630 __le32 qpc_bytes_24;
631 __le32 irrl_ba_l;
632 __le32 qpc_bytes_32;
633 __le32 qpc_bytes_36;
634 __le32 dmac_l;
635 __le32 qpc_bytes_44;
636 __le32 qpc_bytes_48;
637 u8 dgid[16];
638 __le32 qpc_bytes_68;
639 __le32 cur_rq_wqe_ba_l;
640 __le32 qpc_bytes_76;
641 __le32 rx_rnr_time;
642 __le32 qpc_bytes_84;
643 __le32 qpc_bytes_88;
644 union {
645 __le32 rx_sge_len;
646 __le32 dma_length;
647 };
648 union {
649 __le32 rx_sge_num;
650 __le32 rx_send_pktn;
651 __le32 r_key;
652 };
653 __le32 va_l;
654 __le32 va_h;
655 __le32 qpc_bytes_108;
656 __le32 qpc_bytes_112;
657 __le32 rx_cur_sq_wqe_ba_l;
658 __le32 qpc_bytes_120;
659 __le32 qpc_bytes_124;
660 __le32 qpc_bytes_128;
661 __le32 qpc_bytes_132;
662 __le32 qpc_bytes_136;
663 __le32 qpc_bytes_140;
664 __le32 qpc_bytes_144;
665 __le32 qpc_bytes_148;
666 union {
667 __le32 rnr_retry;
668 __le32 ack_time;
669 };
670 __le32 qpc_bytes_156;
671 __le32 pkt_use_len;
672 __le32 qpc_bytes_164;
673 __le32 qpc_bytes_168;
674 union {
675 __le32 sge_use_len;
676 __le32 pa_use_len;
677 };
678 __le32 qpc_bytes_176;
679 __le32 qpc_bytes_180;
680 __le32 tx_cur_sq_wqe_ba_l;
681 __le32 qpc_bytes_188;
682 __le32 rvd21;
683 };
684
685 #define QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S 0
686 #define QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M \
687 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S)
688
689 #define QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S 3
690 #define QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S 4
691 #define QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S 5
692 #define QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S 6
693 #define QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S 7
694
695 #define QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S 8
696 #define QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M \
697 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S)
698
699 #define QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S 12
700 #define QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M \
701 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S)
702
703 #define QP_CONTEXT_QPC_BYTES_4_PD_S 16
704 #define QP_CONTEXT_QPC_BYTES_4_PD_M \
705 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_4_PD_S)
706
707 #define QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S 0
708 #define QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M \
709 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S)
710
711 #define QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S 16
712 #define QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M \
713 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S)
714
715 #define QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S 0
716 #define QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M \
717 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S)
718
719 #define QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S 16
720 #define QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M \
721 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S)
722
723 #define QP_CONTEXT_QPC_BYTES_16_QP_NUM_S 0
724 #define QP_CONTEXT_QPC_BYTES_16_QP_NUM_M \
725 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_16_QP_NUM_S)
726
727 #define QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S 0
728 #define QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M \
729 (((1UL << 17) - 1) << QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S)
730
731 #define QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S 18
732 #define QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M \
733 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S)
734
735 #define QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S 23
736
737 #define QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S 0
738 #define QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M \
739 (((1UL << 17) - 1) << QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S)
740
741 #define QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S 18
742 #define QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M \
743 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S)
744
745 #define QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S 20
746 #define QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S 21
747 #define QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S 22
748 #define QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S 23
749
750 #define QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S 24
751 #define QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M \
752 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S)
753
754 #define QP_CONTEXT_QPC_BYTES_36_DEST_QP_S 0
755 #define QP_CONTEXT_QPC_BYTES_36_DEST_QP_M \
756 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_36_DEST_QP_S)
757
758 #define QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S 24
759 #define QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M \
760 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S)
761
762 #define QP_CONTEXT_QPC_BYTES_44_DMAC_H_S 0
763 #define QP_CONTEXT_QPC_BYTES_44_DMAC_H_M \
764 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_44_DMAC_H_S)
765
766 #define QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S 16
767 #define QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M \
768 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S)
769
770 #define QP_CONTEXT_QPC_BYTES_44_HOPLMT_S 24
771 #define QP_CONTEXT_QPC_BYTES_44_HOPLMT_M \
772 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_44_HOPLMT_S)
773
774 #define QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S 0
775 #define QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M \
776 (((1UL << 20) - 1) << QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S)
777
778 #define QP_CONTEXT_QPC_BYTES_48_TCLASS_S 20
779 #define QP_CONTEXT_QPC_BYTES_48_TCLASS_M \
780 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_48_TCLASS_S)
781
782 #define QP_CONTEXT_QPC_BYTES_48_MTU_S 28
783 #define QP_CONTEXT_QPC_BYTES_48_MTU_M \
784 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_48_MTU_S)
785
786 #define QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S 0
787 #define QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M \
788 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S)
789
790 #define QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S 16
791 #define QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M \
792 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S)
793
794 #define QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S 0
795 #define QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M \
796 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S)
797
798 #define QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S 8
799 #define QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M \
800 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S)
801
802 #define QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S 0
803 #define QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M \
804 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S)
805
806 #define QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S 24
807 #define QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M \
808 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S)
809
810 #define QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S 0
811 #define QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M \
812 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S)
813
814 #define QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S 24
815 #define QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S 25
816
817 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S 26
818 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M \
819 (((1UL << 2) - 1) << \
820 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S)
821
822 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S 29
823 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M \
824 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S)
825
826 #define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S 0
827 #define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M \
828 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S)
829
830 #define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S 24
831 #define QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S 25
832
833 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S 0
834 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M \
835 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S)
836
837 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S 24
838 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M \
839 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S)
840
841 #define QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S 0
842 #define QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M \
843 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S)
844
845 #define QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S 0
846 #define QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M \
847 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S)
848
849 #define QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S 16
850 #define QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M \
851 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S)
852
853 #define QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S 0
854 #define QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M \
855 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S)
856
857 #define QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S 24
858
859 #define QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S 25
860 #define QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M \
861 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S)
862
863 #define QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S 27
864
865 #define QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S 0
866 #define QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M \
867 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S)
868
869 #define QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S 24
870 #define QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M \
871 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S)
872
873 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S 0
874 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M \
875 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S)
876
877 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S 24
878 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M \
879 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S)
880
881 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S 0
882 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M \
883 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S)
884
885 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S 16
886 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M \
887 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S)
888
889 #define QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S 31
890
891 #define QP_CONTEXT_QPC_BYTES_144_QP_STATE_S 0
892 #define QP_CONTEXT_QPC_BYTES_144_QP_STATE_M \
893 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_144_QP_STATE_S)
894
895 #define QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S 0
896 #define QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M \
897 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S)
898
899 #define QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S 2
900 #define QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M \
901 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S)
902
903 #define QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S 5
904 #define QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M \
905 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S)
906
907 #define QP_CONTEXT_QPC_BYTES_148_LSN_S 8
908 #define QP_CONTEXT_QPC_BYTES_148_LSN_M \
909 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_148_LSN_S)
910
911 #define QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S 0
912 #define QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M \
913 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S)
914
915 #define QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S 3
916 #define QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M \
917 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S)
918
919 #define QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S 8
920 #define QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M \
921 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S)
922
923 #define QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S 11
924 #define QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M \
925 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S)
926
927 #define QP_CONTEXT_QPC_BYTES_156_SL_S 14
928 #define QP_CONTEXT_QPC_BYTES_156_SL_M \
929 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_156_SL_S)
930
931 #define QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S 16
932 #define QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M \
933 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S)
934
935 #define QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S 24
936 #define QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M \
937 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S)
938
939 #define QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S 0
940 #define QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M \
941 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S)
942
943 #define QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S 24
944 #define QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M \
945 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S)
946
947 #define QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S 0
948 #define QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M \
949 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S)
950
951 #define QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S 24
952 #define QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M \
953 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S)
954
955 #define QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S 26
956 #define QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M \
957 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S)
958
959 #define QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S 28
960 #define QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S 29
961 #define QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S 30
962
963 #define QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S 0
964 #define QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M \
965 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S)
966
967 #define QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S 16
968 #define QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M \
969 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S)
970
971 #define QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S 0
972 #define QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M \
973 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S)
974
975 #define QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S 16
976 #define QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M \
977 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S)
978
979 #define QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S 0
980 #define QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M \
981 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S)
982
983 #define QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S 8
984
985 #define QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S 16
986 #define QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M \
987 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S)
988
989 #define STATUS_MASK 0xff
990 #define GO_BIT_TIMEOUT_MSECS 10000
991 #define HCR_STATUS_OFFSET 0x18
992 #define HCR_GO_BIT 15
993
994 struct hns_roce_rq_db {
995 __le32 u32_4;
996 __le32 u32_8;
997 };
998
999 #define RQ_DOORBELL_U32_4_RQ_HEAD_S 0
1000 #define RQ_DOORBELL_U32_4_RQ_HEAD_M \
1001 (((1UL << 15) - 1) << RQ_DOORBELL_U32_4_RQ_HEAD_S)
1002
1003 #define RQ_DOORBELL_U32_8_QPN_S 0
1004 #define RQ_DOORBELL_U32_8_QPN_M (((1UL << 24) - 1) << RQ_DOORBELL_U32_8_QPN_S)
1005
1006 #define RQ_DOORBELL_U32_8_CMD_S 28
1007 #define RQ_DOORBELL_U32_8_CMD_M (((1UL << 3) - 1) << RQ_DOORBELL_U32_8_CMD_S)
1008
1009 #define RQ_DOORBELL_U32_8_HW_SYNC_S 31
1010
1011 struct hns_roce_sq_db {
1012 __le32 u32_4;
1013 __le32 u32_8;
1014 };
1015
1016 #define SQ_DOORBELL_U32_4_SQ_HEAD_S 0
1017 #define SQ_DOORBELL_U32_4_SQ_HEAD_M \
1018 (((1UL << 15) - 1) << SQ_DOORBELL_U32_4_SQ_HEAD_S)
1019
1020 #define SQ_DOORBELL_U32_4_SL_S 16
1021 #define SQ_DOORBELL_U32_4_SL_M \
1022 (((1UL << 2) - 1) << SQ_DOORBELL_U32_4_SL_S)
1023
1024 #define SQ_DOORBELL_U32_4_PORT_S 18
1025 #define SQ_DOORBELL_U32_4_PORT_M (((1UL << 3) - 1) << SQ_DOORBELL_U32_4_PORT_S)
1026
1027 #define SQ_DOORBELL_U32_8_QPN_S 0
1028 #define SQ_DOORBELL_U32_8_QPN_M (((1UL << 24) - 1) << SQ_DOORBELL_U32_8_QPN_S)
1029
1030 #define SQ_DOORBELL_HW_SYNC_S 31
1031
1032 struct hns_roce_ext_db {
1033 int esdb_dep;
1034 int eodb_dep;
1035 struct hns_roce_buf_list *sdb_buf_list;
1036 struct hns_roce_buf_list *odb_buf_list;
1037 };
1038
1039 struct hns_roce_db_table {
1040 int sdb_ext_mod;
1041 int odb_ext_mod;
1042 struct hns_roce_ext_db *ext_db;
1043 };
1044
1045 struct hns_roce_bt_table {
1046 struct hns_roce_buf_list qpc_buf;
1047 struct hns_roce_buf_list mtpt_buf;
1048 struct hns_roce_buf_list cqc_buf;
1049 };
1050
1051 struct hns_roce_tptr_table {
1052 struct hns_roce_buf_list tptr_buf;
1053 };
1054
1055 struct hns_roce_qp_work {
1056 struct work_struct work;
1057 struct ib_device *ib_dev;
1058 struct hns_roce_qp *qp;
1059 u32 db_wait_stage;
1060 u32 sdb_issue_ptr;
1061 u32 sdb_inv_cnt;
1062 u32 sche_cnt;
1063 };
1064
1065 struct hns_roce_mr_free_work {
1066 struct work_struct work;
1067 struct ib_device *ib_dev;
1068 struct completion *comp;
1069 int comp_flag;
1070 void *mr;
1071 };
1072
1073 struct hns_roce_recreate_lp_qp_work {
1074 struct work_struct work;
1075 struct ib_device *ib_dev;
1076 struct completion *comp;
1077 int comp_flag;
1078 };
1079
1080 struct hns_roce_free_mr {
1081 struct workqueue_struct *free_mr_wq;
1082 struct hns_roce_qp *mr_free_qp[HNS_ROCE_V1_RESV_QP];
1083 struct hns_roce_cq *mr_free_cq;
1084 struct hns_roce_pd *mr_free_pd;
1085 };
1086
1087 struct hns_roce_v1_priv {
1088 struct hns_roce_db_table db_table;
1089 struct hns_roce_raq_table raq_table;
1090 struct hns_roce_bt_table bt_table;
1091 struct hns_roce_tptr_table tptr_table;
1092 struct hns_roce_free_mr free_mr;
1093 };
1094
1095 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset);
1096 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1097 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata);
1098
1099 #endif