This source file includes following definitions.
- ice40_fpga_ops_state
- ice40_fpga_ops_write_init
- ice40_fpga_ops_write
- ice40_fpga_ops_write_complete
- ice40_fpga_probe
- ice40_fpga_remove
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11 #include <linux/fpga/fpga-mgr.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/module.h>
14 #include <linux/of_gpio.h>
15 #include <linux/spi/spi.h>
16 #include <linux/stringify.h>
17
18 #define ICE40_SPI_MAX_SPEED 25000000
19 #define ICE40_SPI_MIN_SPEED 1000000
20
21 #define ICE40_SPI_RESET_DELAY 1
22 #define ICE40_SPI_HOUSEKEEPING_DELAY 1200
23
24 #define ICE40_SPI_NUM_ACTIVATION_BYTES DIV_ROUND_UP(49, 8)
25
26 struct ice40_fpga_priv {
27 struct spi_device *dev;
28 struct gpio_desc *reset;
29 struct gpio_desc *cdone;
30 };
31
32 static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr)
33 {
34 struct ice40_fpga_priv *priv = mgr->priv;
35
36 return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING :
37 FPGA_MGR_STATE_UNKNOWN;
38 }
39
40 static int ice40_fpga_ops_write_init(struct fpga_manager *mgr,
41 struct fpga_image_info *info,
42 const char *buf, size_t count)
43 {
44 struct ice40_fpga_priv *priv = mgr->priv;
45 struct spi_device *dev = priv->dev;
46 struct spi_message message;
47 struct spi_transfer assert_cs_then_reset_delay = {
48 .cs_change = 1,
49 .delay_usecs = ICE40_SPI_RESET_DELAY
50 };
51 struct spi_transfer housekeeping_delay_then_release_cs = {
52 .delay_usecs = ICE40_SPI_HOUSEKEEPING_DELAY
53 };
54 int ret;
55
56 if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
57 dev_err(&dev->dev,
58 "Partial reconfiguration is not supported\n");
59 return -ENOTSUPP;
60 }
61
62
63 spi_bus_lock(dev->master);
64
65 gpiod_set_value(priv->reset, 1);
66
67 spi_message_init(&message);
68 spi_message_add_tail(&assert_cs_then_reset_delay, &message);
69 ret = spi_sync_locked(dev, &message);
70
71
72 gpiod_set_value(priv->reset, 0);
73
74
75 if (ret)
76 goto fail;
77
78
79 if (gpiod_get_value(priv->cdone)) {
80 dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n");
81 ret = -EIO;
82 goto fail;
83 }
84
85
86 spi_message_init(&message);
87 spi_message_add_tail(&housekeeping_delay_then_release_cs, &message);
88 ret = spi_sync_locked(dev, &message);
89
90 fail:
91 spi_bus_unlock(dev->master);
92
93 return ret;
94 }
95
96 static int ice40_fpga_ops_write(struct fpga_manager *mgr,
97 const char *buf, size_t count)
98 {
99 struct ice40_fpga_priv *priv = mgr->priv;
100
101 return spi_write(priv->dev, buf, count);
102 }
103
104 static int ice40_fpga_ops_write_complete(struct fpga_manager *mgr,
105 struct fpga_image_info *info)
106 {
107 struct ice40_fpga_priv *priv = mgr->priv;
108 struct spi_device *dev = priv->dev;
109 const u8 padding[ICE40_SPI_NUM_ACTIVATION_BYTES] = {0};
110
111
112 if (!gpiod_get_value(priv->cdone)) {
113 dev_err(&dev->dev,
114 "CDONE was not asserted after firmware transfer\n");
115 return -EIO;
116 }
117
118
119 return spi_write(dev, padding, sizeof(padding));
120 }
121
122 static const struct fpga_manager_ops ice40_fpga_ops = {
123 .state = ice40_fpga_ops_state,
124 .write_init = ice40_fpga_ops_write_init,
125 .write = ice40_fpga_ops_write,
126 .write_complete = ice40_fpga_ops_write_complete,
127 };
128
129 static int ice40_fpga_probe(struct spi_device *spi)
130 {
131 struct device *dev = &spi->dev;
132 struct ice40_fpga_priv *priv;
133 struct fpga_manager *mgr;
134 int ret;
135
136 priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
137 if (!priv)
138 return -ENOMEM;
139
140 priv->dev = spi;
141
142
143 if (spi->max_speed_hz > ICE40_SPI_MAX_SPEED) {
144 dev_err(dev, "SPI speed is too high, maximum speed is "
145 __stringify(ICE40_SPI_MAX_SPEED) "\n");
146 return -EINVAL;
147 }
148
149 if (spi->max_speed_hz < ICE40_SPI_MIN_SPEED) {
150 dev_err(dev, "SPI speed is too low, minimum speed is "
151 __stringify(ICE40_SPI_MIN_SPEED) "\n");
152 return -EINVAL;
153 }
154
155 if (spi->mode & SPI_CPHA) {
156 dev_err(dev, "Bad SPI mode, CPHA not supported\n");
157 return -EINVAL;
158 }
159
160
161 priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN);
162 if (IS_ERR(priv->cdone)) {
163 ret = PTR_ERR(priv->cdone);
164 dev_err(dev, "Failed to get CDONE GPIO: %d\n", ret);
165 return ret;
166 }
167
168 priv->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
169 if (IS_ERR(priv->reset)) {
170 ret = PTR_ERR(priv->reset);
171 dev_err(dev, "Failed to get CRESET_B GPIO: %d\n", ret);
172 return ret;
173 }
174
175 mgr = devm_fpga_mgr_create(dev, "Lattice iCE40 FPGA Manager",
176 &ice40_fpga_ops, priv);
177 if (!mgr)
178 return -ENOMEM;
179
180 spi_set_drvdata(spi, mgr);
181
182 return fpga_mgr_register(mgr);
183 }
184
185 static int ice40_fpga_remove(struct spi_device *spi)
186 {
187 struct fpga_manager *mgr = spi_get_drvdata(spi);
188
189 fpga_mgr_unregister(mgr);
190
191 return 0;
192 }
193
194 static const struct of_device_id ice40_fpga_of_match[] = {
195 { .compatible = "lattice,ice40-fpga-mgr", },
196 {},
197 };
198 MODULE_DEVICE_TABLE(of, ice40_fpga_of_match);
199
200 static struct spi_driver ice40_fpga_driver = {
201 .probe = ice40_fpga_probe,
202 .remove = ice40_fpga_remove,
203 .driver = {
204 .name = "ice40spi",
205 .of_match_table = of_match_ptr(ice40_fpga_of_match),
206 },
207 };
208
209 module_spi_driver(ice40_fpga_driver);
210
211 MODULE_AUTHOR("Joel Holdsworth <joel@airwebreathe.org.uk>");
212 MODULE_DESCRIPTION("Lattice iCE40 FPGA Manager");
213 MODULE_LICENSE("GPL v2");