drivers/hwmon/jc42.c

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This source file includes following definitions.
jc42_temp_to_reg
jc42_temp_from_reg
jc42_update_device
jc42_read
jc42_write
jc42_is_visible
jc42_detect
jc42_probe
jc42_remove
jc42_suspend
jc42_resume
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
   4  *
   5  * Copyright (c) 2010  Ericsson AB.
   6  *
   7  * Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
   8  *
   9  * JC42.4 compliant temperature sensors are typically used on memory modules.
  10  */
  11 
  12 #include <linux/bitops.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/slab.h>
  16 #include <linux/jiffies.h>
  17 #include <linux/i2c.h>
  18 #include <linux/hwmon.h>
  19 #include <linux/err.h>
  20 #include <linux/mutex.h>
  21 #include <linux/of.h>
  22 
  23 /* Addresses to scan */
  24 static const unsigned short normal_i2c[] = {
  25         0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
  26 
  27 /* JC42 registers. All registers are 16 bit. */
  28 #define JC42_REG_CAP            0x00
  29 #define JC42_REG_CONFIG         0x01
  30 #define JC42_REG_TEMP_UPPER     0x02
  31 #define JC42_REG_TEMP_LOWER     0x03
  32 #define JC42_REG_TEMP_CRITICAL  0x04
  33 #define JC42_REG_TEMP           0x05
  34 #define JC42_REG_MANID          0x06
  35 #define JC42_REG_DEVICEID       0x07
  36 #define JC42_REG_SMBUS          0x22 /* NXP and Atmel, possibly others? */
  37 
  38 /* Status bits in temperature register */
  39 #define JC42_ALARM_CRIT_BIT     15
  40 #define JC42_ALARM_MAX_BIT      14
  41 #define JC42_ALARM_MIN_BIT      13
  42 
  43 /* Configuration register defines */
  44 #define JC42_CFG_CRIT_ONLY      (1 << 2)
  45 #define JC42_CFG_TCRIT_LOCK     (1 << 6)
  46 #define JC42_CFG_EVENT_LOCK     (1 << 7)
  47 #define JC42_CFG_SHUTDOWN       (1 << 8)
  48 #define JC42_CFG_HYST_SHIFT     9
  49 #define JC42_CFG_HYST_MASK      (0x03 << 9)
  50 
  51 /* Capabilities */
  52 #define JC42_CAP_RANGE          (1 << 2)
  53 
  54 /* Manufacturer IDs */
  55 #define ADT_MANID               0x11d4  /* Analog Devices */
  56 #define ATMEL_MANID             0x001f  /* Atmel */
  57 #define ATMEL_MANID2            0x1114  /* Atmel */
  58 #define MAX_MANID               0x004d  /* Maxim */
  59 #define IDT_MANID               0x00b3  /* IDT */
  60 #define MCP_MANID               0x0054  /* Microchip */
  61 #define NXP_MANID               0x1131  /* NXP Semiconductors */
  62 #define ONS_MANID               0x1b09  /* ON Semiconductor */
  63 #define STM_MANID               0x104a  /* ST Microelectronics */
  64 #define GT_MANID                0x1c68  /* Giantec */
  65 #define GT_MANID2               0x132d  /* Giantec, 2nd mfg ID */
  66 
  67 /* SMBUS register */
  68 #define SMBUS_STMOUT            BIT(7)  /* SMBus time-out, active low */
  69 
  70 /* Supported chips */
  71 
  72 /* Analog Devices */
  73 #define ADT7408_DEVID           0x0801
  74 #define ADT7408_DEVID_MASK      0xffff
  75 
  76 /* Atmel */
  77 #define AT30TS00_DEVID          0x8201
  78 #define AT30TS00_DEVID_MASK     0xffff
  79 
  80 #define AT30TSE004_DEVID        0x2200
  81 #define AT30TSE004_DEVID_MASK   0xffff
  82 
  83 /* Giantec */
  84 #define GT30TS00_DEVID          0x2200
  85 #define GT30TS00_DEVID_MASK     0xff00
  86 
  87 #define GT34TS02_DEVID          0x3300
  88 #define GT34TS02_DEVID_MASK     0xff00
  89 
  90 /* IDT */
  91 #define TSE2004_DEVID           0x2200
  92 #define TSE2004_DEVID_MASK      0xff00
  93 
  94 #define TS3000_DEVID            0x2900  /* Also matches TSE2002 */
  95 #define TS3000_DEVID_MASK       0xff00
  96 
  97 #define TS3001_DEVID            0x3000
  98 #define TS3001_DEVID_MASK       0xff00
  99 
 100 /* Maxim */
 101 #define MAX6604_DEVID           0x3e00
 102 #define MAX6604_DEVID_MASK      0xffff
 103 
 104 /* Microchip */
 105 #define MCP9804_DEVID           0x0200
 106 #define MCP9804_DEVID_MASK      0xfffc
 107 
 108 #define MCP9808_DEVID           0x0400
 109 #define MCP9808_DEVID_MASK      0xfffc
 110 
 111 #define MCP98242_DEVID          0x2000
 112 #define MCP98242_DEVID_MASK     0xfffc
 113 
 114 #define MCP98243_DEVID          0x2100
 115 #define MCP98243_DEVID_MASK     0xfffc
 116 
 117 #define MCP98244_DEVID          0x2200
 118 #define MCP98244_DEVID_MASK     0xfffc
 119 
 120 #define MCP9843_DEVID           0x0000  /* Also matches mcp9805 */
 121 #define MCP9843_DEVID_MASK      0xfffe
 122 
 123 /* NXP */
 124 #define SE97_DEVID              0xa200
 125 #define SE97_DEVID_MASK         0xfffc
 126 
 127 #define SE98_DEVID              0xa100
 128 #define SE98_DEVID_MASK         0xfffc
 129 
 130 /* ON Semiconductor */
 131 #define CAT6095_DEVID           0x0800  /* Also matches CAT34TS02 */
 132 #define CAT6095_DEVID_MASK      0xffe0
 133 
 134 #define CAT34TS02C_DEVID        0x0a00
 135 #define CAT34TS02C_DEVID_MASK   0xfff0
 136 
 137 #define CAT34TS04_DEVID         0x2200
 138 #define CAT34TS04_DEVID_MASK    0xfff0
 139 
 140 /* ST Microelectronics */
 141 #define STTS424_DEVID           0x0101
 142 #define STTS424_DEVID_MASK      0xffff
 143 
 144 #define STTS424E_DEVID          0x0000
 145 #define STTS424E_DEVID_MASK     0xfffe
 146 
 147 #define STTS2002_DEVID          0x0300
 148 #define STTS2002_DEVID_MASK     0xffff
 149 
 150 #define STTS2004_DEVID          0x2201
 151 #define STTS2004_DEVID_MASK     0xffff
 152 
 153 #define STTS3000_DEVID          0x0200
 154 #define STTS3000_DEVID_MASK     0xffff
 155 
 156 static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
 157 
 158 struct jc42_chips {
 159         u16 manid;
 160         u16 devid;
 161         u16 devid_mask;
 162 };
 163 
 164 static struct jc42_chips jc42_chips[] = {
 165         { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
 166         { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
 167         { ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
 168         { GT_MANID, GT30TS00_DEVID, GT30TS00_DEVID_MASK },
 169         { GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK },
 170         { IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
 171         { IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
 172         { IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
 173         { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
 174         { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
 175         { MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK },
 176         { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
 177         { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
 178         { MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
 179         { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
 180         { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
 181         { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
 182         { ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK },
 183         { ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK },
 184         { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
 185         { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
 186         { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
 187         { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
 188         { STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
 189         { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
 190 };
 191 
 192 enum temp_index {
 193         t_input = 0,
 194         t_crit,
 195         t_min,
 196         t_max,
 197         t_num_temp
 198 };
 199 
 200 static const u8 temp_regs[t_num_temp] = {
 201         [t_input] = JC42_REG_TEMP,
 202         [t_crit] = JC42_REG_TEMP_CRITICAL,
 203         [t_min] = JC42_REG_TEMP_LOWER,
 204         [t_max] = JC42_REG_TEMP_UPPER,
 205 };
 206 
 207 /* Each client has this additional data */
 208 struct jc42_data {
 209         struct i2c_client *client;
 210         struct mutex    update_lock;    /* protect register access */
 211         bool            extended;       /* true if extended range supported */
 212         bool            valid;
 213         unsigned long   last_updated;   /* In jiffies */
 214         u16             orig_config;    /* original configuration */
 215         u16             config;         /* current configuration */
 216         u16             temp[t_num_temp];/* Temperatures */
 217 };
 218 
 219 #define JC42_TEMP_MIN_EXTENDED  (-40000)
 220 #define JC42_TEMP_MIN           0
 221 #define JC42_TEMP_MAX           125000
 222 
 223 static u16 jc42_temp_to_reg(long temp, bool extended)
 224 {
 225         int ntemp = clamp_val(temp,
 226                               extended ? JC42_TEMP_MIN_EXTENDED :
 227                               JC42_TEMP_MIN, JC42_TEMP_MAX);
 228 
 229         /* convert from 0.001 to 0.0625 resolution */
 230         return (ntemp * 2 / 125) & 0x1fff;
 231 }
 232 
 233 static int jc42_temp_from_reg(s16 reg)
 234 {
 235         reg = sign_extend32(reg, 12);
 236 
 237         /* convert from 0.0625 to 0.001 resolution */
 238         return reg * 125 / 2;
 239 }
 240 
 241 static struct jc42_data *jc42_update_device(struct device *dev)
 242 {
 243         struct jc42_data *data = dev_get_drvdata(dev);
 244         struct i2c_client *client = data->client;
 245         struct jc42_data *ret = data;
 246         int i, val;
 247 
 248         mutex_lock(&data->update_lock);
 249 
 250         if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
 251                 for (i = 0; i < t_num_temp; i++) {
 252                         val = i2c_smbus_read_word_swapped(client, temp_regs[i]);
 253                         if (val < 0) {
 254                                 ret = ERR_PTR(val);
 255                                 goto abort;
 256                         }
 257                         data->temp[i] = val;
 258                 }
 259                 data->last_updated = jiffies;
 260                 data->valid = true;
 261         }
 262 abort:
 263         mutex_unlock(&data->update_lock);
 264         return ret;
 265 }
 266 
 267 static int jc42_read(struct device *dev, enum hwmon_sensor_types type,
 268                      u32 attr, int channel, long *val)
 269 {
 270         struct jc42_data *data = jc42_update_device(dev);
 271         int temp, hyst;
 272 
 273         if (IS_ERR(data))
 274                 return PTR_ERR(data);
 275 
 276         switch (attr) {
 277         case hwmon_temp_input:
 278                 *val = jc42_temp_from_reg(data->temp[t_input]);
 279                 return 0;
 280         case hwmon_temp_min:
 281                 *val = jc42_temp_from_reg(data->temp[t_min]);
 282                 return 0;
 283         case hwmon_temp_max:
 284                 *val = jc42_temp_from_reg(data->temp[t_max]);
 285                 return 0;
 286         case hwmon_temp_crit:
 287                 *val = jc42_temp_from_reg(data->temp[t_crit]);
 288                 return 0;
 289         case hwmon_temp_max_hyst:
 290                 temp = jc42_temp_from_reg(data->temp[t_max]);
 291                 hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
 292                                                 >> JC42_CFG_HYST_SHIFT];
 293                 *val = temp - hyst;
 294                 return 0;
 295         case hwmon_temp_crit_hyst:
 296                 temp = jc42_temp_from_reg(data->temp[t_crit]);
 297                 hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
 298                                                 >> JC42_CFG_HYST_SHIFT];
 299                 *val = temp - hyst;
 300                 return 0;
 301         case hwmon_temp_min_alarm:
 302                 *val = (data->temp[t_input] >> JC42_ALARM_MIN_BIT) & 1;
 303                 return 0;
 304         case hwmon_temp_max_alarm:
 305                 *val = (data->temp[t_input] >> JC42_ALARM_MAX_BIT) & 1;
 306                 return 0;
 307         case hwmon_temp_crit_alarm:
 308                 *val = (data->temp[t_input] >> JC42_ALARM_CRIT_BIT) & 1;
 309                 return 0;
 310         default:
 311                 return -EOPNOTSUPP;
 312         }
 313 }
 314 
 315 static int jc42_write(struct device *dev, enum hwmon_sensor_types type,
 316                       u32 attr, int channel, long val)
 317 {
 318         struct jc42_data *data = dev_get_drvdata(dev);
 319         struct i2c_client *client = data->client;
 320         int diff, hyst;
 321         int ret;
 322 
 323         mutex_lock(&data->update_lock);
 324 
 325         switch (attr) {
 326         case hwmon_temp_min:
 327                 data->temp[t_min] = jc42_temp_to_reg(val, data->extended);
 328                 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_min],
 329                                                    data->temp[t_min]);
 330                 break;
 331         case hwmon_temp_max:
 332                 data->temp[t_max] = jc42_temp_to_reg(val, data->extended);
 333                 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_max],
 334                                                    data->temp[t_max]);
 335                 break;
 336         case hwmon_temp_crit:
 337                 data->temp[t_crit] = jc42_temp_to_reg(val, data->extended);
 338                 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_crit],
 339                                                    data->temp[t_crit]);
 340                 break;
 341         case hwmon_temp_crit_hyst:
 342                 /*
 343                  * JC42.4 compliant chips only support four hysteresis values.
 344                  * Pick best choice and go from there.
 345                  */
 346                 val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED
 347                                                      : JC42_TEMP_MIN) - 6000,
 348                                 JC42_TEMP_MAX);
 349                 diff = jc42_temp_from_reg(data->temp[t_crit]) - val;
 350                 hyst = 0;
 351                 if (diff > 0) {
 352                         if (diff < 2250)
 353                                 hyst = 1;       /* 1.5 degrees C */
 354                         else if (diff < 4500)
 355                                 hyst = 2;       /* 3.0 degrees C */
 356                         else
 357                                 hyst = 3;       /* 6.0 degrees C */
 358                 }
 359                 data->config = (data->config & ~JC42_CFG_HYST_MASK) |
 360                                 (hyst << JC42_CFG_HYST_SHIFT);
 361                 ret = i2c_smbus_write_word_swapped(data->client,
 362                                                    JC42_REG_CONFIG,
 363                                                    data->config);
 364                 break;
 365         default:
 366                 ret = -EOPNOTSUPP;
 367                 break;
 368         }
 369 
 370         mutex_unlock(&data->update_lock);
 371 
 372         return ret;
 373 }
 374 
 375 static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type,
 376                                u32 attr, int channel)
 377 {
 378         const struct jc42_data *data = _data;
 379         unsigned int config = data->config;
 380         umode_t mode = 0444;
 381 
 382         switch (attr) {
 383         case hwmon_temp_min:
 384         case hwmon_temp_max:
 385                 if (!(config & JC42_CFG_EVENT_LOCK))
 386                         mode |= 0200;
 387                 break;
 388         case hwmon_temp_crit:
 389                 if (!(config & JC42_CFG_TCRIT_LOCK))
 390                         mode |= 0200;
 391                 break;
 392         case hwmon_temp_crit_hyst:
 393                 if (!(config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK)))
 394                         mode |= 0200;
 395                 break;
 396         case hwmon_temp_input:
 397         case hwmon_temp_max_hyst:
 398         case hwmon_temp_min_alarm:
 399         case hwmon_temp_max_alarm:
 400         case hwmon_temp_crit_alarm:
 401                 break;
 402         default:
 403                 mode = 0;
 404                 break;
 405         }
 406         return mode;
 407 }
 408 
 409 /* Return 0 if detection is successful, -ENODEV otherwise */
 410 static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info)
 411 {
 412         struct i2c_adapter *adapter = client->adapter;
 413         int i, config, cap, manid, devid;
 414 
 415         if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
 416                                      I2C_FUNC_SMBUS_WORD_DATA))
 417                 return -ENODEV;
 418 
 419         cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
 420         config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
 421         manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
 422         devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);
 423 
 424         if (cap < 0 || config < 0 || manid < 0 || devid < 0)
 425                 return -ENODEV;
 426 
 427         if ((cap & 0xff00) || (config & 0xf800))
 428                 return -ENODEV;
 429 
 430         for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
 431                 struct jc42_chips *chip = &jc42_chips[i];
 432                 if (manid == chip->manid &&
 433                     (devid & chip->devid_mask) == chip->devid) {
 434                         strlcpy(info->type, "jc42", I2C_NAME_SIZE);
 435                         return 0;
 436                 }
 437         }
 438         return -ENODEV;
 439 }
 440 
 441 static const struct hwmon_channel_info *jc42_info[] = {
 442         HWMON_CHANNEL_INFO(temp,
 443                            HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
 444                            HWMON_T_CRIT | HWMON_T_MAX_HYST |
 445                            HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
 446                            HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM),
 447         NULL
 448 };
 449 
 450 static const struct hwmon_ops jc42_hwmon_ops = {
 451         .is_visible = jc42_is_visible,
 452         .read = jc42_read,
 453         .write = jc42_write,
 454 };
 455 
 456 static const struct hwmon_chip_info jc42_chip_info = {
 457         .ops = &jc42_hwmon_ops,
 458         .info = jc42_info,
 459 };
 460 
 461 static int jc42_probe(struct i2c_client *client, const struct i2c_device_id *id)
 462 {
 463         struct device *dev = &client->dev;
 464         struct device *hwmon_dev;
 465         struct jc42_data *data;
 466         int config, cap;
 467 
 468         data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
 469         if (!data)
 470                 return -ENOMEM;
 471 
 472         data->client = client;
 473         i2c_set_clientdata(client, data);
 474         mutex_init(&data->update_lock);
 475 
 476         cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
 477         if (cap < 0)
 478                 return cap;
 479 
 480         data->extended = !!(cap & JC42_CAP_RANGE);
 481 
 482         if (device_property_read_bool(dev, "smbus-timeout-disable")) {
 483                 int smbus;
 484 
 485                 /*
 486                  * Not all chips support this register, but from a
 487                  * quick read of various datasheets no chip appears
 488                  * incompatible with the below attempt to disable
 489                  * the timeout. And the whole thing is opt-in...
 490                  */
 491                 smbus = i2c_smbus_read_word_swapped(client, JC42_REG_SMBUS);
 492                 if (smbus < 0)
 493                         return smbus;
 494                 i2c_smbus_write_word_swapped(client, JC42_REG_SMBUS,
 495                                              smbus | SMBUS_STMOUT);
 496         }
 497 
 498         config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
 499         if (config < 0)
 500                 return config;
 501 
 502         data->orig_config = config;
 503         if (config & JC42_CFG_SHUTDOWN) {
 504                 config &= ~JC42_CFG_SHUTDOWN;
 505                 i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
 506         }
 507         data->config = config;
 508 
 509         hwmon_dev = devm_hwmon_device_register_with_info(dev, "jc42",
 510                                                          data, &jc42_chip_info,
 511                                                          NULL);
 512         return PTR_ERR_OR_ZERO(hwmon_dev);
 513 }
 514 
 515 static int jc42_remove(struct i2c_client *client)
 516 {
 517         struct jc42_data *data = i2c_get_clientdata(client);
 518 
 519         /* Restore original configuration except hysteresis */
 520         if ((data->config & ~JC42_CFG_HYST_MASK) !=
 521             (data->orig_config & ~JC42_CFG_HYST_MASK)) {
 522                 int config;
 523 
 524                 config = (data->orig_config & ~JC42_CFG_HYST_MASK)
 525                   | (data->config & JC42_CFG_HYST_MASK);
 526                 i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
 527         }
 528         return 0;
 529 }
 530 
 531 #ifdef CONFIG_PM
 532 
 533 static int jc42_suspend(struct device *dev)
 534 {
 535         struct jc42_data *data = dev_get_drvdata(dev);
 536 
 537         data->config |= JC42_CFG_SHUTDOWN;
 538         i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
 539                                      data->config);
 540         return 0;
 541 }
 542 
 543 static int jc42_resume(struct device *dev)
 544 {
 545         struct jc42_data *data = dev_get_drvdata(dev);
 546 
 547         data->config &= ~JC42_CFG_SHUTDOWN;
 548         i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
 549                                      data->config);
 550         return 0;
 551 }
 552 
 553 static const struct dev_pm_ops jc42_dev_pm_ops = {
 554         .suspend = jc42_suspend,
 555         .resume = jc42_resume,
 556 };
 557 
 558 #define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
 559 #else
 560 #define JC42_DEV_PM_OPS NULL
 561 #endif /* CONFIG_PM */
 562 
 563 static const struct i2c_device_id jc42_id[] = {
 564         { "jc42", 0 },
 565         { }
 566 };
 567 MODULE_DEVICE_TABLE(i2c, jc42_id);
 568 
 569 #ifdef CONFIG_OF
 570 static const struct of_device_id jc42_of_ids[] = {
 571         { .compatible = "jedec,jc-42.4-temp", },
 572         { }
 573 };
 574 MODULE_DEVICE_TABLE(of, jc42_of_ids);
 575 #endif
 576 
 577 static struct i2c_driver jc42_driver = {
 578         .class          = I2C_CLASS_SPD | I2C_CLASS_HWMON,
 579         .driver = {
 580                 .name   = "jc42",
 581                 .pm = JC42_DEV_PM_OPS,
 582                 .of_match_table = of_match_ptr(jc42_of_ids),
 583         },
 584         .probe          = jc42_probe,
 585         .remove         = jc42_remove,
 586         .id_table       = jc42_id,
 587         .detect         = jc42_detect,
 588         .address_list   = normal_i2c,
 589 };
 590 
 591 module_i2c_driver(jc42_driver);
 592 
 593 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
 594 MODULE_DESCRIPTION("JC42 driver");
 595 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/hwmon/jc42.c

DEFINITIONS
