1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Defines for the address space, registers and register configuration
4 * (bit masks, access macros etc) for the PMC-Sierra line of MSP products.
5 * This file contains addess maps for all the devices in the line of
6 * products but only has register definitions and configuration masks for
7 * registers which aren't definitely associated with any device. Things
8 * like clock settings, reset access, the ELB etc. Individual device
9 * drivers will reference the appropriate XXX_BASE value defined here
10 * and have individual registers offset from that.
11 *
12 * Copyright (C) 2005-2007 PMC-Sierra, Inc. All rights reserved.
13 * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
14 *
15 * ########################################################################
16 *
17 * ########################################################################
18 */
19
20 #include <asm/addrspace.h>
21 #include <linux/types.h>
22
23 #ifndef _ASM_MSP_REGS_H
24 #define _ASM_MSP_REGS_H
25
26 /*
27 ########################################################################
28 # Address space and device base definitions #
29 ########################################################################
30 */
31
32 /*
33 ***************************************************************************
34 * System Logic and Peripherals (ELB, UART0, etc) device address space *
35 ***************************************************************************
36 */
37 #define MSP_SLP_BASE 0x1c000000
38 /* System Logic and Peripherals */
39 #define MSP_RST_BASE (MSP_SLP_BASE + 0x10)
40 /* System reset register base */
41 #define MSP_RST_SIZE 0x0C /* System reset register space */
42
43 #define MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C)
44 /* watchdog timer base */
45 #define MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054)
46 /* internal timer base */
47 #define MSP_UART0_BASE (MSP_SLP_BASE + 0x100)
48 /* UART0 controller base */
49 #define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120)
50 /* Block Copy controller base */
51 #define MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160)
52 /* Block Copy descriptor base */
53
54 /*
55 ***************************************************************************
56 * PCI address space *
57 ***************************************************************************
58 */
59 #define MSP_PCI_BASE 0x19000000
60
61 /*
62 ***************************************************************************
63 * MSbus device address space *
64 ***************************************************************************
65 */
66 #define MSP_MSB_BASE 0x18000000
67 /* MSbus address start */
68 #define MSP_PER_BASE (MSP_MSB_BASE + 0x400000)
69 /* Peripheral device registers */
70 #define MSP_MAC0_BASE (MSP_MSB_BASE + 0x600000)
71 /* MAC A device registers */
72 #define MSP_MAC1_BASE (MSP_MSB_BASE + 0x700000)
73 /* MAC B device registers */
74 #define MSP_MAC_SIZE 0xE0 /* MAC register space */
75
76 #define MSP_SEC_BASE (MSP_MSB_BASE + 0x800000)
77 /* Security Engine registers */
78 #define MSP_MAC2_BASE (MSP_MSB_BASE + 0x900000)
79 /* MAC C device registers */
80 #define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000)
81 /* ADSL2 device registers */
82 #define MSP_USB0_BASE (MSP_MSB_BASE + 0xB00000)
83 /* USB0 device registers */
84 #define MSP_USB1_BASE (MSP_MSB_BASE + 0x300000)
85 /* USB1 device registers */
86 #define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000)
87 /* CPU interface registers */
88
89 /* Devices within the MSbus peripheral block */
90 #define MSP_UART1_BASE (MSP_PER_BASE + 0x030)
91 /* UART1 controller base */
92 #define MSP_SPI_BASE (MSP_PER_BASE + 0x058)
93 /* SPI/MPI control registers */
94 #define MSP_TWI_BASE (MSP_PER_BASE + 0x090)
95 /* Two-wire control registers */
96 #define MSP_PTIMER_BASE (MSP_PER_BASE + 0x0F0)
97 /* Programmable timer control */
98
99 /*
100 ***************************************************************************
101 * Physical Memory configuration address space *
102 ***************************************************************************
103 */
104 #define MSP_MEM_CFG_BASE 0x17f00000
105
106 #define MSP_MEM_INDIRECT_CTL_10 0x10
107
108 /*
109 * Notes:
110 * 1) The SPI registers are split into two blocks, one offset from the
111 * MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by
112 * 0x68. The SPI driver definitions for the register must be aware
113 * of this.
114 * 2) The block copy engine register are divided into two regions, one
115 * for the control/configuration of the engine proper and one for the
116 * values of the descriptors used in the copy process. These have
117 * different base defines (CTRL_BASE vs DESC_BASE)
118 * 3) These constants are for physical addresses which means that they
119 * work correctly with "ioremap" and friends. This means that device
120 * drivers will need to remap these addresses using ioremap and perhaps
121 * the readw/writew macros. Or they could use the regptr() macro
122 * defined below, but the readw/writew calls are the correct thing.
123 * 4) The UARTs have an additional status register offset from the base
124 * address. This register isn't used in the standard 8250 driver but
125 * may be used in other software. Consult the hardware datasheet for
126 * offset details.
127 * 5) For some unknown reason the security engine (MSP_SEC_BASE) registers
128 * start at an offset of 0x84 from the base address but the block of
129 * registers before this is reserved for the security engine. The
130 * driver will have to be aware of this but it makes the register
131 * definitions line up better with the documentation.
132 */
133
134 /*
135 ########################################################################
136 # System register definitions. Not associated with a specific device #
137 ########################################################################
138 */
139
140 /*
141 * This macro maps the physical register number into uncached space
142 * and (for C code) casts it into a u32 pointer so it can be dereferenced
143 * Normally these would be accessed with ioremap and readX/writeX, but
144 * these are convenient for a lot of internal kernel code.
145 */
146 #ifdef __ASSEMBLER__
147 #define regptr(addr) (KSEG1ADDR(addr))
148 #else
149 #define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr)))
150 #endif
151
152 /*
153 ***************************************************************************
154 * System Logic and Peripherals (RESET, ELB, etc) registers *
155 ***************************************************************************
156 */
157
158 /* System Control register definitions */
159 #define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00)
160 /* Device-ID RO */
161 #define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04)
162 /* Firmware-ID Register RW */
163 #define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08)
164 /* System-ID Register-0 RW */
165 #define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C)
166 /* System-ID Register-1 RW */
167
168 /* System Reset register definitions */
169 #define RST_STS_REG regptr(MSP_SLP_BASE + 0x10)
170 /* System Reset Status RO */
171 #define RST_SET_REG regptr(MSP_SLP_BASE + 0x14)
172 /* System Set Reset WO */
173 #define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18)
174 /* System Clear Reset WO */
175
176 /* System Clock Registers */
177 #define PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C)
178 /* PCI clock generator RW */
179 #define URT_SLP_REG regptr(MSP_SLP_BASE + 0x20)
180 /* UART clock generator RW */
181 /* reserved (MSP_SLP_BASE + 0x24) */
182 /* reserved (MSP_SLP_BASE + 0x28) */
183 #define PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C)
184 /* PLL1 clock generator RW */
185 #define PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30)
186 /* PLL0 clock generator RW */
187 #define MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34)
188 /* MIPS clock generator RW */
189 #define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38)
190 /* Voice Eng clock generator RW */
191 /* reserved (MSP_SLP_BASE + 0x3C) */
192 #define MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40)
193 /* MS-Bus clock generator RW */
194 #define SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44)
195 /* Sec & MAC clock generator RW */
196 #define PERF_SLP_REG regptr(MSP_SLP_BASE + 0x48)
197 /* Per & TDM clock generator RW */
198
199 /* Interrupt Controller Registers */
200 #define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)
201 /* Interrupt status register RW */
202 #define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)
203 /* Interrupt enable/mask RW */
204 #define SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78)
205 /* Security Engine mailbox RW */
206 #define VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C)
207 /* Voice Engine mailbox RW */
208
209 /* ELB Controller Registers */
210 #define CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80)
211 /* ELB CS0 Configuration Reg */
212 #define CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84)
213 /* ELB CS0 Base Address Reg */
214 #define CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88)
215 /* ELB CS0 Mask Register */
216 #define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C)
217 /* ELB CS0 access register */
218
219 #define CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90)
220 /* ELB CS1 Configuration Reg */
221 #define CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94)
222 /* ELB CS1 Base Address Reg */
223 #define CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98)
224 /* ELB CS1 Mask Register */
225 #define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C)
226 /* ELB CS1 access register */
227
228 #define CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0)
229 /* ELB CS2 Configuration Reg */
230 #define CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4)
231 /* ELB CS2 Base Address Reg */
232 #define CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8)
233 /* ELB CS2 Mask Register */
234 #define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC)
235 /* ELB CS2 access register */
236
237 #define CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0)
238 /* ELB CS3 Configuration Reg */
239 #define CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4)
240 /* ELB CS3 Base Address Reg */
241 #define CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8)
242 /* ELB CS3 Mask Register */
243 #define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC)
244 /* ELB CS3 access register */
245
246 #define CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0)
247 /* ELB CS4 Configuration Reg */
248 #define CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4)
249 /* ELB CS4 Base Address Reg */
250 #define CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8)
251 /* ELB CS4 Mask Register */
252 #define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC)
253 /* ELB CS4 access register */
254
255 #define CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0)
256 /* ELB CS5 Configuration Reg */
257 #define CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4)
258 /* ELB CS5 Base Address Reg */
259 #define CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8)
260 /* ELB CS5 Mask Register */
261 #define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC)
262 /* ELB CS5 access register */
263
264 /* reserved 0xE0 - 0xE8 */
265 #define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC)
266 /* ELB single PC card detect */
267
268 /* reserved 0xF0 - 0xF8 */
269 #define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)
270 /* SDRAM read/ELB timing Reg */
271
272 /* Extended UART status registers */
273 #define UART0_STATUS_REG regptr(MSP_UART0_BASE + 0x0c0)
274 /* UART Status Register 0 */
275 #define UART1_STATUS_REG regptr(MSP_UART1_BASE + 0x170)
276 /* UART Status Register 1 */
277
278 /* Performance monitoring registers */
279 #define PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140)
280 /* Performance monitor control */
281 #define PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144)
282 /* Performance monitor clear */
283 #define PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148)
284 /* Perf monitor counter high */
285 #define PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C)
286 /* Perf monitor counter low */
287
288 /* System control registers */
289 #define SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150)
290 /* System control register */
291 #define SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154)
292 /* System Error status 1 */
293 #define SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158)
294 /* System Error status 2 */
295 #define SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C)
296 /* System Interrupt config */
297
298 /* Voice Engine Memory configuration */
299 #define VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C)
300 /* Voice engine memory config */
301
302 /* CPU/SLP Error Status registers */
303 #define CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180)
304 /* CPU/SLP Error status 1 */
305 #define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184)
306 /* CPU/SLP Error status 1 */
307
308 /* Extended GPIO registers */
309 #define EXTENDED_GPIO1_REG regptr(MSP_SLP_BASE + 0x188)
310 #define EXTENDED_GPIO2_REG regptr(MSP_SLP_BASE + 0x18c)
311 #define EXTENDED_GPIO_REG EXTENDED_GPIO1_REG
312 /* Backward-compatibility */
313
314 /* System Error registers */
315 #define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190)
316 /* Int status for SLP errors */
317 #define SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194)
318 /* Int mask for SLP errors */
319 #define SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198)
320 /* External ELB reset */
321 #define SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C)
322 /* Boot Status */
323
324 /* Extended ELB addressing */
325 #define CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0)
326 /* CS0 Extended address */
327 #define CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4)
328 /* CS1 Extended address */
329 #define CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8)
330 /* CS2 Extended address */
331 #define CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC)
332 /* CS3 Extended address */
333 /* reserved 0x1B0 */
334 #define CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4)
335 /* CS5 Extended address */
336
337 /* PLL Adjustment registers */
338 #define PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200)
339 /* PLL0 lock status */
340 #define PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204)
341 /* PLL Analog reset status */
342 #define PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208)
343 /* PLL0 Adjustment value */
344 #define PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C)
345 /* PLL1 Adjustment value */
346
347 /*
348 ***************************************************************************
349 * Peripheral Register definitions *
350 ***************************************************************************
351 */
352
353 /* Peripheral status */
354 #define PER_CTRL_REG regptr(MSP_PER_BASE + 0x50)
355 /* Peripheral control register */
356 #define PER_STS_REG regptr(MSP_PER_BASE + 0x54)
357 /* Peripheral status register */
358
359 /* SPI/MPI Registers */
360 #define SMPI_TX_SZ_REG regptr(MSP_PER_BASE + 0x58)
361 /* SPI/MPI Tx Size register */
362 #define SMPI_RX_SZ_REG regptr(MSP_PER_BASE + 0x5C)
363 /* SPI/MPI Rx Size register */
364 #define SMPI_CTL_REG regptr(MSP_PER_BASE + 0x60)
365 /* SPI/MPI Control register */
366 #define SMPI_MS_REG regptr(MSP_PER_BASE + 0x64)
367 /* SPI/MPI Chip Select reg */
368 #define SMPI_CORE_DATA_REG regptr(MSP_PER_BASE + 0xC0)
369 /* SPI/MPI Core Data reg */
370 #define SMPI_CORE_CTRL_REG regptr(MSP_PER_BASE + 0xC4)
371 /* SPI/MPI Core Control reg */
372 #define SMPI_CORE_STAT_REG regptr(MSP_PER_BASE + 0xC8)
373 /* SPI/MPI Core Status reg */
374 #define SMPI_CORE_SSEL_REG regptr(MSP_PER_BASE + 0xCC)
375 /* SPI/MPI Core Ssel reg */
376 #define SMPI_FIFO_REG regptr(MSP_PER_BASE + 0xD0)
377 /* SPI/MPI Data FIFO reg */
378
379 /* Peripheral Block Error Registers */
380 #define PER_ERR_STS_REG regptr(MSP_PER_BASE + 0x70)
381 /* Error Bit Status Register */
382 #define PER_ERR_MSK_REG regptr(MSP_PER_BASE + 0x74)
383 /* Error Bit Mask Register */
384 #define PER_HDR1_REG regptr(MSP_PER_BASE + 0x78)
385 /* Error Header 1 Register */
386 #define PER_HDR2_REG regptr(MSP_PER_BASE + 0x7C)
387 /* Error Header 2 Register */
388
389 /* Peripheral Block Interrupt Registers */
390 #define PER_INT_STS_REG regptr(MSP_PER_BASE + 0x80)
391 /* Interrupt status register */
392 #define PER_INT_MSK_REG regptr(MSP_PER_BASE + 0x84)
393 /* Interrupt Mask Register */
394 #define GPIO_INT_STS_REG regptr(MSP_PER_BASE + 0x88)
395 /* GPIO interrupt status reg */
396 #define GPIO_INT_MSK_REG regptr(MSP_PER_BASE + 0x8C)
397 /* GPIO interrupt MASK Reg */
398
399 /* POLO GPIO registers */
400 #define POLO_GPIO_DAT1_REG regptr(MSP_PER_BASE + 0x0E0)
401 /* Polo GPIO[8:0] data reg */
402 #define POLO_GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x0E4)
403 /* Polo GPIO[7:0] config reg */
404 #define POLO_GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x0E8)
405 /* Polo GPIO[15:8] config reg */
406 #define POLO_GPIO_OD1_REG regptr(MSP_PER_BASE + 0x0EC)
407 /* Polo GPIO[31:0] output drive */
408 #define POLO_GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x170)
409 /* Polo GPIO[23:16] config reg */
410 #define POLO_GPIO_DAT2_REG regptr(MSP_PER_BASE + 0x174)
411 /* Polo GPIO[15:9] data reg */
412 #define POLO_GPIO_DAT3_REG regptr(MSP_PER_BASE + 0x178)
413 /* Polo GPIO[23:16] data reg */
414 #define POLO_GPIO_DAT4_REG regptr(MSP_PER_BASE + 0x17C)
415 /* Polo GPIO[31:24] data reg */
416 #define POLO_GPIO_DAT5_REG regptr(MSP_PER_BASE + 0x180)
417 /* Polo GPIO[39:32] data reg */
418 #define POLO_GPIO_DAT6_REG regptr(MSP_PER_BASE + 0x184)
419 /* Polo GPIO[47:40] data reg */
420 #define POLO_GPIO_DAT7_REG regptr(MSP_PER_BASE + 0x188)
421 /* Polo GPIO[54:48] data reg */
422 #define POLO_GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)
423 /* Polo GPIO[31:24] config reg */
424 #define POLO_GPIO_CFG5_REG regptr(MSP_PER_BASE + 0x190)
425 /* Polo GPIO[39:32] config reg */
426 #define POLO_GPIO_CFG6_REG regptr(MSP_PER_BASE + 0x194)
427 /* Polo GPIO[47:40] config reg */
428 #define POLO_GPIO_CFG7_REG regptr(MSP_PER_BASE + 0x198)
429 /* Polo GPIO[54:48] config reg */
430 #define POLO_GPIO_OD2_REG regptr(MSP_PER_BASE + 0x19C)
431 /* Polo GPIO[54:32] output drive */
432
433 /* Generic GPIO registers */
434 #define GPIO_DATA1_REG regptr(MSP_PER_BASE + 0x170)
435 /* GPIO[1:0] data register */
436 #define GPIO_DATA2_REG regptr(MSP_PER_BASE + 0x174)
437 /* GPIO[5:2] data register */
438 #define GPIO_DATA3_REG regptr(MSP_PER_BASE + 0x178)
439 /* GPIO[9:6] data register */
440 #define GPIO_DATA4_REG regptr(MSP_PER_BASE + 0x17C)
441 /* GPIO[15:10] data register */
442 #define GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x180)
443 /* GPIO[1:0] config register */
444 #define GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x184)
445 /* GPIO[5:2] config register */
446 #define GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x188)
447 /* GPIO[9:6] config register */
448 #define GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)
449 /* GPIO[15:10] config register */
450 #define GPIO_OD_REG regptr(MSP_PER_BASE + 0x190)
451 /* GPIO[15:0] output drive */
452
453 /*
454 ***************************************************************************
455 * CPU Interface register definitions *
456 ***************************************************************************
457 */
458 #define PCI_FLUSH_REG regptr(MSP_CPUIF_BASE + 0x00)
459 /* PCI-SDRAM queue flush trigger */
460 #define OCP_ERR1_REG regptr(MSP_CPUIF_BASE + 0x04)
461 /* OCP Error Attribute 1 */
462 #define OCP_ERR2_REG regptr(MSP_CPUIF_BASE + 0x08)
463 /* OCP Error Attribute 2 */
464 #define OCP_STS_REG regptr(MSP_CPUIF_BASE + 0x0C)
465 /* OCP Error Status */
466 #define CPUIF_PM_REG regptr(MSP_CPUIF_BASE + 0x10)
467 /* CPU policy configuration */
468 #define CPUIF_CFG_REG regptr(MSP_CPUIF_BASE + 0x10)
469 /* Misc configuration options */
470
471 /* Central Interrupt Controller Registers */
472 #define MSP_CIC_BASE (MSP_CPUIF_BASE + 0x8000)
473 /* Central Interrupt registers */
474 #define CIC_EXT_CFG_REG regptr(MSP_CIC_BASE + 0x00)
475 /* External interrupt config */
476 #define CIC_STS_REG regptr(MSP_CIC_BASE + 0x04)
477 /* CIC Interrupt Status */
478 #define CIC_VPE0_MSK_REG regptr(MSP_CIC_BASE + 0x08)
479 /* VPE0 Interrupt Mask */
480 #define CIC_VPE1_MSK_REG regptr(MSP_CIC_BASE + 0x0C)
481 /* VPE1 Interrupt Mask */
482 #define CIC_TC0_MSK_REG regptr(MSP_CIC_BASE + 0x10)
483 /* Thread Context 0 Int Mask */
484 #define CIC_TC1_MSK_REG regptr(MSP_CIC_BASE + 0x14)
485 /* Thread Context 1 Int Mask */
486 #define CIC_TC2_MSK_REG regptr(MSP_CIC_BASE + 0x18)
487 /* Thread Context 2 Int Mask */
488 #define CIC_TC3_MSK_REG regptr(MSP_CIC_BASE + 0x18)
489 /* Thread Context 3 Int Mask */
490 #define CIC_TC4_MSK_REG regptr(MSP_CIC_BASE + 0x18)
491 /* Thread Context 4 Int Mask */
492 #define CIC_PCIMSI_STS_REG regptr(MSP_CIC_BASE + 0x18)
493 #define CIC_PCIMSI_MSK_REG regptr(MSP_CIC_BASE + 0x18)
494 #define CIC_PCIFLSH_REG regptr(MSP_CIC_BASE + 0x18)
495 #define CIC_VPE0_SWINT_REG regptr(MSP_CIC_BASE + 0x08)
496
497
498 /*
499 ***************************************************************************
500 * Memory controller registers *
501 ***************************************************************************
502 */
503 #define MEM_CFG1_REG regptr(MSP_MEM_CFG_BASE + 0x00)
504 #define MEM_SS_ADDR regptr(MSP_MEM_CFG_BASE + 0x00)
505 #define MEM_SS_DATA regptr(MSP_MEM_CFG_BASE + 0x04)
506 #define MEM_SS_WRITE regptr(MSP_MEM_CFG_BASE + 0x08)
507
508 /*
509 ***************************************************************************
510 * PCI controller registers *
511 ***************************************************************************
512 */
513 #define PCI_BASE_REG regptr(MSP_PCI_BASE + 0x00)
514 #define PCI_CONFIG_SPACE_REG regptr(MSP_PCI_BASE + 0x800)
515 #define PCI_JTAG_DEVID_REG regptr(MSP_SLP_BASE + 0x13c)
516
517 /*
518 ########################################################################
519 # Register content & macro definitions #
520 ########################################################################
521 */
522
523 /*
524 ***************************************************************************
525 * DEV_ID defines *
526 ***************************************************************************
527 */
528 #define DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */
529 #define DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */
530 #define DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */
531 #define DEV_ID_FAMILY (0xff << 8) /* family ID code */
532 #define POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */
533
534 #define MSPFPGA_ID (0x00 << 8) /* you are on your own here */
535 #define MSP5000_ID (0x50 << 8)
536 #define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */
537 #define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */
538 #define MSP4200_ID (0x42 << 8)
539 #define MSP4000_ID (0x40 << 8)
540 #define MSP2XXX_ID (0x20 << 8)
541 #define MSPZEUS_ID (0x10 << 8)
542
543 #define MSP2004_SUB_ID (0x0 << 16)
544 #define MSP2005_SUB_ID (0x1 << 16)
545 #define MSP2006_SUB_ID (0x1 << 16)
546 #define MSP2007_SUB_ID (0x2 << 16)
547 #define MSP2010_SUB_ID (0x3 << 16)
548 #define MSP2015_SUB_ID (0x4 << 16)
549 #define MSP2020_SUB_ID (0x5 << 16)
550 #define MSP2100_SUB_ID (0x6 << 16)
551
552 /*
553 ***************************************************************************
554 * RESET defines *
555 ***************************************************************************
556 */
557 #define MSP_GR_RST (0x01 << 0) /* Global reset bit */
558 #define MSP_MR_RST (0x01 << 1) /* MIPS reset bit */
559 #define MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */
560 #define MSP_PP_RST (0x01 << 3) /* PVC reset bit */
561 /* reserved */
562 #define MSP_EA_RST (0x01 << 6) /* Mac A reset bit */
563 #define MSP_EB_RST (0x01 << 7) /* Mac B reset bit */
564 #define MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */
565 #define MSP_PB_RST (0x01 << 9) /* Per block reset bit */
566 #define MSP_EC_RST (0x01 << 10) /* Mac C reset bit */
567 #define MSP_TW_RST (0x01 << 11) /* TWI reset bit */
568 #define MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */
569 #define MSP_U1_RST (0x01 << 13) /* UART1 reset bit */
570 #define MSP_U0_RST (0x01 << 14) /* UART0 reset bit */
571
572 /*
573 ***************************************************************************
574 * UART defines *
575 ***************************************************************************
576 */
577 #define MSP_BASE_BAUD 25000000
578 #define MSP_UART_REG_LEN 0x20
579
580 /*
581 ***************************************************************************
582 * ELB defines *
583 ***************************************************************************
584 */
585 #define PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */
586 #define SINGLE_PCCARD 0x01 /* Set to enable single PC card */
587
588 /*
589 ***************************************************************************
590 * CIC defines *
591 ***************************************************************************
592 */
593
594 /* CIC_EXT_CFG_REG */
595 #define EXT_INT_POL(eirq) (1 << (eirq + 8))
596 #define EXT_INT_EDGE(eirq) (1 << eirq)
597
598 #define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq) (reg &= ~EXT_INT_EDGE(eirq))
599 #define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq) (reg |= EXT_INT_EDGE(eirq))
600 #define CIC_EXT_SET_ACTIVE_HI(reg, eirq) (reg |= EXT_INT_POL(eirq))
601 #define CIC_EXT_SET_ACTIVE_LO(reg, eirq) (reg &= ~EXT_INT_POL(eirq))
602 #define CIC_EXT_SET_ACTIVE_RISING CIC_EXT_SET_ACTIVE_HI
603 #define CIC_EXT_SET_ACTIVE_FALLING CIC_EXT_SET_ACTIVE_LO
604
605 #define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \
606 ((reg & EXT_INT_EDGE(eirq)) == 0)
607 #define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq) (reg & EXT_INT_EDGE(eirq))
608 #define CIC_EXT_IS_ACTIVE_HI(reg, eirq) (reg & EXT_INT_POL(eirq))
609 #define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \
610 ((reg & EXT_INT_POL(eirq)) == 0)
611 #define CIC_EXT_IS_ACTIVE_RISING CIC_EXT_IS_ACTIVE_HI
612 #define CIC_EXT_IS_ACTIVE_FALLING CIC_EXT_IS_ACTIVE_LO
613
614 /*
615 ***************************************************************************
616 * Memory Controller defines *
617 ***************************************************************************
618 */
619
620 /* Indirect memory controller registers */
621 #define DDRC_CFG(n) (n)
622 #define DDRC_DEBUG(n) (0x04 + n)
623 #define DDRC_CTL(n) (0x40 + n)
624
625 /* Macro to perform DDRC indirect write */
626 #define DDRC_INDIRECT_WRITE(reg, mask, value) \
627 ({ \
628 *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \
629 *MEM_SS_DATA = (value); \
630 *MEM_SS_WRITE = 1; \
631 })
632
633 /*
634 ***************************************************************************
635 * SPI/MPI Mode *
636 ***************************************************************************
637 */
638 #define SPI_MPI_RX_BUSY 0x00008000 /* SPI/MPI Receive Busy */
639 #define SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */
640 #define SPI_MPI_TX_BUSY 0x00002000 /* SPI/MPI Transmit Busy */
641 #define SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */
642
643 /*
644 ***************************************************************************
645 * SPI/MPI Control Register *
646 ***************************************************************************
647 */
648 #define SPI_MPI_RX_START 0x00000004 /* Start receive command */
649 #define SPI_MPI_FLUSH_Q 0x00000002 /* Flush SPI/MPI Queue */
650 #define SPI_MPI_TX_START 0x00000001 /* Start Transmit Command */
651
652 #endif /* !_ASM_MSP_REGS_H */