arch/mips/include/asm/sibyte/sb1250

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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*  *********************************************************************
   3     *  SB1250 Board Support Package
   4     *
   5     *  DMA definitions                          File: sb1250_dma.h
   6     *
   7     *  This module contains constants and macros useful for
   8     *  programming the SB1250's DMA controllers, both the data mover
   9     *  and the Ethernet DMA.
  10     *
  11     *  SB1250 specification level:  User's manual 10/21/02
  12     *  BCM1280 specification level: User's manual 11/24/03
  13     *
  14     *********************************************************************
  15     *
  16     *  Copyright 2000,2001,2002,2003
  17     *  Broadcom Corporation. All rights reserved.
  18     *
  19     ********************************************************************* */
  20 
  21 
  22 #ifndef _SB1250_DMA_H
  23 #define _SB1250_DMA_H
  24 
  25 
  26 #include <asm/sibyte/sb1250_defs.h>
  27 
  28 /*  *********************************************************************
  29     *  DMA Registers
  30     ********************************************************************* */
  31 
  32 /*
  33  * Ethernet and Serial DMA Configuration Register 0  (Table 7-4)
  34  * Registers: DMA_CONFIG0_MAC_x_RX_CH_0
  35  * Registers: DMA_CONFIG0_MAC_x_TX_CH_0
  36  * Registers: DMA_CONFIG0_SER_x_RX
  37  * Registers: DMA_CONFIG0_SER_x_TX
  38  */
  39 
  40 
  41 #define M_DMA_DROP                  _SB_MAKEMASK1(0)
  42 
  43 #define M_DMA_CHAIN_SEL             _SB_MAKEMASK1(1)
  44 #define M_DMA_RESERVED1             _SB_MAKEMASK1(2)
  45 
  46 #define S_DMA_DESC_TYPE             _SB_MAKE64(1)
  47 #define M_DMA_DESC_TYPE             _SB_MAKEMASK(2, S_DMA_DESC_TYPE)
  48 #define V_DMA_DESC_TYPE(x)          _SB_MAKEVALUE(x, S_DMA_DESC_TYPE)
  49 #define G_DMA_DESC_TYPE(x)          _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE)
  50 
  51 #define K_DMA_DESC_TYPE_RING_AL         0
  52 #define K_DMA_DESC_TYPE_CHAIN_AL        1
  53 
  54 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
  55 #define K_DMA_DESC_TYPE_RING_UAL_WI     2
  56 #define K_DMA_DESC_TYPE_RING_UAL_RMW    3
  57 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
  58 
  59 #define M_DMA_EOP_INT_EN            _SB_MAKEMASK1(3)
  60 #define M_DMA_HWM_INT_EN            _SB_MAKEMASK1(4)
  61 #define M_DMA_LWM_INT_EN            _SB_MAKEMASK1(5)
  62 #define M_DMA_TBX_EN                _SB_MAKEMASK1(6)
  63 #define M_DMA_TDX_EN                _SB_MAKEMASK1(7)
  64 
  65 #define S_DMA_INT_PKTCNT            _SB_MAKE64(8)
  66 #define M_DMA_INT_PKTCNT            _SB_MAKEMASK(8, S_DMA_INT_PKTCNT)
  67 #define V_DMA_INT_PKTCNT(x)         _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT)
  68 #define G_DMA_INT_PKTCNT(x)         _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT)
  69 
  70 #define S_DMA_RINGSZ                _SB_MAKE64(16)
  71 #define M_DMA_RINGSZ                _SB_MAKEMASK(16, S_DMA_RINGSZ)
  72 #define V_DMA_RINGSZ(x)             _SB_MAKEVALUE(x, S_DMA_RINGSZ)
  73 #define G_DMA_RINGSZ(x)             _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ)
  74 
  75 #define S_DMA_HIGH_WATERMARK        _SB_MAKE64(32)
  76 #define M_DMA_HIGH_WATERMARK        _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK)
  77 #define V_DMA_HIGH_WATERMARK(x)     _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK)
  78 #define G_DMA_HIGH_WATERMARK(x)     _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK)
  79 
  80 #define S_DMA_LOW_WATERMARK         _SB_MAKE64(48)
  81 #define M_DMA_LOW_WATERMARK         _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK)
  82 #define V_DMA_LOW_WATERMARK(x)      _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK)
  83 #define G_DMA_LOW_WATERMARK(x)      _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK)
  84 
  85 /*
  86  * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
  87  * Registers: DMA_CONFIG1_MAC_x_RX_CH_0
  88  * Registers: DMA_CONFIG1_DMA_x_TX_CH_0
  89  * Registers: DMA_CONFIG1_SER_x_RX
  90  * Registers: DMA_CONFIG1_SER_x_TX
  91  */
  92 
  93 #define M_DMA_HDR_CF_EN             _SB_MAKEMASK1(0)
  94 #define M_DMA_ASIC_XFR_EN           _SB_MAKEMASK1(1)
  95 #define M_DMA_PRE_ADDR_EN           _SB_MAKEMASK1(2)
  96 #define M_DMA_FLOW_CTL_EN           _SB_MAKEMASK1(3)
  97 #define M_DMA_NO_DSCR_UPDT          _SB_MAKEMASK1(4)
  98 #define M_DMA_L2CA                  _SB_MAKEMASK1(5)
  99 
 100 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 101 #define M_DMA_RX_XTRA_STATUS        _SB_MAKEMASK1(6)
 102 #define M_DMA_TX_CPU_PAUSE          _SB_MAKEMASK1(6)
 103 #define M_DMA_TX_FC_PAUSE_EN        _SB_MAKEMASK1(7)
 104 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 105 
 106 #define M_DMA_MBZ1                  _SB_MAKEMASK(6, 15)
 107 
 108 #define S_DMA_HDR_SIZE              _SB_MAKE64(21)
 109 #define M_DMA_HDR_SIZE              _SB_MAKEMASK(9, S_DMA_HDR_SIZE)
 110 #define V_DMA_HDR_SIZE(x)           _SB_MAKEVALUE(x, S_DMA_HDR_SIZE)
 111 #define G_DMA_HDR_SIZE(x)           _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE)
 112 
 113 #define M_DMA_MBZ2                  _SB_MAKEMASK(5, 32)
 114 
 115 #define S_DMA_ASICXFR_SIZE          _SB_MAKE64(37)
 116 #define M_DMA_ASICXFR_SIZE          _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE)
 117 #define V_DMA_ASICXFR_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE)
 118 #define G_DMA_ASICXFR_SIZE(x)       _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE)
 119 
 120 #define S_DMA_INT_TIMEOUT           _SB_MAKE64(48)
 121 #define M_DMA_INT_TIMEOUT           _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT)
 122 #define V_DMA_INT_TIMEOUT(x)        _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT)
 123 #define G_DMA_INT_TIMEOUT(x)        _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT)
 124 
 125 /*
 126  * Ethernet and Serial DMA Descriptor base address (Table 7-6)
 127  */
 128 
 129 #define M_DMA_DSCRBASE_MBZ          _SB_MAKEMASK(4, 0)
 130 
 131 
 132 /*
 133  * ASIC Mode Base Address (Table 7-7)
 134  */
 135 
 136 #define M_DMA_ASIC_BASE_MBZ         _SB_MAKEMASK(20, 0)
 137 
 138 /*
 139  * DMA Descriptor Count Registers (Table 7-8)
 140  */
 141 
 142 /* No bitfields */
 143 
 144 
 145 /*
 146  * Current Descriptor Address Register (Table 7-11)
 147  */
 148 
 149 #define S_DMA_CURDSCR_ADDR          _SB_MAKE64(0)
 150 #define M_DMA_CURDSCR_ADDR          _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR)
 151 #define S_DMA_CURDSCR_COUNT         _SB_MAKE64(40)
 152 #define M_DMA_CURDSCR_COUNT         _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT)
 153 
 154 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 155 #define M_DMA_TX_CH_PAUSE_ON        _SB_MAKEMASK1(56)
 156 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 157 
 158 /*
 159  * Receive Packet Drop Registers
 160  */
 161 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 162 #define S_DMA_OODLOST_RX           _SB_MAKE64(0)
 163 #define M_DMA_OODLOST_RX           _SB_MAKEMASK(16, S_DMA_OODLOST_RX)
 164 #define G_DMA_OODLOST_RX(x)        _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX)
 165 
 166 #define S_DMA_EOP_COUNT_RX         _SB_MAKE64(16)
 167 #define M_DMA_EOP_COUNT_RX         _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX)
 168 #define G_DMA_EOP_COUNT_RX(x)      _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX)
 169 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 170 
 171 /*  *********************************************************************
 172     *  DMA Descriptors
 173     ********************************************************************* */
 174 
 175 /*
 176  * Descriptor doubleword "A"  (Table 7-12)
 177  */
 178 
 179 #define S_DMA_DSCRA_OFFSET          _SB_MAKE64(0)
 180 #define M_DMA_DSCRA_OFFSET          _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET)
 181 #define V_DMA_DSCRA_OFFSET(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET)
 182 #define G_DMA_DSCRA_OFFSET(x)       _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET)
 183 
 184 /* Note: Don't shift the address over, just mask it with the mask below */
 185 #define S_DMA_DSCRA_A_ADDR          _SB_MAKE64(5)
 186 #define M_DMA_DSCRA_A_ADDR          _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR)
 187 
 188 #define M_DMA_DSCRA_A_ADDR_OFFSET   (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
 189 
 190 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 191 #define S_DMA_DSCRA_A_ADDR_UA        _SB_MAKE64(0)
 192 #define M_DMA_DSCRA_A_ADDR_UA        _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA)
 193 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 194 
 195 #define S_DMA_DSCRA_A_SIZE          _SB_MAKE64(40)
 196 #define M_DMA_DSCRA_A_SIZE          _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE)
 197 #define V_DMA_DSCRA_A_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE)
 198 #define G_DMA_DSCRA_A_SIZE(x)       _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE)
 199 
 200 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 201 #define S_DMA_DSCRA_DSCR_CNT        _SB_MAKE64(40)
 202 #define M_DMA_DSCRA_DSCR_CNT        _SB_MAKEMASK(8, S_DMA_DSCRA_DSCR_CNT)
 203 #define G_DMA_DSCRA_DSCR_CNT(x)     _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT)
 204 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 205 
 206 #define M_DMA_DSCRA_INTERRUPT       _SB_MAKEMASK1(49)
 207 #define M_DMA_DSCRA_OFFSETB         _SB_MAKEMASK1(50)
 208 
 209 #define S_DMA_DSCRA_STATUS          _SB_MAKE64(51)
 210 #define M_DMA_DSCRA_STATUS          _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS)
 211 #define V_DMA_DSCRA_STATUS(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS)
 212 #define G_DMA_DSCRA_STATUS(x)       _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS)
 213 
 214 /*
 215  * Descriptor doubleword "B"  (Table 7-13)
 216  */
 217 
 218 
 219 #define S_DMA_DSCRB_OPTIONS         _SB_MAKE64(0)
 220 #define M_DMA_DSCRB_OPTIONS         _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS)
 221 #define V_DMA_DSCRB_OPTIONS(x)      _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS)
 222 #define G_DMA_DSCRB_OPTIONS(x)      _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS)
 223 
 224 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 225 #define S_DMA_DSCRB_A_SIZE        _SB_MAKE64(8)
 226 #define M_DMA_DSCRB_A_SIZE        _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE)
 227 #define V_DMA_DSCRB_A_SIZE(x)     _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE)
 228 #define G_DMA_DSCRB_A_SIZE(x)     _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE)
 229 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 230 
 231 #define R_DMA_DSCRB_ADDR            _SB_MAKE64(0x10)
 232 
 233 /* Note: Don't shift the address over, just mask it with the mask below */
 234 #define S_DMA_DSCRB_B_ADDR          _SB_MAKE64(5)
 235 #define M_DMA_DSCRB_B_ADDR          _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR)
 236 
 237 #define S_DMA_DSCRB_B_SIZE          _SB_MAKE64(40)
 238 #define M_DMA_DSCRB_B_SIZE          _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE)
 239 #define V_DMA_DSCRB_B_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE)
 240 #define G_DMA_DSCRB_B_SIZE(x)       _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE)
 241 
 242 #define M_DMA_DSCRB_B_VALID         _SB_MAKEMASK1(49)
 243 
 244 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 245 #define S_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKE64(48)
 246 #define M_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKEMASK(2, S_DMA_DSCRB_PKT_SIZE_MSB)
 247 #define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB)
 248 #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB)
 249 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 250 
 251 #define S_DMA_DSCRB_PKT_SIZE        _SB_MAKE64(50)
 252 #define M_DMA_DSCRB_PKT_SIZE        _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE)
 253 #define V_DMA_DSCRB_PKT_SIZE(x)     _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE)
 254 #define G_DMA_DSCRB_PKT_SIZE(x)     _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE)
 255 
 256 /*
 257  * from pass2 some bits in dscr_b are also used for rx status
 258  */
 259 #define S_DMA_DSCRB_STATUS          _SB_MAKE64(0)
 260 #define M_DMA_DSCRB_STATUS          _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS)
 261 #define V_DMA_DSCRB_STATUS(x)       _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS)
 262 #define G_DMA_DSCRB_STATUS(x)       _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS)
 263 
 264 /*
 265  * Ethernet Descriptor Status Bits (Table 7-15)
 266  */
 267 
 268 #define M_DMA_ETHRX_BADIP4CS        _SB_MAKEMASK1(51)
 269 #define M_DMA_ETHRX_DSCRERR         _SB_MAKEMASK1(52)
 270 
 271 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 272 /* Note: This bit is in the DSCR_B options field */
 273 #define M_DMA_ETHRX_BADTCPCS    _SB_MAKEMASK1(0)
 274 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 275 
 276 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 277 /* Note: These bits are in the DSCR_B options field */
 278 #define M_DMA_ETH_VLAN_FLAG     _SB_MAKEMASK1(1)
 279 #define M_DMA_ETH_CRC_FLAG      _SB_MAKEMASK1(2)
 280 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 281 
 282 #define S_DMA_ETHRX_RXCH            53
 283 #define M_DMA_ETHRX_RXCH            _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH)
 284 #define V_DMA_ETHRX_RXCH(x)         _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH)
 285 #define G_DMA_ETHRX_RXCH(x)         _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH)
 286 
 287 #define S_DMA_ETHRX_PKTTYPE         55
 288 #define M_DMA_ETHRX_PKTTYPE         _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE)
 289 #define V_DMA_ETHRX_PKTTYPE(x)      _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE)
 290 #define G_DMA_ETHRX_PKTTYPE(x)      _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE)
 291 
 292 #define K_DMA_ETHRX_PKTTYPE_IPV4    0
 293 #define K_DMA_ETHRX_PKTTYPE_ARPV4   1
 294 #define K_DMA_ETHRX_PKTTYPE_802     2
 295 #define K_DMA_ETHRX_PKTTYPE_OTHER   3
 296 #define K_DMA_ETHRX_PKTTYPE_USER0   4
 297 #define K_DMA_ETHRX_PKTTYPE_USER1   5
 298 #define K_DMA_ETHRX_PKTTYPE_USER2   6
 299 #define K_DMA_ETHRX_PKTTYPE_USER3   7
 300 
 301 #define M_DMA_ETHRX_MATCH_HASH      _SB_MAKEMASK1(58)
 302 #define M_DMA_ETHRX_MATCH_EXACT     _SB_MAKEMASK1(59)
 303 #define M_DMA_ETHRX_BCAST           _SB_MAKEMASK1(60)
 304 #define M_DMA_ETHRX_MCAST           _SB_MAKEMASK1(61)
 305 #define M_DMA_ETHRX_BAD             _SB_MAKEMASK1(62)
 306 #define M_DMA_ETHRX_SOP             _SB_MAKEMASK1(63)
 307 
 308 /*
 309  * Ethernet Transmit Status Bits (Table 7-16)
 310  */
 311 
 312 #define M_DMA_ETHTX_SOP             _SB_MAKEMASK1(63)
 313 
 314 /*
 315  * Ethernet Transmit Options (Table 7-17)
 316  */
 317 
 318 #define K_DMA_ETHTX_NOTSOP          _SB_MAKE64(0x00)
 319 #define K_DMA_ETHTX_APPENDCRC       _SB_MAKE64(0x01)
 320 #define K_DMA_ETHTX_REPLACECRC      _SB_MAKE64(0x02)
 321 #define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
 322 #define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
 323 #define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
 324 #define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
 325 #define K_DMA_ETHTX_NOMODS          _SB_MAKE64(0x07)
 326 #define K_DMA_ETHTX_RESERVED1       _SB_MAKE64(0x08)
 327 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
 328 #define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
 329 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
 330 #define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
 331 #define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
 332 #define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
 333 #define K_DMA_ETHTX_RESERVED2       _SB_MAKE64(0x0F)
 334 
 335 /*
 336  * Serial Receive Options (Table 7-18)
 337  */
 338 #define M_DMA_SERRX_CRC_ERROR       _SB_MAKEMASK1(56)
 339 #define M_DMA_SERRX_ABORT           _SB_MAKEMASK1(57)
 340 #define M_DMA_SERRX_OCTET_ERROR     _SB_MAKEMASK1(58)
 341 #define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
 342 #define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
 343 #define M_DMA_SERRX_OVERRUN_ERROR   _SB_MAKEMASK1(61)
 344 #define M_DMA_SERRX_GOOD            _SB_MAKEMASK1(62)
 345 #define M_DMA_SERRX_SOP             _SB_MAKEMASK1(63)
 346 
 347 /*
 348  * Serial Transmit Status Bits (Table 7-20)
 349  */
 350 
 351 #define M_DMA_SERTX_FLAG            _SB_MAKEMASK1(63)
 352 
 353 /*
 354  * Serial Transmit Options (Table 7-21)
 355  */
 356 
 357 #define K_DMA_SERTX_RESERVED        _SB_MAKEMASK1(0)
 358 #define K_DMA_SERTX_APPENDCRC       _SB_MAKEMASK1(1)
 359 #define K_DMA_SERTX_APPENDPAD       _SB_MAKEMASK1(2)
 360 #define K_DMA_SERTX_ABORT           _SB_MAKEMASK1(3)
 361 
 362 
 363 /*  *********************************************************************
 364     *  Data Mover Registers
 365     ********************************************************************* */
 366 
 367 /*
 368  * Data Mover Descriptor Base Address Register (Table 7-22)
 369  * Register: DM_DSCR_BASE_0
 370  * Register: DM_DSCR_BASE_1
 371  * Register: DM_DSCR_BASE_2
 372  * Register: DM_DSCR_BASE_3
 373  */
 374 
 375 #define M_DM_DSCR_BASE_MBZ          _SB_MAKEMASK(4, 0)
 376 
 377 /*  Note: Just mask the base address and then OR it in. */
 378 #define S_DM_DSCR_BASE_ADDR         _SB_MAKE64(4)
 379 #define M_DM_DSCR_BASE_ADDR         _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR)
 380 
 381 #define S_DM_DSCR_BASE_RINGSZ       _SB_MAKE64(40)
 382 #define M_DM_DSCR_BASE_RINGSZ       _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ)
 383 #define V_DM_DSCR_BASE_RINGSZ(x)    _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ)
 384 #define G_DM_DSCR_BASE_RINGSZ(x)    _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ)
 385 
 386 #define S_DM_DSCR_BASE_PRIORITY     _SB_MAKE64(56)
 387 #define M_DM_DSCR_BASE_PRIORITY     _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY)
 388 #define V_DM_DSCR_BASE_PRIORITY(x)  _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY)
 389 #define G_DM_DSCR_BASE_PRIORITY(x)  _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY)
 390 
 391 #define K_DM_DSCR_BASE_PRIORITY_1   0
 392 #define K_DM_DSCR_BASE_PRIORITY_2   1
 393 #define K_DM_DSCR_BASE_PRIORITY_4   2
 394 #define K_DM_DSCR_BASE_PRIORITY_8   3
 395 #define K_DM_DSCR_BASE_PRIORITY_16  4
 396 
 397 #define M_DM_DSCR_BASE_ACTIVE       _SB_MAKEMASK1(59)
 398 #define M_DM_DSCR_BASE_INTERRUPT    _SB_MAKEMASK1(60)
 399 #define M_DM_DSCR_BASE_RESET        _SB_MAKEMASK1(61)   /* write register */
 400 #define M_DM_DSCR_BASE_ERROR        _SB_MAKEMASK1(61)   /* read register */
 401 #define M_DM_DSCR_BASE_ABORT        _SB_MAKEMASK1(62)
 402 #define M_DM_DSCR_BASE_ENABL        _SB_MAKEMASK1(63)
 403 
 404 /*
 405  * Data Mover Descriptor Count Register (Table 7-25)
 406  */
 407 
 408 /* no bitfields */
 409 
 410 /*
 411  * Data Mover Current Descriptor Address (Table 7-24)
 412  * Register: DM_CUR_DSCR_ADDR_0
 413  * Register: DM_CUR_DSCR_ADDR_1
 414  * Register: DM_CUR_DSCR_ADDR_2
 415  * Register: DM_CUR_DSCR_ADDR_3
 416  */
 417 
 418 #define S_DM_CUR_DSCR_DSCR_ADDR     _SB_MAKE64(0)
 419 #define M_DM_CUR_DSCR_DSCR_ADDR     _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR)
 420 
 421 #define S_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKE64(48)
 422 #define M_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT)
 423 #define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT)
 424 #define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\
 425                                      M_DM_CUR_DSCR_DSCR_COUNT)
 426 
 427 
 428 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 429 /*
 430  * Data Mover Channel Partial Result Registers
 431  * Register: DM_PARTIAL_0
 432  * Register: DM_PARTIAL_1
 433  * Register: DM_PARTIAL_2
 434  * Register: DM_PARTIAL_3
 435  */
 436 #define S_DM_PARTIAL_CRC_PARTIAL      _SB_MAKE64(0)
 437 #define M_DM_PARTIAL_CRC_PARTIAL      _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL)
 438 #define V_DM_PARTIAL_CRC_PARTIAL(r)   _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL)
 439 #define G_DM_PARTIAL_CRC_PARTIAL(r)   _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\
 440                                        M_DM_PARTIAL_CRC_PARTIAL)
 441 
 442 #define S_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKE64(32)
 443 #define M_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL)
 444 #define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL)
 445 #define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\
 446                                        M_DM_PARTIAL_TCPCS_PARTIAL)
 447 
 448 #define M_DM_PARTIAL_ODD_BYTE         _SB_MAKEMASK1(48)
 449 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 450 
 451 
 452 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 453 /*
 454  * Data Mover CRC Definition Registers
 455  * Register: CRC_DEF_0
 456  * Register: CRC_DEF_1
 457  */
 458 #define S_CRC_DEF_CRC_INIT            _SB_MAKE64(0)
 459 #define M_CRC_DEF_CRC_INIT            _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT)
 460 #define V_CRC_DEF_CRC_INIT(r)         _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT)
 461 #define G_CRC_DEF_CRC_INIT(r)         _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\
 462                                        M_CRC_DEF_CRC_INIT)
 463 
 464 #define S_CRC_DEF_CRC_POLY            _SB_MAKE64(32)
 465 #define M_CRC_DEF_CRC_POLY            _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY)
 466 #define V_CRC_DEF_CRC_POLY(r)         _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY)
 467 #define G_CRC_DEF_CRC_POLY(r)         _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\
 468                                        M_CRC_DEF_CRC_POLY)
 469 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 470 
 471 
 472 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 473 /*
 474  * Data Mover CRC/Checksum Definition Registers
 475  * Register: CTCP_DEF_0
 476  * Register: CTCP_DEF_1
 477  */
 478 #define S_CTCP_DEF_CRC_TXOR           _SB_MAKE64(0)
 479 #define M_CTCP_DEF_CRC_TXOR           _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR)
 480 #define V_CTCP_DEF_CRC_TXOR(r)        _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR)
 481 #define G_CTCP_DEF_CRC_TXOR(r)        _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\
 482                                        M_CTCP_DEF_CRC_TXOR)
 483 
 484 #define S_CTCP_DEF_TCPCS_INIT         _SB_MAKE64(32)
 485 #define M_CTCP_DEF_TCPCS_INIT         _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT)
 486 #define V_CTCP_DEF_TCPCS_INIT(r)      _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT)
 487 #define G_CTCP_DEF_TCPCS_INIT(r)      _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\
 488                                        M_CTCP_DEF_TCPCS_INIT)
 489 
 490 #define S_CTCP_DEF_CRC_WIDTH          _SB_MAKE64(48)
 491 #define M_CTCP_DEF_CRC_WIDTH          _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH)
 492 #define V_CTCP_DEF_CRC_WIDTH(r)       _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH)
 493 #define G_CTCP_DEF_CRC_WIDTH(r)       _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\
 494                                        M_CTCP_DEF_CRC_WIDTH)
 495 
 496 #define K_CTCP_DEF_CRC_WIDTH_4        0
 497 #define K_CTCP_DEF_CRC_WIDTH_2        1
 498 #define K_CTCP_DEF_CRC_WIDTH_1        2
 499 
 500 #define M_CTCP_DEF_CRC_BIT_ORDER      _SB_MAKEMASK1(50)
 501 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 502 
 503 
 504 /*
 505  * Data Mover Descriptor Doubleword "A"  (Table 7-26)
 506  */
 507 
 508 #define S_DM_DSCRA_DST_ADDR         _SB_MAKE64(0)
 509 #define M_DM_DSCRA_DST_ADDR         _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR)
 510 
 511 #define M_DM_DSCRA_UN_DEST          _SB_MAKEMASK1(40)
 512 #define M_DM_DSCRA_UN_SRC           _SB_MAKEMASK1(41)
 513 #define M_DM_DSCRA_INTERRUPT        _SB_MAKEMASK1(42)
 514 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
 515 #define M_DM_DSCRA_THROTTLE         _SB_MAKEMASK1(43)
 516 #endif /* up to 1250 PASS1 */
 517 
 518 #define S_DM_DSCRA_DIR_DEST         _SB_MAKE64(44)
 519 #define M_DM_DSCRA_DIR_DEST         _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST)
 520 #define V_DM_DSCRA_DIR_DEST(x)      _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST)
 521 #define G_DM_DSCRA_DIR_DEST(x)      _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST)
 522 
 523 #define K_DM_DSCRA_DIR_DEST_INCR    0
 524 #define K_DM_DSCRA_DIR_DEST_DECR    1
 525 #define K_DM_DSCRA_DIR_DEST_CONST   2
 526 
 527 #define V_DM_DSCRA_DIR_DEST_INCR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR, S_DM_DSCRA_DIR_DEST)
 528 #define V_DM_DSCRA_DIR_DEST_DECR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST)
 529 #define V_DM_DSCRA_DIR_DEST_CONST   _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST)
 530 
 531 #define S_DM_DSCRA_DIR_SRC          _SB_MAKE64(46)
 532 #define M_DM_DSCRA_DIR_SRC          _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC)
 533 #define V_DM_DSCRA_DIR_SRC(x)       _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC)
 534 #define G_DM_DSCRA_DIR_SRC(x)       _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC)
 535 
 536 #define K_DM_DSCRA_DIR_SRC_INCR     0
 537 #define K_DM_DSCRA_DIR_SRC_DECR     1
 538 #define K_DM_DSCRA_DIR_SRC_CONST    2
 539 
 540 #define V_DM_DSCRA_DIR_SRC_INCR     _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC)
 541 #define V_DM_DSCRA_DIR_SRC_DECR     _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC)
 542 #define V_DM_DSCRA_DIR_SRC_CONST    _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC)
 543 
 544 
 545 #define M_DM_DSCRA_ZERO_MEM         _SB_MAKEMASK1(48)
 546 #define M_DM_DSCRA_PREFETCH         _SB_MAKEMASK1(49)
 547 #define M_DM_DSCRA_L2C_DEST         _SB_MAKEMASK1(50)
 548 #define M_DM_DSCRA_L2C_SRC          _SB_MAKEMASK1(51)
 549 
 550 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 551 #define M_DM_DSCRA_RD_BKOFF         _SB_MAKEMASK1(52)
 552 #define M_DM_DSCRA_WR_BKOFF         _SB_MAKEMASK1(53)
 553 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 554 
 555 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 556 #define M_DM_DSCRA_TCPCS_EN         _SB_MAKEMASK1(54)
 557 #define M_DM_DSCRA_TCPCS_RES        _SB_MAKEMASK1(55)
 558 #define M_DM_DSCRA_TCPCS_AP         _SB_MAKEMASK1(56)
 559 #define M_DM_DSCRA_CRC_EN           _SB_MAKEMASK1(57)
 560 #define M_DM_DSCRA_CRC_RES          _SB_MAKEMASK1(58)
 561 #define M_DM_DSCRA_CRC_AP           _SB_MAKEMASK1(59)
 562 #define M_DM_DSCRA_CRC_DFN          _SB_MAKEMASK1(60)
 563 #define M_DM_DSCRA_CRC_XBIT         _SB_MAKEMASK1(61)
 564 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 565 
 566 #define M_DM_DSCRA_RESERVED2        _SB_MAKEMASK(3, 61)
 567 
 568 /*
 569  * Data Mover Descriptor Doubleword "B"  (Table 7-25)
 570  */
 571 
 572 #define S_DM_DSCRB_SRC_ADDR         _SB_MAKE64(0)
 573 #define M_DM_DSCRB_SRC_ADDR         _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR)
 574 
 575 #define S_DM_DSCRB_SRC_LENGTH       _SB_MAKE64(40)
 576 #define M_DM_DSCRB_SRC_LENGTH       _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH)
 577 #define V_DM_DSCRB_SRC_LENGTH(x)    _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH)
 578 #define G_DM_DSCRB_SRC_LENGTH(x)    _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH)
 579 
 580 
 581 #endif
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root/arch/mips/include/asm/sibyte/sb1250_dma.h

INCLUDED FROM
