root/arch/mips/include/asm/sibyte/bcm1480_scd.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*  *********************************************************************
   3     *  BCM1280/BCM1400 Board Support Package
   4     *
   5     *  SCD Constants and Macros                     File: bcm1480_scd.h
   6     *
   7     *  This module contains constants and macros useful for
   8     *  manipulating the System Control and Debug module.
   9     *
  10     *  BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03)
  11     *
  12     *********************************************************************
  13     *
  14     *  Copyright 2000,2001,2002,2003,2004,2005
  15     *  Broadcom Corporation. All rights reserved.
  16     *
  17     ********************************************************************* */
  18 
  19 #ifndef _BCM1480_SCD_H
  20 #define _BCM1480_SCD_H
  21 
  22 #include <asm/sibyte/sb1250_defs.h>
  23 
  24 /*  *********************************************************************
  25     *  Pull in the BCM1250's SCD since lots of stuff is the same.
  26     ********************************************************************* */
  27 
  28 #include <asm/sibyte/sb1250_scd.h>
  29 
  30 /*  *********************************************************************
  31     *  Some general notes:
  32     *
  33     *  This file is basically a "what's new" header file.  Since the
  34     *  BCM1250 and the new BCM1480 (and derivatives) share many common
  35     *  features, this file contains only what's new or changed from
  36     *  the 1250.  (above, you can see that we include the 1250 symbols
  37     *  to get the base functionality).
  38     *
  39     *  In software, be sure to use the correct symbols, particularly
  40     *  for blocks that are different between the two chip families.
  41     *  All BCM1480-specific symbols have _BCM1480_ in their names,
  42     *  and all BCM1250-specific and "base" functions that are common in
  43     *  both chips have no special names (this is for compatibility with
  44     *  older include files).  Therefore, if you're working with the
  45     *  SCD, which is very different on each chip, A_SCD_xxx implies
  46     *  the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
  47     *  version.
  48     ********************************************************************* */
  49 
  50 /*  *********************************************************************
  51     *  System control/debug registers
  52     ********************************************************************* */
  53 
  54 /*
  55  * System Identification and Revision Register (Table 12)
  56  * Register: SCD_SYSTEM_REVISION
  57  * This register is field compatible with the 1250.
  58  */
  59 
  60 /*
  61  * New part definitions
  62  */
  63 
  64 #define K_SYS_PART_BCM1480          0x1406
  65 #define K_SYS_PART_BCM1280          0x1206
  66 #define K_SYS_PART_BCM1455          0x1407
  67 #define K_SYS_PART_BCM1255          0x1257
  68 #define K_SYS_PART_BCM1158          0x1156
  69 
  70 /*
  71  * Manufacturing Information Register (Table 14)
  72  * Register: SCD_SYSTEM_MANUF
  73  */
  74 
  75 /*
  76  * System Configuration Register (Table 15)
  77  * Register: SCD_SYSTEM_CFG
  78  * Entire register is different from 1250, all new constants below
  79  */
  80 
  81 #define M_BCM1480_SYS_RESERVED0             _SB_MAKEMASK1(0)
  82 #define M_BCM1480_SYS_HT_MINRSTCNT          _SB_MAKEMASK1(1)
  83 #define M_BCM1480_SYS_RESERVED2             _SB_MAKEMASK1(2)
  84 #define M_BCM1480_SYS_RESERVED3             _SB_MAKEMASK1(3)
  85 #define M_BCM1480_SYS_RESERVED4             _SB_MAKEMASK1(4)
  86 #define M_BCM1480_SYS_IOB_DIV               _SB_MAKEMASK1(5)
  87 
  88 #define S_BCM1480_SYS_PLL_DIV               _SB_MAKE64(6)
  89 #define M_BCM1480_SYS_PLL_DIV               _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV)
  90 #define V_BCM1480_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV)
  91 #define G_BCM1480_SYS_PLL_DIV(x)            _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV)
  92 
  93 #define S_BCM1480_SYS_SW_DIV                _SB_MAKE64(11)
  94 #define M_BCM1480_SYS_SW_DIV                _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV)
  95 #define V_BCM1480_SYS_SW_DIV(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV)
  96 #define G_BCM1480_SYS_SW_DIV(x)             _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV)
  97 
  98 #define M_BCM1480_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)
  99 #define M_BCM1480_SYS_DUART1_ENABLE         _SB_MAKEMASK1(17)
 100 
 101 #define S_BCM1480_SYS_BOOT_MODE             _SB_MAKE64(18)
 102 #define M_BCM1480_SYS_BOOT_MODE             _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE)
 103 #define V_BCM1480_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE)
 104 #define G_BCM1480_SYS_BOOT_MODE(x)          _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE)
 105 #define K_BCM1480_SYS_BOOT_MODE_ROM32       0
 106 #define K_BCM1480_SYS_BOOT_MODE_ROM8        1
 107 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2
 108 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG   3
 109 #define M_BCM1480_SYS_BOOT_MODE_SMBUS       _SB_MAKEMASK1(19)
 110 
 111 #define M_BCM1480_SYS_PCI_HOST              _SB_MAKEMASK1(20)
 112 #define M_BCM1480_SYS_PCI_ARBITER           _SB_MAKEMASK1(21)
 113 #define M_BCM1480_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
 114 #define M_BCM1480_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
 115 #define M_BCM1480_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(24)
 116 #define M_BCM1480_SYS_RESERVED25            _SB_MAKEMASK1(25)
 117 
 118 #define S_BCM1480_SYS_CONFIG                26
 119 #define M_BCM1480_SYS_CONFIG                _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG)
 120 #define V_BCM1480_SYS_CONFIG(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG)
 121 #define G_BCM1480_SYS_CONFIG(x)             _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG)
 122 
 123 #define M_BCM1480_SYS_RESERVED32            _SB_MAKEMASK(32, 15)
 124 
 125 #define S_BCM1480_SYS_NODEID                47
 126 #define M_BCM1480_SYS_NODEID                _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID)
 127 #define V_BCM1480_SYS_NODEID(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID)
 128 #define G_BCM1480_SYS_NODEID(x)             _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID)
 129 
 130 #define M_BCM1480_SYS_CCNUMA_EN             _SB_MAKEMASK1(51)
 131 #define M_BCM1480_SYS_CPU_RESET_0           _SB_MAKEMASK1(52)
 132 #define M_BCM1480_SYS_CPU_RESET_1           _SB_MAKEMASK1(53)
 133 #define M_BCM1480_SYS_CPU_RESET_2           _SB_MAKEMASK1(54)
 134 #define M_BCM1480_SYS_CPU_RESET_3           _SB_MAKEMASK1(55)
 135 #define S_BCM1480_SYS_DISABLECPU0           56
 136 #define M_BCM1480_SYS_DISABLECPU0           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0)
 137 #define S_BCM1480_SYS_DISABLECPU1           57
 138 #define M_BCM1480_SYS_DISABLECPU1           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1)
 139 #define S_BCM1480_SYS_DISABLECPU2           58
 140 #define M_BCM1480_SYS_DISABLECPU2           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2)
 141 #define S_BCM1480_SYS_DISABLECPU3           59
 142 #define M_BCM1480_SYS_DISABLECPU3           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3)
 143 
 144 #define M_BCM1480_SYS_SB_SOFTRES            _SB_MAKEMASK1(60)
 145 #define M_BCM1480_SYS_EXT_RESET             _SB_MAKEMASK1(61)
 146 #define M_BCM1480_SYS_SYSTEM_RESET          _SB_MAKEMASK1(62)
 147 #define M_BCM1480_SYS_SW_FLAG               _SB_MAKEMASK1(63)
 148 
 149 /*
 150  * Scratch Register (Table 16)
 151  * Register: SCD_SYSTEM_SCRATCH
 152  * Same as BCM1250
 153  */
 154 
 155 
 156 /*
 157  * Mailbox Registers (Table 17)
 158  * Registers: SCD_MBOX_{0,1}_CPU_x
 159  * Same as BCM1250
 160  */
 161 
 162 
 163 /*
 164  * See bcm1480_int.h for interrupt mapper registers.
 165  */
 166 
 167 
 168 /*
 169  * Watchdog Timer Initial Count Registers (Table 23)
 170  * Registers: SCD_WDOG_INIT_CNT_x
 171  *
 172  * The watchdogs are almost the same as the 1250, except
 173  * the configuration register has more bits to control the
 174  * other CPUs.
 175  */
 176 
 177 
 178 /*
 179  * Watchdog Timer Configuration Registers (Table 25)
 180  * Registers: SCD_WDOG_CFG_x
 181  */
 182 
 183 #define M_BCM1480_SCD_WDOG_ENABLE           _SB_MAKEMASK1(0)
 184 
 185 #define S_BCM1480_SCD_WDOG_RESET_TYPE       2
 186 #define M_BCM1480_SCD_WDOG_RESET_TYPE       _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE)
 187 #define V_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE)
 188 #define G_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE)
 189 
 190 #define K_BCM1480_SCD_WDOG_RESET_FULL       0   /* actually, (x & 1) == 0  */
 191 #define K_BCM1480_SCD_WDOG_RESET_SOFT       1
 192 #define K_BCM1480_SCD_WDOG_RESET_CPU0       3
 193 #define K_BCM1480_SCD_WDOG_RESET_CPU1       5
 194 #define K_BCM1480_SCD_WDOG_RESET_CPU2       9
 195 #define K_BCM1480_SCD_WDOG_RESET_CPU3       17
 196 #define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS   31
 197 
 198 
 199 #define M_BCM1480_SCD_WDOG_HAS_RESET        _SB_MAKEMASK1(8)
 200 
 201 /*
 202  * General Timer Initial Count Registers (Table 26)
 203  * Registers: SCD_TIMER_INIT_x
 204  *
 205  * The timer registers are the same as the BCM1250
 206  */
 207 
 208 
 209 /*
 210  * ZBbus Count Register (Table 29)
 211  * Register: ZBBUS_CYCLE_COUNT
 212  *
 213  * Same as BCM1250
 214  */
 215 
 216 /*
 217  * ZBbus Compare Registers (Table 30)
 218  * Registers: ZBBUS_CYCLE_CPx
 219  *
 220  * Same as BCM1250
 221  */
 222 
 223 
 224 /*
 225  * System Performance Counter Configuration Register (Table 31)
 226  * Register: PERF_CNT_CFG_0
 227  *
 228  * SPC_CFG_SRC[0-3] is the same as the 1250.
 229  * SPC_CFG_SRC[4-7] only exist on the 1480
 230  * The clear/enable bits are in different locations on the 1250 and 1480.
 231  */
 232 
 233 #define S_SPC_CFG_SRC4              32
 234 #define M_SPC_CFG_SRC4              _SB_MAKEMASK(8, S_SPC_CFG_SRC4)
 235 #define V_SPC_CFG_SRC4(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC4)
 236 #define G_SPC_CFG_SRC4(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4)
 237 
 238 #define S_SPC_CFG_SRC5              40
 239 #define M_SPC_CFG_SRC5              _SB_MAKEMASK(8, S_SPC_CFG_SRC5)
 240 #define V_SPC_CFG_SRC5(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC5)
 241 #define G_SPC_CFG_SRC5(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5)
 242 
 243 #define S_SPC_CFG_SRC6              48
 244 #define M_SPC_CFG_SRC6              _SB_MAKEMASK(8, S_SPC_CFG_SRC6)
 245 #define V_SPC_CFG_SRC6(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC6)
 246 #define G_SPC_CFG_SRC6(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6)
 247 
 248 #define S_SPC_CFG_SRC7              56
 249 #define M_SPC_CFG_SRC7              _SB_MAKEMASK(8, S_SPC_CFG_SRC7)
 250 #define V_SPC_CFG_SRC7(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC7)
 251 #define G_SPC_CFG_SRC7(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7)
 252 
 253 /*
 254  * System Performance Counter Control Register (Table 32)
 255  * Register: PERF_CNT_CFG_1
 256  * BCM1480 specific
 257  */
 258 #define M_BCM1480_SPC_CFG_CLEAR     _SB_MAKEMASK1(0)
 259 #define M_BCM1480_SPC_CFG_ENABLE    _SB_MAKEMASK1(1)
 260 #if SIBYTE_HDR_FEATURE_CHIP(1480)
 261 #define M_SPC_CFG_CLEAR                 M_BCM1480_SPC_CFG_CLEAR
 262 #define M_SPC_CFG_ENABLE                M_BCM1480_SPC_CFG_ENABLE
 263 #endif
 264 
 265 /*
 266  * System Performance Counters (Table 33)
 267  * Registers: PERF_CNT_x
 268  */
 269 
 270 #define S_BCM1480_SPC_CNT_COUNT             0
 271 #define M_BCM1480_SPC_CNT_COUNT             _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT)
 272 #define V_BCM1480_SPC_CNT_COUNT(x)          _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT)
 273 #define G_BCM1480_SPC_CNT_COUNT(x)          _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT)
 274 
 275 #define M_BCM1480_SPC_CNT_OFLOW             _SB_MAKEMASK1(40)
 276 
 277 
 278 /*
 279  * Bus Watcher Error Status Register (Tables 36, 37)
 280  * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG
 281  * Same as BCM1250.
 282  */
 283 
 284 /*
 285  * Bus Watcher Error Data Registers (Table 38)
 286  * Registers: BUS_ERR_DATA_x
 287  * Same as BCM1250.
 288  */
 289 
 290 /*
 291  * Bus Watcher L2 ECC Counter Register (Table 39)
 292  * Register: BUS_L2_ERRORS
 293  * Same as BCM1250.
 294  */
 295 
 296 
 297 /*
 298  * Bus Watcher Memory and I/O Error Counter Register (Table 40)
 299  * Register: BUS_MEM_IO_ERRORS
 300  * Same as BCM1250.
 301  */
 302 
 303 
 304 /*
 305  * Address Trap Registers
 306  *
 307  * Register layout same as BCM1250, almost.  The bus agents
 308  * are different, and the address trap configuration bits are
 309  * slightly different.
 310  */
 311 
 312 #define M_BCM1480_ATRAP_INDEX             _SB_MAKEMASK(4, 0)
 313 #define M_BCM1480_ATRAP_ADDRESS           _SB_MAKEMASK(40, 0)
 314 
 315 #define S_BCM1480_ATRAP_CFG_CNT            0
 316 #define M_BCM1480_ATRAP_CFG_CNT            _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT)
 317 #define V_BCM1480_ATRAP_CFG_CNT(x)         _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT)
 318 #define G_BCM1480_ATRAP_CFG_CNT(x)         _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT)
 319 
 320 #define M_BCM1480_ATRAP_CFG_WRITE          _SB_MAKEMASK1(3)
 321 #define M_BCM1480_ATRAP_CFG_ALL            _SB_MAKEMASK1(4)
 322 #define M_BCM1480_ATRAP_CFG_INV            _SB_MAKEMASK1(5)
 323 #define M_BCM1480_ATRAP_CFG_USESRC         _SB_MAKEMASK1(6)
 324 #define M_BCM1480_ATRAP_CFG_SRCINV         _SB_MAKEMASK1(7)
 325 
 326 #define S_BCM1480_ATRAP_CFG_AGENTID     8
 327 #define M_BCM1480_ATRAP_CFG_AGENTID     _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID)
 328 #define V_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID)
 329 #define G_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID)
 330 
 331 
 332 #define K_BCM1480_BUS_AGENT_CPU0            0
 333 #define K_BCM1480_BUS_AGENT_CPU1            1
 334 #define K_BCM1480_BUS_AGENT_NC              2
 335 #define K_BCM1480_BUS_AGENT_IOB             3
 336 #define K_BCM1480_BUS_AGENT_SCD             4
 337 #define K_BCM1480_BUS_AGENT_L2C             6
 338 #define K_BCM1480_BUS_AGENT_MC              7
 339 #define K_BCM1480_BUS_AGENT_CPU2            8
 340 #define K_BCM1480_BUS_AGENT_CPU3            9
 341 #define K_BCM1480_BUS_AGENT_PM              10
 342 
 343 #define S_BCM1480_ATRAP_CFG_CATTR           12
 344 #define M_BCM1480_ATRAP_CFG_CATTR           _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR)
 345 #define V_BCM1480_ATRAP_CFG_CATTR(x)        _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR)
 346 #define G_BCM1480_ATRAP_CFG_CATTR(x)        _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR)
 347 
 348 #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE    0
 349 #define K_BCM1480_ATRAP_CFG_CATTR_UNC       1
 350 #define K_BCM1480_ATRAP_CFG_CATTR_NONCOH    2
 351 #define K_BCM1480_ATRAP_CFG_CATTR_COHERENT  3
 352 
 353 #define M_BCM1480_ATRAP_CFG_CATTRINV        _SB_MAKEMASK1(14)
 354 
 355 
 356 /*
 357  * Trace Event Registers (Table 47)
 358  * Same as BCM1250.
 359  */
 360 
 361 /*
 362  * Trace Sequence Control Registers (Table 48)
 363  * Registers: TRACE_SEQUENCE_x
 364  *
 365  * Same as BCM1250 except for two new fields.
 366  */
 367 
 368 
 369 #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN    _SB_MAKEMASK1(25)
 370 
 371 #define S_BCM1480_SCD_TRSEQ_SWFUNC          26
 372 #define M_BCM1480_SCD_TRSEQ_SWFUNC          _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC)
 373 #define V_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC)
 374 #define G_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC)
 375 
 376 /*
 377  * Trace Control Register (Table 49)
 378  * Register: TRACE_CFG
 379  *
 380  * BCM1480 changes to this register (other than location of the CUR_ADDR field)
 381  * are defined below.
 382  */
 383 
 384 #define S_BCM1480_SCD_TRACE_CFG_MODE        16
 385 #define M_BCM1480_SCD_TRACE_CFG_MODE        _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE)
 386 #define V_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE)
 387 #define G_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE)
 388 
 389 #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS   0
 390 #define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
 391 #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID    2
 392 
 393 #endif /* _BCM1480_SCD_H */