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28 #ifndef __CVMX_PKO_DEFS_H__
29 #define __CVMX_PKO_DEFS_H__
30
31 #define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull))
32 #define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull))
33 #define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull))
34 #define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull))
35 #define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull))
36 #define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull))
37 #define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull))
38 #define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull))
39 #define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull))
40 #define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull))
41 #define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull))
42 #define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull))
43 #define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull))
44 #define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull))
45 #define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull))
46 #define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull))
47 #define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull))
48 #define CVMX_PKO_MEM_IPORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001030ull))
49 #define CVMX_PKO_MEM_IPORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001038ull))
50 #define CVMX_PKO_MEM_IQUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001040ull))
51 #define CVMX_PKO_MEM_IQUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001048ull))
52 #define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull))
53 #define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull))
54 #define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull))
55 #define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull))
56 #define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull))
57 #define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull))
58 #define CVMX_PKO_MEM_THROTTLE_INT (CVMX_ADD_IO_SEG(0x0001180050001058ull))
59 #define CVMX_PKO_MEM_THROTTLE_PIPE (CVMX_ADD_IO_SEG(0x0001180050001050ull))
60 #define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull))
61 #define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull))
62 #define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8)
63 #define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull))
64 #define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8)
65 #define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull))
66 #define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull))
67 #define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull))
68 #define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull))
69 #define CVMX_PKO_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x00011800500000B8ull))
70 #define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull))
71 #define CVMX_PKO_REG_ENGINE_INFLIGHT1 (CVMX_ADD_IO_SEG(0x0001180050000318ull))
72 #define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8)
73 #define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull))
74 #define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull))
75 #define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull))
76 #define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull))
77 #define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull))
78 #define CVMX_PKO_REG_LOOPBACK_BPID (CVMX_ADD_IO_SEG(0x0001180050000118ull))
79 #define CVMX_PKO_REG_LOOPBACK_PKIND (CVMX_ADD_IO_SEG(0x0001180050000068ull))
80 #define CVMX_PKO_REG_MIN_PKT (CVMX_ADD_IO_SEG(0x0001180050000070ull))
81 #define CVMX_PKO_REG_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000110ull))
82 #define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull))
83 #define CVMX_PKO_REG_QUEUE_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000108ull))
84 #define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull))
85 #define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull))
86 #define CVMX_PKO_REG_THROTTLE (CVMX_ADD_IO_SEG(0x0001180050000078ull))
87 #define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull))
88
89 union cvmx_pko_mem_count0 {
90 uint64_t u64;
91 struct cvmx_pko_mem_count0_s {
92 #ifdef __BIG_ENDIAN_BITFIELD
93 uint64_t reserved_32_63:32;
94 uint64_t count:32;
95 #else
96 uint64_t count:32;
97 uint64_t reserved_32_63:32;
98 #endif
99 } s;
100 };
101
102 union cvmx_pko_mem_count1 {
103 uint64_t u64;
104 struct cvmx_pko_mem_count1_s {
105 #ifdef __BIG_ENDIAN_BITFIELD
106 uint64_t reserved_48_63:16;
107 uint64_t count:48;
108 #else
109 uint64_t count:48;
110 uint64_t reserved_48_63:16;
111 #endif
112 } s;
113 };
114
115 union cvmx_pko_mem_debug0 {
116 uint64_t u64;
117 struct cvmx_pko_mem_debug0_s {
118 #ifdef __BIG_ENDIAN_BITFIELD
119 uint64_t fau:28;
120 uint64_t cmd:14;
121 uint64_t segs:6;
122 uint64_t size:16;
123 #else
124 uint64_t size:16;
125 uint64_t segs:6;
126 uint64_t cmd:14;
127 uint64_t fau:28;
128 #endif
129 } s;
130 };
131
132 union cvmx_pko_mem_debug1 {
133 uint64_t u64;
134 struct cvmx_pko_mem_debug1_s {
135 #ifdef __BIG_ENDIAN_BITFIELD
136 uint64_t i:1;
137 uint64_t back:4;
138 uint64_t pool:3;
139 uint64_t size:16;
140 uint64_t ptr:40;
141 #else
142 uint64_t ptr:40;
143 uint64_t size:16;
144 uint64_t pool:3;
145 uint64_t back:4;
146 uint64_t i:1;
147 #endif
148 } s;
149 };
150
151 union cvmx_pko_mem_debug10 {
152 uint64_t u64;
153 struct cvmx_pko_mem_debug10_s {
154 #ifdef __BIG_ENDIAN_BITFIELD
155 uint64_t reserved_0_63:64;
156 #else
157 uint64_t reserved_0_63:64;
158 #endif
159 } s;
160 struct cvmx_pko_mem_debug10_cn30xx {
161 #ifdef __BIG_ENDIAN_BITFIELD
162 uint64_t fau:28;
163 uint64_t cmd:14;
164 uint64_t segs:6;
165 uint64_t size:16;
166 #else
167 uint64_t size:16;
168 uint64_t segs:6;
169 uint64_t cmd:14;
170 uint64_t fau:28;
171 #endif
172 } cn30xx;
173 struct cvmx_pko_mem_debug10_cn50xx {
174 #ifdef __BIG_ENDIAN_BITFIELD
175 uint64_t reserved_49_63:15;
176 uint64_t ptrs1:17;
177 uint64_t reserved_17_31:15;
178 uint64_t ptrs2:17;
179 #else
180 uint64_t ptrs2:17;
181 uint64_t reserved_17_31:15;
182 uint64_t ptrs1:17;
183 uint64_t reserved_49_63:15;
184 #endif
185 } cn50xx;
186 };
187
188 union cvmx_pko_mem_debug11 {
189 uint64_t u64;
190 struct cvmx_pko_mem_debug11_s {
191 #ifdef __BIG_ENDIAN_BITFIELD
192 uint64_t i:1;
193 uint64_t back:4;
194 uint64_t pool:3;
195 uint64_t size:16;
196 uint64_t reserved_0_39:40;
197 #else
198 uint64_t reserved_0_39:40;
199 uint64_t size:16;
200 uint64_t pool:3;
201 uint64_t back:4;
202 uint64_t i:1;
203 #endif
204 } s;
205 struct cvmx_pko_mem_debug11_cn30xx {
206 #ifdef __BIG_ENDIAN_BITFIELD
207 uint64_t i:1;
208 uint64_t back:4;
209 uint64_t pool:3;
210 uint64_t size:16;
211 uint64_t ptr:40;
212 #else
213 uint64_t ptr:40;
214 uint64_t size:16;
215 uint64_t pool:3;
216 uint64_t back:4;
217 uint64_t i:1;
218 #endif
219 } cn30xx;
220 struct cvmx_pko_mem_debug11_cn50xx {
221 #ifdef __BIG_ENDIAN_BITFIELD
222 uint64_t reserved_23_63:41;
223 uint64_t maj:1;
224 uint64_t uid:3;
225 uint64_t sop:1;
226 uint64_t len:1;
227 uint64_t chk:1;
228 uint64_t cnt:13;
229 uint64_t mod:3;
230 #else
231 uint64_t mod:3;
232 uint64_t cnt:13;
233 uint64_t chk:1;
234 uint64_t len:1;
235 uint64_t sop:1;
236 uint64_t uid:3;
237 uint64_t maj:1;
238 uint64_t reserved_23_63:41;
239 #endif
240 } cn50xx;
241 };
242
243 union cvmx_pko_mem_debug12 {
244 uint64_t u64;
245 struct cvmx_pko_mem_debug12_s {
246 #ifdef __BIG_ENDIAN_BITFIELD
247 uint64_t reserved_0_63:64;
248 #else
249 uint64_t reserved_0_63:64;
250 #endif
251 } s;
252 struct cvmx_pko_mem_debug12_cn30xx {
253 #ifdef __BIG_ENDIAN_BITFIELD
254 uint64_t data:64;
255 #else
256 uint64_t data:64;
257 #endif
258 } cn30xx;
259 struct cvmx_pko_mem_debug12_cn50xx {
260 #ifdef __BIG_ENDIAN_BITFIELD
261 uint64_t fau:28;
262 uint64_t cmd:14;
263 uint64_t segs:6;
264 uint64_t size:16;
265 #else
266 uint64_t size:16;
267 uint64_t segs:6;
268 uint64_t cmd:14;
269 uint64_t fau:28;
270 #endif
271 } cn50xx;
272 struct cvmx_pko_mem_debug12_cn68xx {
273 #ifdef __BIG_ENDIAN_BITFIELD
274 uint64_t state:64;
275 #else
276 uint64_t state:64;
277 #endif
278 } cn68xx;
279 };
280
281 union cvmx_pko_mem_debug13 {
282 uint64_t u64;
283 struct cvmx_pko_mem_debug13_s {
284 #ifdef __BIG_ENDIAN_BITFIELD
285 uint64_t reserved_0_63:64;
286 #else
287 uint64_t reserved_0_63:64;
288 #endif
289 } s;
290 struct cvmx_pko_mem_debug13_cn30xx {
291 #ifdef __BIG_ENDIAN_BITFIELD
292 uint64_t reserved_51_63:13;
293 uint64_t widx:17;
294 uint64_t ridx2:17;
295 uint64_t widx2:17;
296 #else
297 uint64_t widx2:17;
298 uint64_t ridx2:17;
299 uint64_t widx:17;
300 uint64_t reserved_51_63:13;
301 #endif
302 } cn30xx;
303 struct cvmx_pko_mem_debug13_cn50xx {
304 #ifdef __BIG_ENDIAN_BITFIELD
305 uint64_t i:1;
306 uint64_t back:4;
307 uint64_t pool:3;
308 uint64_t size:16;
309 uint64_t ptr:40;
310 #else
311 uint64_t ptr:40;
312 uint64_t size:16;
313 uint64_t pool:3;
314 uint64_t back:4;
315 uint64_t i:1;
316 #endif
317 } cn50xx;
318 struct cvmx_pko_mem_debug13_cn68xx {
319 #ifdef __BIG_ENDIAN_BITFIELD
320 uint64_t state:64;
321 #else
322 uint64_t state:64;
323 #endif
324 } cn68xx;
325 };
326
327 union cvmx_pko_mem_debug14 {
328 uint64_t u64;
329 struct cvmx_pko_mem_debug14_s {
330 #ifdef __BIG_ENDIAN_BITFIELD
331 uint64_t reserved_0_63:64;
332 #else
333 uint64_t reserved_0_63:64;
334 #endif
335 } s;
336 struct cvmx_pko_mem_debug14_cn30xx {
337 #ifdef __BIG_ENDIAN_BITFIELD
338 uint64_t reserved_17_63:47;
339 uint64_t ridx:17;
340 #else
341 uint64_t ridx:17;
342 uint64_t reserved_17_63:47;
343 #endif
344 } cn30xx;
345 struct cvmx_pko_mem_debug14_cn52xx {
346 #ifdef __BIG_ENDIAN_BITFIELD
347 uint64_t data:64;
348 #else
349 uint64_t data:64;
350 #endif
351 } cn52xx;
352 };
353
354 union cvmx_pko_mem_debug2 {
355 uint64_t u64;
356 struct cvmx_pko_mem_debug2_s {
357 #ifdef __BIG_ENDIAN_BITFIELD
358 uint64_t i:1;
359 uint64_t back:4;
360 uint64_t pool:3;
361 uint64_t size:16;
362 uint64_t ptr:40;
363 #else
364 uint64_t ptr:40;
365 uint64_t size:16;
366 uint64_t pool:3;
367 uint64_t back:4;
368 uint64_t i:1;
369 #endif
370 } s;
371 };
372
373 union cvmx_pko_mem_debug3 {
374 uint64_t u64;
375 struct cvmx_pko_mem_debug3_s {
376 #ifdef __BIG_ENDIAN_BITFIELD
377 uint64_t reserved_0_63:64;
378 #else
379 uint64_t reserved_0_63:64;
380 #endif
381 } s;
382 struct cvmx_pko_mem_debug3_cn30xx {
383 #ifdef __BIG_ENDIAN_BITFIELD
384 uint64_t i:1;
385 uint64_t back:4;
386 uint64_t pool:3;
387 uint64_t size:16;
388 uint64_t ptr:40;
389 #else
390 uint64_t ptr:40;
391 uint64_t size:16;
392 uint64_t pool:3;
393 uint64_t back:4;
394 uint64_t i:1;
395 #endif
396 } cn30xx;
397 struct cvmx_pko_mem_debug3_cn50xx {
398 #ifdef __BIG_ENDIAN_BITFIELD
399 uint64_t data:64;
400 #else
401 uint64_t data:64;
402 #endif
403 } cn50xx;
404 };
405
406 union cvmx_pko_mem_debug4 {
407 uint64_t u64;
408 struct cvmx_pko_mem_debug4_s {
409 #ifdef __BIG_ENDIAN_BITFIELD
410 uint64_t reserved_0_63:64;
411 #else
412 uint64_t reserved_0_63:64;
413 #endif
414 } s;
415 struct cvmx_pko_mem_debug4_cn30xx {
416 #ifdef __BIG_ENDIAN_BITFIELD
417 uint64_t data:64;
418 #else
419 uint64_t data:64;
420 #endif
421 } cn30xx;
422 struct cvmx_pko_mem_debug4_cn50xx {
423 #ifdef __BIG_ENDIAN_BITFIELD
424 uint64_t cmnd_segs:3;
425 uint64_t cmnd_siz:16;
426 uint64_t cmnd_off:6;
427 uint64_t uid:3;
428 uint64_t dread_sop:1;
429 uint64_t init_dwrite:1;
430 uint64_t chk_once:1;
431 uint64_t chk_mode:1;
432 uint64_t active:1;
433 uint64_t static_p:1;
434 uint64_t qos:3;
435 uint64_t qcb_ridx:5;
436 uint64_t qid_off_max:4;
437 uint64_t qid_off:4;
438 uint64_t qid_base:8;
439 uint64_t wait:1;
440 uint64_t minor:2;
441 uint64_t major:3;
442 #else
443 uint64_t major:3;
444 uint64_t minor:2;
445 uint64_t wait:1;
446 uint64_t qid_base:8;
447 uint64_t qid_off:4;
448 uint64_t qid_off_max:4;
449 uint64_t qcb_ridx:5;
450 uint64_t qos:3;
451 uint64_t static_p:1;
452 uint64_t active:1;
453 uint64_t chk_mode:1;
454 uint64_t chk_once:1;
455 uint64_t init_dwrite:1;
456 uint64_t dread_sop:1;
457 uint64_t uid:3;
458 uint64_t cmnd_off:6;
459 uint64_t cmnd_siz:16;
460 uint64_t cmnd_segs:3;
461 #endif
462 } cn50xx;
463 struct cvmx_pko_mem_debug4_cn52xx {
464 #ifdef __BIG_ENDIAN_BITFIELD
465 uint64_t curr_siz:8;
466 uint64_t curr_off:16;
467 uint64_t cmnd_segs:6;
468 uint64_t cmnd_siz:16;
469 uint64_t cmnd_off:6;
470 uint64_t uid:2;
471 uint64_t dread_sop:1;
472 uint64_t init_dwrite:1;
473 uint64_t chk_once:1;
474 uint64_t chk_mode:1;
475 uint64_t wait:1;
476 uint64_t minor:2;
477 uint64_t major:3;
478 #else
479 uint64_t major:3;
480 uint64_t minor:2;
481 uint64_t wait:1;
482 uint64_t chk_mode:1;
483 uint64_t chk_once:1;
484 uint64_t init_dwrite:1;
485 uint64_t dread_sop:1;
486 uint64_t uid:2;
487 uint64_t cmnd_off:6;
488 uint64_t cmnd_siz:16;
489 uint64_t cmnd_segs:6;
490 uint64_t curr_off:16;
491 uint64_t curr_siz:8;
492 #endif
493 } cn52xx;
494 };
495
496 union cvmx_pko_mem_debug5 {
497 uint64_t u64;
498 struct cvmx_pko_mem_debug5_s {
499 #ifdef __BIG_ENDIAN_BITFIELD
500 uint64_t reserved_0_63:64;
501 #else
502 uint64_t reserved_0_63:64;
503 #endif
504 } s;
505 struct cvmx_pko_mem_debug5_cn30xx {
506 #ifdef __BIG_ENDIAN_BITFIELD
507 uint64_t dwri_mod:1;
508 uint64_t dwri_sop:1;
509 uint64_t dwri_len:1;
510 uint64_t dwri_cnt:13;
511 uint64_t cmnd_siz:16;
512 uint64_t uid:1;
513 uint64_t xfer_wor:1;
514 uint64_t xfer_dwr:1;
515 uint64_t cbuf_fre:1;
516 uint64_t reserved_27_27:1;
517 uint64_t chk_mode:1;
518 uint64_t active:1;
519 uint64_t qos:3;
520 uint64_t qcb_ridx:5;
521 uint64_t qid_off:3;
522 uint64_t qid_base:7;
523 uint64_t wait:1;
524 uint64_t minor:2;
525 uint64_t major:4;
526 #else
527 uint64_t major:4;
528 uint64_t minor:2;
529 uint64_t wait:1;
530 uint64_t qid_base:7;
531 uint64_t qid_off:3;
532 uint64_t qcb_ridx:5;
533 uint64_t qos:3;
534 uint64_t active:1;
535 uint64_t chk_mode:1;
536 uint64_t reserved_27_27:1;
537 uint64_t cbuf_fre:1;
538 uint64_t xfer_dwr:1;
539 uint64_t xfer_wor:1;
540 uint64_t uid:1;
541 uint64_t cmnd_siz:16;
542 uint64_t dwri_cnt:13;
543 uint64_t dwri_len:1;
544 uint64_t dwri_sop:1;
545 uint64_t dwri_mod:1;
546 #endif
547 } cn30xx;
548 struct cvmx_pko_mem_debug5_cn50xx {
549 #ifdef __BIG_ENDIAN_BITFIELD
550 uint64_t curr_ptr:29;
551 uint64_t curr_siz:16;
552 uint64_t curr_off:16;
553 uint64_t cmnd_segs:3;
554 #else
555 uint64_t cmnd_segs:3;
556 uint64_t curr_off:16;
557 uint64_t curr_siz:16;
558 uint64_t curr_ptr:29;
559 #endif
560 } cn50xx;
561 struct cvmx_pko_mem_debug5_cn52xx {
562 #ifdef __BIG_ENDIAN_BITFIELD
563 uint64_t reserved_54_63:10;
564 uint64_t nxt_inflt:6;
565 uint64_t curr_ptr:40;
566 uint64_t curr_siz:8;
567 #else
568 uint64_t curr_siz:8;
569 uint64_t curr_ptr:40;
570 uint64_t nxt_inflt:6;
571 uint64_t reserved_54_63:10;
572 #endif
573 } cn52xx;
574 struct cvmx_pko_mem_debug5_cn61xx {
575 #ifdef __BIG_ENDIAN_BITFIELD
576 uint64_t reserved_56_63:8;
577 uint64_t ptp:1;
578 uint64_t major_3:1;
579 uint64_t nxt_inflt:6;
580 uint64_t curr_ptr:40;
581 uint64_t curr_siz:8;
582 #else
583 uint64_t curr_siz:8;
584 uint64_t curr_ptr:40;
585 uint64_t nxt_inflt:6;
586 uint64_t major_3:1;
587 uint64_t ptp:1;
588 uint64_t reserved_56_63:8;
589 #endif
590 } cn61xx;
591 struct cvmx_pko_mem_debug5_cn68xx {
592 #ifdef __BIG_ENDIAN_BITFIELD
593 uint64_t reserved_57_63:7;
594 uint64_t uid_2:1;
595 uint64_t ptp:1;
596 uint64_t major_3:1;
597 uint64_t nxt_inflt:6;
598 uint64_t curr_ptr:40;
599 uint64_t curr_siz:8;
600 #else
601 uint64_t curr_siz:8;
602 uint64_t curr_ptr:40;
603 uint64_t nxt_inflt:6;
604 uint64_t major_3:1;
605 uint64_t ptp:1;
606 uint64_t uid_2:1;
607 uint64_t reserved_57_63:7;
608 #endif
609 } cn68xx;
610 };
611
612 union cvmx_pko_mem_debug6 {
613 uint64_t u64;
614 struct cvmx_pko_mem_debug6_s {
615 #ifdef __BIG_ENDIAN_BITFIELD
616 uint64_t reserved_37_63:27;
617 uint64_t qid_offres:4;
618 uint64_t qid_offths:4;
619 uint64_t preempter:1;
620 uint64_t preemptee:1;
621 uint64_t preempted:1;
622 uint64_t active:1;
623 uint64_t statc:1;
624 uint64_t qos:3;
625 uint64_t qcb_ridx:5;
626 uint64_t qid_offmax:4;
627 uint64_t reserved_0_11:12;
628 #else
629 uint64_t reserved_0_11:12;
630 uint64_t qid_offmax:4;
631 uint64_t qcb_ridx:5;
632 uint64_t qos:3;
633 uint64_t statc:1;
634 uint64_t active:1;
635 uint64_t preempted:1;
636 uint64_t preemptee:1;
637 uint64_t preempter:1;
638 uint64_t qid_offths:4;
639 uint64_t qid_offres:4;
640 uint64_t reserved_37_63:27;
641 #endif
642 } s;
643 struct cvmx_pko_mem_debug6_cn30xx {
644 #ifdef __BIG_ENDIAN_BITFIELD
645 uint64_t reserved_11_63:53;
646 uint64_t qid_offm:3;
647 uint64_t static_p:1;
648 uint64_t work_min:3;
649 uint64_t dwri_chk:1;
650 uint64_t dwri_uid:1;
651 uint64_t dwri_mod:2;
652 #else
653 uint64_t dwri_mod:2;
654 uint64_t dwri_uid:1;
655 uint64_t dwri_chk:1;
656 uint64_t work_min:3;
657 uint64_t static_p:1;
658 uint64_t qid_offm:3;
659 uint64_t reserved_11_63:53;
660 #endif
661 } cn30xx;
662 struct cvmx_pko_mem_debug6_cn50xx {
663 #ifdef __BIG_ENDIAN_BITFIELD
664 uint64_t reserved_11_63:53;
665 uint64_t curr_ptr:11;
666 #else
667 uint64_t curr_ptr:11;
668 uint64_t reserved_11_63:53;
669 #endif
670 } cn50xx;
671 struct cvmx_pko_mem_debug6_cn52xx {
672 #ifdef __BIG_ENDIAN_BITFIELD
673 uint64_t reserved_37_63:27;
674 uint64_t qid_offres:4;
675 uint64_t qid_offths:4;
676 uint64_t preempter:1;
677 uint64_t preemptee:1;
678 uint64_t preempted:1;
679 uint64_t active:1;
680 uint64_t statc:1;
681 uint64_t qos:3;
682 uint64_t qcb_ridx:5;
683 uint64_t qid_offmax:4;
684 uint64_t qid_off:4;
685 uint64_t qid_base:8;
686 #else
687 uint64_t qid_base:8;
688 uint64_t qid_off:4;
689 uint64_t qid_offmax:4;
690 uint64_t qcb_ridx:5;
691 uint64_t qos:3;
692 uint64_t statc:1;
693 uint64_t active:1;
694 uint64_t preempted:1;
695 uint64_t preemptee:1;
696 uint64_t preempter:1;
697 uint64_t qid_offths:4;
698 uint64_t qid_offres:4;
699 uint64_t reserved_37_63:27;
700 #endif
701 } cn52xx;
702 };
703
704 union cvmx_pko_mem_debug7 {
705 uint64_t u64;
706 struct cvmx_pko_mem_debug7_s {
707 #ifdef __BIG_ENDIAN_BITFIELD
708 uint64_t reserved_0_63:64;
709 #else
710 uint64_t reserved_0_63:64;
711 #endif
712 } s;
713 struct cvmx_pko_mem_debug7_cn30xx {
714 #ifdef __BIG_ENDIAN_BITFIELD
715 uint64_t reserved_58_63:6;
716 uint64_t dwb:9;
717 uint64_t start:33;
718 uint64_t size:16;
719 #else
720 uint64_t size:16;
721 uint64_t start:33;
722 uint64_t dwb:9;
723 uint64_t reserved_58_63:6;
724 #endif
725 } cn30xx;
726 struct cvmx_pko_mem_debug7_cn50xx {
727 #ifdef __BIG_ENDIAN_BITFIELD
728 uint64_t qos:5;
729 uint64_t tail:1;
730 uint64_t buf_siz:13;
731 uint64_t buf_ptr:33;
732 uint64_t qcb_widx:6;
733 uint64_t qcb_ridx:6;
734 #else
735 uint64_t qcb_ridx:6;
736 uint64_t qcb_widx:6;
737 uint64_t buf_ptr:33;
738 uint64_t buf_siz:13;
739 uint64_t tail:1;
740 uint64_t qos:5;
741 #endif
742 } cn50xx;
743 struct cvmx_pko_mem_debug7_cn68xx {
744 #ifdef __BIG_ENDIAN_BITFIELD
745 uint64_t qos:3;
746 uint64_t tail:1;
747 uint64_t buf_siz:13;
748 uint64_t buf_ptr:33;
749 uint64_t qcb_widx:7;
750 uint64_t qcb_ridx:7;
751 #else
752 uint64_t qcb_ridx:7;
753 uint64_t qcb_widx:7;
754 uint64_t buf_ptr:33;
755 uint64_t buf_siz:13;
756 uint64_t tail:1;
757 uint64_t qos:3;
758 #endif
759 } cn68xx;
760 };
761
762 union cvmx_pko_mem_debug8 {
763 uint64_t u64;
764 struct cvmx_pko_mem_debug8_s {
765 #ifdef __BIG_ENDIAN_BITFIELD
766 uint64_t reserved_59_63:5;
767 uint64_t tail:1;
768 uint64_t buf_siz:13;
769 uint64_t reserved_0_44:45;
770 #else
771 uint64_t reserved_0_44:45;
772 uint64_t buf_siz:13;
773 uint64_t tail:1;
774 uint64_t reserved_59_63:5;
775 #endif
776 } s;
777 struct cvmx_pko_mem_debug8_cn30xx {
778 #ifdef __BIG_ENDIAN_BITFIELD
779 uint64_t qos:5;
780 uint64_t tail:1;
781 uint64_t buf_siz:13;
782 uint64_t buf_ptr:33;
783 uint64_t qcb_widx:6;
784 uint64_t qcb_ridx:6;
785 #else
786 uint64_t qcb_ridx:6;
787 uint64_t qcb_widx:6;
788 uint64_t buf_ptr:33;
789 uint64_t buf_siz:13;
790 uint64_t tail:1;
791 uint64_t qos:5;
792 #endif
793 } cn30xx;
794 struct cvmx_pko_mem_debug8_cn50xx {
795 #ifdef __BIG_ENDIAN_BITFIELD
796 uint64_t reserved_28_63:36;
797 uint64_t doorbell:20;
798 uint64_t reserved_6_7:2;
799 uint64_t static_p:1;
800 uint64_t s_tail:1;
801 uint64_t static_q:1;
802 uint64_t qos:3;
803 #else
804 uint64_t qos:3;
805 uint64_t static_q:1;
806 uint64_t s_tail:1;
807 uint64_t static_p:1;
808 uint64_t reserved_6_7:2;
809 uint64_t doorbell:20;
810 uint64_t reserved_28_63:36;
811 #endif
812 } cn50xx;
813 struct cvmx_pko_mem_debug8_cn52xx {
814 #ifdef __BIG_ENDIAN_BITFIELD
815 uint64_t reserved_29_63:35;
816 uint64_t preempter:1;
817 uint64_t doorbell:20;
818 uint64_t reserved_7_7:1;
819 uint64_t preemptee:1;
820 uint64_t static_p:1;
821 uint64_t s_tail:1;
822 uint64_t static_q:1;
823 uint64_t qos:3;
824 #else
825 uint64_t qos:3;
826 uint64_t static_q:1;
827 uint64_t s_tail:1;
828 uint64_t static_p:1;
829 uint64_t preemptee:1;
830 uint64_t reserved_7_7:1;
831 uint64_t doorbell:20;
832 uint64_t preempter:1;
833 uint64_t reserved_29_63:35;
834 #endif
835 } cn52xx;
836 struct cvmx_pko_mem_debug8_cn61xx {
837 #ifdef __BIG_ENDIAN_BITFIELD
838 uint64_t reserved_42_63:22;
839 uint64_t qid_qqos:8;
840 uint64_t reserved_33_33:1;
841 uint64_t qid_idx:4;
842 uint64_t preempter:1;
843 uint64_t doorbell:20;
844 uint64_t reserved_7_7:1;
845 uint64_t preemptee:1;
846 uint64_t static_p:1;
847 uint64_t s_tail:1;
848 uint64_t static_q:1;
849 uint64_t qos:3;
850 #else
851 uint64_t qos:3;
852 uint64_t static_q:1;
853 uint64_t s_tail:1;
854 uint64_t static_p:1;
855 uint64_t preemptee:1;
856 uint64_t reserved_7_7:1;
857 uint64_t doorbell:20;
858 uint64_t preempter:1;
859 uint64_t qid_idx:4;
860 uint64_t reserved_33_33:1;
861 uint64_t qid_qqos:8;
862 uint64_t reserved_42_63:22;
863 #endif
864 } cn61xx;
865 struct cvmx_pko_mem_debug8_cn68xx {
866 #ifdef __BIG_ENDIAN_BITFIELD
867 uint64_t reserved_37_63:27;
868 uint64_t preempter:1;
869 uint64_t doorbell:20;
870 uint64_t reserved_9_15:7;
871 uint64_t preemptee:1;
872 uint64_t static_p:1;
873 uint64_t s_tail:1;
874 uint64_t static_q:1;
875 uint64_t qos:5;
876 #else
877 uint64_t qos:5;
878 uint64_t static_q:1;
879 uint64_t s_tail:1;
880 uint64_t static_p:1;
881 uint64_t preemptee:1;
882 uint64_t reserved_9_15:7;
883 uint64_t doorbell:20;
884 uint64_t preempter:1;
885 uint64_t reserved_37_63:27;
886 #endif
887 } cn68xx;
888 };
889
890 union cvmx_pko_mem_debug9 {
891 uint64_t u64;
892 struct cvmx_pko_mem_debug9_s {
893 #ifdef __BIG_ENDIAN_BITFIELD
894 uint64_t reserved_49_63:15;
895 uint64_t ptrs0:17;
896 uint64_t reserved_0_31:32;
897 #else
898 uint64_t reserved_0_31:32;
899 uint64_t ptrs0:17;
900 uint64_t reserved_49_63:15;
901 #endif
902 } s;
903 struct cvmx_pko_mem_debug9_cn30xx {
904 #ifdef __BIG_ENDIAN_BITFIELD
905 uint64_t reserved_28_63:36;
906 uint64_t doorbell:20;
907 uint64_t reserved_5_7:3;
908 uint64_t s_tail:1;
909 uint64_t static_q:1;
910 uint64_t qos:3;
911 #else
912 uint64_t qos:3;
913 uint64_t static_q:1;
914 uint64_t s_tail:1;
915 uint64_t reserved_5_7:3;
916 uint64_t doorbell:20;
917 uint64_t reserved_28_63:36;
918 #endif
919 } cn30xx;
920 struct cvmx_pko_mem_debug9_cn38xx {
921 #ifdef __BIG_ENDIAN_BITFIELD
922 uint64_t reserved_28_63:36;
923 uint64_t doorbell:20;
924 uint64_t reserved_6_7:2;
925 uint64_t static_p:1;
926 uint64_t s_tail:1;
927 uint64_t static_q:1;
928 uint64_t qos:3;
929 #else
930 uint64_t qos:3;
931 uint64_t static_q:1;
932 uint64_t s_tail:1;
933 uint64_t static_p:1;
934 uint64_t reserved_6_7:2;
935 uint64_t doorbell:20;
936 uint64_t reserved_28_63:36;
937 #endif
938 } cn38xx;
939 struct cvmx_pko_mem_debug9_cn50xx {
940 #ifdef __BIG_ENDIAN_BITFIELD
941 uint64_t reserved_49_63:15;
942 uint64_t ptrs0:17;
943 uint64_t reserved_17_31:15;
944 uint64_t ptrs3:17;
945 #else
946 uint64_t ptrs3:17;
947 uint64_t reserved_17_31:15;
948 uint64_t ptrs0:17;
949 uint64_t reserved_49_63:15;
950 #endif
951 } cn50xx;
952 };
953
954 union cvmx_pko_mem_iport_ptrs {
955 uint64_t u64;
956 struct cvmx_pko_mem_iport_ptrs_s {
957 #ifdef __BIG_ENDIAN_BITFIELD
958 uint64_t reserved_63_63:1;
959 uint64_t crc:1;
960 uint64_t static_p:1;
961 uint64_t qos_mask:8;
962 uint64_t min_pkt:3;
963 uint64_t reserved_31_49:19;
964 uint64_t pipe:7;
965 uint64_t reserved_21_23:3;
966 uint64_t intr:5;
967 uint64_t reserved_13_15:3;
968 uint64_t eid:5;
969 uint64_t reserved_7_7:1;
970 uint64_t ipid:7;
971 #else
972 uint64_t ipid:7;
973 uint64_t reserved_7_7:1;
974 uint64_t eid:5;
975 uint64_t reserved_13_15:3;
976 uint64_t intr:5;
977 uint64_t reserved_21_23:3;
978 uint64_t pipe:7;
979 uint64_t reserved_31_49:19;
980 uint64_t min_pkt:3;
981 uint64_t qos_mask:8;
982 uint64_t static_p:1;
983 uint64_t crc:1;
984 uint64_t reserved_63_63:1;
985 #endif
986 } s;
987 };
988
989 union cvmx_pko_mem_iport_qos {
990 uint64_t u64;
991 struct cvmx_pko_mem_iport_qos_s {
992 #ifdef __BIG_ENDIAN_BITFIELD
993 uint64_t reserved_61_63:3;
994 uint64_t qos_mask:8;
995 uint64_t reserved_13_52:40;
996 uint64_t eid:5;
997 uint64_t reserved_7_7:1;
998 uint64_t ipid:7;
999 #else
1000 uint64_t ipid:7;
1001 uint64_t reserved_7_7:1;
1002 uint64_t eid:5;
1003 uint64_t reserved_13_52:40;
1004 uint64_t qos_mask:8;
1005 uint64_t reserved_61_63:3;
1006 #endif
1007 } s;
1008 };
1009
1010 union cvmx_pko_mem_iqueue_ptrs {
1011 uint64_t u64;
1012 struct cvmx_pko_mem_iqueue_ptrs_s {
1013 #ifdef __BIG_ENDIAN_BITFIELD
1014 uint64_t s_tail:1;
1015 uint64_t static_p:1;
1016 uint64_t static_q:1;
1017 uint64_t qos_mask:8;
1018 uint64_t buf_ptr:31;
1019 uint64_t tail:1;
1020 uint64_t index:5;
1021 uint64_t reserved_15_15:1;
1022 uint64_t ipid:7;
1023 uint64_t qid:8;
1024 #else
1025 uint64_t qid:8;
1026 uint64_t ipid:7;
1027 uint64_t reserved_15_15:1;
1028 uint64_t index:5;
1029 uint64_t tail:1;
1030 uint64_t buf_ptr:31;
1031 uint64_t qos_mask:8;
1032 uint64_t static_q:1;
1033 uint64_t static_p:1;
1034 uint64_t s_tail:1;
1035 #endif
1036 } s;
1037 };
1038
1039 union cvmx_pko_mem_iqueue_qos {
1040 uint64_t u64;
1041 struct cvmx_pko_mem_iqueue_qos_s {
1042 #ifdef __BIG_ENDIAN_BITFIELD
1043 uint64_t reserved_61_63:3;
1044 uint64_t qos_mask:8;
1045 uint64_t reserved_15_52:38;
1046 uint64_t ipid:7;
1047 uint64_t qid:8;
1048 #else
1049 uint64_t qid:8;
1050 uint64_t ipid:7;
1051 uint64_t reserved_15_52:38;
1052 uint64_t qos_mask:8;
1053 uint64_t reserved_61_63:3;
1054 #endif
1055 } s;
1056 };
1057
1058 union cvmx_pko_mem_port_ptrs {
1059 uint64_t u64;
1060 struct cvmx_pko_mem_port_ptrs_s {
1061 #ifdef __BIG_ENDIAN_BITFIELD
1062 uint64_t reserved_62_63:2;
1063 uint64_t static_p:1;
1064 uint64_t qos_mask:8;
1065 uint64_t reserved_16_52:37;
1066 uint64_t bp_port:6;
1067 uint64_t eid:4;
1068 uint64_t pid:6;
1069 #else
1070 uint64_t pid:6;
1071 uint64_t eid:4;
1072 uint64_t bp_port:6;
1073 uint64_t reserved_16_52:37;
1074 uint64_t qos_mask:8;
1075 uint64_t static_p:1;
1076 uint64_t reserved_62_63:2;
1077 #endif
1078 } s;
1079 };
1080
1081 union cvmx_pko_mem_port_qos {
1082 uint64_t u64;
1083 struct cvmx_pko_mem_port_qos_s {
1084 #ifdef __BIG_ENDIAN_BITFIELD
1085 uint64_t reserved_61_63:3;
1086 uint64_t qos_mask:8;
1087 uint64_t reserved_10_52:43;
1088 uint64_t eid:4;
1089 uint64_t pid:6;
1090 #else
1091 uint64_t pid:6;
1092 uint64_t eid:4;
1093 uint64_t reserved_10_52:43;
1094 uint64_t qos_mask:8;
1095 uint64_t reserved_61_63:3;
1096 #endif
1097 } s;
1098 };
1099
1100 union cvmx_pko_mem_port_rate0 {
1101 uint64_t u64;
1102 struct cvmx_pko_mem_port_rate0_s {
1103 #ifdef __BIG_ENDIAN_BITFIELD
1104 uint64_t reserved_51_63:13;
1105 uint64_t rate_word:19;
1106 uint64_t rate_pkt:24;
1107 uint64_t reserved_7_7:1;
1108 uint64_t pid:7;
1109 #else
1110 uint64_t pid:7;
1111 uint64_t reserved_7_7:1;
1112 uint64_t rate_pkt:24;
1113 uint64_t rate_word:19;
1114 uint64_t reserved_51_63:13;
1115 #endif
1116 } s;
1117 struct cvmx_pko_mem_port_rate0_cn52xx {
1118 #ifdef __BIG_ENDIAN_BITFIELD
1119 uint64_t reserved_51_63:13;
1120 uint64_t rate_word:19;
1121 uint64_t rate_pkt:24;
1122 uint64_t reserved_6_7:2;
1123 uint64_t pid:6;
1124 #else
1125 uint64_t pid:6;
1126 uint64_t reserved_6_7:2;
1127 uint64_t rate_pkt:24;
1128 uint64_t rate_word:19;
1129 uint64_t reserved_51_63:13;
1130 #endif
1131 } cn52xx;
1132 };
1133
1134 union cvmx_pko_mem_port_rate1 {
1135 uint64_t u64;
1136 struct cvmx_pko_mem_port_rate1_s {
1137 #ifdef __BIG_ENDIAN_BITFIELD
1138 uint64_t reserved_32_63:32;
1139 uint64_t rate_lim:24;
1140 uint64_t reserved_7_7:1;
1141 uint64_t pid:7;
1142 #else
1143 uint64_t pid:7;
1144 uint64_t reserved_7_7:1;
1145 uint64_t rate_lim:24;
1146 uint64_t reserved_32_63:32;
1147 #endif
1148 } s;
1149 struct cvmx_pko_mem_port_rate1_cn52xx {
1150 #ifdef __BIG_ENDIAN_BITFIELD
1151 uint64_t reserved_32_63:32;
1152 uint64_t rate_lim:24;
1153 uint64_t reserved_6_7:2;
1154 uint64_t pid:6;
1155 #else
1156 uint64_t pid:6;
1157 uint64_t reserved_6_7:2;
1158 uint64_t rate_lim:24;
1159 uint64_t reserved_32_63:32;
1160 #endif
1161 } cn52xx;
1162 };
1163
1164 union cvmx_pko_mem_queue_ptrs {
1165 uint64_t u64;
1166 struct cvmx_pko_mem_queue_ptrs_s {
1167 #ifdef __BIG_ENDIAN_BITFIELD
1168 uint64_t s_tail:1;
1169 uint64_t static_p:1;
1170 uint64_t static_q:1;
1171 uint64_t qos_mask:8;
1172 uint64_t buf_ptr:36;
1173 uint64_t tail:1;
1174 uint64_t index:3;
1175 uint64_t port:6;
1176 uint64_t queue:7;
1177 #else
1178 uint64_t queue:7;
1179 uint64_t port:6;
1180 uint64_t index:3;
1181 uint64_t tail:1;
1182 uint64_t buf_ptr:36;
1183 uint64_t qos_mask:8;
1184 uint64_t static_q:1;
1185 uint64_t static_p:1;
1186 uint64_t s_tail:1;
1187 #endif
1188 } s;
1189 };
1190
1191 union cvmx_pko_mem_queue_qos {
1192 uint64_t u64;
1193 struct cvmx_pko_mem_queue_qos_s {
1194 #ifdef __BIG_ENDIAN_BITFIELD
1195 uint64_t reserved_61_63:3;
1196 uint64_t qos_mask:8;
1197 uint64_t reserved_13_52:40;
1198 uint64_t pid:6;
1199 uint64_t qid:7;
1200 #else
1201 uint64_t qid:7;
1202 uint64_t pid:6;
1203 uint64_t reserved_13_52:40;
1204 uint64_t qos_mask:8;
1205 uint64_t reserved_61_63:3;
1206 #endif
1207 } s;
1208 };
1209
1210 union cvmx_pko_mem_throttle_int {
1211 uint64_t u64;
1212 struct cvmx_pko_mem_throttle_int_s {
1213 #ifdef __BIG_ENDIAN_BITFIELD
1214 uint64_t reserved_47_63:17;
1215 uint64_t word:15;
1216 uint64_t reserved_14_31:18;
1217 uint64_t packet:6;
1218 uint64_t reserved_5_7:3;
1219 uint64_t intr:5;
1220 #else
1221 uint64_t intr:5;
1222 uint64_t reserved_5_7:3;
1223 uint64_t packet:6;
1224 uint64_t reserved_14_31:18;
1225 uint64_t word:15;
1226 uint64_t reserved_47_63:17;
1227 #endif
1228 } s;
1229 };
1230
1231 union cvmx_pko_mem_throttle_pipe {
1232 uint64_t u64;
1233 struct cvmx_pko_mem_throttle_pipe_s {
1234 #ifdef __BIG_ENDIAN_BITFIELD
1235 uint64_t reserved_47_63:17;
1236 uint64_t word:15;
1237 uint64_t reserved_14_31:18;
1238 uint64_t packet:6;
1239 uint64_t reserved_7_7:1;
1240 uint64_t pipe:7;
1241 #else
1242 uint64_t pipe:7;
1243 uint64_t reserved_7_7:1;
1244 uint64_t packet:6;
1245 uint64_t reserved_14_31:18;
1246 uint64_t word:15;
1247 uint64_t reserved_47_63:17;
1248 #endif
1249 } s;
1250 };
1251
1252 union cvmx_pko_reg_bist_result {
1253 uint64_t u64;
1254 struct cvmx_pko_reg_bist_result_s {
1255 #ifdef __BIG_ENDIAN_BITFIELD
1256 uint64_t reserved_0_63:64;
1257 #else
1258 uint64_t reserved_0_63:64;
1259 #endif
1260 } s;
1261 struct cvmx_pko_reg_bist_result_cn30xx {
1262 #ifdef __BIG_ENDIAN_BITFIELD
1263 uint64_t reserved_27_63:37;
1264 uint64_t psb2:5;
1265 uint64_t count:1;
1266 uint64_t rif:1;
1267 uint64_t wif:1;
1268 uint64_t ncb:1;
1269 uint64_t out:1;
1270 uint64_t crc:1;
1271 uint64_t chk:1;
1272 uint64_t qsb:2;
1273 uint64_t qcb:2;
1274 uint64_t pdb:4;
1275 uint64_t psb:7;
1276 #else
1277 uint64_t psb:7;
1278 uint64_t pdb:4;
1279 uint64_t qcb:2;
1280 uint64_t qsb:2;
1281 uint64_t chk:1;
1282 uint64_t crc:1;
1283 uint64_t out:1;
1284 uint64_t ncb:1;
1285 uint64_t wif:1;
1286 uint64_t rif:1;
1287 uint64_t count:1;
1288 uint64_t psb2:5;
1289 uint64_t reserved_27_63:37;
1290 #endif
1291 } cn30xx;
1292 struct cvmx_pko_reg_bist_result_cn50xx {
1293 #ifdef __BIG_ENDIAN_BITFIELD
1294 uint64_t reserved_33_63:31;
1295 uint64_t csr:1;
1296 uint64_t iob:1;
1297 uint64_t out_crc:1;
1298 uint64_t out_ctl:3;
1299 uint64_t out_sta:1;
1300 uint64_t out_wif:1;
1301 uint64_t prt_chk:3;
1302 uint64_t prt_nxt:1;
1303 uint64_t prt_psb:6;
1304 uint64_t ncb_inb:2;
1305 uint64_t prt_qcb:2;
1306 uint64_t prt_qsb:3;
1307 uint64_t dat_dat:4;
1308 uint64_t dat_ptr:4;
1309 #else
1310 uint64_t dat_ptr:4;
1311 uint64_t dat_dat:4;
1312 uint64_t prt_qsb:3;
1313 uint64_t prt_qcb:2;
1314 uint64_t ncb_inb:2;
1315 uint64_t prt_psb:6;
1316 uint64_t prt_nxt:1;
1317 uint64_t prt_chk:3;
1318 uint64_t out_wif:1;
1319 uint64_t out_sta:1;
1320 uint64_t out_ctl:3;
1321 uint64_t out_crc:1;
1322 uint64_t iob:1;
1323 uint64_t csr:1;
1324 uint64_t reserved_33_63:31;
1325 #endif
1326 } cn50xx;
1327 struct cvmx_pko_reg_bist_result_cn52xx {
1328 #ifdef __BIG_ENDIAN_BITFIELD
1329 uint64_t reserved_35_63:29;
1330 uint64_t csr:1;
1331 uint64_t iob:1;
1332 uint64_t out_dat:1;
1333 uint64_t out_ctl:3;
1334 uint64_t out_sta:1;
1335 uint64_t out_wif:1;
1336 uint64_t prt_chk:3;
1337 uint64_t prt_nxt:1;
1338 uint64_t prt_psb:8;
1339 uint64_t ncb_inb:2;
1340 uint64_t prt_qcb:2;
1341 uint64_t prt_qsb:3;
1342 uint64_t prt_ctl:2;
1343 uint64_t dat_dat:2;
1344 uint64_t dat_ptr:4;
1345 #else
1346 uint64_t dat_ptr:4;
1347 uint64_t dat_dat:2;
1348 uint64_t prt_ctl:2;
1349 uint64_t prt_qsb:3;
1350 uint64_t prt_qcb:2;
1351 uint64_t ncb_inb:2;
1352 uint64_t prt_psb:8;
1353 uint64_t prt_nxt:1;
1354 uint64_t prt_chk:3;
1355 uint64_t out_wif:1;
1356 uint64_t out_sta:1;
1357 uint64_t out_ctl:3;
1358 uint64_t out_dat:1;
1359 uint64_t iob:1;
1360 uint64_t csr:1;
1361 uint64_t reserved_35_63:29;
1362 #endif
1363 } cn52xx;
1364 struct cvmx_pko_reg_bist_result_cn68xx {
1365 #ifdef __BIG_ENDIAN_BITFIELD
1366 uint64_t reserved_36_63:28;
1367 uint64_t crc:1;
1368 uint64_t csr:1;
1369 uint64_t iob:1;
1370 uint64_t out_dat:1;
1371 uint64_t reserved_31_31:1;
1372 uint64_t out_ctl:2;
1373 uint64_t out_sta:1;
1374 uint64_t out_wif:1;
1375 uint64_t prt_chk:3;
1376 uint64_t prt_nxt:1;
1377 uint64_t prt_psb7:1;
1378 uint64_t reserved_21_21:1;
1379 uint64_t prt_psb:6;
1380 uint64_t ncb_inb:2;
1381 uint64_t prt_qcb:2;
1382 uint64_t prt_qsb:3;
1383 uint64_t prt_ctl:2;
1384 uint64_t dat_dat:2;
1385 uint64_t dat_ptr:4;
1386 #else
1387 uint64_t dat_ptr:4;
1388 uint64_t dat_dat:2;
1389 uint64_t prt_ctl:2;
1390 uint64_t prt_qsb:3;
1391 uint64_t prt_qcb:2;
1392 uint64_t ncb_inb:2;
1393 uint64_t prt_psb:6;
1394 uint64_t reserved_21_21:1;
1395 uint64_t prt_psb7:1;
1396 uint64_t prt_nxt:1;
1397 uint64_t prt_chk:3;
1398 uint64_t out_wif:1;
1399 uint64_t out_sta:1;
1400 uint64_t out_ctl:2;
1401 uint64_t reserved_31_31:1;
1402 uint64_t out_dat:1;
1403 uint64_t iob:1;
1404 uint64_t csr:1;
1405 uint64_t crc:1;
1406 uint64_t reserved_36_63:28;
1407 #endif
1408 } cn68xx;
1409 struct cvmx_pko_reg_bist_result_cn68xxp1 {
1410 #ifdef __BIG_ENDIAN_BITFIELD
1411 uint64_t reserved_35_63:29;
1412 uint64_t csr:1;
1413 uint64_t iob:1;
1414 uint64_t out_dat:1;
1415 uint64_t reserved_31_31:1;
1416 uint64_t out_ctl:2;
1417 uint64_t out_sta:1;
1418 uint64_t out_wif:1;
1419 uint64_t prt_chk:3;
1420 uint64_t prt_nxt:1;
1421 uint64_t prt_psb7:1;
1422 uint64_t reserved_21_21:1;
1423 uint64_t prt_psb:6;
1424 uint64_t ncb_inb:2;
1425 uint64_t prt_qcb:2;
1426 uint64_t prt_qsb:3;
1427 uint64_t prt_ctl:2;
1428 uint64_t dat_dat:2;
1429 uint64_t dat_ptr:4;
1430 #else
1431 uint64_t dat_ptr:4;
1432 uint64_t dat_dat:2;
1433 uint64_t prt_ctl:2;
1434 uint64_t prt_qsb:3;
1435 uint64_t prt_qcb:2;
1436 uint64_t ncb_inb:2;
1437 uint64_t prt_psb:6;
1438 uint64_t reserved_21_21:1;
1439 uint64_t prt_psb7:1;
1440 uint64_t prt_nxt:1;
1441 uint64_t prt_chk:3;
1442 uint64_t out_wif:1;
1443 uint64_t out_sta:1;
1444 uint64_t out_ctl:2;
1445 uint64_t reserved_31_31:1;
1446 uint64_t out_dat:1;
1447 uint64_t iob:1;
1448 uint64_t csr:1;
1449 uint64_t reserved_35_63:29;
1450 #endif
1451 } cn68xxp1;
1452 };
1453
1454 union cvmx_pko_reg_cmd_buf {
1455 uint64_t u64;
1456 struct cvmx_pko_reg_cmd_buf_s {
1457 #ifdef __BIG_ENDIAN_BITFIELD
1458 uint64_t reserved_23_63:41;
1459 uint64_t pool:3;
1460 uint64_t reserved_13_19:7;
1461 uint64_t size:13;
1462 #else
1463 uint64_t size:13;
1464 uint64_t reserved_13_19:7;
1465 uint64_t pool:3;
1466 uint64_t reserved_23_63:41;
1467 #endif
1468 } s;
1469 };
1470
1471 union cvmx_pko_reg_crc_ctlx {
1472 uint64_t u64;
1473 struct cvmx_pko_reg_crc_ctlx_s {
1474 #ifdef __BIG_ENDIAN_BITFIELD
1475 uint64_t reserved_2_63:62;
1476 uint64_t invres:1;
1477 uint64_t refin:1;
1478 #else
1479 uint64_t refin:1;
1480 uint64_t invres:1;
1481 uint64_t reserved_2_63:62;
1482 #endif
1483 } s;
1484 };
1485
1486 union cvmx_pko_reg_crc_enable {
1487 uint64_t u64;
1488 struct cvmx_pko_reg_crc_enable_s {
1489 #ifdef __BIG_ENDIAN_BITFIELD
1490 uint64_t reserved_32_63:32;
1491 uint64_t enable:32;
1492 #else
1493 uint64_t enable:32;
1494 uint64_t reserved_32_63:32;
1495 #endif
1496 } s;
1497 };
1498
1499 union cvmx_pko_reg_crc_ivx {
1500 uint64_t u64;
1501 struct cvmx_pko_reg_crc_ivx_s {
1502 #ifdef __BIG_ENDIAN_BITFIELD
1503 uint64_t reserved_32_63:32;
1504 uint64_t iv:32;
1505 #else
1506 uint64_t iv:32;
1507 uint64_t reserved_32_63:32;
1508 #endif
1509 } s;
1510 };
1511
1512 union cvmx_pko_reg_debug0 {
1513 uint64_t u64;
1514 struct cvmx_pko_reg_debug0_s {
1515 #ifdef __BIG_ENDIAN_BITFIELD
1516 uint64_t asserts:64;
1517 #else
1518 uint64_t asserts:64;
1519 #endif
1520 } s;
1521 struct cvmx_pko_reg_debug0_cn30xx {
1522 #ifdef __BIG_ENDIAN_BITFIELD
1523 uint64_t reserved_17_63:47;
1524 uint64_t asserts:17;
1525 #else
1526 uint64_t asserts:17;
1527 uint64_t reserved_17_63:47;
1528 #endif
1529 } cn30xx;
1530 };
1531
1532 union cvmx_pko_reg_debug1 {
1533 uint64_t u64;
1534 struct cvmx_pko_reg_debug1_s {
1535 #ifdef __BIG_ENDIAN_BITFIELD
1536 uint64_t asserts:64;
1537 #else
1538 uint64_t asserts:64;
1539 #endif
1540 } s;
1541 };
1542
1543 union cvmx_pko_reg_debug2 {
1544 uint64_t u64;
1545 struct cvmx_pko_reg_debug2_s {
1546 #ifdef __BIG_ENDIAN_BITFIELD
1547 uint64_t asserts:64;
1548 #else
1549 uint64_t asserts:64;
1550 #endif
1551 } s;
1552 };
1553
1554 union cvmx_pko_reg_debug3 {
1555 uint64_t u64;
1556 struct cvmx_pko_reg_debug3_s {
1557 #ifdef __BIG_ENDIAN_BITFIELD
1558 uint64_t asserts:64;
1559 #else
1560 uint64_t asserts:64;
1561 #endif
1562 } s;
1563 };
1564
1565 union cvmx_pko_reg_debug4 {
1566 uint64_t u64;
1567 struct cvmx_pko_reg_debug4_s {
1568 #ifdef __BIG_ENDIAN_BITFIELD
1569 uint64_t asserts:64;
1570 #else
1571 uint64_t asserts:64;
1572 #endif
1573 } s;
1574 };
1575
1576 union cvmx_pko_reg_engine_inflight {
1577 uint64_t u64;
1578 struct cvmx_pko_reg_engine_inflight_s {
1579 #ifdef __BIG_ENDIAN_BITFIELD
1580 uint64_t engine15:4;
1581 uint64_t engine14:4;
1582 uint64_t engine13:4;
1583 uint64_t engine12:4;
1584 uint64_t engine11:4;
1585 uint64_t engine10:4;
1586 uint64_t engine9:4;
1587 uint64_t engine8:4;
1588 uint64_t engine7:4;
1589 uint64_t engine6:4;
1590 uint64_t engine5:4;
1591 uint64_t engine4:4;
1592 uint64_t engine3:4;
1593 uint64_t engine2:4;
1594 uint64_t engine1:4;
1595 uint64_t engine0:4;
1596 #else
1597 uint64_t engine0:4;
1598 uint64_t engine1:4;
1599 uint64_t engine2:4;
1600 uint64_t engine3:4;
1601 uint64_t engine4:4;
1602 uint64_t engine5:4;
1603 uint64_t engine6:4;
1604 uint64_t engine7:4;
1605 uint64_t engine8:4;
1606 uint64_t engine9:4;
1607 uint64_t engine10:4;
1608 uint64_t engine11:4;
1609 uint64_t engine12:4;
1610 uint64_t engine13:4;
1611 uint64_t engine14:4;
1612 uint64_t engine15:4;
1613 #endif
1614 } s;
1615 struct cvmx_pko_reg_engine_inflight_cn52xx {
1616 #ifdef __BIG_ENDIAN_BITFIELD
1617 uint64_t reserved_40_63:24;
1618 uint64_t engine9:4;
1619 uint64_t engine8:4;
1620 uint64_t engine7:4;
1621 uint64_t engine6:4;
1622 uint64_t engine5:4;
1623 uint64_t engine4:4;
1624 uint64_t engine3:4;
1625 uint64_t engine2:4;
1626 uint64_t engine1:4;
1627 uint64_t engine0:4;
1628 #else
1629 uint64_t engine0:4;
1630 uint64_t engine1:4;
1631 uint64_t engine2:4;
1632 uint64_t engine3:4;
1633 uint64_t engine4:4;
1634 uint64_t engine5:4;
1635 uint64_t engine6:4;
1636 uint64_t engine7:4;
1637 uint64_t engine8:4;
1638 uint64_t engine9:4;
1639 uint64_t reserved_40_63:24;
1640 #endif
1641 } cn52xx;
1642 struct cvmx_pko_reg_engine_inflight_cn61xx {
1643 #ifdef __BIG_ENDIAN_BITFIELD
1644 uint64_t reserved_56_63:8;
1645 uint64_t engine13:4;
1646 uint64_t engine12:4;
1647 uint64_t engine11:4;
1648 uint64_t engine10:4;
1649 uint64_t engine9:4;
1650 uint64_t engine8:4;
1651 uint64_t engine7:4;
1652 uint64_t engine6:4;
1653 uint64_t engine5:4;
1654 uint64_t engine4:4;
1655 uint64_t engine3:4;
1656 uint64_t engine2:4;
1657 uint64_t engine1:4;
1658 uint64_t engine0:4;
1659 #else
1660 uint64_t engine0:4;
1661 uint64_t engine1:4;
1662 uint64_t engine2:4;
1663 uint64_t engine3:4;
1664 uint64_t engine4:4;
1665 uint64_t engine5:4;
1666 uint64_t engine6:4;
1667 uint64_t engine7:4;
1668 uint64_t engine8:4;
1669 uint64_t engine9:4;
1670 uint64_t engine10:4;
1671 uint64_t engine11:4;
1672 uint64_t engine12:4;
1673 uint64_t engine13:4;
1674 uint64_t reserved_56_63:8;
1675 #endif
1676 } cn61xx;
1677 struct cvmx_pko_reg_engine_inflight_cn63xx {
1678 #ifdef __BIG_ENDIAN_BITFIELD
1679 uint64_t reserved_48_63:16;
1680 uint64_t engine11:4;
1681 uint64_t engine10:4;
1682 uint64_t engine9:4;
1683 uint64_t engine8:4;
1684 uint64_t engine7:4;
1685 uint64_t engine6:4;
1686 uint64_t engine5:4;
1687 uint64_t engine4:4;
1688 uint64_t engine3:4;
1689 uint64_t engine2:4;
1690 uint64_t engine1:4;
1691 uint64_t engine0:4;
1692 #else
1693 uint64_t engine0:4;
1694 uint64_t engine1:4;
1695 uint64_t engine2:4;
1696 uint64_t engine3:4;
1697 uint64_t engine4:4;
1698 uint64_t engine5:4;
1699 uint64_t engine6:4;
1700 uint64_t engine7:4;
1701 uint64_t engine8:4;
1702 uint64_t engine9:4;
1703 uint64_t engine10:4;
1704 uint64_t engine11:4;
1705 uint64_t reserved_48_63:16;
1706 #endif
1707 } cn63xx;
1708 };
1709
1710 union cvmx_pko_reg_engine_inflight1 {
1711 uint64_t u64;
1712 struct cvmx_pko_reg_engine_inflight1_s {
1713 #ifdef __BIG_ENDIAN_BITFIELD
1714 uint64_t reserved_16_63:48;
1715 uint64_t engine19:4;
1716 uint64_t engine18:4;
1717 uint64_t engine17:4;
1718 uint64_t engine16:4;
1719 #else
1720 uint64_t engine16:4;
1721 uint64_t engine17:4;
1722 uint64_t engine18:4;
1723 uint64_t engine19:4;
1724 uint64_t reserved_16_63:48;
1725 #endif
1726 } s;
1727 };
1728
1729 union cvmx_pko_reg_engine_storagex {
1730 uint64_t u64;
1731 struct cvmx_pko_reg_engine_storagex_s {
1732 #ifdef __BIG_ENDIAN_BITFIELD
1733 uint64_t engine15:4;
1734 uint64_t engine14:4;
1735 uint64_t engine13:4;
1736 uint64_t engine12:4;
1737 uint64_t engine11:4;
1738 uint64_t engine10:4;
1739 uint64_t engine9:4;
1740 uint64_t engine8:4;
1741 uint64_t engine7:4;
1742 uint64_t engine6:4;
1743 uint64_t engine5:4;
1744 uint64_t engine4:4;
1745 uint64_t engine3:4;
1746 uint64_t engine2:4;
1747 uint64_t engine1:4;
1748 uint64_t engine0:4;
1749 #else
1750 uint64_t engine0:4;
1751 uint64_t engine1:4;
1752 uint64_t engine2:4;
1753 uint64_t engine3:4;
1754 uint64_t engine4:4;
1755 uint64_t engine5:4;
1756 uint64_t engine6:4;
1757 uint64_t engine7:4;
1758 uint64_t engine8:4;
1759 uint64_t engine9:4;
1760 uint64_t engine10:4;
1761 uint64_t engine11:4;
1762 uint64_t engine12:4;
1763 uint64_t engine13:4;
1764 uint64_t engine14:4;
1765 uint64_t engine15:4;
1766 #endif
1767 } s;
1768 };
1769
1770 union cvmx_pko_reg_engine_thresh {
1771 uint64_t u64;
1772 struct cvmx_pko_reg_engine_thresh_s {
1773 #ifdef __BIG_ENDIAN_BITFIELD
1774 uint64_t reserved_20_63:44;
1775 uint64_t mask:20;
1776 #else
1777 uint64_t mask:20;
1778 uint64_t reserved_20_63:44;
1779 #endif
1780 } s;
1781 struct cvmx_pko_reg_engine_thresh_cn52xx {
1782 #ifdef __BIG_ENDIAN_BITFIELD
1783 uint64_t reserved_10_63:54;
1784 uint64_t mask:10;
1785 #else
1786 uint64_t mask:10;
1787 uint64_t reserved_10_63:54;
1788 #endif
1789 } cn52xx;
1790 struct cvmx_pko_reg_engine_thresh_cn61xx {
1791 #ifdef __BIG_ENDIAN_BITFIELD
1792 uint64_t reserved_14_63:50;
1793 uint64_t mask:14;
1794 #else
1795 uint64_t mask:14;
1796 uint64_t reserved_14_63:50;
1797 #endif
1798 } cn61xx;
1799 struct cvmx_pko_reg_engine_thresh_cn63xx {
1800 #ifdef __BIG_ENDIAN_BITFIELD
1801 uint64_t reserved_12_63:52;
1802 uint64_t mask:12;
1803 #else
1804 uint64_t mask:12;
1805 uint64_t reserved_12_63:52;
1806 #endif
1807 } cn63xx;
1808 };
1809
1810 union cvmx_pko_reg_error {
1811 uint64_t u64;
1812 struct cvmx_pko_reg_error_s {
1813 #ifdef __BIG_ENDIAN_BITFIELD
1814 uint64_t reserved_4_63:60;
1815 uint64_t loopback:1;
1816 uint64_t currzero:1;
1817 uint64_t doorbell:1;
1818 uint64_t parity:1;
1819 #else
1820 uint64_t parity:1;
1821 uint64_t doorbell:1;
1822 uint64_t currzero:1;
1823 uint64_t loopback:1;
1824 uint64_t reserved_4_63:60;
1825 #endif
1826 } s;
1827 struct cvmx_pko_reg_error_cn30xx {
1828 #ifdef __BIG_ENDIAN_BITFIELD
1829 uint64_t reserved_2_63:62;
1830 uint64_t doorbell:1;
1831 uint64_t parity:1;
1832 #else
1833 uint64_t parity:1;
1834 uint64_t doorbell:1;
1835 uint64_t reserved_2_63:62;
1836 #endif
1837 } cn30xx;
1838 struct cvmx_pko_reg_error_cn50xx {
1839 #ifdef __BIG_ENDIAN_BITFIELD
1840 uint64_t reserved_3_63:61;
1841 uint64_t currzero:1;
1842 uint64_t doorbell:1;
1843 uint64_t parity:1;
1844 #else
1845 uint64_t parity:1;
1846 uint64_t doorbell:1;
1847 uint64_t currzero:1;
1848 uint64_t reserved_3_63:61;
1849 #endif
1850 } cn50xx;
1851 };
1852
1853 union cvmx_pko_reg_flags {
1854 uint64_t u64;
1855 struct cvmx_pko_reg_flags_s {
1856 #ifdef __BIG_ENDIAN_BITFIELD
1857 uint64_t reserved_9_63:55;
1858 uint64_t dis_perf3:1;
1859 uint64_t dis_perf2:1;
1860 uint64_t dis_perf1:1;
1861 uint64_t dis_perf0:1;
1862 uint64_t ena_throttle:1;
1863 uint64_t reset:1;
1864 uint64_t store_be:1;
1865 uint64_t ena_dwb:1;
1866 uint64_t ena_pko:1;
1867 #else
1868 uint64_t ena_pko:1;
1869 uint64_t ena_dwb:1;
1870 uint64_t store_be:1;
1871 uint64_t reset:1;
1872 uint64_t ena_throttle:1;
1873 uint64_t dis_perf0:1;
1874 uint64_t dis_perf1:1;
1875 uint64_t dis_perf2:1;
1876 uint64_t dis_perf3:1;
1877 uint64_t reserved_9_63:55;
1878 #endif
1879 } s;
1880 struct cvmx_pko_reg_flags_cn30xx {
1881 #ifdef __BIG_ENDIAN_BITFIELD
1882 uint64_t reserved_4_63:60;
1883 uint64_t reset:1;
1884 uint64_t store_be:1;
1885 uint64_t ena_dwb:1;
1886 uint64_t ena_pko:1;
1887 #else
1888 uint64_t ena_pko:1;
1889 uint64_t ena_dwb:1;
1890 uint64_t store_be:1;
1891 uint64_t reset:1;
1892 uint64_t reserved_4_63:60;
1893 #endif
1894 } cn30xx;
1895 struct cvmx_pko_reg_flags_cn61xx {
1896 #ifdef __BIG_ENDIAN_BITFIELD
1897 uint64_t reserved_9_63:55;
1898 uint64_t dis_perf3:1;
1899 uint64_t dis_perf2:1;
1900 uint64_t reserved_4_6:3;
1901 uint64_t reset:1;
1902 uint64_t store_be:1;
1903 uint64_t ena_dwb:1;
1904 uint64_t ena_pko:1;
1905 #else
1906 uint64_t ena_pko:1;
1907 uint64_t ena_dwb:1;
1908 uint64_t store_be:1;
1909 uint64_t reset:1;
1910 uint64_t reserved_4_6:3;
1911 uint64_t dis_perf2:1;
1912 uint64_t dis_perf3:1;
1913 uint64_t reserved_9_63:55;
1914 #endif
1915 } cn61xx;
1916 struct cvmx_pko_reg_flags_cn68xxp1 {
1917 #ifdef __BIG_ENDIAN_BITFIELD
1918 uint64_t reserved_7_63:57;
1919 uint64_t dis_perf1:1;
1920 uint64_t dis_perf0:1;
1921 uint64_t ena_throttle:1;
1922 uint64_t reset:1;
1923 uint64_t store_be:1;
1924 uint64_t ena_dwb:1;
1925 uint64_t ena_pko:1;
1926 #else
1927 uint64_t ena_pko:1;
1928 uint64_t ena_dwb:1;
1929 uint64_t store_be:1;
1930 uint64_t reset:1;
1931 uint64_t ena_throttle:1;
1932 uint64_t dis_perf0:1;
1933 uint64_t dis_perf1:1;
1934 uint64_t reserved_7_63:57;
1935 #endif
1936 } cn68xxp1;
1937 };
1938
1939 union cvmx_pko_reg_gmx_port_mode {
1940 uint64_t u64;
1941 struct cvmx_pko_reg_gmx_port_mode_s {
1942 #ifdef __BIG_ENDIAN_BITFIELD
1943 uint64_t reserved_6_63:58;
1944 uint64_t mode1:3;
1945 uint64_t mode0:3;
1946 #else
1947 uint64_t mode0:3;
1948 uint64_t mode1:3;
1949 uint64_t reserved_6_63:58;
1950 #endif
1951 } s;
1952 };
1953
1954 union cvmx_pko_reg_int_mask {
1955 uint64_t u64;
1956 struct cvmx_pko_reg_int_mask_s {
1957 #ifdef __BIG_ENDIAN_BITFIELD
1958 uint64_t reserved_4_63:60;
1959 uint64_t loopback:1;
1960 uint64_t currzero:1;
1961 uint64_t doorbell:1;
1962 uint64_t parity:1;
1963 #else
1964 uint64_t parity:1;
1965 uint64_t doorbell:1;
1966 uint64_t currzero:1;
1967 uint64_t loopback:1;
1968 uint64_t reserved_4_63:60;
1969 #endif
1970 } s;
1971 struct cvmx_pko_reg_int_mask_cn30xx {
1972 #ifdef __BIG_ENDIAN_BITFIELD
1973 uint64_t reserved_2_63:62;
1974 uint64_t doorbell:1;
1975 uint64_t parity:1;
1976 #else
1977 uint64_t parity:1;
1978 uint64_t doorbell:1;
1979 uint64_t reserved_2_63:62;
1980 #endif
1981 } cn30xx;
1982 struct cvmx_pko_reg_int_mask_cn50xx {
1983 #ifdef __BIG_ENDIAN_BITFIELD
1984 uint64_t reserved_3_63:61;
1985 uint64_t currzero:1;
1986 uint64_t doorbell:1;
1987 uint64_t parity:1;
1988 #else
1989 uint64_t parity:1;
1990 uint64_t doorbell:1;
1991 uint64_t currzero:1;
1992 uint64_t reserved_3_63:61;
1993 #endif
1994 } cn50xx;
1995 };
1996
1997 union cvmx_pko_reg_loopback_bpid {
1998 uint64_t u64;
1999 struct cvmx_pko_reg_loopback_bpid_s {
2000 #ifdef __BIG_ENDIAN_BITFIELD
2001 uint64_t reserved_59_63:5;
2002 uint64_t bpid7:6;
2003 uint64_t reserved_52_52:1;
2004 uint64_t bpid6:6;
2005 uint64_t reserved_45_45:1;
2006 uint64_t bpid5:6;
2007 uint64_t reserved_38_38:1;
2008 uint64_t bpid4:6;
2009 uint64_t reserved_31_31:1;
2010 uint64_t bpid3:6;
2011 uint64_t reserved_24_24:1;
2012 uint64_t bpid2:6;
2013 uint64_t reserved_17_17:1;
2014 uint64_t bpid1:6;
2015 uint64_t reserved_10_10:1;
2016 uint64_t bpid0:6;
2017 uint64_t reserved_0_3:4;
2018 #else
2019 uint64_t reserved_0_3:4;
2020 uint64_t bpid0:6;
2021 uint64_t reserved_10_10:1;
2022 uint64_t bpid1:6;
2023 uint64_t reserved_17_17:1;
2024 uint64_t bpid2:6;
2025 uint64_t reserved_24_24:1;
2026 uint64_t bpid3:6;
2027 uint64_t reserved_31_31:1;
2028 uint64_t bpid4:6;
2029 uint64_t reserved_38_38:1;
2030 uint64_t bpid5:6;
2031 uint64_t reserved_45_45:1;
2032 uint64_t bpid6:6;
2033 uint64_t reserved_52_52:1;
2034 uint64_t bpid7:6;
2035 uint64_t reserved_59_63:5;
2036 #endif
2037 } s;
2038 };
2039
2040 union cvmx_pko_reg_loopback_pkind {
2041 uint64_t u64;
2042 struct cvmx_pko_reg_loopback_pkind_s {
2043 #ifdef __BIG_ENDIAN_BITFIELD
2044 uint64_t reserved_59_63:5;
2045 uint64_t pkind7:6;
2046 uint64_t reserved_52_52:1;
2047 uint64_t pkind6:6;
2048 uint64_t reserved_45_45:1;
2049 uint64_t pkind5:6;
2050 uint64_t reserved_38_38:1;
2051 uint64_t pkind4:6;
2052 uint64_t reserved_31_31:1;
2053 uint64_t pkind3:6;
2054 uint64_t reserved_24_24:1;
2055 uint64_t pkind2:6;
2056 uint64_t reserved_17_17:1;
2057 uint64_t pkind1:6;
2058 uint64_t reserved_10_10:1;
2059 uint64_t pkind0:6;
2060 uint64_t num_ports:4;
2061 #else
2062 uint64_t num_ports:4;
2063 uint64_t pkind0:6;
2064 uint64_t reserved_10_10:1;
2065 uint64_t pkind1:6;
2066 uint64_t reserved_17_17:1;
2067 uint64_t pkind2:6;
2068 uint64_t reserved_24_24:1;
2069 uint64_t pkind3:6;
2070 uint64_t reserved_31_31:1;
2071 uint64_t pkind4:6;
2072 uint64_t reserved_38_38:1;
2073 uint64_t pkind5:6;
2074 uint64_t reserved_45_45:1;
2075 uint64_t pkind6:6;
2076 uint64_t reserved_52_52:1;
2077 uint64_t pkind7:6;
2078 uint64_t reserved_59_63:5;
2079 #endif
2080 } s;
2081 };
2082
2083 union cvmx_pko_reg_min_pkt {
2084 uint64_t u64;
2085 struct cvmx_pko_reg_min_pkt_s {
2086 #ifdef __BIG_ENDIAN_BITFIELD
2087 uint64_t size7:8;
2088 uint64_t size6:8;
2089 uint64_t size5:8;
2090 uint64_t size4:8;
2091 uint64_t size3:8;
2092 uint64_t size2:8;
2093 uint64_t size1:8;
2094 uint64_t size0:8;
2095 #else
2096 uint64_t size0:8;
2097 uint64_t size1:8;
2098 uint64_t size2:8;
2099 uint64_t size3:8;
2100 uint64_t size4:8;
2101 uint64_t size5:8;
2102 uint64_t size6:8;
2103 uint64_t size7:8;
2104 #endif
2105 } s;
2106 };
2107
2108 union cvmx_pko_reg_preempt {
2109 uint64_t u64;
2110 struct cvmx_pko_reg_preempt_s {
2111 #ifdef __BIG_ENDIAN_BITFIELD
2112 uint64_t reserved_16_63:48;
2113 uint64_t min_size:16;
2114 #else
2115 uint64_t min_size:16;
2116 uint64_t reserved_16_63:48;
2117 #endif
2118 } s;
2119 };
2120
2121 union cvmx_pko_reg_queue_mode {
2122 uint64_t u64;
2123 struct cvmx_pko_reg_queue_mode_s {
2124 #ifdef __BIG_ENDIAN_BITFIELD
2125 uint64_t reserved_2_63:62;
2126 uint64_t mode:2;
2127 #else
2128 uint64_t mode:2;
2129 uint64_t reserved_2_63:62;
2130 #endif
2131 } s;
2132 };
2133
2134 union cvmx_pko_reg_queue_preempt {
2135 uint64_t u64;
2136 struct cvmx_pko_reg_queue_preempt_s {
2137 #ifdef __BIG_ENDIAN_BITFIELD
2138 uint64_t reserved_2_63:62;
2139 uint64_t preemptee:1;
2140 uint64_t preempter:1;
2141 #else
2142 uint64_t preempter:1;
2143 uint64_t preemptee:1;
2144 uint64_t reserved_2_63:62;
2145 #endif
2146 } s;
2147 };
2148
2149 union cvmx_pko_reg_queue_ptrs1 {
2150 uint64_t u64;
2151 struct cvmx_pko_reg_queue_ptrs1_s {
2152 #ifdef __BIG_ENDIAN_BITFIELD
2153 uint64_t reserved_2_63:62;
2154 uint64_t idx3:1;
2155 uint64_t qid7:1;
2156 #else
2157 uint64_t qid7:1;
2158 uint64_t idx3:1;
2159 uint64_t reserved_2_63:62;
2160 #endif
2161 } s;
2162 };
2163
2164 union cvmx_pko_reg_read_idx {
2165 uint64_t u64;
2166 struct cvmx_pko_reg_read_idx_s {
2167 #ifdef __BIG_ENDIAN_BITFIELD
2168 uint64_t reserved_16_63:48;
2169 uint64_t inc:8;
2170 uint64_t index:8;
2171 #else
2172 uint64_t index:8;
2173 uint64_t inc:8;
2174 uint64_t reserved_16_63:48;
2175 #endif
2176 } s;
2177 };
2178
2179 union cvmx_pko_reg_throttle {
2180 uint64_t u64;
2181 struct cvmx_pko_reg_throttle_s {
2182 #ifdef __BIG_ENDIAN_BITFIELD
2183 uint64_t reserved_32_63:32;
2184 uint64_t int_mask:32;
2185 #else
2186 uint64_t int_mask:32;
2187 uint64_t reserved_32_63:32;
2188 #endif
2189 } s;
2190 };
2191
2192 union cvmx_pko_reg_timestamp {
2193 uint64_t u64;
2194 struct cvmx_pko_reg_timestamp_s {
2195 #ifdef __BIG_ENDIAN_BITFIELD
2196 uint64_t reserved_4_63:60;
2197 uint64_t wqe_word:4;
2198 #else
2199 uint64_t wqe_word:4;
2200 uint64_t reserved_4_63:60;
2201 #endif
2202 } s;
2203 };
2204
2205 #endif