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28 #ifndef __CVMX_ASXX_DEFS_H__
29 #define __CVMX_ASXX_DEFS_H__
30
31 #define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
32 #define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
33 #define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
34 #define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull))
36 #define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull)
37 #define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull)
38 #define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull)
39 #define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull)
40 #define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull)
41 #define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull)
42 #define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull)
43 #define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull)
44 #define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull)
45 #define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull)
46 #define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull)
47 #define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
48 #define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull)
49 #define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull)
50 #define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull)
51 #define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull)
52 #define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull)
53 #define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
54 #define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull)
55 #define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
56 #define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)
57
58 void __cvmx_interrupt_asxx_enable(int block);
59
60 union cvmx_asxx_gmii_rx_clk_set {
61 uint64_t u64;
62 struct cvmx_asxx_gmii_rx_clk_set_s {
63 #ifdef __BIG_ENDIAN_BITFIELD
64 uint64_t reserved_5_63:59;
65 uint64_t setting:5;
66 #else
67 uint64_t setting:5;
68 uint64_t reserved_5_63:59;
69 #endif
70 } s;
71 };
72
73 union cvmx_asxx_gmii_rx_dat_set {
74 uint64_t u64;
75 struct cvmx_asxx_gmii_rx_dat_set_s {
76 #ifdef __BIG_ENDIAN_BITFIELD
77 uint64_t reserved_5_63:59;
78 uint64_t setting:5;
79 #else
80 uint64_t setting:5;
81 uint64_t reserved_5_63:59;
82 #endif
83 } s;
84 };
85
86 union cvmx_asxx_int_en {
87 uint64_t u64;
88 struct cvmx_asxx_int_en_s {
89 #ifdef __BIG_ENDIAN_BITFIELD
90 uint64_t reserved_12_63:52;
91 uint64_t txpsh:4;
92 uint64_t txpop:4;
93 uint64_t ovrflw:4;
94 #else
95 uint64_t ovrflw:4;
96 uint64_t txpop:4;
97 uint64_t txpsh:4;
98 uint64_t reserved_12_63:52;
99 #endif
100 } s;
101 struct cvmx_asxx_int_en_cn30xx {
102 #ifdef __BIG_ENDIAN_BITFIELD
103 uint64_t reserved_11_63:53;
104 uint64_t txpsh:3;
105 uint64_t reserved_7_7:1;
106 uint64_t txpop:3;
107 uint64_t reserved_3_3:1;
108 uint64_t ovrflw:3;
109 #else
110 uint64_t ovrflw:3;
111 uint64_t reserved_3_3:1;
112 uint64_t txpop:3;
113 uint64_t reserved_7_7:1;
114 uint64_t txpsh:3;
115 uint64_t reserved_11_63:53;
116 #endif
117 } cn30xx;
118 };
119
120 union cvmx_asxx_int_reg {
121 uint64_t u64;
122 struct cvmx_asxx_int_reg_s {
123 #ifdef __BIG_ENDIAN_BITFIELD
124 uint64_t reserved_12_63:52;
125 uint64_t txpsh:4;
126 uint64_t txpop:4;
127 uint64_t ovrflw:4;
128 #else
129 uint64_t ovrflw:4;
130 uint64_t txpop:4;
131 uint64_t txpsh:4;
132 uint64_t reserved_12_63:52;
133 #endif
134 } s;
135 struct cvmx_asxx_int_reg_cn30xx {
136 #ifdef __BIG_ENDIAN_BITFIELD
137 uint64_t reserved_11_63:53;
138 uint64_t txpsh:3;
139 uint64_t reserved_7_7:1;
140 uint64_t txpop:3;
141 uint64_t reserved_3_3:1;
142 uint64_t ovrflw:3;
143 #else
144 uint64_t ovrflw:3;
145 uint64_t reserved_3_3:1;
146 uint64_t txpop:3;
147 uint64_t reserved_7_7:1;
148 uint64_t txpsh:3;
149 uint64_t reserved_11_63:53;
150 #endif
151 } cn30xx;
152 };
153
154 union cvmx_asxx_mii_rx_dat_set {
155 uint64_t u64;
156 struct cvmx_asxx_mii_rx_dat_set_s {
157 #ifdef __BIG_ENDIAN_BITFIELD
158 uint64_t reserved_5_63:59;
159 uint64_t setting:5;
160 #else
161 uint64_t setting:5;
162 uint64_t reserved_5_63:59;
163 #endif
164 } s;
165 };
166
167 union cvmx_asxx_prt_loop {
168 uint64_t u64;
169 struct cvmx_asxx_prt_loop_s {
170 #ifdef __BIG_ENDIAN_BITFIELD
171 uint64_t reserved_8_63:56;
172 uint64_t ext_loop:4;
173 uint64_t int_loop:4;
174 #else
175 uint64_t int_loop:4;
176 uint64_t ext_loop:4;
177 uint64_t reserved_8_63:56;
178 #endif
179 } s;
180 struct cvmx_asxx_prt_loop_cn30xx {
181 #ifdef __BIG_ENDIAN_BITFIELD
182 uint64_t reserved_7_63:57;
183 uint64_t ext_loop:3;
184 uint64_t reserved_3_3:1;
185 uint64_t int_loop:3;
186 #else
187 uint64_t int_loop:3;
188 uint64_t reserved_3_3:1;
189 uint64_t ext_loop:3;
190 uint64_t reserved_7_63:57;
191 #endif
192 } cn30xx;
193 };
194
195 union cvmx_asxx_rld_bypass {
196 uint64_t u64;
197 struct cvmx_asxx_rld_bypass_s {
198 #ifdef __BIG_ENDIAN_BITFIELD
199 uint64_t reserved_1_63:63;
200 uint64_t bypass:1;
201 #else
202 uint64_t bypass:1;
203 uint64_t reserved_1_63:63;
204 #endif
205 } s;
206 };
207
208 union cvmx_asxx_rld_bypass_setting {
209 uint64_t u64;
210 struct cvmx_asxx_rld_bypass_setting_s {
211 #ifdef __BIG_ENDIAN_BITFIELD
212 uint64_t reserved_5_63:59;
213 uint64_t setting:5;
214 #else
215 uint64_t setting:5;
216 uint64_t reserved_5_63:59;
217 #endif
218 } s;
219 };
220
221 union cvmx_asxx_rld_comp {
222 uint64_t u64;
223 struct cvmx_asxx_rld_comp_s {
224 #ifdef __BIG_ENDIAN_BITFIELD
225 uint64_t reserved_9_63:55;
226 uint64_t pctl:5;
227 uint64_t nctl:4;
228 #else
229 uint64_t nctl:4;
230 uint64_t pctl:5;
231 uint64_t reserved_9_63:55;
232 #endif
233 } s;
234 struct cvmx_asxx_rld_comp_cn38xx {
235 #ifdef __BIG_ENDIAN_BITFIELD
236 uint64_t reserved_8_63:56;
237 uint64_t pctl:4;
238 uint64_t nctl:4;
239 #else
240 uint64_t nctl:4;
241 uint64_t pctl:4;
242 uint64_t reserved_8_63:56;
243 #endif
244 } cn38xx;
245 };
246
247 union cvmx_asxx_rld_data_drv {
248 uint64_t u64;
249 struct cvmx_asxx_rld_data_drv_s {
250 #ifdef __BIG_ENDIAN_BITFIELD
251 uint64_t reserved_8_63:56;
252 uint64_t pctl:4;
253 uint64_t nctl:4;
254 #else
255 uint64_t nctl:4;
256 uint64_t pctl:4;
257 uint64_t reserved_8_63:56;
258 #endif
259 } s;
260 };
261
262 union cvmx_asxx_rld_fcram_mode {
263 uint64_t u64;
264 struct cvmx_asxx_rld_fcram_mode_s {
265 #ifdef __BIG_ENDIAN_BITFIELD
266 uint64_t reserved_1_63:63;
267 uint64_t mode:1;
268 #else
269 uint64_t mode:1;
270 uint64_t reserved_1_63:63;
271 #endif
272 } s;
273 };
274
275 union cvmx_asxx_rld_nctl_strong {
276 uint64_t u64;
277 struct cvmx_asxx_rld_nctl_strong_s {
278 #ifdef __BIG_ENDIAN_BITFIELD
279 uint64_t reserved_5_63:59;
280 uint64_t nctl:5;
281 #else
282 uint64_t nctl:5;
283 uint64_t reserved_5_63:59;
284 #endif
285 } s;
286 };
287
288 union cvmx_asxx_rld_nctl_weak {
289 uint64_t u64;
290 struct cvmx_asxx_rld_nctl_weak_s {
291 #ifdef __BIG_ENDIAN_BITFIELD
292 uint64_t reserved_5_63:59;
293 uint64_t nctl:5;
294 #else
295 uint64_t nctl:5;
296 uint64_t reserved_5_63:59;
297 #endif
298 } s;
299 };
300
301 union cvmx_asxx_rld_pctl_strong {
302 uint64_t u64;
303 struct cvmx_asxx_rld_pctl_strong_s {
304 #ifdef __BIG_ENDIAN_BITFIELD
305 uint64_t reserved_5_63:59;
306 uint64_t pctl:5;
307 #else
308 uint64_t pctl:5;
309 uint64_t reserved_5_63:59;
310 #endif
311 } s;
312 };
313
314 union cvmx_asxx_rld_pctl_weak {
315 uint64_t u64;
316 struct cvmx_asxx_rld_pctl_weak_s {
317 #ifdef __BIG_ENDIAN_BITFIELD
318 uint64_t reserved_5_63:59;
319 uint64_t pctl:5;
320 #else
321 uint64_t pctl:5;
322 uint64_t reserved_5_63:59;
323 #endif
324 } s;
325 };
326
327 union cvmx_asxx_rld_setting {
328 uint64_t u64;
329 struct cvmx_asxx_rld_setting_s {
330 #ifdef __BIG_ENDIAN_BITFIELD
331 uint64_t reserved_13_63:51;
332 uint64_t dfaset:5;
333 uint64_t dfalag:1;
334 uint64_t dfalead:1;
335 uint64_t dfalock:1;
336 uint64_t setting:5;
337 #else
338 uint64_t setting:5;
339 uint64_t dfalock:1;
340 uint64_t dfalead:1;
341 uint64_t dfalag:1;
342 uint64_t dfaset:5;
343 uint64_t reserved_13_63:51;
344 #endif
345 } s;
346 struct cvmx_asxx_rld_setting_cn38xx {
347 #ifdef __BIG_ENDIAN_BITFIELD
348 uint64_t reserved_5_63:59;
349 uint64_t setting:5;
350 #else
351 uint64_t setting:5;
352 uint64_t reserved_5_63:59;
353 #endif
354 } cn38xx;
355 };
356
357 union cvmx_asxx_rx_clk_setx {
358 uint64_t u64;
359 struct cvmx_asxx_rx_clk_setx_s {
360 #ifdef __BIG_ENDIAN_BITFIELD
361 uint64_t reserved_5_63:59;
362 uint64_t setting:5;
363 #else
364 uint64_t setting:5;
365 uint64_t reserved_5_63:59;
366 #endif
367 } s;
368 };
369
370 union cvmx_asxx_rx_prt_en {
371 uint64_t u64;
372 struct cvmx_asxx_rx_prt_en_s {
373 #ifdef __BIG_ENDIAN_BITFIELD
374 uint64_t reserved_4_63:60;
375 uint64_t prt_en:4;
376 #else
377 uint64_t prt_en:4;
378 uint64_t reserved_4_63:60;
379 #endif
380 } s;
381 struct cvmx_asxx_rx_prt_en_cn30xx {
382 #ifdef __BIG_ENDIAN_BITFIELD
383 uint64_t reserved_3_63:61;
384 uint64_t prt_en:3;
385 #else
386 uint64_t prt_en:3;
387 uint64_t reserved_3_63:61;
388 #endif
389 } cn30xx;
390 };
391
392 union cvmx_asxx_rx_wol {
393 uint64_t u64;
394 struct cvmx_asxx_rx_wol_s {
395 #ifdef __BIG_ENDIAN_BITFIELD
396 uint64_t reserved_2_63:62;
397 uint64_t status:1;
398 uint64_t enable:1;
399 #else
400 uint64_t enable:1;
401 uint64_t status:1;
402 uint64_t reserved_2_63:62;
403 #endif
404 } s;
405 };
406
407 union cvmx_asxx_rx_wol_msk {
408 uint64_t u64;
409 struct cvmx_asxx_rx_wol_msk_s {
410 #ifdef __BIG_ENDIAN_BITFIELD
411 uint64_t msk:64;
412 #else
413 uint64_t msk:64;
414 #endif
415 } s;
416 };
417
418 union cvmx_asxx_rx_wol_powok {
419 uint64_t u64;
420 struct cvmx_asxx_rx_wol_powok_s {
421 #ifdef __BIG_ENDIAN_BITFIELD
422 uint64_t reserved_1_63:63;
423 uint64_t powerok:1;
424 #else
425 uint64_t powerok:1;
426 uint64_t reserved_1_63:63;
427 #endif
428 } s;
429 };
430
431 union cvmx_asxx_rx_wol_sig {
432 uint64_t u64;
433 struct cvmx_asxx_rx_wol_sig_s {
434 #ifdef __BIG_ENDIAN_BITFIELD
435 uint64_t reserved_32_63:32;
436 uint64_t sig:32;
437 #else
438 uint64_t sig:32;
439 uint64_t reserved_32_63:32;
440 #endif
441 } s;
442 };
443
444 union cvmx_asxx_tx_clk_setx {
445 uint64_t u64;
446 struct cvmx_asxx_tx_clk_setx_s {
447 #ifdef __BIG_ENDIAN_BITFIELD
448 uint64_t reserved_5_63:59;
449 uint64_t setting:5;
450 #else
451 uint64_t setting:5;
452 uint64_t reserved_5_63:59;
453 #endif
454 } s;
455 };
456
457 union cvmx_asxx_tx_comp_byp {
458 uint64_t u64;
459 struct cvmx_asxx_tx_comp_byp_s {
460 #ifdef __BIG_ENDIAN_BITFIELD
461 uint64_t reserved_0_63:64;
462 #else
463 uint64_t reserved_0_63:64;
464 #endif
465 } s;
466 struct cvmx_asxx_tx_comp_byp_cn30xx {
467 #ifdef __BIG_ENDIAN_BITFIELD
468 uint64_t reserved_9_63:55;
469 uint64_t bypass:1;
470 uint64_t pctl:4;
471 uint64_t nctl:4;
472 #else
473 uint64_t nctl:4;
474 uint64_t pctl:4;
475 uint64_t bypass:1;
476 uint64_t reserved_9_63:55;
477 #endif
478 } cn30xx;
479 struct cvmx_asxx_tx_comp_byp_cn38xx {
480 #ifdef __BIG_ENDIAN_BITFIELD
481 uint64_t reserved_8_63:56;
482 uint64_t pctl:4;
483 uint64_t nctl:4;
484 #else
485 uint64_t nctl:4;
486 uint64_t pctl:4;
487 uint64_t reserved_8_63:56;
488 #endif
489 } cn38xx;
490 struct cvmx_asxx_tx_comp_byp_cn50xx {
491 #ifdef __BIG_ENDIAN_BITFIELD
492 uint64_t reserved_17_63:47;
493 uint64_t bypass:1;
494 uint64_t reserved_13_15:3;
495 uint64_t pctl:5;
496 uint64_t reserved_5_7:3;
497 uint64_t nctl:5;
498 #else
499 uint64_t nctl:5;
500 uint64_t reserved_5_7:3;
501 uint64_t pctl:5;
502 uint64_t reserved_13_15:3;
503 uint64_t bypass:1;
504 uint64_t reserved_17_63:47;
505 #endif
506 } cn50xx;
507 struct cvmx_asxx_tx_comp_byp_cn58xx {
508 #ifdef __BIG_ENDIAN_BITFIELD
509 uint64_t reserved_13_63:51;
510 uint64_t pctl:5;
511 uint64_t reserved_5_7:3;
512 uint64_t nctl:5;
513 #else
514 uint64_t nctl:5;
515 uint64_t reserved_5_7:3;
516 uint64_t pctl:5;
517 uint64_t reserved_13_63:51;
518 #endif
519 } cn58xx;
520 };
521
522 union cvmx_asxx_tx_hi_waterx {
523 uint64_t u64;
524 struct cvmx_asxx_tx_hi_waterx_s {
525 #ifdef __BIG_ENDIAN_BITFIELD
526 uint64_t reserved_4_63:60;
527 uint64_t mark:4;
528 #else
529 uint64_t mark:4;
530 uint64_t reserved_4_63:60;
531 #endif
532 } s;
533 struct cvmx_asxx_tx_hi_waterx_cn30xx {
534 #ifdef __BIG_ENDIAN_BITFIELD
535 uint64_t reserved_3_63:61;
536 uint64_t mark:3;
537 #else
538 uint64_t mark:3;
539 uint64_t reserved_3_63:61;
540 #endif
541 } cn30xx;
542 };
543
544 union cvmx_asxx_tx_prt_en {
545 uint64_t u64;
546 struct cvmx_asxx_tx_prt_en_s {
547 #ifdef __BIG_ENDIAN_BITFIELD
548 uint64_t reserved_4_63:60;
549 uint64_t prt_en:4;
550 #else
551 uint64_t prt_en:4;
552 uint64_t reserved_4_63:60;
553 #endif
554 } s;
555 struct cvmx_asxx_tx_prt_en_cn30xx {
556 #ifdef __BIG_ENDIAN_BITFIELD
557 uint64_t reserved_3_63:61;
558 uint64_t prt_en:3;
559 #else
560 uint64_t prt_en:3;
561 uint64_t reserved_3_63:61;
562 #endif
563 } cn30xx;
564 };
565
566 #endif