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28 #ifndef __CVMX_NPEI_DEFS_H__
29 #define __CVMX_NPEI_DEFS_H__
30
31 #define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16)
32 #define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull)
33 #define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull)
34 #define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull)
35 #define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull)
36 #define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull)
37 #define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull)
38 #define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull)
39 #define CVMX_NPEI_DBG_DATA (0x0000000000000510ull)
40 #define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull)
41 #define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull)
42 #define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull)
43 #define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16)
44 #define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16)
45 #define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16)
46 #define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16)
47 #define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull)
48 #define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull)
49 #define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull)
50 #define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull)
51 #define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull)
52 #define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull)
53 #define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull)
54 #define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull)
55 #define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull)
56 #define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull)
57 #define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull)
58 #define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull)
59 #define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull)
60 #define CVMX_NPEI_INT_ENB (0x0000000000000540ull)
61 #define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull)
62 #define CVMX_NPEI_INT_INFO (0x0000000000000590ull)
63 #define CVMX_NPEI_INT_SUM (0x0000000000000530ull)
64 #define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull)
65 #define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
66 #define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
67 #define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
68 #define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
69 #define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
70 #define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
71 #define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
72 #define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull)
73 #define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull)
74 #define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull)
75 #define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull)
76 #define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull)
77 #define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull)
78 #define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
79 #define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull)
80 #define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull)
81 #define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull)
82 #define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull)
83 #define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull)
84 #define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull)
85 #define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull)
86 #define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull)
87 #define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull)
88 #define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull)
89 #define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
90 #define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
91 #define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
92 #define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
93 #define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
94 #define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
95 #define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
96 #define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
97 #define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
98 #define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
99 #define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
100 #define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
101 #define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull)
102 #define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull)
103 #define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
104 #define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
105 #define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
106 #define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull)
107 #define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull)
108 #define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull)
109 #define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull)
110 #define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull)
111 #define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull)
112 #define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull)
113 #define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
114 #define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull)
115 #define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull)
116 #define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull)
117 #define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull)
118 #define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull)
119 #define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull)
120 #define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull)
121 #define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull)
122 #define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull)
123 #define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull)
124 #define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull)
125 #define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull)
126 #define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull)
127 #define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull)
128 #define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull)
129 #define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull)
130 #define CVMX_NPEI_STATE1 (0x0000000000000620ull)
131 #define CVMX_NPEI_STATE2 (0x0000000000000630ull)
132 #define CVMX_NPEI_STATE3 (0x0000000000000640ull)
133 #define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull)
134 #define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull)
135 #define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull)
136 #define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull)
137 #define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull)
138 #define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull)
139
140 union cvmx_npei_bar1_indexx {
141 uint32_t u32;
142 struct cvmx_npei_bar1_indexx_s {
143 #ifdef __BIG_ENDIAN_BITFIELD
144 uint32_t reserved_18_31:14;
145 uint32_t addr_idx:14;
146 uint32_t ca:1;
147 uint32_t end_swp:2;
148 uint32_t addr_v:1;
149 #else
150 uint32_t addr_v:1;
151 uint32_t end_swp:2;
152 uint32_t ca:1;
153 uint32_t addr_idx:14;
154 uint32_t reserved_18_31:14;
155 #endif
156 } s;
157 };
158
159 union cvmx_npei_bist_status {
160 uint64_t u64;
161 struct cvmx_npei_bist_status_s {
162 #ifdef __BIG_ENDIAN_BITFIELD
163 uint64_t pkt_rdf:1;
164 uint64_t reserved_60_62:3;
165 uint64_t pcr_gim:1;
166 uint64_t pkt_pif:1;
167 uint64_t pcsr_int:1;
168 uint64_t pcsr_im:1;
169 uint64_t pcsr_cnt:1;
170 uint64_t pcsr_id:1;
171 uint64_t pcsr_sl:1;
172 uint64_t reserved_50_52:3;
173 uint64_t pkt_ind:1;
174 uint64_t pkt_slm:1;
175 uint64_t reserved_36_47:12;
176 uint64_t d0_pst:1;
177 uint64_t d1_pst:1;
178 uint64_t d2_pst:1;
179 uint64_t d3_pst:1;
180 uint64_t reserved_31_31:1;
181 uint64_t n2p0_c:1;
182 uint64_t n2p0_o:1;
183 uint64_t n2p1_c:1;
184 uint64_t n2p1_o:1;
185 uint64_t cpl_p0:1;
186 uint64_t cpl_p1:1;
187 uint64_t p2n1_po:1;
188 uint64_t p2n1_no:1;
189 uint64_t p2n1_co:1;
190 uint64_t p2n0_po:1;
191 uint64_t p2n0_no:1;
192 uint64_t p2n0_co:1;
193 uint64_t p2n0_c0:1;
194 uint64_t p2n0_c1:1;
195 uint64_t p2n0_n:1;
196 uint64_t p2n0_p0:1;
197 uint64_t p2n0_p1:1;
198 uint64_t p2n1_c0:1;
199 uint64_t p2n1_c1:1;
200 uint64_t p2n1_n:1;
201 uint64_t p2n1_p0:1;
202 uint64_t p2n1_p1:1;
203 uint64_t csm0:1;
204 uint64_t csm1:1;
205 uint64_t dif0:1;
206 uint64_t dif1:1;
207 uint64_t dif2:1;
208 uint64_t dif3:1;
209 uint64_t reserved_2_2:1;
210 uint64_t msi:1;
211 uint64_t ncb_cmd:1;
212 #else
213 uint64_t ncb_cmd:1;
214 uint64_t msi:1;
215 uint64_t reserved_2_2:1;
216 uint64_t dif3:1;
217 uint64_t dif2:1;
218 uint64_t dif1:1;
219 uint64_t dif0:1;
220 uint64_t csm1:1;
221 uint64_t csm0:1;
222 uint64_t p2n1_p1:1;
223 uint64_t p2n1_p0:1;
224 uint64_t p2n1_n:1;
225 uint64_t p2n1_c1:1;
226 uint64_t p2n1_c0:1;
227 uint64_t p2n0_p1:1;
228 uint64_t p2n0_p0:1;
229 uint64_t p2n0_n:1;
230 uint64_t p2n0_c1:1;
231 uint64_t p2n0_c0:1;
232 uint64_t p2n0_co:1;
233 uint64_t p2n0_no:1;
234 uint64_t p2n0_po:1;
235 uint64_t p2n1_co:1;
236 uint64_t p2n1_no:1;
237 uint64_t p2n1_po:1;
238 uint64_t cpl_p1:1;
239 uint64_t cpl_p0:1;
240 uint64_t n2p1_o:1;
241 uint64_t n2p1_c:1;
242 uint64_t n2p0_o:1;
243 uint64_t n2p0_c:1;
244 uint64_t reserved_31_31:1;
245 uint64_t d3_pst:1;
246 uint64_t d2_pst:1;
247 uint64_t d1_pst:1;
248 uint64_t d0_pst:1;
249 uint64_t reserved_36_47:12;
250 uint64_t pkt_slm:1;
251 uint64_t pkt_ind:1;
252 uint64_t reserved_50_52:3;
253 uint64_t pcsr_sl:1;
254 uint64_t pcsr_id:1;
255 uint64_t pcsr_cnt:1;
256 uint64_t pcsr_im:1;
257 uint64_t pcsr_int:1;
258 uint64_t pkt_pif:1;
259 uint64_t pcr_gim:1;
260 uint64_t reserved_60_62:3;
261 uint64_t pkt_rdf:1;
262 #endif
263 } s;
264 struct cvmx_npei_bist_status_cn52xx {
265 #ifdef __BIG_ENDIAN_BITFIELD
266 uint64_t pkt_rdf:1;
267 uint64_t reserved_60_62:3;
268 uint64_t pcr_gim:1;
269 uint64_t pkt_pif:1;
270 uint64_t pcsr_int:1;
271 uint64_t pcsr_im:1;
272 uint64_t pcsr_cnt:1;
273 uint64_t pcsr_id:1;
274 uint64_t pcsr_sl:1;
275 uint64_t pkt_imem:1;
276 uint64_t pkt_pfm:1;
277 uint64_t pkt_pof:1;
278 uint64_t reserved_48_49:2;
279 uint64_t pkt_pop0:1;
280 uint64_t pkt_pop1:1;
281 uint64_t d0_mem:1;
282 uint64_t d1_mem:1;
283 uint64_t d2_mem:1;
284 uint64_t d3_mem:1;
285 uint64_t d4_mem:1;
286 uint64_t ds_mem:1;
287 uint64_t reserved_36_39:4;
288 uint64_t d0_pst:1;
289 uint64_t d1_pst:1;
290 uint64_t d2_pst:1;
291 uint64_t d3_pst:1;
292 uint64_t d4_pst:1;
293 uint64_t n2p0_c:1;
294 uint64_t n2p0_o:1;
295 uint64_t n2p1_c:1;
296 uint64_t n2p1_o:1;
297 uint64_t cpl_p0:1;
298 uint64_t cpl_p1:1;
299 uint64_t p2n1_po:1;
300 uint64_t p2n1_no:1;
301 uint64_t p2n1_co:1;
302 uint64_t p2n0_po:1;
303 uint64_t p2n0_no:1;
304 uint64_t p2n0_co:1;
305 uint64_t p2n0_c0:1;
306 uint64_t p2n0_c1:1;
307 uint64_t p2n0_n:1;
308 uint64_t p2n0_p0:1;
309 uint64_t p2n0_p1:1;
310 uint64_t p2n1_c0:1;
311 uint64_t p2n1_c1:1;
312 uint64_t p2n1_n:1;
313 uint64_t p2n1_p0:1;
314 uint64_t p2n1_p1:1;
315 uint64_t csm0:1;
316 uint64_t csm1:1;
317 uint64_t dif0:1;
318 uint64_t dif1:1;
319 uint64_t dif2:1;
320 uint64_t dif3:1;
321 uint64_t dif4:1;
322 uint64_t msi:1;
323 uint64_t ncb_cmd:1;
324 #else
325 uint64_t ncb_cmd:1;
326 uint64_t msi:1;
327 uint64_t dif4:1;
328 uint64_t dif3:1;
329 uint64_t dif2:1;
330 uint64_t dif1:1;
331 uint64_t dif0:1;
332 uint64_t csm1:1;
333 uint64_t csm0:1;
334 uint64_t p2n1_p1:1;
335 uint64_t p2n1_p0:1;
336 uint64_t p2n1_n:1;
337 uint64_t p2n1_c1:1;
338 uint64_t p2n1_c0:1;
339 uint64_t p2n0_p1:1;
340 uint64_t p2n0_p0:1;
341 uint64_t p2n0_n:1;
342 uint64_t p2n0_c1:1;
343 uint64_t p2n0_c0:1;
344 uint64_t p2n0_co:1;
345 uint64_t p2n0_no:1;
346 uint64_t p2n0_po:1;
347 uint64_t p2n1_co:1;
348 uint64_t p2n1_no:1;
349 uint64_t p2n1_po:1;
350 uint64_t cpl_p1:1;
351 uint64_t cpl_p0:1;
352 uint64_t n2p1_o:1;
353 uint64_t n2p1_c:1;
354 uint64_t n2p0_o:1;
355 uint64_t n2p0_c:1;
356 uint64_t d4_pst:1;
357 uint64_t d3_pst:1;
358 uint64_t d2_pst:1;
359 uint64_t d1_pst:1;
360 uint64_t d0_pst:1;
361 uint64_t reserved_36_39:4;
362 uint64_t ds_mem:1;
363 uint64_t d4_mem:1;
364 uint64_t d3_mem:1;
365 uint64_t d2_mem:1;
366 uint64_t d1_mem:1;
367 uint64_t d0_mem:1;
368 uint64_t pkt_pop1:1;
369 uint64_t pkt_pop0:1;
370 uint64_t reserved_48_49:2;
371 uint64_t pkt_pof:1;
372 uint64_t pkt_pfm:1;
373 uint64_t pkt_imem:1;
374 uint64_t pcsr_sl:1;
375 uint64_t pcsr_id:1;
376 uint64_t pcsr_cnt:1;
377 uint64_t pcsr_im:1;
378 uint64_t pcsr_int:1;
379 uint64_t pkt_pif:1;
380 uint64_t pcr_gim:1;
381 uint64_t reserved_60_62:3;
382 uint64_t pkt_rdf:1;
383 #endif
384 } cn52xx;
385 struct cvmx_npei_bist_status_cn52xxp1 {
386 #ifdef __BIG_ENDIAN_BITFIELD
387 uint64_t reserved_46_63:18;
388 uint64_t d0_mem0:1;
389 uint64_t d1_mem1:1;
390 uint64_t d2_mem2:1;
391 uint64_t d3_mem3:1;
392 uint64_t dr0_mem:1;
393 uint64_t d0_mem:1;
394 uint64_t d1_mem:1;
395 uint64_t d2_mem:1;
396 uint64_t d3_mem:1;
397 uint64_t dr1_mem:1;
398 uint64_t d0_pst:1;
399 uint64_t d1_pst:1;
400 uint64_t d2_pst:1;
401 uint64_t d3_pst:1;
402 uint64_t dr2_mem:1;
403 uint64_t n2p0_c:1;
404 uint64_t n2p0_o:1;
405 uint64_t n2p1_c:1;
406 uint64_t n2p1_o:1;
407 uint64_t cpl_p0:1;
408 uint64_t cpl_p1:1;
409 uint64_t p2n1_po:1;
410 uint64_t p2n1_no:1;
411 uint64_t p2n1_co:1;
412 uint64_t p2n0_po:1;
413 uint64_t p2n0_no:1;
414 uint64_t p2n0_co:1;
415 uint64_t p2n0_c0:1;
416 uint64_t p2n0_c1:1;
417 uint64_t p2n0_n:1;
418 uint64_t p2n0_p0:1;
419 uint64_t p2n0_p1:1;
420 uint64_t p2n1_c0:1;
421 uint64_t p2n1_c1:1;
422 uint64_t p2n1_n:1;
423 uint64_t p2n1_p0:1;
424 uint64_t p2n1_p1:1;
425 uint64_t csm0:1;
426 uint64_t csm1:1;
427 uint64_t dif0:1;
428 uint64_t dif1:1;
429 uint64_t dif2:1;
430 uint64_t dif3:1;
431 uint64_t dr3_mem:1;
432 uint64_t msi:1;
433 uint64_t ncb_cmd:1;
434 #else
435 uint64_t ncb_cmd:1;
436 uint64_t msi:1;
437 uint64_t dr3_mem:1;
438 uint64_t dif3:1;
439 uint64_t dif2:1;
440 uint64_t dif1:1;
441 uint64_t dif0:1;
442 uint64_t csm1:1;
443 uint64_t csm0:1;
444 uint64_t p2n1_p1:1;
445 uint64_t p2n1_p0:1;
446 uint64_t p2n1_n:1;
447 uint64_t p2n1_c1:1;
448 uint64_t p2n1_c0:1;
449 uint64_t p2n0_p1:1;
450 uint64_t p2n0_p0:1;
451 uint64_t p2n0_n:1;
452 uint64_t p2n0_c1:1;
453 uint64_t p2n0_c0:1;
454 uint64_t p2n0_co:1;
455 uint64_t p2n0_no:1;
456 uint64_t p2n0_po:1;
457 uint64_t p2n1_co:1;
458 uint64_t p2n1_no:1;
459 uint64_t p2n1_po:1;
460 uint64_t cpl_p1:1;
461 uint64_t cpl_p0:1;
462 uint64_t n2p1_o:1;
463 uint64_t n2p1_c:1;
464 uint64_t n2p0_o:1;
465 uint64_t n2p0_c:1;
466 uint64_t dr2_mem:1;
467 uint64_t d3_pst:1;
468 uint64_t d2_pst:1;
469 uint64_t d1_pst:1;
470 uint64_t d0_pst:1;
471 uint64_t dr1_mem:1;
472 uint64_t d3_mem:1;
473 uint64_t d2_mem:1;
474 uint64_t d1_mem:1;
475 uint64_t d0_mem:1;
476 uint64_t dr0_mem:1;
477 uint64_t d3_mem3:1;
478 uint64_t d2_mem2:1;
479 uint64_t d1_mem1:1;
480 uint64_t d0_mem0:1;
481 uint64_t reserved_46_63:18;
482 #endif
483 } cn52xxp1;
484 struct cvmx_npei_bist_status_cn56xxp1 {
485 #ifdef __BIG_ENDIAN_BITFIELD
486 uint64_t reserved_58_63:6;
487 uint64_t pcsr_int:1;
488 uint64_t pcsr_im:1;
489 uint64_t pcsr_cnt:1;
490 uint64_t pcsr_id:1;
491 uint64_t pcsr_sl:1;
492 uint64_t pkt_pout:1;
493 uint64_t pkt_imem:1;
494 uint64_t pkt_cntm:1;
495 uint64_t pkt_ind:1;
496 uint64_t pkt_slm:1;
497 uint64_t pkt_odf:1;
498 uint64_t pkt_oif:1;
499 uint64_t pkt_out:1;
500 uint64_t pkt_i0:1;
501 uint64_t pkt_i1:1;
502 uint64_t pkt_s0:1;
503 uint64_t pkt_s1:1;
504 uint64_t d0_mem:1;
505 uint64_t d1_mem:1;
506 uint64_t d2_mem:1;
507 uint64_t d3_mem:1;
508 uint64_t d4_mem:1;
509 uint64_t d0_pst:1;
510 uint64_t d1_pst:1;
511 uint64_t d2_pst:1;
512 uint64_t d3_pst:1;
513 uint64_t d4_pst:1;
514 uint64_t n2p0_c:1;
515 uint64_t n2p0_o:1;
516 uint64_t n2p1_c:1;
517 uint64_t n2p1_o:1;
518 uint64_t cpl_p0:1;
519 uint64_t cpl_p1:1;
520 uint64_t p2n1_po:1;
521 uint64_t p2n1_no:1;
522 uint64_t p2n1_co:1;
523 uint64_t p2n0_po:1;
524 uint64_t p2n0_no:1;
525 uint64_t p2n0_co:1;
526 uint64_t p2n0_c0:1;
527 uint64_t p2n0_c1:1;
528 uint64_t p2n0_n:1;
529 uint64_t p2n0_p0:1;
530 uint64_t p2n0_p1:1;
531 uint64_t p2n1_c0:1;
532 uint64_t p2n1_c1:1;
533 uint64_t p2n1_n:1;
534 uint64_t p2n1_p0:1;
535 uint64_t p2n1_p1:1;
536 uint64_t csm0:1;
537 uint64_t csm1:1;
538 uint64_t dif0:1;
539 uint64_t dif1:1;
540 uint64_t dif2:1;
541 uint64_t dif3:1;
542 uint64_t dif4:1;
543 uint64_t msi:1;
544 uint64_t ncb_cmd:1;
545 #else
546 uint64_t ncb_cmd:1;
547 uint64_t msi:1;
548 uint64_t dif4:1;
549 uint64_t dif3:1;
550 uint64_t dif2:1;
551 uint64_t dif1:1;
552 uint64_t dif0:1;
553 uint64_t csm1:1;
554 uint64_t csm0:1;
555 uint64_t p2n1_p1:1;
556 uint64_t p2n1_p0:1;
557 uint64_t p2n1_n:1;
558 uint64_t p2n1_c1:1;
559 uint64_t p2n1_c0:1;
560 uint64_t p2n0_p1:1;
561 uint64_t p2n0_p0:1;
562 uint64_t p2n0_n:1;
563 uint64_t p2n0_c1:1;
564 uint64_t p2n0_c0:1;
565 uint64_t p2n0_co:1;
566 uint64_t p2n0_no:1;
567 uint64_t p2n0_po:1;
568 uint64_t p2n1_co:1;
569 uint64_t p2n1_no:1;
570 uint64_t p2n1_po:1;
571 uint64_t cpl_p1:1;
572 uint64_t cpl_p0:1;
573 uint64_t n2p1_o:1;
574 uint64_t n2p1_c:1;
575 uint64_t n2p0_o:1;
576 uint64_t n2p0_c:1;
577 uint64_t d4_pst:1;
578 uint64_t d3_pst:1;
579 uint64_t d2_pst:1;
580 uint64_t d1_pst:1;
581 uint64_t d0_pst:1;
582 uint64_t d4_mem:1;
583 uint64_t d3_mem:1;
584 uint64_t d2_mem:1;
585 uint64_t d1_mem:1;
586 uint64_t d0_mem:1;
587 uint64_t pkt_s1:1;
588 uint64_t pkt_s0:1;
589 uint64_t pkt_i1:1;
590 uint64_t pkt_i0:1;
591 uint64_t pkt_out:1;
592 uint64_t pkt_oif:1;
593 uint64_t pkt_odf:1;
594 uint64_t pkt_slm:1;
595 uint64_t pkt_ind:1;
596 uint64_t pkt_cntm:1;
597 uint64_t pkt_imem:1;
598 uint64_t pkt_pout:1;
599 uint64_t pcsr_sl:1;
600 uint64_t pcsr_id:1;
601 uint64_t pcsr_cnt:1;
602 uint64_t pcsr_im:1;
603 uint64_t pcsr_int:1;
604 uint64_t reserved_58_63:6;
605 #endif
606 } cn56xxp1;
607 };
608
609 union cvmx_npei_bist_status2 {
610 uint64_t u64;
611 struct cvmx_npei_bist_status2_s {
612 #ifdef __BIG_ENDIAN_BITFIELD
613 uint64_t reserved_14_63:50;
614 uint64_t prd_tag:1;
615 uint64_t prd_st0:1;
616 uint64_t prd_st1:1;
617 uint64_t prd_err:1;
618 uint64_t nrd_st:1;
619 uint64_t nwe_st:1;
620 uint64_t nwe_wr0:1;
621 uint64_t nwe_wr1:1;
622 uint64_t pkt_rd:1;
623 uint64_t psc_p0:1;
624 uint64_t psc_p1:1;
625 uint64_t pkt_gd:1;
626 uint64_t pkt_gl:1;
627 uint64_t pkt_blk:1;
628 #else
629 uint64_t pkt_blk:1;
630 uint64_t pkt_gl:1;
631 uint64_t pkt_gd:1;
632 uint64_t psc_p1:1;
633 uint64_t psc_p0:1;
634 uint64_t pkt_rd:1;
635 uint64_t nwe_wr1:1;
636 uint64_t nwe_wr0:1;
637 uint64_t nwe_st:1;
638 uint64_t nrd_st:1;
639 uint64_t prd_err:1;
640 uint64_t prd_st1:1;
641 uint64_t prd_st0:1;
642 uint64_t prd_tag:1;
643 uint64_t reserved_14_63:50;
644 #endif
645 } s;
646 };
647
648 union cvmx_npei_ctl_port0 {
649 uint64_t u64;
650 struct cvmx_npei_ctl_port0_s {
651 #ifdef __BIG_ENDIAN_BITFIELD
652 uint64_t reserved_21_63:43;
653 uint64_t waitl_com:1;
654 uint64_t intd:1;
655 uint64_t intc:1;
656 uint64_t intb:1;
657 uint64_t inta:1;
658 uint64_t intd_map:2;
659 uint64_t intc_map:2;
660 uint64_t intb_map:2;
661 uint64_t inta_map:2;
662 uint64_t ctlp_ro:1;
663 uint64_t reserved_6_6:1;
664 uint64_t ptlp_ro:1;
665 uint64_t bar2_enb:1;
666 uint64_t bar2_esx:2;
667 uint64_t bar2_cax:1;
668 uint64_t wait_com:1;
669 #else
670 uint64_t wait_com:1;
671 uint64_t bar2_cax:1;
672 uint64_t bar2_esx:2;
673 uint64_t bar2_enb:1;
674 uint64_t ptlp_ro:1;
675 uint64_t reserved_6_6:1;
676 uint64_t ctlp_ro:1;
677 uint64_t inta_map:2;
678 uint64_t intb_map:2;
679 uint64_t intc_map:2;
680 uint64_t intd_map:2;
681 uint64_t inta:1;
682 uint64_t intb:1;
683 uint64_t intc:1;
684 uint64_t intd:1;
685 uint64_t waitl_com:1;
686 uint64_t reserved_21_63:43;
687 #endif
688 } s;
689 };
690
691 union cvmx_npei_ctl_port1 {
692 uint64_t u64;
693 struct cvmx_npei_ctl_port1_s {
694 #ifdef __BIG_ENDIAN_BITFIELD
695 uint64_t reserved_21_63:43;
696 uint64_t waitl_com:1;
697 uint64_t intd:1;
698 uint64_t intc:1;
699 uint64_t intb:1;
700 uint64_t inta:1;
701 uint64_t intd_map:2;
702 uint64_t intc_map:2;
703 uint64_t intb_map:2;
704 uint64_t inta_map:2;
705 uint64_t ctlp_ro:1;
706 uint64_t reserved_6_6:1;
707 uint64_t ptlp_ro:1;
708 uint64_t bar2_enb:1;
709 uint64_t bar2_esx:2;
710 uint64_t bar2_cax:1;
711 uint64_t wait_com:1;
712 #else
713 uint64_t wait_com:1;
714 uint64_t bar2_cax:1;
715 uint64_t bar2_esx:2;
716 uint64_t bar2_enb:1;
717 uint64_t ptlp_ro:1;
718 uint64_t reserved_6_6:1;
719 uint64_t ctlp_ro:1;
720 uint64_t inta_map:2;
721 uint64_t intb_map:2;
722 uint64_t intc_map:2;
723 uint64_t intd_map:2;
724 uint64_t inta:1;
725 uint64_t intb:1;
726 uint64_t intc:1;
727 uint64_t intd:1;
728 uint64_t waitl_com:1;
729 uint64_t reserved_21_63:43;
730 #endif
731 } s;
732 };
733
734 union cvmx_npei_ctl_status {
735 uint64_t u64;
736 struct cvmx_npei_ctl_status_s {
737 #ifdef __BIG_ENDIAN_BITFIELD
738 uint64_t reserved_44_63:20;
739 uint64_t p1_ntags:6;
740 uint64_t p0_ntags:6;
741 uint64_t cfg_rtry:16;
742 uint64_t ring_en:1;
743 uint64_t lnk_rst:1;
744 uint64_t arb:1;
745 uint64_t pkt_bp:4;
746 uint64_t host_mode:1;
747 uint64_t chip_rev:8;
748 #else
749 uint64_t chip_rev:8;
750 uint64_t host_mode:1;
751 uint64_t pkt_bp:4;
752 uint64_t arb:1;
753 uint64_t lnk_rst:1;
754 uint64_t ring_en:1;
755 uint64_t cfg_rtry:16;
756 uint64_t p0_ntags:6;
757 uint64_t p1_ntags:6;
758 uint64_t reserved_44_63:20;
759 #endif
760 } s;
761 struct cvmx_npei_ctl_status_cn52xxp1 {
762 #ifdef __BIG_ENDIAN_BITFIELD
763 uint64_t reserved_44_63:20;
764 uint64_t p1_ntags:6;
765 uint64_t p0_ntags:6;
766 uint64_t cfg_rtry:16;
767 uint64_t reserved_15_15:1;
768 uint64_t lnk_rst:1;
769 uint64_t arb:1;
770 uint64_t reserved_9_12:4;
771 uint64_t host_mode:1;
772 uint64_t chip_rev:8;
773 #else
774 uint64_t chip_rev:8;
775 uint64_t host_mode:1;
776 uint64_t reserved_9_12:4;
777 uint64_t arb:1;
778 uint64_t lnk_rst:1;
779 uint64_t reserved_15_15:1;
780 uint64_t cfg_rtry:16;
781 uint64_t p0_ntags:6;
782 uint64_t p1_ntags:6;
783 uint64_t reserved_44_63:20;
784 #endif
785 } cn52xxp1;
786 struct cvmx_npei_ctl_status_cn56xxp1 {
787 #ifdef __BIG_ENDIAN_BITFIELD
788 uint64_t reserved_15_63:49;
789 uint64_t lnk_rst:1;
790 uint64_t arb:1;
791 uint64_t pkt_bp:4;
792 uint64_t host_mode:1;
793 uint64_t chip_rev:8;
794 #else
795 uint64_t chip_rev:8;
796 uint64_t host_mode:1;
797 uint64_t pkt_bp:4;
798 uint64_t arb:1;
799 uint64_t lnk_rst:1;
800 uint64_t reserved_15_63:49;
801 #endif
802 } cn56xxp1;
803 };
804
805 union cvmx_npei_ctl_status2 {
806 uint64_t u64;
807 struct cvmx_npei_ctl_status2_s {
808 #ifdef __BIG_ENDIAN_BITFIELD
809 uint64_t reserved_16_63:48;
810 uint64_t mps:1;
811 uint64_t mrrs:3;
812 uint64_t c1_w_flt:1;
813 uint64_t c0_w_flt:1;
814 uint64_t c1_b1_s:3;
815 uint64_t c0_b1_s:3;
816 uint64_t c1_wi_d:1;
817 uint64_t c1_b0_d:1;
818 uint64_t c0_wi_d:1;
819 uint64_t c0_b0_d:1;
820 #else
821 uint64_t c0_b0_d:1;
822 uint64_t c0_wi_d:1;
823 uint64_t c1_b0_d:1;
824 uint64_t c1_wi_d:1;
825 uint64_t c0_b1_s:3;
826 uint64_t c1_b1_s:3;
827 uint64_t c0_w_flt:1;
828 uint64_t c1_w_flt:1;
829 uint64_t mrrs:3;
830 uint64_t mps:1;
831 uint64_t reserved_16_63:48;
832 #endif
833 } s;
834 };
835
836 union cvmx_npei_data_out_cnt {
837 uint64_t u64;
838 struct cvmx_npei_data_out_cnt_s {
839 #ifdef __BIG_ENDIAN_BITFIELD
840 uint64_t reserved_44_63:20;
841 uint64_t p1_ucnt:16;
842 uint64_t p1_fcnt:6;
843 uint64_t p0_ucnt:16;
844 uint64_t p0_fcnt:6;
845 #else
846 uint64_t p0_fcnt:6;
847 uint64_t p0_ucnt:16;
848 uint64_t p1_fcnt:6;
849 uint64_t p1_ucnt:16;
850 uint64_t reserved_44_63:20;
851 #endif
852 } s;
853 };
854
855 union cvmx_npei_dbg_data {
856 uint64_t u64;
857 struct cvmx_npei_dbg_data_s {
858 #ifdef __BIG_ENDIAN_BITFIELD
859 uint64_t reserved_28_63:36;
860 uint64_t qlm0_rev_lanes:1;
861 uint64_t reserved_25_26:2;
862 uint64_t qlm1_spd:2;
863 uint64_t c_mul:5;
864 uint64_t dsel_ext:1;
865 uint64_t data:17;
866 #else
867 uint64_t data:17;
868 uint64_t dsel_ext:1;
869 uint64_t c_mul:5;
870 uint64_t qlm1_spd:2;
871 uint64_t reserved_25_26:2;
872 uint64_t qlm0_rev_lanes:1;
873 uint64_t reserved_28_63:36;
874 #endif
875 } s;
876 struct cvmx_npei_dbg_data_cn52xx {
877 #ifdef __BIG_ENDIAN_BITFIELD
878 uint64_t reserved_29_63:35;
879 uint64_t qlm0_link_width:1;
880 uint64_t qlm0_rev_lanes:1;
881 uint64_t qlm1_mode:2;
882 uint64_t qlm1_spd:2;
883 uint64_t c_mul:5;
884 uint64_t dsel_ext:1;
885 uint64_t data:17;
886 #else
887 uint64_t data:17;
888 uint64_t dsel_ext:1;
889 uint64_t c_mul:5;
890 uint64_t qlm1_spd:2;
891 uint64_t qlm1_mode:2;
892 uint64_t qlm0_rev_lanes:1;
893 uint64_t qlm0_link_width:1;
894 uint64_t reserved_29_63:35;
895 #endif
896 } cn52xx;
897 struct cvmx_npei_dbg_data_cn56xx {
898 #ifdef __BIG_ENDIAN_BITFIELD
899 uint64_t reserved_29_63:35;
900 uint64_t qlm2_rev_lanes:1;
901 uint64_t qlm0_rev_lanes:1;
902 uint64_t qlm3_spd:2;
903 uint64_t qlm1_spd:2;
904 uint64_t c_mul:5;
905 uint64_t dsel_ext:1;
906 uint64_t data:17;
907 #else
908 uint64_t data:17;
909 uint64_t dsel_ext:1;
910 uint64_t c_mul:5;
911 uint64_t qlm1_spd:2;
912 uint64_t qlm3_spd:2;
913 uint64_t qlm0_rev_lanes:1;
914 uint64_t qlm2_rev_lanes:1;
915 uint64_t reserved_29_63:35;
916 #endif
917 } cn56xx;
918 };
919
920 union cvmx_npei_dbg_select {
921 uint64_t u64;
922 struct cvmx_npei_dbg_select_s {
923 #ifdef __BIG_ENDIAN_BITFIELD
924 uint64_t reserved_16_63:48;
925 uint64_t dbg_sel:16;
926 #else
927 uint64_t dbg_sel:16;
928 uint64_t reserved_16_63:48;
929 #endif
930 } s;
931 };
932
933 union cvmx_npei_dmax_counts {
934 uint64_t u64;
935 struct cvmx_npei_dmax_counts_s {
936 #ifdef __BIG_ENDIAN_BITFIELD
937 uint64_t reserved_39_63:25;
938 uint64_t fcnt:7;
939 uint64_t dbell:32;
940 #else
941 uint64_t dbell:32;
942 uint64_t fcnt:7;
943 uint64_t reserved_39_63:25;
944 #endif
945 } s;
946 };
947
948 union cvmx_npei_dmax_dbell {
949 uint32_t u32;
950 struct cvmx_npei_dmax_dbell_s {
951 #ifdef __BIG_ENDIAN_BITFIELD
952 uint32_t reserved_16_31:16;
953 uint32_t dbell:16;
954 #else
955 uint32_t dbell:16;
956 uint32_t reserved_16_31:16;
957 #endif
958 } s;
959 };
960
961 union cvmx_npei_dmax_ibuff_saddr {
962 uint64_t u64;
963 struct cvmx_npei_dmax_ibuff_saddr_s {
964 #ifdef __BIG_ENDIAN_BITFIELD
965 uint64_t reserved_37_63:27;
966 uint64_t idle:1;
967 uint64_t saddr:29;
968 uint64_t reserved_0_6:7;
969 #else
970 uint64_t reserved_0_6:7;
971 uint64_t saddr:29;
972 uint64_t idle:1;
973 uint64_t reserved_37_63:27;
974 #endif
975 } s;
976 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
977 #ifdef __BIG_ENDIAN_BITFIELD
978 uint64_t reserved_36_63:28;
979 uint64_t saddr:29;
980 uint64_t reserved_0_6:7;
981 #else
982 uint64_t reserved_0_6:7;
983 uint64_t saddr:29;
984 uint64_t reserved_36_63:28;
985 #endif
986 } cn52xxp1;
987 };
988
989 union cvmx_npei_dmax_naddr {
990 uint64_t u64;
991 struct cvmx_npei_dmax_naddr_s {
992 #ifdef __BIG_ENDIAN_BITFIELD
993 uint64_t reserved_36_63:28;
994 uint64_t addr:36;
995 #else
996 uint64_t addr:36;
997 uint64_t reserved_36_63:28;
998 #endif
999 } s;
1000 };
1001
1002 union cvmx_npei_dma0_int_level {
1003 uint64_t u64;
1004 struct cvmx_npei_dma0_int_level_s {
1005 #ifdef __BIG_ENDIAN_BITFIELD
1006 uint64_t time:32;
1007 uint64_t cnt:32;
1008 #else
1009 uint64_t cnt:32;
1010 uint64_t time:32;
1011 #endif
1012 } s;
1013 };
1014
1015 union cvmx_npei_dma1_int_level {
1016 uint64_t u64;
1017 struct cvmx_npei_dma1_int_level_s {
1018 #ifdef __BIG_ENDIAN_BITFIELD
1019 uint64_t time:32;
1020 uint64_t cnt:32;
1021 #else
1022 uint64_t cnt:32;
1023 uint64_t time:32;
1024 #endif
1025 } s;
1026 };
1027
1028 union cvmx_npei_dma_cnts {
1029 uint64_t u64;
1030 struct cvmx_npei_dma_cnts_s {
1031 #ifdef __BIG_ENDIAN_BITFIELD
1032 uint64_t dma1:32;
1033 uint64_t dma0:32;
1034 #else
1035 uint64_t dma0:32;
1036 uint64_t dma1:32;
1037 #endif
1038 } s;
1039 };
1040
1041 union cvmx_npei_dma_control {
1042 uint64_t u64;
1043 struct cvmx_npei_dma_control_s {
1044 #ifdef __BIG_ENDIAN_BITFIELD
1045 uint64_t reserved_40_63:24;
1046 uint64_t p_32b_m:1;
1047 uint64_t dma4_enb:1;
1048 uint64_t dma3_enb:1;
1049 uint64_t dma2_enb:1;
1050 uint64_t dma1_enb:1;
1051 uint64_t dma0_enb:1;
1052 uint64_t b0_lend:1;
1053 uint64_t dwb_denb:1;
1054 uint64_t dwb_ichk:9;
1055 uint64_t fpa_que:3;
1056 uint64_t o_add1:1;
1057 uint64_t o_ro:1;
1058 uint64_t o_ns:1;
1059 uint64_t o_es:2;
1060 uint64_t o_mode:1;
1061 uint64_t csize:14;
1062 #else
1063 uint64_t csize:14;
1064 uint64_t o_mode:1;
1065 uint64_t o_es:2;
1066 uint64_t o_ns:1;
1067 uint64_t o_ro:1;
1068 uint64_t o_add1:1;
1069 uint64_t fpa_que:3;
1070 uint64_t dwb_ichk:9;
1071 uint64_t dwb_denb:1;
1072 uint64_t b0_lend:1;
1073 uint64_t dma0_enb:1;
1074 uint64_t dma1_enb:1;
1075 uint64_t dma2_enb:1;
1076 uint64_t dma3_enb:1;
1077 uint64_t dma4_enb:1;
1078 uint64_t p_32b_m:1;
1079 uint64_t reserved_40_63:24;
1080 #endif
1081 } s;
1082 struct cvmx_npei_dma_control_cn52xxp1 {
1083 #ifdef __BIG_ENDIAN_BITFIELD
1084 uint64_t reserved_38_63:26;
1085 uint64_t dma3_enb:1;
1086 uint64_t dma2_enb:1;
1087 uint64_t dma1_enb:1;
1088 uint64_t dma0_enb:1;
1089 uint64_t b0_lend:1;
1090 uint64_t dwb_denb:1;
1091 uint64_t dwb_ichk:9;
1092 uint64_t fpa_que:3;
1093 uint64_t o_add1:1;
1094 uint64_t o_ro:1;
1095 uint64_t o_ns:1;
1096 uint64_t o_es:2;
1097 uint64_t o_mode:1;
1098 uint64_t csize:14;
1099 #else
1100 uint64_t csize:14;
1101 uint64_t o_mode:1;
1102 uint64_t o_es:2;
1103 uint64_t o_ns:1;
1104 uint64_t o_ro:1;
1105 uint64_t o_add1:1;
1106 uint64_t fpa_que:3;
1107 uint64_t dwb_ichk:9;
1108 uint64_t dwb_denb:1;
1109 uint64_t b0_lend:1;
1110 uint64_t dma0_enb:1;
1111 uint64_t dma1_enb:1;
1112 uint64_t dma2_enb:1;
1113 uint64_t dma3_enb:1;
1114 uint64_t reserved_38_63:26;
1115 #endif
1116 } cn52xxp1;
1117 struct cvmx_npei_dma_control_cn56xxp1 {
1118 #ifdef __BIG_ENDIAN_BITFIELD
1119 uint64_t reserved_39_63:25;
1120 uint64_t dma4_enb:1;
1121 uint64_t dma3_enb:1;
1122 uint64_t dma2_enb:1;
1123 uint64_t dma1_enb:1;
1124 uint64_t dma0_enb:1;
1125 uint64_t b0_lend:1;
1126 uint64_t dwb_denb:1;
1127 uint64_t dwb_ichk:9;
1128 uint64_t fpa_que:3;
1129 uint64_t o_add1:1;
1130 uint64_t o_ro:1;
1131 uint64_t o_ns:1;
1132 uint64_t o_es:2;
1133 uint64_t o_mode:1;
1134 uint64_t csize:14;
1135 #else
1136 uint64_t csize:14;
1137 uint64_t o_mode:1;
1138 uint64_t o_es:2;
1139 uint64_t o_ns:1;
1140 uint64_t o_ro:1;
1141 uint64_t o_add1:1;
1142 uint64_t fpa_que:3;
1143 uint64_t dwb_ichk:9;
1144 uint64_t dwb_denb:1;
1145 uint64_t b0_lend:1;
1146 uint64_t dma0_enb:1;
1147 uint64_t dma1_enb:1;
1148 uint64_t dma2_enb:1;
1149 uint64_t dma3_enb:1;
1150 uint64_t dma4_enb:1;
1151 uint64_t reserved_39_63:25;
1152 #endif
1153 } cn56xxp1;
1154 };
1155
1156 union cvmx_npei_dma_pcie_req_num {
1157 uint64_t u64;
1158 struct cvmx_npei_dma_pcie_req_num_s {
1159 #ifdef __BIG_ENDIAN_BITFIELD
1160 uint64_t dma_arb:1;
1161 uint64_t reserved_53_62:10;
1162 uint64_t pkt_cnt:5;
1163 uint64_t reserved_45_47:3;
1164 uint64_t dma4_cnt:5;
1165 uint64_t reserved_37_39:3;
1166 uint64_t dma3_cnt:5;
1167 uint64_t reserved_29_31:3;
1168 uint64_t dma2_cnt:5;
1169 uint64_t reserved_21_23:3;
1170 uint64_t dma1_cnt:5;
1171 uint64_t reserved_13_15:3;
1172 uint64_t dma0_cnt:5;
1173 uint64_t reserved_5_7:3;
1174 uint64_t dma_cnt:5;
1175 #else
1176 uint64_t dma_cnt:5;
1177 uint64_t reserved_5_7:3;
1178 uint64_t dma0_cnt:5;
1179 uint64_t reserved_13_15:3;
1180 uint64_t dma1_cnt:5;
1181 uint64_t reserved_21_23:3;
1182 uint64_t dma2_cnt:5;
1183 uint64_t reserved_29_31:3;
1184 uint64_t dma3_cnt:5;
1185 uint64_t reserved_37_39:3;
1186 uint64_t dma4_cnt:5;
1187 uint64_t reserved_45_47:3;
1188 uint64_t pkt_cnt:5;
1189 uint64_t reserved_53_62:10;
1190 uint64_t dma_arb:1;
1191 #endif
1192 } s;
1193 };
1194
1195 union cvmx_npei_dma_state1 {
1196 uint64_t u64;
1197 struct cvmx_npei_dma_state1_s {
1198 #ifdef __BIG_ENDIAN_BITFIELD
1199 uint64_t reserved_40_63:24;
1200 uint64_t d4_dwe:8;
1201 uint64_t d3_dwe:8;
1202 uint64_t d2_dwe:8;
1203 uint64_t d1_dwe:8;
1204 uint64_t d0_dwe:8;
1205 #else
1206 uint64_t d0_dwe:8;
1207 uint64_t d1_dwe:8;
1208 uint64_t d2_dwe:8;
1209 uint64_t d3_dwe:8;
1210 uint64_t d4_dwe:8;
1211 uint64_t reserved_40_63:24;
1212 #endif
1213 } s;
1214 };
1215
1216 union cvmx_npei_dma_state1_p1 {
1217 uint64_t u64;
1218 struct cvmx_npei_dma_state1_p1_s {
1219 #ifdef __BIG_ENDIAN_BITFIELD
1220 uint64_t reserved_60_63:4;
1221 uint64_t d0_difst:7;
1222 uint64_t d1_difst:7;
1223 uint64_t d2_difst:7;
1224 uint64_t d3_difst:7;
1225 uint64_t d4_difst:7;
1226 uint64_t d0_reqst:5;
1227 uint64_t d1_reqst:5;
1228 uint64_t d2_reqst:5;
1229 uint64_t d3_reqst:5;
1230 uint64_t d4_reqst:5;
1231 #else
1232 uint64_t d4_reqst:5;
1233 uint64_t d3_reqst:5;
1234 uint64_t d2_reqst:5;
1235 uint64_t d1_reqst:5;
1236 uint64_t d0_reqst:5;
1237 uint64_t d4_difst:7;
1238 uint64_t d3_difst:7;
1239 uint64_t d2_difst:7;
1240 uint64_t d1_difst:7;
1241 uint64_t d0_difst:7;
1242 uint64_t reserved_60_63:4;
1243 #endif
1244 } s;
1245 struct cvmx_npei_dma_state1_p1_cn52xxp1 {
1246 #ifdef __BIG_ENDIAN_BITFIELD
1247 uint64_t reserved_60_63:4;
1248 uint64_t d0_difst:7;
1249 uint64_t d1_difst:7;
1250 uint64_t d2_difst:7;
1251 uint64_t d3_difst:7;
1252 uint64_t reserved_25_31:7;
1253 uint64_t d0_reqst:5;
1254 uint64_t d1_reqst:5;
1255 uint64_t d2_reqst:5;
1256 uint64_t d3_reqst:5;
1257 uint64_t reserved_0_4:5;
1258 #else
1259 uint64_t reserved_0_4:5;
1260 uint64_t d3_reqst:5;
1261 uint64_t d2_reqst:5;
1262 uint64_t d1_reqst:5;
1263 uint64_t d0_reqst:5;
1264 uint64_t reserved_25_31:7;
1265 uint64_t d3_difst:7;
1266 uint64_t d2_difst:7;
1267 uint64_t d1_difst:7;
1268 uint64_t d0_difst:7;
1269 uint64_t reserved_60_63:4;
1270 #endif
1271 } cn52xxp1;
1272 };
1273
1274 union cvmx_npei_dma_state2 {
1275 uint64_t u64;
1276 struct cvmx_npei_dma_state2_s {
1277 #ifdef __BIG_ENDIAN_BITFIELD
1278 uint64_t reserved_28_63:36;
1279 uint64_t ndwe:4;
1280 uint64_t reserved_21_23:3;
1281 uint64_t ndre:5;
1282 uint64_t reserved_10_15:6;
1283 uint64_t prd:10;
1284 #else
1285 uint64_t prd:10;
1286 uint64_t reserved_10_15:6;
1287 uint64_t ndre:5;
1288 uint64_t reserved_21_23:3;
1289 uint64_t ndwe:4;
1290 uint64_t reserved_28_63:36;
1291 #endif
1292 } s;
1293 };
1294
1295 union cvmx_npei_dma_state2_p1 {
1296 uint64_t u64;
1297 struct cvmx_npei_dma_state2_p1_s {
1298 #ifdef __BIG_ENDIAN_BITFIELD
1299 uint64_t reserved_45_63:19;
1300 uint64_t d0_dffst:9;
1301 uint64_t d1_dffst:9;
1302 uint64_t d2_dffst:9;
1303 uint64_t d3_dffst:9;
1304 uint64_t d4_dffst:9;
1305 #else
1306 uint64_t d4_dffst:9;
1307 uint64_t d3_dffst:9;
1308 uint64_t d2_dffst:9;
1309 uint64_t d1_dffst:9;
1310 uint64_t d0_dffst:9;
1311 uint64_t reserved_45_63:19;
1312 #endif
1313 } s;
1314 struct cvmx_npei_dma_state2_p1_cn52xxp1 {
1315 #ifdef __BIG_ENDIAN_BITFIELD
1316 uint64_t reserved_45_63:19;
1317 uint64_t d0_dffst:9;
1318 uint64_t d1_dffst:9;
1319 uint64_t d2_dffst:9;
1320 uint64_t d3_dffst:9;
1321 uint64_t reserved_0_8:9;
1322 #else
1323 uint64_t reserved_0_8:9;
1324 uint64_t d3_dffst:9;
1325 uint64_t d2_dffst:9;
1326 uint64_t d1_dffst:9;
1327 uint64_t d0_dffst:9;
1328 uint64_t reserved_45_63:19;
1329 #endif
1330 } cn52xxp1;
1331 };
1332
1333 union cvmx_npei_dma_state3_p1 {
1334 uint64_t u64;
1335 struct cvmx_npei_dma_state3_p1_s {
1336 #ifdef __BIG_ENDIAN_BITFIELD
1337 uint64_t reserved_60_63:4;
1338 uint64_t d0_drest:15;
1339 uint64_t d1_drest:15;
1340 uint64_t d2_drest:15;
1341 uint64_t d3_drest:15;
1342 #else
1343 uint64_t d3_drest:15;
1344 uint64_t d2_drest:15;
1345 uint64_t d1_drest:15;
1346 uint64_t d0_drest:15;
1347 uint64_t reserved_60_63:4;
1348 #endif
1349 } s;
1350 };
1351
1352 union cvmx_npei_dma_state4_p1 {
1353 uint64_t u64;
1354 struct cvmx_npei_dma_state4_p1_s {
1355 #ifdef __BIG_ENDIAN_BITFIELD
1356 uint64_t reserved_52_63:12;
1357 uint64_t d0_dwest:13;
1358 uint64_t d1_dwest:13;
1359 uint64_t d2_dwest:13;
1360 uint64_t d3_dwest:13;
1361 #else
1362 uint64_t d3_dwest:13;
1363 uint64_t d2_dwest:13;
1364 uint64_t d1_dwest:13;
1365 uint64_t d0_dwest:13;
1366 uint64_t reserved_52_63:12;
1367 #endif
1368 } s;
1369 };
1370
1371 union cvmx_npei_dma_state5_p1 {
1372 uint64_t u64;
1373 struct cvmx_npei_dma_state5_p1_s {
1374 #ifdef __BIG_ENDIAN_BITFIELD
1375 uint64_t reserved_28_63:36;
1376 uint64_t d4_drest:15;
1377 uint64_t d4_dwest:13;
1378 #else
1379 uint64_t d4_dwest:13;
1380 uint64_t d4_drest:15;
1381 uint64_t reserved_28_63:36;
1382 #endif
1383 } s;
1384 };
1385
1386 union cvmx_npei_int_a_enb {
1387 uint64_t u64;
1388 struct cvmx_npei_int_a_enb_s {
1389 #ifdef __BIG_ENDIAN_BITFIELD
1390 uint64_t reserved_10_63:54;
1391 uint64_t pout_err:1;
1392 uint64_t pin_bp:1;
1393 uint64_t p1_rdlk:1;
1394 uint64_t p0_rdlk:1;
1395 uint64_t pgl_err:1;
1396 uint64_t pdi_err:1;
1397 uint64_t pop_err:1;
1398 uint64_t pins_err:1;
1399 uint64_t dma1_cpl:1;
1400 uint64_t dma0_cpl:1;
1401 #else
1402 uint64_t dma0_cpl:1;
1403 uint64_t dma1_cpl:1;
1404 uint64_t pins_err:1;
1405 uint64_t pop_err:1;
1406 uint64_t pdi_err:1;
1407 uint64_t pgl_err:1;
1408 uint64_t p0_rdlk:1;
1409 uint64_t p1_rdlk:1;
1410 uint64_t pin_bp:1;
1411 uint64_t pout_err:1;
1412 uint64_t reserved_10_63:54;
1413 #endif
1414 } s;
1415 struct cvmx_npei_int_a_enb_cn52xxp1 {
1416 #ifdef __BIG_ENDIAN_BITFIELD
1417 uint64_t reserved_2_63:62;
1418 uint64_t dma1_cpl:1;
1419 uint64_t dma0_cpl:1;
1420 #else
1421 uint64_t dma0_cpl:1;
1422 uint64_t dma1_cpl:1;
1423 uint64_t reserved_2_63:62;
1424 #endif
1425 } cn52xxp1;
1426 };
1427
1428 union cvmx_npei_int_a_enb2 {
1429 uint64_t u64;
1430 struct cvmx_npei_int_a_enb2_s {
1431 #ifdef __BIG_ENDIAN_BITFIELD
1432 uint64_t reserved_10_63:54;
1433 uint64_t pout_err:1;
1434 uint64_t pin_bp:1;
1435 uint64_t p1_rdlk:1;
1436 uint64_t p0_rdlk:1;
1437 uint64_t pgl_err:1;
1438 uint64_t pdi_err:1;
1439 uint64_t pop_err:1;
1440 uint64_t pins_err:1;
1441 uint64_t dma1_cpl:1;
1442 uint64_t dma0_cpl:1;
1443 #else
1444 uint64_t dma0_cpl:1;
1445 uint64_t dma1_cpl:1;
1446 uint64_t pins_err:1;
1447 uint64_t pop_err:1;
1448 uint64_t pdi_err:1;
1449 uint64_t pgl_err:1;
1450 uint64_t p0_rdlk:1;
1451 uint64_t p1_rdlk:1;
1452 uint64_t pin_bp:1;
1453 uint64_t pout_err:1;
1454 uint64_t reserved_10_63:54;
1455 #endif
1456 } s;
1457 struct cvmx_npei_int_a_enb2_cn52xxp1 {
1458 #ifdef __BIG_ENDIAN_BITFIELD
1459 uint64_t reserved_2_63:62;
1460 uint64_t dma1_cpl:1;
1461 uint64_t dma0_cpl:1;
1462 #else
1463 uint64_t dma0_cpl:1;
1464 uint64_t dma1_cpl:1;
1465 uint64_t reserved_2_63:62;
1466 #endif
1467 } cn52xxp1;
1468 };
1469
1470 union cvmx_npei_int_a_sum {
1471 uint64_t u64;
1472 struct cvmx_npei_int_a_sum_s {
1473 #ifdef __BIG_ENDIAN_BITFIELD
1474 uint64_t reserved_10_63:54;
1475 uint64_t pout_err:1;
1476 uint64_t pin_bp:1;
1477 uint64_t p1_rdlk:1;
1478 uint64_t p0_rdlk:1;
1479 uint64_t pgl_err:1;
1480 uint64_t pdi_err:1;
1481 uint64_t pop_err:1;
1482 uint64_t pins_err:1;
1483 uint64_t dma1_cpl:1;
1484 uint64_t dma0_cpl:1;
1485 #else
1486 uint64_t dma0_cpl:1;
1487 uint64_t dma1_cpl:1;
1488 uint64_t pins_err:1;
1489 uint64_t pop_err:1;
1490 uint64_t pdi_err:1;
1491 uint64_t pgl_err:1;
1492 uint64_t p0_rdlk:1;
1493 uint64_t p1_rdlk:1;
1494 uint64_t pin_bp:1;
1495 uint64_t pout_err:1;
1496 uint64_t reserved_10_63:54;
1497 #endif
1498 } s;
1499 struct cvmx_npei_int_a_sum_cn52xxp1 {
1500 #ifdef __BIG_ENDIAN_BITFIELD
1501 uint64_t reserved_2_63:62;
1502 uint64_t dma1_cpl:1;
1503 uint64_t dma0_cpl:1;
1504 #else
1505 uint64_t dma0_cpl:1;
1506 uint64_t dma1_cpl:1;
1507 uint64_t reserved_2_63:62;
1508 #endif
1509 } cn52xxp1;
1510 };
1511
1512 union cvmx_npei_int_enb {
1513 uint64_t u64;
1514 struct cvmx_npei_int_enb_s {
1515 #ifdef __BIG_ENDIAN_BITFIELD
1516 uint64_t mio_inta:1;
1517 uint64_t reserved_62_62:1;
1518 uint64_t int_a:1;
1519 uint64_t c1_ldwn:1;
1520 uint64_t c0_ldwn:1;
1521 uint64_t c1_exc:1;
1522 uint64_t c0_exc:1;
1523 uint64_t c1_up_wf:1;
1524 uint64_t c0_up_wf:1;
1525 uint64_t c1_un_wf:1;
1526 uint64_t c0_un_wf:1;
1527 uint64_t c1_un_bx:1;
1528 uint64_t c1_un_wi:1;
1529 uint64_t c1_un_b2:1;
1530 uint64_t c1_un_b1:1;
1531 uint64_t c1_un_b0:1;
1532 uint64_t c1_up_bx:1;
1533 uint64_t c1_up_wi:1;
1534 uint64_t c1_up_b2:1;
1535 uint64_t c1_up_b1:1;
1536 uint64_t c1_up_b0:1;
1537 uint64_t c0_un_bx:1;
1538 uint64_t c0_un_wi:1;
1539 uint64_t c0_un_b2:1;
1540 uint64_t c0_un_b1:1;
1541 uint64_t c0_un_b0:1;
1542 uint64_t c0_up_bx:1;
1543 uint64_t c0_up_wi:1;
1544 uint64_t c0_up_b2:1;
1545 uint64_t c0_up_b1:1;
1546 uint64_t c0_up_b0:1;
1547 uint64_t c1_hpint:1;
1548 uint64_t c1_pmei:1;
1549 uint64_t c1_wake:1;
1550 uint64_t crs1_dr:1;
1551 uint64_t c1_se:1;
1552 uint64_t crs1_er:1;
1553 uint64_t c1_aeri:1;
1554 uint64_t c0_hpint:1;
1555 uint64_t c0_pmei:1;
1556 uint64_t c0_wake:1;
1557 uint64_t crs0_dr:1;
1558 uint64_t c0_se:1;
1559 uint64_t crs0_er:1;
1560 uint64_t c0_aeri:1;
1561 uint64_t ptime:1;
1562 uint64_t pcnt:1;
1563 uint64_t pidbof:1;
1564 uint64_t psldbof:1;
1565 uint64_t dtime1:1;
1566 uint64_t dtime0:1;
1567 uint64_t dcnt1:1;
1568 uint64_t dcnt0:1;
1569 uint64_t dma1fi:1;
1570 uint64_t dma0fi:1;
1571 uint64_t dma4dbo:1;
1572 uint64_t dma3dbo:1;
1573 uint64_t dma2dbo:1;
1574 uint64_t dma1dbo:1;
1575 uint64_t dma0dbo:1;
1576 uint64_t iob2big:1;
1577 uint64_t bar0_to:1;
1578 uint64_t rml_wto:1;
1579 uint64_t rml_rto:1;
1580 #else
1581 uint64_t rml_rto:1;
1582 uint64_t rml_wto:1;
1583 uint64_t bar0_to:1;
1584 uint64_t iob2big:1;
1585 uint64_t dma0dbo:1;
1586 uint64_t dma1dbo:1;
1587 uint64_t dma2dbo:1;
1588 uint64_t dma3dbo:1;
1589 uint64_t dma4dbo:1;
1590 uint64_t dma0fi:1;
1591 uint64_t dma1fi:1;
1592 uint64_t dcnt0:1;
1593 uint64_t dcnt1:1;
1594 uint64_t dtime0:1;
1595 uint64_t dtime1:1;
1596 uint64_t psldbof:1;
1597 uint64_t pidbof:1;
1598 uint64_t pcnt:1;
1599 uint64_t ptime:1;
1600 uint64_t c0_aeri:1;
1601 uint64_t crs0_er:1;
1602 uint64_t c0_se:1;
1603 uint64_t crs0_dr:1;
1604 uint64_t c0_wake:1;
1605 uint64_t c0_pmei:1;
1606 uint64_t c0_hpint:1;
1607 uint64_t c1_aeri:1;
1608 uint64_t crs1_er:1;
1609 uint64_t c1_se:1;
1610 uint64_t crs1_dr:1;
1611 uint64_t c1_wake:1;
1612 uint64_t c1_pmei:1;
1613 uint64_t c1_hpint:1;
1614 uint64_t c0_up_b0:1;
1615 uint64_t c0_up_b1:1;
1616 uint64_t c0_up_b2:1;
1617 uint64_t c0_up_wi:1;
1618 uint64_t c0_up_bx:1;
1619 uint64_t c0_un_b0:1;
1620 uint64_t c0_un_b1:1;
1621 uint64_t c0_un_b2:1;
1622 uint64_t c0_un_wi:1;
1623 uint64_t c0_un_bx:1;
1624 uint64_t c1_up_b0:1;
1625 uint64_t c1_up_b1:1;
1626 uint64_t c1_up_b2:1;
1627 uint64_t c1_up_wi:1;
1628 uint64_t c1_up_bx:1;
1629 uint64_t c1_un_b0:1;
1630 uint64_t c1_un_b1:1;
1631 uint64_t c1_un_b2:1;
1632 uint64_t c1_un_wi:1;
1633 uint64_t c1_un_bx:1;
1634 uint64_t c0_un_wf:1;
1635 uint64_t c1_un_wf:1;
1636 uint64_t c0_up_wf:1;
1637 uint64_t c1_up_wf:1;
1638 uint64_t c0_exc:1;
1639 uint64_t c1_exc:1;
1640 uint64_t c0_ldwn:1;
1641 uint64_t c1_ldwn:1;
1642 uint64_t int_a:1;
1643 uint64_t reserved_62_62:1;
1644 uint64_t mio_inta:1;
1645 #endif
1646 } s;
1647 struct cvmx_npei_int_enb_cn52xxp1 {
1648 #ifdef __BIG_ENDIAN_BITFIELD
1649 uint64_t mio_inta:1;
1650 uint64_t reserved_62_62:1;
1651 uint64_t int_a:1;
1652 uint64_t c1_ldwn:1;
1653 uint64_t c0_ldwn:1;
1654 uint64_t c1_exc:1;
1655 uint64_t c0_exc:1;
1656 uint64_t c1_up_wf:1;
1657 uint64_t c0_up_wf:1;
1658 uint64_t c1_un_wf:1;
1659 uint64_t c0_un_wf:1;
1660 uint64_t c1_un_bx:1;
1661 uint64_t c1_un_wi:1;
1662 uint64_t c1_un_b2:1;
1663 uint64_t c1_un_b1:1;
1664 uint64_t c1_un_b0:1;
1665 uint64_t c1_up_bx:1;
1666 uint64_t c1_up_wi:1;
1667 uint64_t c1_up_b2:1;
1668 uint64_t c1_up_b1:1;
1669 uint64_t c1_up_b0:1;
1670 uint64_t c0_un_bx:1;
1671 uint64_t c0_un_wi:1;
1672 uint64_t c0_un_b2:1;
1673 uint64_t c0_un_b1:1;
1674 uint64_t c0_un_b0:1;
1675 uint64_t c0_up_bx:1;
1676 uint64_t c0_up_wi:1;
1677 uint64_t c0_up_b2:1;
1678 uint64_t c0_up_b1:1;
1679 uint64_t c0_up_b0:1;
1680 uint64_t c1_hpint:1;
1681 uint64_t c1_pmei:1;
1682 uint64_t c1_wake:1;
1683 uint64_t crs1_dr:1;
1684 uint64_t c1_se:1;
1685 uint64_t crs1_er:1;
1686 uint64_t c1_aeri:1;
1687 uint64_t c0_hpint:1;
1688 uint64_t c0_pmei:1;
1689 uint64_t c0_wake:1;
1690 uint64_t crs0_dr:1;
1691 uint64_t c0_se:1;
1692 uint64_t crs0_er:1;
1693 uint64_t c0_aeri:1;
1694 uint64_t ptime:1;
1695 uint64_t pcnt:1;
1696 uint64_t pidbof:1;
1697 uint64_t psldbof:1;
1698 uint64_t dtime1:1;
1699 uint64_t dtime0:1;
1700 uint64_t dcnt1:1;
1701 uint64_t dcnt0:1;
1702 uint64_t dma1fi:1;
1703 uint64_t dma0fi:1;
1704 uint64_t reserved_8_8:1;
1705 uint64_t dma3dbo:1;
1706 uint64_t dma2dbo:1;
1707 uint64_t dma1dbo:1;
1708 uint64_t dma0dbo:1;
1709 uint64_t iob2big:1;
1710 uint64_t bar0_to:1;
1711 uint64_t rml_wto:1;
1712 uint64_t rml_rto:1;
1713 #else
1714 uint64_t rml_rto:1;
1715 uint64_t rml_wto:1;
1716 uint64_t bar0_to:1;
1717 uint64_t iob2big:1;
1718 uint64_t dma0dbo:1;
1719 uint64_t dma1dbo:1;
1720 uint64_t dma2dbo:1;
1721 uint64_t dma3dbo:1;
1722 uint64_t reserved_8_8:1;
1723 uint64_t dma0fi:1;
1724 uint64_t dma1fi:1;
1725 uint64_t dcnt0:1;
1726 uint64_t dcnt1:1;
1727 uint64_t dtime0:1;
1728 uint64_t dtime1:1;
1729 uint64_t psldbof:1;
1730 uint64_t pidbof:1;
1731 uint64_t pcnt:1;
1732 uint64_t ptime:1;
1733 uint64_t c0_aeri:1;
1734 uint64_t crs0_er:1;
1735 uint64_t c0_se:1;
1736 uint64_t crs0_dr:1;
1737 uint64_t c0_wake:1;
1738 uint64_t c0_pmei:1;
1739 uint64_t c0_hpint:1;
1740 uint64_t c1_aeri:1;
1741 uint64_t crs1_er:1;
1742 uint64_t c1_se:1;
1743 uint64_t crs1_dr:1;
1744 uint64_t c1_wake:1;
1745 uint64_t c1_pmei:1;
1746 uint64_t c1_hpint:1;
1747 uint64_t c0_up_b0:1;
1748 uint64_t c0_up_b1:1;
1749 uint64_t c0_up_b2:1;
1750 uint64_t c0_up_wi:1;
1751 uint64_t c0_up_bx:1;
1752 uint64_t c0_un_b0:1;
1753 uint64_t c0_un_b1:1;
1754 uint64_t c0_un_b2:1;
1755 uint64_t c0_un_wi:1;
1756 uint64_t c0_un_bx:1;
1757 uint64_t c1_up_b0:1;
1758 uint64_t c1_up_b1:1;
1759 uint64_t c1_up_b2:1;
1760 uint64_t c1_up_wi:1;
1761 uint64_t c1_up_bx:1;
1762 uint64_t c1_un_b0:1;
1763 uint64_t c1_un_b1:1;
1764 uint64_t c1_un_b2:1;
1765 uint64_t c1_un_wi:1;
1766 uint64_t c1_un_bx:1;
1767 uint64_t c0_un_wf:1;
1768 uint64_t c1_un_wf:1;
1769 uint64_t c0_up_wf:1;
1770 uint64_t c1_up_wf:1;
1771 uint64_t c0_exc:1;
1772 uint64_t c1_exc:1;
1773 uint64_t c0_ldwn:1;
1774 uint64_t c1_ldwn:1;
1775 uint64_t int_a:1;
1776 uint64_t reserved_62_62:1;
1777 uint64_t mio_inta:1;
1778 #endif
1779 } cn52xxp1;
1780 struct cvmx_npei_int_enb_cn56xxp1 {
1781 #ifdef __BIG_ENDIAN_BITFIELD
1782 uint64_t mio_inta:1;
1783 uint64_t reserved_61_62:2;
1784 uint64_t c1_ldwn:1;
1785 uint64_t c0_ldwn:1;
1786 uint64_t c1_exc:1;
1787 uint64_t c0_exc:1;
1788 uint64_t c1_up_wf:1;
1789 uint64_t c0_up_wf:1;
1790 uint64_t c1_un_wf:1;
1791 uint64_t c0_un_wf:1;
1792 uint64_t c1_un_bx:1;
1793 uint64_t c1_un_wi:1;
1794 uint64_t c1_un_b2:1;
1795 uint64_t c1_un_b1:1;
1796 uint64_t c1_un_b0:1;
1797 uint64_t c1_up_bx:1;
1798 uint64_t c1_up_wi:1;
1799 uint64_t c1_up_b2:1;
1800 uint64_t c1_up_b1:1;
1801 uint64_t c1_up_b0:1;
1802 uint64_t c0_un_bx:1;
1803 uint64_t c0_un_wi:1;
1804 uint64_t c0_un_b2:1;
1805 uint64_t c0_un_b1:1;
1806 uint64_t c0_un_b0:1;
1807 uint64_t c0_up_bx:1;
1808 uint64_t c0_up_wi:1;
1809 uint64_t c0_up_b2:1;
1810 uint64_t c0_up_b1:1;
1811 uint64_t c0_up_b0:1;
1812 uint64_t c1_hpint:1;
1813 uint64_t c1_pmei:1;
1814 uint64_t c1_wake:1;
1815 uint64_t reserved_29_29:1;
1816 uint64_t c1_se:1;
1817 uint64_t reserved_27_27:1;
1818 uint64_t c1_aeri:1;
1819 uint64_t c0_hpint:1;
1820 uint64_t c0_pmei:1;
1821 uint64_t c0_wake:1;
1822 uint64_t reserved_22_22:1;
1823 uint64_t c0_se:1;
1824 uint64_t reserved_20_20:1;
1825 uint64_t c0_aeri:1;
1826 uint64_t ptime:1;
1827 uint64_t pcnt:1;
1828 uint64_t pidbof:1;
1829 uint64_t psldbof:1;
1830 uint64_t dtime1:1;
1831 uint64_t dtime0:1;
1832 uint64_t dcnt1:1;
1833 uint64_t dcnt0:1;
1834 uint64_t dma1fi:1;
1835 uint64_t dma0fi:1;
1836 uint64_t dma4dbo:1;
1837 uint64_t dma3dbo:1;
1838 uint64_t dma2dbo:1;
1839 uint64_t dma1dbo:1;
1840 uint64_t dma0dbo:1;
1841 uint64_t iob2big:1;
1842 uint64_t bar0_to:1;
1843 uint64_t rml_wto:1;
1844 uint64_t rml_rto:1;
1845 #else
1846 uint64_t rml_rto:1;
1847 uint64_t rml_wto:1;
1848 uint64_t bar0_to:1;
1849 uint64_t iob2big:1;
1850 uint64_t dma0dbo:1;
1851 uint64_t dma1dbo:1;
1852 uint64_t dma2dbo:1;
1853 uint64_t dma3dbo:1;
1854 uint64_t dma4dbo:1;
1855 uint64_t dma0fi:1;
1856 uint64_t dma1fi:1;
1857 uint64_t dcnt0:1;
1858 uint64_t dcnt1:1;
1859 uint64_t dtime0:1;
1860 uint64_t dtime1:1;
1861 uint64_t psldbof:1;
1862 uint64_t pidbof:1;
1863 uint64_t pcnt:1;
1864 uint64_t ptime:1;
1865 uint64_t c0_aeri:1;
1866 uint64_t reserved_20_20:1;
1867 uint64_t c0_se:1;
1868 uint64_t reserved_22_22:1;
1869 uint64_t c0_wake:1;
1870 uint64_t c0_pmei:1;
1871 uint64_t c0_hpint:1;
1872 uint64_t c1_aeri:1;
1873 uint64_t reserved_27_27:1;
1874 uint64_t c1_se:1;
1875 uint64_t reserved_29_29:1;
1876 uint64_t c1_wake:1;
1877 uint64_t c1_pmei:1;
1878 uint64_t c1_hpint:1;
1879 uint64_t c0_up_b0:1;
1880 uint64_t c0_up_b1:1;
1881 uint64_t c0_up_b2:1;
1882 uint64_t c0_up_wi:1;
1883 uint64_t c0_up_bx:1;
1884 uint64_t c0_un_b0:1;
1885 uint64_t c0_un_b1:1;
1886 uint64_t c0_un_b2:1;
1887 uint64_t c0_un_wi:1;
1888 uint64_t c0_un_bx:1;
1889 uint64_t c1_up_b0:1;
1890 uint64_t c1_up_b1:1;
1891 uint64_t c1_up_b2:1;
1892 uint64_t c1_up_wi:1;
1893 uint64_t c1_up_bx:1;
1894 uint64_t c1_un_b0:1;
1895 uint64_t c1_un_b1:1;
1896 uint64_t c1_un_b2:1;
1897 uint64_t c1_un_wi:1;
1898 uint64_t c1_un_bx:1;
1899 uint64_t c0_un_wf:1;
1900 uint64_t c1_un_wf:1;
1901 uint64_t c0_up_wf:1;
1902 uint64_t c1_up_wf:1;
1903 uint64_t c0_exc:1;
1904 uint64_t c1_exc:1;
1905 uint64_t c0_ldwn:1;
1906 uint64_t c1_ldwn:1;
1907 uint64_t reserved_61_62:2;
1908 uint64_t mio_inta:1;
1909 #endif
1910 } cn56xxp1;
1911 };
1912
1913 union cvmx_npei_int_enb2 {
1914 uint64_t u64;
1915 struct cvmx_npei_int_enb2_s {
1916 #ifdef __BIG_ENDIAN_BITFIELD
1917 uint64_t reserved_62_63:2;
1918 uint64_t int_a:1;
1919 uint64_t c1_ldwn:1;
1920 uint64_t c0_ldwn:1;
1921 uint64_t c1_exc:1;
1922 uint64_t c0_exc:1;
1923 uint64_t c1_up_wf:1;
1924 uint64_t c0_up_wf:1;
1925 uint64_t c1_un_wf:1;
1926 uint64_t c0_un_wf:1;
1927 uint64_t c1_un_bx:1;
1928 uint64_t c1_un_wi:1;
1929 uint64_t c1_un_b2:1;
1930 uint64_t c1_un_b1:1;
1931 uint64_t c1_un_b0:1;
1932 uint64_t c1_up_bx:1;
1933 uint64_t c1_up_wi:1;
1934 uint64_t c1_up_b2:1;
1935 uint64_t c1_up_b1:1;
1936 uint64_t c1_up_b0:1;
1937 uint64_t c0_un_bx:1;
1938 uint64_t c0_un_wi:1;
1939 uint64_t c0_un_b2:1;
1940 uint64_t c0_un_b1:1;
1941 uint64_t c0_un_b0:1;
1942 uint64_t c0_up_bx:1;
1943 uint64_t c0_up_wi:1;
1944 uint64_t c0_up_b2:1;
1945 uint64_t c0_up_b1:1;
1946 uint64_t c0_up_b0:1;
1947 uint64_t c1_hpint:1;
1948 uint64_t c1_pmei:1;
1949 uint64_t c1_wake:1;
1950 uint64_t crs1_dr:1;
1951 uint64_t c1_se:1;
1952 uint64_t crs1_er:1;
1953 uint64_t c1_aeri:1;
1954 uint64_t c0_hpint:1;
1955 uint64_t c0_pmei:1;
1956 uint64_t c0_wake:1;
1957 uint64_t crs0_dr:1;
1958 uint64_t c0_se:1;
1959 uint64_t crs0_er:1;
1960 uint64_t c0_aeri:1;
1961 uint64_t ptime:1;
1962 uint64_t pcnt:1;
1963 uint64_t pidbof:1;
1964 uint64_t psldbof:1;
1965 uint64_t dtime1:1;
1966 uint64_t dtime0:1;
1967 uint64_t dcnt1:1;
1968 uint64_t dcnt0:1;
1969 uint64_t dma1fi:1;
1970 uint64_t dma0fi:1;
1971 uint64_t dma4dbo:1;
1972 uint64_t dma3dbo:1;
1973 uint64_t dma2dbo:1;
1974 uint64_t dma1dbo:1;
1975 uint64_t dma0dbo:1;
1976 uint64_t iob2big:1;
1977 uint64_t bar0_to:1;
1978 uint64_t rml_wto:1;
1979 uint64_t rml_rto:1;
1980 #else
1981 uint64_t rml_rto:1;
1982 uint64_t rml_wto:1;
1983 uint64_t bar0_to:1;
1984 uint64_t iob2big:1;
1985 uint64_t dma0dbo:1;
1986 uint64_t dma1dbo:1;
1987 uint64_t dma2dbo:1;
1988 uint64_t dma3dbo:1;
1989 uint64_t dma4dbo:1;
1990 uint64_t dma0fi:1;
1991 uint64_t dma1fi:1;
1992 uint64_t dcnt0:1;
1993 uint64_t dcnt1:1;
1994 uint64_t dtime0:1;
1995 uint64_t dtime1:1;
1996 uint64_t psldbof:1;
1997 uint64_t pidbof:1;
1998 uint64_t pcnt:1;
1999 uint64_t ptime:1;
2000 uint64_t c0_aeri:1;
2001 uint64_t crs0_er:1;
2002 uint64_t c0_se:1;
2003 uint64_t crs0_dr:1;
2004 uint64_t c0_wake:1;
2005 uint64_t c0_pmei:1;
2006 uint64_t c0_hpint:1;
2007 uint64_t c1_aeri:1;
2008 uint64_t crs1_er:1;
2009 uint64_t c1_se:1;
2010 uint64_t crs1_dr:1;
2011 uint64_t c1_wake:1;
2012 uint64_t c1_pmei:1;
2013 uint64_t c1_hpint:1;
2014 uint64_t c0_up_b0:1;
2015 uint64_t c0_up_b1:1;
2016 uint64_t c0_up_b2:1;
2017 uint64_t c0_up_wi:1;
2018 uint64_t c0_up_bx:1;
2019 uint64_t c0_un_b0:1;
2020 uint64_t c0_un_b1:1;
2021 uint64_t c0_un_b2:1;
2022 uint64_t c0_un_wi:1;
2023 uint64_t c0_un_bx:1;
2024 uint64_t c1_up_b0:1;
2025 uint64_t c1_up_b1:1;
2026 uint64_t c1_up_b2:1;
2027 uint64_t c1_up_wi:1;
2028 uint64_t c1_up_bx:1;
2029 uint64_t c1_un_b0:1;
2030 uint64_t c1_un_b1:1;
2031 uint64_t c1_un_b2:1;
2032 uint64_t c1_un_wi:1;
2033 uint64_t c1_un_bx:1;
2034 uint64_t c0_un_wf:1;
2035 uint64_t c1_un_wf:1;
2036 uint64_t c0_up_wf:1;
2037 uint64_t c1_up_wf:1;
2038 uint64_t c0_exc:1;
2039 uint64_t c1_exc:1;
2040 uint64_t c0_ldwn:1;
2041 uint64_t c1_ldwn:1;
2042 uint64_t int_a:1;
2043 uint64_t reserved_62_63:2;
2044 #endif
2045 } s;
2046 struct cvmx_npei_int_enb2_cn52xxp1 {
2047 #ifdef __BIG_ENDIAN_BITFIELD
2048 uint64_t reserved_62_63:2;
2049 uint64_t int_a:1;
2050 uint64_t c1_ldwn:1;
2051 uint64_t c0_ldwn:1;
2052 uint64_t c1_exc:1;
2053 uint64_t c0_exc:1;
2054 uint64_t c1_up_wf:1;
2055 uint64_t c0_up_wf:1;
2056 uint64_t c1_un_wf:1;
2057 uint64_t c0_un_wf:1;
2058 uint64_t c1_un_bx:1;
2059 uint64_t c1_un_wi:1;
2060 uint64_t c1_un_b2:1;
2061 uint64_t c1_un_b1:1;
2062 uint64_t c1_un_b0:1;
2063 uint64_t c1_up_bx:1;
2064 uint64_t c1_up_wi:1;
2065 uint64_t c1_up_b2:1;
2066 uint64_t c1_up_b1:1;
2067 uint64_t c1_up_b0:1;
2068 uint64_t c0_un_bx:1;
2069 uint64_t c0_un_wi:1;
2070 uint64_t c0_un_b2:1;
2071 uint64_t c0_un_b1:1;
2072 uint64_t c0_un_b0:1;
2073 uint64_t c0_up_bx:1;
2074 uint64_t c0_up_wi:1;
2075 uint64_t c0_up_b2:1;
2076 uint64_t c0_up_b1:1;
2077 uint64_t c0_up_b0:1;
2078 uint64_t c1_hpint:1;
2079 uint64_t c1_pmei:1;
2080 uint64_t c1_wake:1;
2081 uint64_t crs1_dr:1;
2082 uint64_t c1_se:1;
2083 uint64_t crs1_er:1;
2084 uint64_t c1_aeri:1;
2085 uint64_t c0_hpint:1;
2086 uint64_t c0_pmei:1;
2087 uint64_t c0_wake:1;
2088 uint64_t crs0_dr:1;
2089 uint64_t c0_se:1;
2090 uint64_t crs0_er:1;
2091 uint64_t c0_aeri:1;
2092 uint64_t ptime:1;
2093 uint64_t pcnt:1;
2094 uint64_t pidbof:1;
2095 uint64_t psldbof:1;
2096 uint64_t dtime1:1;
2097 uint64_t dtime0:1;
2098 uint64_t dcnt1:1;
2099 uint64_t dcnt0:1;
2100 uint64_t dma1fi:1;
2101 uint64_t dma0fi:1;
2102 uint64_t reserved_8_8:1;
2103 uint64_t dma3dbo:1;
2104 uint64_t dma2dbo:1;
2105 uint64_t dma1dbo:1;
2106 uint64_t dma0dbo:1;
2107 uint64_t iob2big:1;
2108 uint64_t bar0_to:1;
2109 uint64_t rml_wto:1;
2110 uint64_t rml_rto:1;
2111 #else
2112 uint64_t rml_rto:1;
2113 uint64_t rml_wto:1;
2114 uint64_t bar0_to:1;
2115 uint64_t iob2big:1;
2116 uint64_t dma0dbo:1;
2117 uint64_t dma1dbo:1;
2118 uint64_t dma2dbo:1;
2119 uint64_t dma3dbo:1;
2120 uint64_t reserved_8_8:1;
2121 uint64_t dma0fi:1;
2122 uint64_t dma1fi:1;
2123 uint64_t dcnt0:1;
2124 uint64_t dcnt1:1;
2125 uint64_t dtime0:1;
2126 uint64_t dtime1:1;
2127 uint64_t psldbof:1;
2128 uint64_t pidbof:1;
2129 uint64_t pcnt:1;
2130 uint64_t ptime:1;
2131 uint64_t c0_aeri:1;
2132 uint64_t crs0_er:1;
2133 uint64_t c0_se:1;
2134 uint64_t crs0_dr:1;
2135 uint64_t c0_wake:1;
2136 uint64_t c0_pmei:1;
2137 uint64_t c0_hpint:1;
2138 uint64_t c1_aeri:1;
2139 uint64_t crs1_er:1;
2140 uint64_t c1_se:1;
2141 uint64_t crs1_dr:1;
2142 uint64_t c1_wake:1;
2143 uint64_t c1_pmei:1;
2144 uint64_t c1_hpint:1;
2145 uint64_t c0_up_b0:1;
2146 uint64_t c0_up_b1:1;
2147 uint64_t c0_up_b2:1;
2148 uint64_t c0_up_wi:1;
2149 uint64_t c0_up_bx:1;
2150 uint64_t c0_un_b0:1;
2151 uint64_t c0_un_b1:1;
2152 uint64_t c0_un_b2:1;
2153 uint64_t c0_un_wi:1;
2154 uint64_t c0_un_bx:1;
2155 uint64_t c1_up_b0:1;
2156 uint64_t c1_up_b1:1;
2157 uint64_t c1_up_b2:1;
2158 uint64_t c1_up_wi:1;
2159 uint64_t c1_up_bx:1;
2160 uint64_t c1_un_b0:1;
2161 uint64_t c1_un_b1:1;
2162 uint64_t c1_un_b2:1;
2163 uint64_t c1_un_wi:1;
2164 uint64_t c1_un_bx:1;
2165 uint64_t c0_un_wf:1;
2166 uint64_t c1_un_wf:1;
2167 uint64_t c0_up_wf:1;
2168 uint64_t c1_up_wf:1;
2169 uint64_t c0_exc:1;
2170 uint64_t c1_exc:1;
2171 uint64_t c0_ldwn:1;
2172 uint64_t c1_ldwn:1;
2173 uint64_t int_a:1;
2174 uint64_t reserved_62_63:2;
2175 #endif
2176 } cn52xxp1;
2177 struct cvmx_npei_int_enb2_cn56xxp1 {
2178 #ifdef __BIG_ENDIAN_BITFIELD
2179 uint64_t reserved_61_63:3;
2180 uint64_t c1_ldwn:1;
2181 uint64_t c0_ldwn:1;
2182 uint64_t c1_exc:1;
2183 uint64_t c0_exc:1;
2184 uint64_t c1_up_wf:1;
2185 uint64_t c0_up_wf:1;
2186 uint64_t c1_un_wf:1;
2187 uint64_t c0_un_wf:1;
2188 uint64_t c1_un_bx:1;
2189 uint64_t c1_un_wi:1;
2190 uint64_t c1_un_b2:1;
2191 uint64_t c1_un_b1:1;
2192 uint64_t c1_un_b0:1;
2193 uint64_t c1_up_bx:1;
2194 uint64_t c1_up_wi:1;
2195 uint64_t c1_up_b2:1;
2196 uint64_t c1_up_b1:1;
2197 uint64_t c1_up_b0:1;
2198 uint64_t c0_un_bx:1;
2199 uint64_t c0_un_wi:1;
2200 uint64_t c0_un_b2:1;
2201 uint64_t c0_un_b1:1;
2202 uint64_t c0_un_b0:1;
2203 uint64_t c0_up_bx:1;
2204 uint64_t c0_up_wi:1;
2205 uint64_t c0_up_b2:1;
2206 uint64_t c0_up_b1:1;
2207 uint64_t c0_up_b0:1;
2208 uint64_t c1_hpint:1;
2209 uint64_t c1_pmei:1;
2210 uint64_t c1_wake:1;
2211 uint64_t reserved_29_29:1;
2212 uint64_t c1_se:1;
2213 uint64_t reserved_27_27:1;
2214 uint64_t c1_aeri:1;
2215 uint64_t c0_hpint:1;
2216 uint64_t c0_pmei:1;
2217 uint64_t c0_wake:1;
2218 uint64_t reserved_22_22:1;
2219 uint64_t c0_se:1;
2220 uint64_t reserved_20_20:1;
2221 uint64_t c0_aeri:1;
2222 uint64_t ptime:1;
2223 uint64_t pcnt:1;
2224 uint64_t pidbof:1;
2225 uint64_t psldbof:1;
2226 uint64_t dtime1:1;
2227 uint64_t dtime0:1;
2228 uint64_t dcnt1:1;
2229 uint64_t dcnt0:1;
2230 uint64_t dma1fi:1;
2231 uint64_t dma0fi:1;
2232 uint64_t dma4dbo:1;
2233 uint64_t dma3dbo:1;
2234 uint64_t dma2dbo:1;
2235 uint64_t dma1dbo:1;
2236 uint64_t dma0dbo:1;
2237 uint64_t iob2big:1;
2238 uint64_t bar0_to:1;
2239 uint64_t rml_wto:1;
2240 uint64_t rml_rto:1;
2241 #else
2242 uint64_t rml_rto:1;
2243 uint64_t rml_wto:1;
2244 uint64_t bar0_to:1;
2245 uint64_t iob2big:1;
2246 uint64_t dma0dbo:1;
2247 uint64_t dma1dbo:1;
2248 uint64_t dma2dbo:1;
2249 uint64_t dma3dbo:1;
2250 uint64_t dma4dbo:1;
2251 uint64_t dma0fi:1;
2252 uint64_t dma1fi:1;
2253 uint64_t dcnt0:1;
2254 uint64_t dcnt1:1;
2255 uint64_t dtime0:1;
2256 uint64_t dtime1:1;
2257 uint64_t psldbof:1;
2258 uint64_t pidbof:1;
2259 uint64_t pcnt:1;
2260 uint64_t ptime:1;
2261 uint64_t c0_aeri:1;
2262 uint64_t reserved_20_20:1;
2263 uint64_t c0_se:1;
2264 uint64_t reserved_22_22:1;
2265 uint64_t c0_wake:1;
2266 uint64_t c0_pmei:1;
2267 uint64_t c0_hpint:1;
2268 uint64_t c1_aeri:1;
2269 uint64_t reserved_27_27:1;
2270 uint64_t c1_se:1;
2271 uint64_t reserved_29_29:1;
2272 uint64_t c1_wake:1;
2273 uint64_t c1_pmei:1;
2274 uint64_t c1_hpint:1;
2275 uint64_t c0_up_b0:1;
2276 uint64_t c0_up_b1:1;
2277 uint64_t c0_up_b2:1;
2278 uint64_t c0_up_wi:1;
2279 uint64_t c0_up_bx:1;
2280 uint64_t c0_un_b0:1;
2281 uint64_t c0_un_b1:1;
2282 uint64_t c0_un_b2:1;
2283 uint64_t c0_un_wi:1;
2284 uint64_t c0_un_bx:1;
2285 uint64_t c1_up_b0:1;
2286 uint64_t c1_up_b1:1;
2287 uint64_t c1_up_b2:1;
2288 uint64_t c1_up_wi:1;
2289 uint64_t c1_up_bx:1;
2290 uint64_t c1_un_b0:1;
2291 uint64_t c1_un_b1:1;
2292 uint64_t c1_un_b2:1;
2293 uint64_t c1_un_wi:1;
2294 uint64_t c1_un_bx:1;
2295 uint64_t c0_un_wf:1;
2296 uint64_t c1_un_wf:1;
2297 uint64_t c0_up_wf:1;
2298 uint64_t c1_up_wf:1;
2299 uint64_t c0_exc:1;
2300 uint64_t c1_exc:1;
2301 uint64_t c0_ldwn:1;
2302 uint64_t c1_ldwn:1;
2303 uint64_t reserved_61_63:3;
2304 #endif
2305 } cn56xxp1;
2306 };
2307
2308 union cvmx_npei_int_info {
2309 uint64_t u64;
2310 struct cvmx_npei_int_info_s {
2311 #ifdef __BIG_ENDIAN_BITFIELD
2312 uint64_t reserved_12_63:52;
2313 uint64_t pidbof:6;
2314 uint64_t psldbof:6;
2315 #else
2316 uint64_t psldbof:6;
2317 uint64_t pidbof:6;
2318 uint64_t reserved_12_63:52;
2319 #endif
2320 } s;
2321 };
2322
2323 union cvmx_npei_int_sum {
2324 uint64_t u64;
2325 struct cvmx_npei_int_sum_s {
2326 #ifdef __BIG_ENDIAN_BITFIELD
2327 uint64_t mio_inta:1;
2328 uint64_t reserved_62_62:1;
2329 uint64_t int_a:1;
2330 uint64_t c1_ldwn:1;
2331 uint64_t c0_ldwn:1;
2332 uint64_t c1_exc:1;
2333 uint64_t c0_exc:1;
2334 uint64_t c1_up_wf:1;
2335 uint64_t c0_up_wf:1;
2336 uint64_t c1_un_wf:1;
2337 uint64_t c0_un_wf:1;
2338 uint64_t c1_un_bx:1;
2339 uint64_t c1_un_wi:1;
2340 uint64_t c1_un_b2:1;
2341 uint64_t c1_un_b1:1;
2342 uint64_t c1_un_b0:1;
2343 uint64_t c1_up_bx:1;
2344 uint64_t c1_up_wi:1;
2345 uint64_t c1_up_b2:1;
2346 uint64_t c1_up_b1:1;
2347 uint64_t c1_up_b0:1;
2348 uint64_t c0_un_bx:1;
2349 uint64_t c0_un_wi:1;
2350 uint64_t c0_un_b2:1;
2351 uint64_t c0_un_b1:1;
2352 uint64_t c0_un_b0:1;
2353 uint64_t c0_up_bx:1;
2354 uint64_t c0_up_wi:1;
2355 uint64_t c0_up_b2:1;
2356 uint64_t c0_up_b1:1;
2357 uint64_t c0_up_b0:1;
2358 uint64_t c1_hpint:1;
2359 uint64_t c1_pmei:1;
2360 uint64_t c1_wake:1;
2361 uint64_t crs1_dr:1;
2362 uint64_t c1_se:1;
2363 uint64_t crs1_er:1;
2364 uint64_t c1_aeri:1;
2365 uint64_t c0_hpint:1;
2366 uint64_t c0_pmei:1;
2367 uint64_t c0_wake:1;
2368 uint64_t crs0_dr:1;
2369 uint64_t c0_se:1;
2370 uint64_t crs0_er:1;
2371 uint64_t c0_aeri:1;
2372 uint64_t ptime:1;
2373 uint64_t pcnt:1;
2374 uint64_t pidbof:1;
2375 uint64_t psldbof:1;
2376 uint64_t dtime1:1;
2377 uint64_t dtime0:1;
2378 uint64_t dcnt1:1;
2379 uint64_t dcnt0:1;
2380 uint64_t dma1fi:1;
2381 uint64_t dma0fi:1;
2382 uint64_t dma4dbo:1;
2383 uint64_t dma3dbo:1;
2384 uint64_t dma2dbo:1;
2385 uint64_t dma1dbo:1;
2386 uint64_t dma0dbo:1;
2387 uint64_t iob2big:1;
2388 uint64_t bar0_to:1;
2389 uint64_t rml_wto:1;
2390 uint64_t rml_rto:1;
2391 #else
2392 uint64_t rml_rto:1;
2393 uint64_t rml_wto:1;
2394 uint64_t bar0_to:1;
2395 uint64_t iob2big:1;
2396 uint64_t dma0dbo:1;
2397 uint64_t dma1dbo:1;
2398 uint64_t dma2dbo:1;
2399 uint64_t dma3dbo:1;
2400 uint64_t dma4dbo:1;
2401 uint64_t dma0fi:1;
2402 uint64_t dma1fi:1;
2403 uint64_t dcnt0:1;
2404 uint64_t dcnt1:1;
2405 uint64_t dtime0:1;
2406 uint64_t dtime1:1;
2407 uint64_t psldbof:1;
2408 uint64_t pidbof:1;
2409 uint64_t pcnt:1;
2410 uint64_t ptime:1;
2411 uint64_t c0_aeri:1;
2412 uint64_t crs0_er:1;
2413 uint64_t c0_se:1;
2414 uint64_t crs0_dr:1;
2415 uint64_t c0_wake:1;
2416 uint64_t c0_pmei:1;
2417 uint64_t c0_hpint:1;
2418 uint64_t c1_aeri:1;
2419 uint64_t crs1_er:1;
2420 uint64_t c1_se:1;
2421 uint64_t crs1_dr:1;
2422 uint64_t c1_wake:1;
2423 uint64_t c1_pmei:1;
2424 uint64_t c1_hpint:1;
2425 uint64_t c0_up_b0:1;
2426 uint64_t c0_up_b1:1;
2427 uint64_t c0_up_b2:1;
2428 uint64_t c0_up_wi:1;
2429 uint64_t c0_up_bx:1;
2430 uint64_t c0_un_b0:1;
2431 uint64_t c0_un_b1:1;
2432 uint64_t c0_un_b2:1;
2433 uint64_t c0_un_wi:1;
2434 uint64_t c0_un_bx:1;
2435 uint64_t c1_up_b0:1;
2436 uint64_t c1_up_b1:1;
2437 uint64_t c1_up_b2:1;
2438 uint64_t c1_up_wi:1;
2439 uint64_t c1_up_bx:1;
2440 uint64_t c1_un_b0:1;
2441 uint64_t c1_un_b1:1;
2442 uint64_t c1_un_b2:1;
2443 uint64_t c1_un_wi:1;
2444 uint64_t c1_un_bx:1;
2445 uint64_t c0_un_wf:1;
2446 uint64_t c1_un_wf:1;
2447 uint64_t c0_up_wf:1;
2448 uint64_t c1_up_wf:1;
2449 uint64_t c0_exc:1;
2450 uint64_t c1_exc:1;
2451 uint64_t c0_ldwn:1;
2452 uint64_t c1_ldwn:1;
2453 uint64_t int_a:1;
2454 uint64_t reserved_62_62:1;
2455 uint64_t mio_inta:1;
2456 #endif
2457 } s;
2458 struct cvmx_npei_int_sum_cn52xxp1 {
2459 #ifdef __BIG_ENDIAN_BITFIELD
2460 uint64_t mio_inta:1;
2461 uint64_t reserved_62_62:1;
2462 uint64_t int_a:1;
2463 uint64_t c1_ldwn:1;
2464 uint64_t c0_ldwn:1;
2465 uint64_t c1_exc:1;
2466 uint64_t c0_exc:1;
2467 uint64_t c1_up_wf:1;
2468 uint64_t c0_up_wf:1;
2469 uint64_t c1_un_wf:1;
2470 uint64_t c0_un_wf:1;
2471 uint64_t c1_un_bx:1;
2472 uint64_t c1_un_wi:1;
2473 uint64_t c1_un_b2:1;
2474 uint64_t c1_un_b1:1;
2475 uint64_t c1_un_b0:1;
2476 uint64_t c1_up_bx:1;
2477 uint64_t c1_up_wi:1;
2478 uint64_t c1_up_b2:1;
2479 uint64_t c1_up_b1:1;
2480 uint64_t c1_up_b0:1;
2481 uint64_t c0_un_bx:1;
2482 uint64_t c0_un_wi:1;
2483 uint64_t c0_un_b2:1;
2484 uint64_t c0_un_b1:1;
2485 uint64_t c0_un_b0:1;
2486 uint64_t c0_up_bx:1;
2487 uint64_t c0_up_wi:1;
2488 uint64_t c0_up_b2:1;
2489 uint64_t c0_up_b1:1;
2490 uint64_t c0_up_b0:1;
2491 uint64_t c1_hpint:1;
2492 uint64_t c1_pmei:1;
2493 uint64_t c1_wake:1;
2494 uint64_t crs1_dr:1;
2495 uint64_t c1_se:1;
2496 uint64_t crs1_er:1;
2497 uint64_t c1_aeri:1;
2498 uint64_t c0_hpint:1;
2499 uint64_t c0_pmei:1;
2500 uint64_t c0_wake:1;
2501 uint64_t crs0_dr:1;
2502 uint64_t c0_se:1;
2503 uint64_t crs0_er:1;
2504 uint64_t c0_aeri:1;
2505 uint64_t reserved_15_18:4;
2506 uint64_t dtime1:1;
2507 uint64_t dtime0:1;
2508 uint64_t dcnt1:1;
2509 uint64_t dcnt0:1;
2510 uint64_t dma1fi:1;
2511 uint64_t dma0fi:1;
2512 uint64_t reserved_8_8:1;
2513 uint64_t dma3dbo:1;
2514 uint64_t dma2dbo:1;
2515 uint64_t dma1dbo:1;
2516 uint64_t dma0dbo:1;
2517 uint64_t iob2big:1;
2518 uint64_t bar0_to:1;
2519 uint64_t rml_wto:1;
2520 uint64_t rml_rto:1;
2521 #else
2522 uint64_t rml_rto:1;
2523 uint64_t rml_wto:1;
2524 uint64_t bar0_to:1;
2525 uint64_t iob2big:1;
2526 uint64_t dma0dbo:1;
2527 uint64_t dma1dbo:1;
2528 uint64_t dma2dbo:1;
2529 uint64_t dma3dbo:1;
2530 uint64_t reserved_8_8:1;
2531 uint64_t dma0fi:1;
2532 uint64_t dma1fi:1;
2533 uint64_t dcnt0:1;
2534 uint64_t dcnt1:1;
2535 uint64_t dtime0:1;
2536 uint64_t dtime1:1;
2537 uint64_t reserved_15_18:4;
2538 uint64_t c0_aeri:1;
2539 uint64_t crs0_er:1;
2540 uint64_t c0_se:1;
2541 uint64_t crs0_dr:1;
2542 uint64_t c0_wake:1;
2543 uint64_t c0_pmei:1;
2544 uint64_t c0_hpint:1;
2545 uint64_t c1_aeri:1;
2546 uint64_t crs1_er:1;
2547 uint64_t c1_se:1;
2548 uint64_t crs1_dr:1;
2549 uint64_t c1_wake:1;
2550 uint64_t c1_pmei:1;
2551 uint64_t c1_hpint:1;
2552 uint64_t c0_up_b0:1;
2553 uint64_t c0_up_b1:1;
2554 uint64_t c0_up_b2:1;
2555 uint64_t c0_up_wi:1;
2556 uint64_t c0_up_bx:1;
2557 uint64_t c0_un_b0:1;
2558 uint64_t c0_un_b1:1;
2559 uint64_t c0_un_b2:1;
2560 uint64_t c0_un_wi:1;
2561 uint64_t c0_un_bx:1;
2562 uint64_t c1_up_b0:1;
2563 uint64_t c1_up_b1:1;
2564 uint64_t c1_up_b2:1;
2565 uint64_t c1_up_wi:1;
2566 uint64_t c1_up_bx:1;
2567 uint64_t c1_un_b0:1;
2568 uint64_t c1_un_b1:1;
2569 uint64_t c1_un_b2:1;
2570 uint64_t c1_un_wi:1;
2571 uint64_t c1_un_bx:1;
2572 uint64_t c0_un_wf:1;
2573 uint64_t c1_un_wf:1;
2574 uint64_t c0_up_wf:1;
2575 uint64_t c1_up_wf:1;
2576 uint64_t c0_exc:1;
2577 uint64_t c1_exc:1;
2578 uint64_t c0_ldwn:1;
2579 uint64_t c1_ldwn:1;
2580 uint64_t int_a:1;
2581 uint64_t reserved_62_62:1;
2582 uint64_t mio_inta:1;
2583 #endif
2584 } cn52xxp1;
2585 struct cvmx_npei_int_sum_cn56xxp1 {
2586 #ifdef __BIG_ENDIAN_BITFIELD
2587 uint64_t mio_inta:1;
2588 uint64_t reserved_61_62:2;
2589 uint64_t c1_ldwn:1;
2590 uint64_t c0_ldwn:1;
2591 uint64_t c1_exc:1;
2592 uint64_t c0_exc:1;
2593 uint64_t c1_up_wf:1;
2594 uint64_t c0_up_wf:1;
2595 uint64_t c1_un_wf:1;
2596 uint64_t c0_un_wf:1;
2597 uint64_t c1_un_bx:1;
2598 uint64_t c1_un_wi:1;
2599 uint64_t c1_un_b2:1;
2600 uint64_t c1_un_b1:1;
2601 uint64_t c1_un_b0:1;
2602 uint64_t c1_up_bx:1;
2603 uint64_t c1_up_wi:1;
2604 uint64_t c1_up_b2:1;
2605 uint64_t c1_up_b1:1;
2606 uint64_t c1_up_b0:1;
2607 uint64_t c0_un_bx:1;
2608 uint64_t c0_un_wi:1;
2609 uint64_t c0_un_b2:1;
2610 uint64_t c0_un_b1:1;
2611 uint64_t c0_un_b0:1;
2612 uint64_t c0_up_bx:1;
2613 uint64_t c0_up_wi:1;
2614 uint64_t c0_up_b2:1;
2615 uint64_t c0_up_b1:1;
2616 uint64_t c0_up_b0:1;
2617 uint64_t c1_hpint:1;
2618 uint64_t c1_pmei:1;
2619 uint64_t c1_wake:1;
2620 uint64_t reserved_29_29:1;
2621 uint64_t c1_se:1;
2622 uint64_t reserved_27_27:1;
2623 uint64_t c1_aeri:1;
2624 uint64_t c0_hpint:1;
2625 uint64_t c0_pmei:1;
2626 uint64_t c0_wake:1;
2627 uint64_t reserved_22_22:1;
2628 uint64_t c0_se:1;
2629 uint64_t reserved_20_20:1;
2630 uint64_t c0_aeri:1;
2631 uint64_t reserved_15_18:4;
2632 uint64_t dtime1:1;
2633 uint64_t dtime0:1;
2634 uint64_t dcnt1:1;
2635 uint64_t dcnt0:1;
2636 uint64_t dma1fi:1;
2637 uint64_t dma0fi:1;
2638 uint64_t dma4dbo:1;
2639 uint64_t dma3dbo:1;
2640 uint64_t dma2dbo:1;
2641 uint64_t dma1dbo:1;
2642 uint64_t dma0dbo:1;
2643 uint64_t iob2big:1;
2644 uint64_t bar0_to:1;
2645 uint64_t rml_wto:1;
2646 uint64_t rml_rto:1;
2647 #else
2648 uint64_t rml_rto:1;
2649 uint64_t rml_wto:1;
2650 uint64_t bar0_to:1;
2651 uint64_t iob2big:1;
2652 uint64_t dma0dbo:1;
2653 uint64_t dma1dbo:1;
2654 uint64_t dma2dbo:1;
2655 uint64_t dma3dbo:1;
2656 uint64_t dma4dbo:1;
2657 uint64_t dma0fi:1;
2658 uint64_t dma1fi:1;
2659 uint64_t dcnt0:1;
2660 uint64_t dcnt1:1;
2661 uint64_t dtime0:1;
2662 uint64_t dtime1:1;
2663 uint64_t reserved_15_18:4;
2664 uint64_t c0_aeri:1;
2665 uint64_t reserved_20_20:1;
2666 uint64_t c0_se:1;
2667 uint64_t reserved_22_22:1;
2668 uint64_t c0_wake:1;
2669 uint64_t c0_pmei:1;
2670 uint64_t c0_hpint:1;
2671 uint64_t c1_aeri:1;
2672 uint64_t reserved_27_27:1;
2673 uint64_t c1_se:1;
2674 uint64_t reserved_29_29:1;
2675 uint64_t c1_wake:1;
2676 uint64_t c1_pmei:1;
2677 uint64_t c1_hpint:1;
2678 uint64_t c0_up_b0:1;
2679 uint64_t c0_up_b1:1;
2680 uint64_t c0_up_b2:1;
2681 uint64_t c0_up_wi:1;
2682 uint64_t c0_up_bx:1;
2683 uint64_t c0_un_b0:1;
2684 uint64_t c0_un_b1:1;
2685 uint64_t c0_un_b2:1;
2686 uint64_t c0_un_wi:1;
2687 uint64_t c0_un_bx:1;
2688 uint64_t c1_up_b0:1;
2689 uint64_t c1_up_b1:1;
2690 uint64_t c1_up_b2:1;
2691 uint64_t c1_up_wi:1;
2692 uint64_t c1_up_bx:1;
2693 uint64_t c1_un_b0:1;
2694 uint64_t c1_un_b1:1;
2695 uint64_t c1_un_b2:1;
2696 uint64_t c1_un_wi:1;
2697 uint64_t c1_un_bx:1;
2698 uint64_t c0_un_wf:1;
2699 uint64_t c1_un_wf:1;
2700 uint64_t c0_up_wf:1;
2701 uint64_t c1_up_wf:1;
2702 uint64_t c0_exc:1;
2703 uint64_t c1_exc:1;
2704 uint64_t c0_ldwn:1;
2705 uint64_t c1_ldwn:1;
2706 uint64_t reserved_61_62:2;
2707 uint64_t mio_inta:1;
2708 #endif
2709 } cn56xxp1;
2710 };
2711
2712 union cvmx_npei_int_sum2 {
2713 uint64_t u64;
2714 struct cvmx_npei_int_sum2_s {
2715 #ifdef __BIG_ENDIAN_BITFIELD
2716 uint64_t mio_inta:1;
2717 uint64_t reserved_62_62:1;
2718 uint64_t int_a:1;
2719 uint64_t c1_ldwn:1;
2720 uint64_t c0_ldwn:1;
2721 uint64_t c1_exc:1;
2722 uint64_t c0_exc:1;
2723 uint64_t c1_up_wf:1;
2724 uint64_t c0_up_wf:1;
2725 uint64_t c1_un_wf:1;
2726 uint64_t c0_un_wf:1;
2727 uint64_t c1_un_bx:1;
2728 uint64_t c1_un_wi:1;
2729 uint64_t c1_un_b2:1;
2730 uint64_t c1_un_b1:1;
2731 uint64_t c1_un_b0:1;
2732 uint64_t c1_up_bx:1;
2733 uint64_t c1_up_wi:1;
2734 uint64_t c1_up_b2:1;
2735 uint64_t c1_up_b1:1;
2736 uint64_t c1_up_b0:1;
2737 uint64_t c0_un_bx:1;
2738 uint64_t c0_un_wi:1;
2739 uint64_t c0_un_b2:1;
2740 uint64_t c0_un_b1:1;
2741 uint64_t c0_un_b0:1;
2742 uint64_t c0_up_bx:1;
2743 uint64_t c0_up_wi:1;
2744 uint64_t c0_up_b2:1;
2745 uint64_t c0_up_b1:1;
2746 uint64_t c0_up_b0:1;
2747 uint64_t c1_hpint:1;
2748 uint64_t c1_pmei:1;
2749 uint64_t c1_wake:1;
2750 uint64_t crs1_dr:1;
2751 uint64_t c1_se:1;
2752 uint64_t crs1_er:1;
2753 uint64_t c1_aeri:1;
2754 uint64_t c0_hpint:1;
2755 uint64_t c0_pmei:1;
2756 uint64_t c0_wake:1;
2757 uint64_t crs0_dr:1;
2758 uint64_t c0_se:1;
2759 uint64_t crs0_er:1;
2760 uint64_t c0_aeri:1;
2761 uint64_t reserved_15_18:4;
2762 uint64_t dtime1:1;
2763 uint64_t dtime0:1;
2764 uint64_t dcnt1:1;
2765 uint64_t dcnt0:1;
2766 uint64_t dma1fi:1;
2767 uint64_t dma0fi:1;
2768 uint64_t reserved_8_8:1;
2769 uint64_t dma3dbo:1;
2770 uint64_t dma2dbo:1;
2771 uint64_t dma1dbo:1;
2772 uint64_t dma0dbo:1;
2773 uint64_t iob2big:1;
2774 uint64_t bar0_to:1;
2775 uint64_t rml_wto:1;
2776 uint64_t rml_rto:1;
2777 #else
2778 uint64_t rml_rto:1;
2779 uint64_t rml_wto:1;
2780 uint64_t bar0_to:1;
2781 uint64_t iob2big:1;
2782 uint64_t dma0dbo:1;
2783 uint64_t dma1dbo:1;
2784 uint64_t dma2dbo:1;
2785 uint64_t dma3dbo:1;
2786 uint64_t reserved_8_8:1;
2787 uint64_t dma0fi:1;
2788 uint64_t dma1fi:1;
2789 uint64_t dcnt0:1;
2790 uint64_t dcnt1:1;
2791 uint64_t dtime0:1;
2792 uint64_t dtime1:1;
2793 uint64_t reserved_15_18:4;
2794 uint64_t c0_aeri:1;
2795 uint64_t crs0_er:1;
2796 uint64_t c0_se:1;
2797 uint64_t crs0_dr:1;
2798 uint64_t c0_wake:1;
2799 uint64_t c0_pmei:1;
2800 uint64_t c0_hpint:1;
2801 uint64_t c1_aeri:1;
2802 uint64_t crs1_er:1;
2803 uint64_t c1_se:1;
2804 uint64_t crs1_dr:1;
2805 uint64_t c1_wake:1;
2806 uint64_t c1_pmei:1;
2807 uint64_t c1_hpint:1;
2808 uint64_t c0_up_b0:1;
2809 uint64_t c0_up_b1:1;
2810 uint64_t c0_up_b2:1;
2811 uint64_t c0_up_wi:1;
2812 uint64_t c0_up_bx:1;
2813 uint64_t c0_un_b0:1;
2814 uint64_t c0_un_b1:1;
2815 uint64_t c0_un_b2:1;
2816 uint64_t c0_un_wi:1;
2817 uint64_t c0_un_bx:1;
2818 uint64_t c1_up_b0:1;
2819 uint64_t c1_up_b1:1;
2820 uint64_t c1_up_b2:1;
2821 uint64_t c1_up_wi:1;
2822 uint64_t c1_up_bx:1;
2823 uint64_t c1_un_b0:1;
2824 uint64_t c1_un_b1:1;
2825 uint64_t c1_un_b2:1;
2826 uint64_t c1_un_wi:1;
2827 uint64_t c1_un_bx:1;
2828 uint64_t c0_un_wf:1;
2829 uint64_t c1_un_wf:1;
2830 uint64_t c0_up_wf:1;
2831 uint64_t c1_up_wf:1;
2832 uint64_t c0_exc:1;
2833 uint64_t c1_exc:1;
2834 uint64_t c0_ldwn:1;
2835 uint64_t c1_ldwn:1;
2836 uint64_t int_a:1;
2837 uint64_t reserved_62_62:1;
2838 uint64_t mio_inta:1;
2839 #endif
2840 } s;
2841 };
2842
2843 union cvmx_npei_last_win_rdata0 {
2844 uint64_t u64;
2845 struct cvmx_npei_last_win_rdata0_s {
2846 #ifdef __BIG_ENDIAN_BITFIELD
2847 uint64_t data:64;
2848 #else
2849 uint64_t data:64;
2850 #endif
2851 } s;
2852 };
2853
2854 union cvmx_npei_last_win_rdata1 {
2855 uint64_t u64;
2856 struct cvmx_npei_last_win_rdata1_s {
2857 #ifdef __BIG_ENDIAN_BITFIELD
2858 uint64_t data:64;
2859 #else
2860 uint64_t data:64;
2861 #endif
2862 } s;
2863 };
2864
2865 union cvmx_npei_mem_access_ctl {
2866 uint64_t u64;
2867 struct cvmx_npei_mem_access_ctl_s {
2868 #ifdef __BIG_ENDIAN_BITFIELD
2869 uint64_t reserved_14_63:50;
2870 uint64_t max_word:4;
2871 uint64_t timer:10;
2872 #else
2873 uint64_t timer:10;
2874 uint64_t max_word:4;
2875 uint64_t reserved_14_63:50;
2876 #endif
2877 } s;
2878 };
2879
2880 union cvmx_npei_mem_access_subidx {
2881 uint64_t u64;
2882 struct cvmx_npei_mem_access_subidx_s {
2883 #ifdef __BIG_ENDIAN_BITFIELD
2884 uint64_t reserved_42_63:22;
2885 uint64_t zero:1;
2886 uint64_t port:2;
2887 uint64_t nmerge:1;
2888 uint64_t esr:2;
2889 uint64_t esw:2;
2890 uint64_t nsr:1;
2891 uint64_t nsw:1;
2892 uint64_t ror:1;
2893 uint64_t row:1;
2894 uint64_t ba:30;
2895 #else
2896 uint64_t ba:30;
2897 uint64_t row:1;
2898 uint64_t ror:1;
2899 uint64_t nsw:1;
2900 uint64_t nsr:1;
2901 uint64_t esw:2;
2902 uint64_t esr:2;
2903 uint64_t nmerge:1;
2904 uint64_t port:2;
2905 uint64_t zero:1;
2906 uint64_t reserved_42_63:22;
2907 #endif
2908 } s;
2909 };
2910
2911 union cvmx_npei_msi_enb0 {
2912 uint64_t u64;
2913 struct cvmx_npei_msi_enb0_s {
2914 #ifdef __BIG_ENDIAN_BITFIELD
2915 uint64_t enb:64;
2916 #else
2917 uint64_t enb:64;
2918 #endif
2919 } s;
2920 };
2921
2922 union cvmx_npei_msi_enb1 {
2923 uint64_t u64;
2924 struct cvmx_npei_msi_enb1_s {
2925 #ifdef __BIG_ENDIAN_BITFIELD
2926 uint64_t enb:64;
2927 #else
2928 uint64_t enb:64;
2929 #endif
2930 } s;
2931 };
2932
2933 union cvmx_npei_msi_enb2 {
2934 uint64_t u64;
2935 struct cvmx_npei_msi_enb2_s {
2936 #ifdef __BIG_ENDIAN_BITFIELD
2937 uint64_t enb:64;
2938 #else
2939 uint64_t enb:64;
2940 #endif
2941 } s;
2942 };
2943
2944 union cvmx_npei_msi_enb3 {
2945 uint64_t u64;
2946 struct cvmx_npei_msi_enb3_s {
2947 #ifdef __BIG_ENDIAN_BITFIELD
2948 uint64_t enb:64;
2949 #else
2950 uint64_t enb:64;
2951 #endif
2952 } s;
2953 };
2954
2955 union cvmx_npei_msi_rcv0 {
2956 uint64_t u64;
2957 struct cvmx_npei_msi_rcv0_s {
2958 #ifdef __BIG_ENDIAN_BITFIELD
2959 uint64_t intr:64;
2960 #else
2961 uint64_t intr:64;
2962 #endif
2963 } s;
2964 };
2965
2966 union cvmx_npei_msi_rcv1 {
2967 uint64_t u64;
2968 struct cvmx_npei_msi_rcv1_s {
2969 #ifdef __BIG_ENDIAN_BITFIELD
2970 uint64_t intr:64;
2971 #else
2972 uint64_t intr:64;
2973 #endif
2974 } s;
2975 };
2976
2977 union cvmx_npei_msi_rcv2 {
2978 uint64_t u64;
2979 struct cvmx_npei_msi_rcv2_s {
2980 #ifdef __BIG_ENDIAN_BITFIELD
2981 uint64_t intr:64;
2982 #else
2983 uint64_t intr:64;
2984 #endif
2985 } s;
2986 };
2987
2988 union cvmx_npei_msi_rcv3 {
2989 uint64_t u64;
2990 struct cvmx_npei_msi_rcv3_s {
2991 #ifdef __BIG_ENDIAN_BITFIELD
2992 uint64_t intr:64;
2993 #else
2994 uint64_t intr:64;
2995 #endif
2996 } s;
2997 };
2998
2999 union cvmx_npei_msi_rd_map {
3000 uint64_t u64;
3001 struct cvmx_npei_msi_rd_map_s {
3002 #ifdef __BIG_ENDIAN_BITFIELD
3003 uint64_t reserved_16_63:48;
3004 uint64_t rd_int:8;
3005 uint64_t msi_int:8;
3006 #else
3007 uint64_t msi_int:8;
3008 uint64_t rd_int:8;
3009 uint64_t reserved_16_63:48;
3010 #endif
3011 } s;
3012 };
3013
3014 union cvmx_npei_msi_w1c_enb0 {
3015 uint64_t u64;
3016 struct cvmx_npei_msi_w1c_enb0_s {
3017 #ifdef __BIG_ENDIAN_BITFIELD
3018 uint64_t clr:64;
3019 #else
3020 uint64_t clr:64;
3021 #endif
3022 } s;
3023 };
3024
3025 union cvmx_npei_msi_w1c_enb1 {
3026 uint64_t u64;
3027 struct cvmx_npei_msi_w1c_enb1_s {
3028 #ifdef __BIG_ENDIAN_BITFIELD
3029 uint64_t clr:64;
3030 #else
3031 uint64_t clr:64;
3032 #endif
3033 } s;
3034 };
3035
3036 union cvmx_npei_msi_w1c_enb2 {
3037 uint64_t u64;
3038 struct cvmx_npei_msi_w1c_enb2_s {
3039 #ifdef __BIG_ENDIAN_BITFIELD
3040 uint64_t clr:64;
3041 #else
3042 uint64_t clr:64;
3043 #endif
3044 } s;
3045 };
3046
3047 union cvmx_npei_msi_w1c_enb3 {
3048 uint64_t u64;
3049 struct cvmx_npei_msi_w1c_enb3_s {
3050 #ifdef __BIG_ENDIAN_BITFIELD
3051 uint64_t clr:64;
3052 #else
3053 uint64_t clr:64;
3054 #endif
3055 } s;
3056 };
3057
3058 union cvmx_npei_msi_w1s_enb0 {
3059 uint64_t u64;
3060 struct cvmx_npei_msi_w1s_enb0_s {
3061 #ifdef __BIG_ENDIAN_BITFIELD
3062 uint64_t set:64;
3063 #else
3064 uint64_t set:64;
3065 #endif
3066 } s;
3067 };
3068
3069 union cvmx_npei_msi_w1s_enb1 {
3070 uint64_t u64;
3071 struct cvmx_npei_msi_w1s_enb1_s {
3072 #ifdef __BIG_ENDIAN_BITFIELD
3073 uint64_t set:64;
3074 #else
3075 uint64_t set:64;
3076 #endif
3077 } s;
3078 };
3079
3080 union cvmx_npei_msi_w1s_enb2 {
3081 uint64_t u64;
3082 struct cvmx_npei_msi_w1s_enb2_s {
3083 #ifdef __BIG_ENDIAN_BITFIELD
3084 uint64_t set:64;
3085 #else
3086 uint64_t set:64;
3087 #endif
3088 } s;
3089 };
3090
3091 union cvmx_npei_msi_w1s_enb3 {
3092 uint64_t u64;
3093 struct cvmx_npei_msi_w1s_enb3_s {
3094 #ifdef __BIG_ENDIAN_BITFIELD
3095 uint64_t set:64;
3096 #else
3097 uint64_t set:64;
3098 #endif
3099 } s;
3100 };
3101
3102 union cvmx_npei_msi_wr_map {
3103 uint64_t u64;
3104 struct cvmx_npei_msi_wr_map_s {
3105 #ifdef __BIG_ENDIAN_BITFIELD
3106 uint64_t reserved_16_63:48;
3107 uint64_t ciu_int:8;
3108 uint64_t msi_int:8;
3109 #else
3110 uint64_t msi_int:8;
3111 uint64_t ciu_int:8;
3112 uint64_t reserved_16_63:48;
3113 #endif
3114 } s;
3115 };
3116
3117 union cvmx_npei_pcie_credit_cnt {
3118 uint64_t u64;
3119 struct cvmx_npei_pcie_credit_cnt_s {
3120 #ifdef __BIG_ENDIAN_BITFIELD
3121 uint64_t reserved_48_63:16;
3122 uint64_t p1_ccnt:8;
3123 uint64_t p1_ncnt:8;
3124 uint64_t p1_pcnt:8;
3125 uint64_t p0_ccnt:8;
3126 uint64_t p0_ncnt:8;
3127 uint64_t p0_pcnt:8;
3128 #else
3129 uint64_t p0_pcnt:8;
3130 uint64_t p0_ncnt:8;
3131 uint64_t p0_ccnt:8;
3132 uint64_t p1_pcnt:8;
3133 uint64_t p1_ncnt:8;
3134 uint64_t p1_ccnt:8;
3135 uint64_t reserved_48_63:16;
3136 #endif
3137 } s;
3138 };
3139
3140 union cvmx_npei_pcie_msi_rcv {
3141 uint64_t u64;
3142 struct cvmx_npei_pcie_msi_rcv_s {
3143 #ifdef __BIG_ENDIAN_BITFIELD
3144 uint64_t reserved_8_63:56;
3145 uint64_t intr:8;
3146 #else
3147 uint64_t intr:8;
3148 uint64_t reserved_8_63:56;
3149 #endif
3150 } s;
3151 };
3152
3153 union cvmx_npei_pcie_msi_rcv_b1 {
3154 uint64_t u64;
3155 struct cvmx_npei_pcie_msi_rcv_b1_s {
3156 #ifdef __BIG_ENDIAN_BITFIELD
3157 uint64_t reserved_16_63:48;
3158 uint64_t intr:8;
3159 uint64_t reserved_0_7:8;
3160 #else
3161 uint64_t reserved_0_7:8;
3162 uint64_t intr:8;
3163 uint64_t reserved_16_63:48;
3164 #endif
3165 } s;
3166 };
3167
3168 union cvmx_npei_pcie_msi_rcv_b2 {
3169 uint64_t u64;
3170 struct cvmx_npei_pcie_msi_rcv_b2_s {
3171 #ifdef __BIG_ENDIAN_BITFIELD
3172 uint64_t reserved_24_63:40;
3173 uint64_t intr:8;
3174 uint64_t reserved_0_15:16;
3175 #else
3176 uint64_t reserved_0_15:16;
3177 uint64_t intr:8;
3178 uint64_t reserved_24_63:40;
3179 #endif
3180 } s;
3181 };
3182
3183 union cvmx_npei_pcie_msi_rcv_b3 {
3184 uint64_t u64;
3185 struct cvmx_npei_pcie_msi_rcv_b3_s {
3186 #ifdef __BIG_ENDIAN_BITFIELD
3187 uint64_t reserved_32_63:32;
3188 uint64_t intr:8;
3189 uint64_t reserved_0_23:24;
3190 #else
3191 uint64_t reserved_0_23:24;
3192 uint64_t intr:8;
3193 uint64_t reserved_32_63:32;
3194 #endif
3195 } s;
3196 };
3197
3198 union cvmx_npei_pktx_cnts {
3199 uint64_t u64;
3200 struct cvmx_npei_pktx_cnts_s {
3201 #ifdef __BIG_ENDIAN_BITFIELD
3202 uint64_t reserved_54_63:10;
3203 uint64_t timer:22;
3204 uint64_t cnt:32;
3205 #else
3206 uint64_t cnt:32;
3207 uint64_t timer:22;
3208 uint64_t reserved_54_63:10;
3209 #endif
3210 } s;
3211 };
3212
3213 union cvmx_npei_pktx_in_bp {
3214 uint64_t u64;
3215 struct cvmx_npei_pktx_in_bp_s {
3216 #ifdef __BIG_ENDIAN_BITFIELD
3217 uint64_t wmark:32;
3218 uint64_t cnt:32;
3219 #else
3220 uint64_t cnt:32;
3221 uint64_t wmark:32;
3222 #endif
3223 } s;
3224 };
3225
3226 union cvmx_npei_pktx_instr_baddr {
3227 uint64_t u64;
3228 struct cvmx_npei_pktx_instr_baddr_s {
3229 #ifdef __BIG_ENDIAN_BITFIELD
3230 uint64_t addr:61;
3231 uint64_t reserved_0_2:3;
3232 #else
3233 uint64_t reserved_0_2:3;
3234 uint64_t addr:61;
3235 #endif
3236 } s;
3237 };
3238
3239 union cvmx_npei_pktx_instr_baoff_dbell {
3240 uint64_t u64;
3241 struct cvmx_npei_pktx_instr_baoff_dbell_s {
3242 #ifdef __BIG_ENDIAN_BITFIELD
3243 uint64_t aoff:32;
3244 uint64_t dbell:32;
3245 #else
3246 uint64_t dbell:32;
3247 uint64_t aoff:32;
3248 #endif
3249 } s;
3250 };
3251
3252 union cvmx_npei_pktx_instr_fifo_rsize {
3253 uint64_t u64;
3254 struct cvmx_npei_pktx_instr_fifo_rsize_s {
3255 #ifdef __BIG_ENDIAN_BITFIELD
3256 uint64_t max:9;
3257 uint64_t rrp:9;
3258 uint64_t wrp:9;
3259 uint64_t fcnt:5;
3260 uint64_t rsize:32;
3261 #else
3262 uint64_t rsize:32;
3263 uint64_t fcnt:5;
3264 uint64_t wrp:9;
3265 uint64_t rrp:9;
3266 uint64_t max:9;
3267 #endif
3268 } s;
3269 };
3270
3271 union cvmx_npei_pktx_instr_header {
3272 uint64_t u64;
3273 struct cvmx_npei_pktx_instr_header_s {
3274 #ifdef __BIG_ENDIAN_BITFIELD
3275 uint64_t reserved_44_63:20;
3276 uint64_t pbp:1;
3277 uint64_t reserved_38_42:5;
3278 uint64_t rparmode:2;
3279 uint64_t reserved_35_35:1;
3280 uint64_t rskp_len:7;
3281 uint64_t reserved_22_27:6;
3282 uint64_t use_ihdr:1;
3283 uint64_t reserved_16_20:5;
3284 uint64_t par_mode:2;
3285 uint64_t reserved_13_13:1;
3286 uint64_t skp_len:7;
3287 uint64_t reserved_0_5:6;
3288 #else
3289 uint64_t reserved_0_5:6;
3290 uint64_t skp_len:7;
3291 uint64_t reserved_13_13:1;
3292 uint64_t par_mode:2;
3293 uint64_t reserved_16_20:5;
3294 uint64_t use_ihdr:1;
3295 uint64_t reserved_22_27:6;
3296 uint64_t rskp_len:7;
3297 uint64_t reserved_35_35:1;
3298 uint64_t rparmode:2;
3299 uint64_t reserved_38_42:5;
3300 uint64_t pbp:1;
3301 uint64_t reserved_44_63:20;
3302 #endif
3303 } s;
3304 };
3305
3306 union cvmx_npei_pktx_slist_baddr {
3307 uint64_t u64;
3308 struct cvmx_npei_pktx_slist_baddr_s {
3309 #ifdef __BIG_ENDIAN_BITFIELD
3310 uint64_t addr:60;
3311 uint64_t reserved_0_3:4;
3312 #else
3313 uint64_t reserved_0_3:4;
3314 uint64_t addr:60;
3315 #endif
3316 } s;
3317 };
3318
3319 union cvmx_npei_pktx_slist_baoff_dbell {
3320 uint64_t u64;
3321 struct cvmx_npei_pktx_slist_baoff_dbell_s {
3322 #ifdef __BIG_ENDIAN_BITFIELD
3323 uint64_t aoff:32;
3324 uint64_t dbell:32;
3325 #else
3326 uint64_t dbell:32;
3327 uint64_t aoff:32;
3328 #endif
3329 } s;
3330 };
3331
3332 union cvmx_npei_pktx_slist_fifo_rsize {
3333 uint64_t u64;
3334 struct cvmx_npei_pktx_slist_fifo_rsize_s {
3335 #ifdef __BIG_ENDIAN_BITFIELD
3336 uint64_t reserved_32_63:32;
3337 uint64_t rsize:32;
3338 #else
3339 uint64_t rsize:32;
3340 uint64_t reserved_32_63:32;
3341 #endif
3342 } s;
3343 };
3344
3345 union cvmx_npei_pkt_cnt_int {
3346 uint64_t u64;
3347 struct cvmx_npei_pkt_cnt_int_s {
3348 #ifdef __BIG_ENDIAN_BITFIELD
3349 uint64_t reserved_32_63:32;
3350 uint64_t port:32;
3351 #else
3352 uint64_t port:32;
3353 uint64_t reserved_32_63:32;
3354 #endif
3355 } s;
3356 };
3357
3358 union cvmx_npei_pkt_cnt_int_enb {
3359 uint64_t u64;
3360 struct cvmx_npei_pkt_cnt_int_enb_s {
3361 #ifdef __BIG_ENDIAN_BITFIELD
3362 uint64_t reserved_32_63:32;
3363 uint64_t port:32;
3364 #else
3365 uint64_t port:32;
3366 uint64_t reserved_32_63:32;
3367 #endif
3368 } s;
3369 };
3370
3371 union cvmx_npei_pkt_data_out_es {
3372 uint64_t u64;
3373 struct cvmx_npei_pkt_data_out_es_s {
3374 #ifdef __BIG_ENDIAN_BITFIELD
3375 uint64_t es:64;
3376 #else
3377 uint64_t es:64;
3378 #endif
3379 } s;
3380 };
3381
3382 union cvmx_npei_pkt_data_out_ns {
3383 uint64_t u64;
3384 struct cvmx_npei_pkt_data_out_ns_s {
3385 #ifdef __BIG_ENDIAN_BITFIELD
3386 uint64_t reserved_32_63:32;
3387 uint64_t nsr:32;
3388 #else
3389 uint64_t nsr:32;
3390 uint64_t reserved_32_63:32;
3391 #endif
3392 } s;
3393 };
3394
3395 union cvmx_npei_pkt_data_out_ror {
3396 uint64_t u64;
3397 struct cvmx_npei_pkt_data_out_ror_s {
3398 #ifdef __BIG_ENDIAN_BITFIELD
3399 uint64_t reserved_32_63:32;
3400 uint64_t ror:32;
3401 #else
3402 uint64_t ror:32;
3403 uint64_t reserved_32_63:32;
3404 #endif
3405 } s;
3406 };
3407
3408 union cvmx_npei_pkt_dpaddr {
3409 uint64_t u64;
3410 struct cvmx_npei_pkt_dpaddr_s {
3411 #ifdef __BIG_ENDIAN_BITFIELD
3412 uint64_t reserved_32_63:32;
3413 uint64_t dptr:32;
3414 #else
3415 uint64_t dptr:32;
3416 uint64_t reserved_32_63:32;
3417 #endif
3418 } s;
3419 };
3420
3421 union cvmx_npei_pkt_in_bp {
3422 uint64_t u64;
3423 struct cvmx_npei_pkt_in_bp_s {
3424 #ifdef __BIG_ENDIAN_BITFIELD
3425 uint64_t reserved_32_63:32;
3426 uint64_t bp:32;
3427 #else
3428 uint64_t bp:32;
3429 uint64_t reserved_32_63:32;
3430 #endif
3431 } s;
3432 };
3433
3434 union cvmx_npei_pkt_in_donex_cnts {
3435 uint64_t u64;
3436 struct cvmx_npei_pkt_in_donex_cnts_s {
3437 #ifdef __BIG_ENDIAN_BITFIELD
3438 uint64_t reserved_32_63:32;
3439 uint64_t cnt:32;
3440 #else
3441 uint64_t cnt:32;
3442 uint64_t reserved_32_63:32;
3443 #endif
3444 } s;
3445 };
3446
3447 union cvmx_npei_pkt_in_instr_counts {
3448 uint64_t u64;
3449 struct cvmx_npei_pkt_in_instr_counts_s {
3450 #ifdef __BIG_ENDIAN_BITFIELD
3451 uint64_t wr_cnt:32;
3452 uint64_t rd_cnt:32;
3453 #else
3454 uint64_t rd_cnt:32;
3455 uint64_t wr_cnt:32;
3456 #endif
3457 } s;
3458 };
3459
3460 union cvmx_npei_pkt_in_pcie_port {
3461 uint64_t u64;
3462 struct cvmx_npei_pkt_in_pcie_port_s {
3463 #ifdef __BIG_ENDIAN_BITFIELD
3464 uint64_t pp:64;
3465 #else
3466 uint64_t pp:64;
3467 #endif
3468 } s;
3469 };
3470
3471 union cvmx_npei_pkt_input_control {
3472 uint64_t u64;
3473 struct cvmx_npei_pkt_input_control_s {
3474 #ifdef __BIG_ENDIAN_BITFIELD
3475 uint64_t reserved_23_63:41;
3476 uint64_t pkt_rr:1;
3477 uint64_t pbp_dhi:13;
3478 uint64_t d_nsr:1;
3479 uint64_t d_esr:2;
3480 uint64_t d_ror:1;
3481 uint64_t use_csr:1;
3482 uint64_t nsr:1;
3483 uint64_t esr:2;
3484 uint64_t ror:1;
3485 #else
3486 uint64_t ror:1;
3487 uint64_t esr:2;
3488 uint64_t nsr:1;
3489 uint64_t use_csr:1;
3490 uint64_t d_ror:1;
3491 uint64_t d_esr:2;
3492 uint64_t d_nsr:1;
3493 uint64_t pbp_dhi:13;
3494 uint64_t pkt_rr:1;
3495 uint64_t reserved_23_63:41;
3496 #endif
3497 } s;
3498 };
3499
3500 union cvmx_npei_pkt_instr_enb {
3501 uint64_t u64;
3502 struct cvmx_npei_pkt_instr_enb_s {
3503 #ifdef __BIG_ENDIAN_BITFIELD
3504 uint64_t reserved_32_63:32;
3505 uint64_t enb:32;
3506 #else
3507 uint64_t enb:32;
3508 uint64_t reserved_32_63:32;
3509 #endif
3510 } s;
3511 };
3512
3513 union cvmx_npei_pkt_instr_rd_size {
3514 uint64_t u64;
3515 struct cvmx_npei_pkt_instr_rd_size_s {
3516 #ifdef __BIG_ENDIAN_BITFIELD
3517 uint64_t rdsize:64;
3518 #else
3519 uint64_t rdsize:64;
3520 #endif
3521 } s;
3522 };
3523
3524 union cvmx_npei_pkt_instr_size {
3525 uint64_t u64;
3526 struct cvmx_npei_pkt_instr_size_s {
3527 #ifdef __BIG_ENDIAN_BITFIELD
3528 uint64_t reserved_32_63:32;
3529 uint64_t is_64b:32;
3530 #else
3531 uint64_t is_64b:32;
3532 uint64_t reserved_32_63:32;
3533 #endif
3534 } s;
3535 };
3536
3537 union cvmx_npei_pkt_int_levels {
3538 uint64_t u64;
3539 struct cvmx_npei_pkt_int_levels_s {
3540 #ifdef __BIG_ENDIAN_BITFIELD
3541 uint64_t reserved_54_63:10;
3542 uint64_t time:22;
3543 uint64_t cnt:32;
3544 #else
3545 uint64_t cnt:32;
3546 uint64_t time:22;
3547 uint64_t reserved_54_63:10;
3548 #endif
3549 } s;
3550 };
3551
3552 union cvmx_npei_pkt_iptr {
3553 uint64_t u64;
3554 struct cvmx_npei_pkt_iptr_s {
3555 #ifdef __BIG_ENDIAN_BITFIELD
3556 uint64_t reserved_32_63:32;
3557 uint64_t iptr:32;
3558 #else
3559 uint64_t iptr:32;
3560 uint64_t reserved_32_63:32;
3561 #endif
3562 } s;
3563 };
3564
3565 union cvmx_npei_pkt_out_bmode {
3566 uint64_t u64;
3567 struct cvmx_npei_pkt_out_bmode_s {
3568 #ifdef __BIG_ENDIAN_BITFIELD
3569 uint64_t reserved_32_63:32;
3570 uint64_t bmode:32;
3571 #else
3572 uint64_t bmode:32;
3573 uint64_t reserved_32_63:32;
3574 #endif
3575 } s;
3576 };
3577
3578 union cvmx_npei_pkt_out_enb {
3579 uint64_t u64;
3580 struct cvmx_npei_pkt_out_enb_s {
3581 #ifdef __BIG_ENDIAN_BITFIELD
3582 uint64_t reserved_32_63:32;
3583 uint64_t enb:32;
3584 #else
3585 uint64_t enb:32;
3586 uint64_t reserved_32_63:32;
3587 #endif
3588 } s;
3589 };
3590
3591 union cvmx_npei_pkt_output_wmark {
3592 uint64_t u64;
3593 struct cvmx_npei_pkt_output_wmark_s {
3594 #ifdef __BIG_ENDIAN_BITFIELD
3595 uint64_t reserved_32_63:32;
3596 uint64_t wmark:32;
3597 #else
3598 uint64_t wmark:32;
3599 uint64_t reserved_32_63:32;
3600 #endif
3601 } s;
3602 };
3603
3604 union cvmx_npei_pkt_pcie_port {
3605 uint64_t u64;
3606 struct cvmx_npei_pkt_pcie_port_s {
3607 #ifdef __BIG_ENDIAN_BITFIELD
3608 uint64_t pp:64;
3609 #else
3610 uint64_t pp:64;
3611 #endif
3612 } s;
3613 };
3614
3615 union cvmx_npei_pkt_port_in_rst {
3616 uint64_t u64;
3617 struct cvmx_npei_pkt_port_in_rst_s {
3618 #ifdef __BIG_ENDIAN_BITFIELD
3619 uint64_t in_rst:32;
3620 uint64_t out_rst:32;
3621 #else
3622 uint64_t out_rst:32;
3623 uint64_t in_rst:32;
3624 #endif
3625 } s;
3626 };
3627
3628 union cvmx_npei_pkt_slist_es {
3629 uint64_t u64;
3630 struct cvmx_npei_pkt_slist_es_s {
3631 #ifdef __BIG_ENDIAN_BITFIELD
3632 uint64_t es:64;
3633 #else
3634 uint64_t es:64;
3635 #endif
3636 } s;
3637 };
3638
3639 union cvmx_npei_pkt_slist_id_size {
3640 uint64_t u64;
3641 struct cvmx_npei_pkt_slist_id_size_s {
3642 #ifdef __BIG_ENDIAN_BITFIELD
3643 uint64_t reserved_23_63:41;
3644 uint64_t isize:7;
3645 uint64_t bsize:16;
3646 #else
3647 uint64_t bsize:16;
3648 uint64_t isize:7;
3649 uint64_t reserved_23_63:41;
3650 #endif
3651 } s;
3652 };
3653
3654 union cvmx_npei_pkt_slist_ns {
3655 uint64_t u64;
3656 struct cvmx_npei_pkt_slist_ns_s {
3657 #ifdef __BIG_ENDIAN_BITFIELD
3658 uint64_t reserved_32_63:32;
3659 uint64_t nsr:32;
3660 #else
3661 uint64_t nsr:32;
3662 uint64_t reserved_32_63:32;
3663 #endif
3664 } s;
3665 };
3666
3667 union cvmx_npei_pkt_slist_ror {
3668 uint64_t u64;
3669 struct cvmx_npei_pkt_slist_ror_s {
3670 #ifdef __BIG_ENDIAN_BITFIELD
3671 uint64_t reserved_32_63:32;
3672 uint64_t ror:32;
3673 #else
3674 uint64_t ror:32;
3675 uint64_t reserved_32_63:32;
3676 #endif
3677 } s;
3678 };
3679
3680 union cvmx_npei_pkt_time_int {
3681 uint64_t u64;
3682 struct cvmx_npei_pkt_time_int_s {
3683 #ifdef __BIG_ENDIAN_BITFIELD
3684 uint64_t reserved_32_63:32;
3685 uint64_t port:32;
3686 #else
3687 uint64_t port:32;
3688 uint64_t reserved_32_63:32;
3689 #endif
3690 } s;
3691 };
3692
3693 union cvmx_npei_pkt_time_int_enb {
3694 uint64_t u64;
3695 struct cvmx_npei_pkt_time_int_enb_s {
3696 #ifdef __BIG_ENDIAN_BITFIELD
3697 uint64_t reserved_32_63:32;
3698 uint64_t port:32;
3699 #else
3700 uint64_t port:32;
3701 uint64_t reserved_32_63:32;
3702 #endif
3703 } s;
3704 };
3705
3706 union cvmx_npei_rsl_int_blocks {
3707 uint64_t u64;
3708 struct cvmx_npei_rsl_int_blocks_s {
3709 #ifdef __BIG_ENDIAN_BITFIELD
3710 uint64_t reserved_31_63:33;
3711 uint64_t iob:1;
3712 uint64_t lmc1:1;
3713 uint64_t agl:1;
3714 uint64_t reserved_24_27:4;
3715 uint64_t asxpcs1:1;
3716 uint64_t asxpcs0:1;
3717 uint64_t reserved_21_21:1;
3718 uint64_t pip:1;
3719 uint64_t spx1:1;
3720 uint64_t spx0:1;
3721 uint64_t lmc0:1;
3722 uint64_t l2c:1;
3723 uint64_t usb1:1;
3724 uint64_t rad:1;
3725 uint64_t usb:1;
3726 uint64_t pow:1;
3727 uint64_t tim:1;
3728 uint64_t pko:1;
3729 uint64_t ipd:1;
3730 uint64_t reserved_8_8:1;
3731 uint64_t zip:1;
3732 uint64_t dfa:1;
3733 uint64_t fpa:1;
3734 uint64_t key:1;
3735 uint64_t npei:1;
3736 uint64_t gmx1:1;
3737 uint64_t gmx0:1;
3738 uint64_t mio:1;
3739 #else
3740 uint64_t mio:1;
3741 uint64_t gmx0:1;
3742 uint64_t gmx1:1;
3743 uint64_t npei:1;
3744 uint64_t key:1;
3745 uint64_t fpa:1;
3746 uint64_t dfa:1;
3747 uint64_t zip:1;
3748 uint64_t reserved_8_8:1;
3749 uint64_t ipd:1;
3750 uint64_t pko:1;
3751 uint64_t tim:1;
3752 uint64_t pow:1;
3753 uint64_t usb:1;
3754 uint64_t rad:1;
3755 uint64_t usb1:1;
3756 uint64_t l2c:1;
3757 uint64_t lmc0:1;
3758 uint64_t spx0:1;
3759 uint64_t spx1:1;
3760 uint64_t pip:1;
3761 uint64_t reserved_21_21:1;
3762 uint64_t asxpcs0:1;
3763 uint64_t asxpcs1:1;
3764 uint64_t reserved_24_27:4;
3765 uint64_t agl:1;
3766 uint64_t lmc1:1;
3767 uint64_t iob:1;
3768 uint64_t reserved_31_63:33;
3769 #endif
3770 } s;
3771 };
3772
3773 union cvmx_npei_scratch_1 {
3774 uint64_t u64;
3775 struct cvmx_npei_scratch_1_s {
3776 #ifdef __BIG_ENDIAN_BITFIELD
3777 uint64_t data:64;
3778 #else
3779 uint64_t data:64;
3780 #endif
3781 } s;
3782 };
3783
3784 union cvmx_npei_state1 {
3785 uint64_t u64;
3786 struct cvmx_npei_state1_s {
3787 #ifdef __BIG_ENDIAN_BITFIELD
3788 uint64_t cpl1:12;
3789 uint64_t cpl0:12;
3790 uint64_t arb:1;
3791 uint64_t csr:39;
3792 #else
3793 uint64_t csr:39;
3794 uint64_t arb:1;
3795 uint64_t cpl0:12;
3796 uint64_t cpl1:12;
3797 #endif
3798 } s;
3799 };
3800
3801 union cvmx_npei_state2 {
3802 uint64_t u64;
3803 struct cvmx_npei_state2_s {
3804 #ifdef __BIG_ENDIAN_BITFIELD
3805 uint64_t reserved_48_63:16;
3806 uint64_t npei:1;
3807 uint64_t rac:1;
3808 uint64_t csm1:15;
3809 uint64_t csm0:15;
3810 uint64_t nnp0:8;
3811 uint64_t nnd:8;
3812 #else
3813 uint64_t nnd:8;
3814 uint64_t nnp0:8;
3815 uint64_t csm0:15;
3816 uint64_t csm1:15;
3817 uint64_t rac:1;
3818 uint64_t npei:1;
3819 uint64_t reserved_48_63:16;
3820 #endif
3821 } s;
3822 };
3823
3824 union cvmx_npei_state3 {
3825 uint64_t u64;
3826 struct cvmx_npei_state3_s {
3827 #ifdef __BIG_ENDIAN_BITFIELD
3828 uint64_t reserved_56_63:8;
3829 uint64_t psm1:15;
3830 uint64_t psm0:15;
3831 uint64_t nsm1:13;
3832 uint64_t nsm0:13;
3833 #else
3834 uint64_t nsm0:13;
3835 uint64_t nsm1:13;
3836 uint64_t psm0:15;
3837 uint64_t psm1:15;
3838 uint64_t reserved_56_63:8;
3839 #endif
3840 } s;
3841 };
3842
3843 union cvmx_npei_win_rd_addr {
3844 uint64_t u64;
3845 struct cvmx_npei_win_rd_addr_s {
3846 #ifdef __BIG_ENDIAN_BITFIELD
3847 uint64_t reserved_51_63:13;
3848 uint64_t ld_cmd:2;
3849 uint64_t iobit:1;
3850 uint64_t rd_addr:48;
3851 #else
3852 uint64_t rd_addr:48;
3853 uint64_t iobit:1;
3854 uint64_t ld_cmd:2;
3855 uint64_t reserved_51_63:13;
3856 #endif
3857 } s;
3858 };
3859
3860 union cvmx_npei_win_rd_data {
3861 uint64_t u64;
3862 struct cvmx_npei_win_rd_data_s {
3863 #ifdef __BIG_ENDIAN_BITFIELD
3864 uint64_t rd_data:64;
3865 #else
3866 uint64_t rd_data:64;
3867 #endif
3868 } s;
3869 };
3870
3871 union cvmx_npei_win_wr_addr {
3872 uint64_t u64;
3873 struct cvmx_npei_win_wr_addr_s {
3874 #ifdef __BIG_ENDIAN_BITFIELD
3875 uint64_t reserved_49_63:15;
3876 uint64_t iobit:1;
3877 uint64_t wr_addr:46;
3878 uint64_t reserved_0_1:2;
3879 #else
3880 uint64_t reserved_0_1:2;
3881 uint64_t wr_addr:46;
3882 uint64_t iobit:1;
3883 uint64_t reserved_49_63:15;
3884 #endif
3885 } s;
3886 };
3887
3888 union cvmx_npei_win_wr_data {
3889 uint64_t u64;
3890 struct cvmx_npei_win_wr_data_s {
3891 #ifdef __BIG_ENDIAN_BITFIELD
3892 uint64_t wr_data:64;
3893 #else
3894 uint64_t wr_data:64;
3895 #endif
3896 } s;
3897 };
3898
3899 union cvmx_npei_win_wr_mask {
3900 uint64_t u64;
3901 struct cvmx_npei_win_wr_mask_s {
3902 #ifdef __BIG_ENDIAN_BITFIELD
3903 uint64_t reserved_8_63:56;
3904 uint64_t wr_mask:8;
3905 #else
3906 uint64_t wr_mask:8;
3907 uint64_t reserved_8_63:56;
3908 #endif
3909 } s;
3910 };
3911
3912 union cvmx_npei_window_ctl {
3913 uint64_t u64;
3914 struct cvmx_npei_window_ctl_s {
3915 #ifdef __BIG_ENDIAN_BITFIELD
3916 uint64_t reserved_32_63:32;
3917 uint64_t time:32;
3918 #else
3919 uint64_t time:32;
3920 uint64_t reserved_32_63:32;
3921 #endif
3922 } s;
3923 };
3924
3925 #endif