1
2 #ifndef __CVMX_CONFIG_H__
3 #define __CVMX_CONFIG_H__
4
5
6 #define CVMX_LLM_NUM_PORTS 1
7 #define CVMX_NULL_POINTER_PROTECT 1
8 #define CVMX_ENABLE_DEBUG_PRINTS 1
9
10 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1
11
12 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1
13
14 #define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
15
16 #define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
17
18 #define CVMX_PKO_QUEUES_PER_PORT_PCI 1
19
20 #define CVMX_PKO_QUEUES_PER_PORT_LOOP 1
21
22
23
24 #define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)
25 #define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
26 #define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
27 #define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE)
28 #define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
29 #define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
30 #define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE)
31 #define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)
32
33
34
35 #define CVMX_FPA_PACKET_POOL (0)
36 #define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE
37
38 #define CVMX_FPA_WQE_POOL (1)
39 #define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE
40
41 #define CVMX_FPA_OUTPUT_BUFFER_POOL (2)
42 #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE
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53
54
55 #define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START)
56 typedef enum {
57 CVMX_FAU_REG_64_START = 0,
58 CVMX_FAU_REG_64_END = CVMX_FAU_REG_64_ADDR(0),
59 } cvmx_fau_reg_64_t;
60
61 #define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START)
62 typedef enum {
63 CVMX_FAU_REG_32_START = CVMX_FAU_REG_64_END,
64 CVMX_FAU_REG_32_END = CVMX_FAU_REG_32_ADDR(0),
65 } cvmx_fau_reg_32_t;
66
67 #define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START)
68 typedef enum {
69 CVMX_FAU_REG_16_START = CVMX_FAU_REG_32_END,
70 CVMX_FAU_REG_16_END = CVMX_FAU_REG_16_ADDR(0),
71 } cvmx_fau_reg_16_t;
72
73 #define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START)
74 typedef enum {
75 CVMX_FAU_REG_8_START = CVMX_FAU_REG_16_END,
76 CVMX_FAU_REG_8_END = CVMX_FAU_REG_8_ADDR(0),
77 } cvmx_fau_reg_8_t;
78
79
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82
83
84 #define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL))
85 #define CVMX_FAU_REG_END (2048)
86
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92
93
94 #define CVMX_SCR_SCRATCH (0)
95
96 #define CVMX_SCR_REG_AVAIL_BASE (8)
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103
104 #define CVMX_HELPER_FIRST_MBUFF_SKIP 184
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111 #define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0
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121
122
123 #define CVMX_HELPER_ENABLE_BACK_PRESSURE 1
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131
132 #define CVMX_HELPER_ENABLE_IPD 0
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136
137
138 #define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED
139
140 #define CVMX_ENABLE_PARAMETER_CHECKING 0
141
142
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146
147
148 #define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP 0
149 #define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0
150 #define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0
151 #define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0
152 #define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0
153 #define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP 0
154 #define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0
155 #define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0
156 #define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0
157 #define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0
158 #define CVMX_HELPER_INPUT_TAG_INPUT_PORT 1
159
160
161 #define CVMX_HELPER_INPUT_PORT_SKIP_MODE CVMX_PIP_PORT_CFG_MODE_SKIPL2
162
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166
167 #define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
168
169 #endif